Semiconductor device and method for manufacturing semiconductor device

Abstract

The purpose of the present invention is to provide a technique capable of suppressing interdiffusion between silicon and aluminum. The semiconductor device includes a semiconductor substrate, an electrode, and a first silicon burr. The semiconductor substrate includes a drift layer of a first conductivity type, and an anode layer of a second conductivity type provided on at least a portion of the drift layer. The electrode is disposed above the anode layer and includes aluminum. The first silicon burr is disposed between the anode layer and the electrode and includes oxygen.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device. Background Art

[0002] In recent years, in an RC-IGBT provided with an IGBT region and a diode region, a structure in which an electrode containing aluminum is provided near an anode layer in the diode region has been proposed (for example, Patent Document 1).

[0003] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2022-56498

[0004] In a structure in which an electrode containing aluminum is provided near the anode layer as in Patent Document 1, aluminum having a high diffusion coefficient contained in the electrode has an effect of accelerating diffusion in the anode layer containing silicon. Therefore, there is a problem that the non-uniformity of the diffusion profile of the anode layer becomes large. Summary of the Invention

[0005] Therefore, the present disclosure has been made in view of the above problems, and an object thereof is to provide a technique capable of suppressing the mutual diffusion of silicon and aluminum.

[0006] The semiconductor device of the present disclosure includes: a semiconductor substrate including a drift layer of a first conductivity type and an anode layer of a second conductivity type provided on at least a part of the drift layer; an electrode provided above the anode layer and containing aluminum; and a first silicon nodule provided between the anode layer and the electrode and containing oxygen.

[0007] According to the present disclosure, the first silicon nodule containing oxygen is provided between the anode layer and the electrode containing aluminum. With such a structure, the mutual diffusion of silicon and aluminum can be suppressed. Brief Description of the Drawings

[0008] Figure 1 It is a top view showing the structure of the semiconductor device of Embodiment 1.

[0009] Figure 2 It is a top view showing another structure of the semiconductor device of Embodiment 1.

[0010] Figure 3 It is a partially enlarged top view showing the structure of the IGBT region of the semiconductor device of Embodiment 1.

[0011] Figure 4 It is a cross-sectional view showing the structure of the IGBT region of the semiconductor device of Embodiment 1.

[0012] Figure 5 It is a cross-sectional view showing the structure of the IGBT region of the semiconductor device of Embodiment 1.

[0013] Figure 6 It is a partially enlarged top view showing the structure of the diode region of the semiconductor device according to Embodiment 1.

[0014] Figure 7 It is a cross-sectional view showing the structure of the diode region of the semiconductor device according to Embodiment 1.

[0015] Figure 8 It is a cross-sectional view showing the structure of the diode region of the semiconductor device according to Embodiment 1.

[0016] Figure 9 It is a cross-sectional view showing the structure of the boundary region between the IGBT region and the diode region of the semiconductor device according to Embodiment 1.

[0017] Figure 10 It is a graph showing the relationship between the depth from the back surface, the impurity concentration, and the carrier density in the on-state in the IGBT region according to Embodiment 1.

[0018] Figure 11 It is a cross-sectional view showing the structure of the terminal region of the semiconductor device according to Embodiment 1.

[0019] Figure 12 It is a cross-sectional view showing the structure of the terminal region of the semiconductor device according to Embodiment 1.

[0020] Figure 13 It is a cross-sectional view showing the manufacturing method of the semiconductor device according to Embodiment 1.

[0021] Figure 14 It is a cross-sectional view showing the manufacturing method of the semiconductor device according to Embodiment 1.

[0022] Figure 15 It is a cross-sectional view showing the manufacturing method of the semiconductor device according to Embodiment 1.

[0023] Figure 16 It is a cross-sectional view showing the manufacturing method of the semiconductor device according to Embodiment 1.

[0024] Figure 17 It is a cross-sectional view showing the manufacturing method of the semiconductor device according to Embodiment 1.

[0025] Figure 18 It is a cross-sectional view showing the manufacturing method of the semiconductor device according to Embodiment 1.

[0026] Figure 19 It is a flowchart showing the manufacturing method of the semiconductor device according to Embodiment 1.

[0027] Figure 20It is a cross-sectional view showing the structure of the boundary region between the IGBT region and the diode region of the semiconductor device according to Embodiment 2.

[0028] Figure 21 It is a diagram showing the result of the oxygen concentration in the manufacturing method of the semiconductor device according to Embodiment 2.

[0029] Figure 22 It is a cross-sectional view showing the structure of the boundary region between the IGBT region and the diode region of the semiconductor device according to Embodiment 3.

[0030] Figure 23 It is a cross-sectional view showing the structure of the boundary region between the IGBT region and the diode region of the semiconductor device according to Embodiment 4.

[0031] Figure 24 It is a cross-sectional view showing the structure of the boundary region between the IGBT region and the diode region of the semiconductor device according to Embodiment 5.

[0032] Figure 25 It is a cross-sectional view showing the structure of the boundary region between the IGBT region and the diode region of the semiconductor device according to Embodiment 6.

[0033] Figure 26 It is a cross-sectional view showing the structure of the boundary region between the IGBT region and the diode region of the semiconductor device according to Embodiment 7.

[0034] Figure 27 It is a cross-sectional view showing the structure of the boundary region between the IGBT region and the diode region of the semiconductor device according to Embodiment 8.

[0035] Figure 28 It is a cross-sectional view showing the structure of the boundary region between the IGBT region and the diode region of the semiconductor device according to Embodiment 9.

[0036] Figure 29 It is a cross-sectional view showing the structure of the boundary region between the IGBT region and the diode region of the semiconductor device according to Embodiment 10.

[0037] Figure 30 It is a cross-sectional view showing the structure of the boundary region between the IGBT region and the diode region of the semiconductor device according to Embodiment 11.

[0038] Explanation of reference numerals: 1...n - Type drift layer; 5...Barrier metal; 6...Emitter electrode; 6b...Conductive film; 6c...Grain boundary; 10...IGBT region; 11...Active trench gate; 12...Dummy trench gate; 13...n + Type source layer; 14...p +Type contact layer; 15... p-type base layer; 20... Diode region; 21... Diode trench gate; 24a... p + Type contact layer; 25... p-type anode layer; 51... Silicon layer; 52, 52a, 52b... First silicon burr; 53... n + Type impurity layer; 54... Schottky layer; 55... Second silicon burr; 56... Third silicon burr. Detailed implementation mode

[0039] Hereinafter, the implementation mode will be described with reference to the attached drawings. The features described in the following implementation modes are examples, and not all features are necessary. In addition, in the following descriptions, the same or similar reference numerals are assigned to the same structural elements in multiple implementation modes, and mainly different structural elements will be described. In addition, in the descriptions recorded below, specific positions and directions such as "upper", "lower", "left", "right", "front" or "back" may not necessarily be the same as the positions and directions during actual implementation. In addition, when a certain part has a higher concentration than other parts, it means that the average concentration of a certain part is higher than the average concentration of other parts. On the contrary, when a certain part has a lower concentration than other parts, it means that the average concentration of a certain part is lower than the average concentration of other parts. In addition, the following describes the case where the first conductivity type is n-type and the second conductivity type is p-type, but it can also be the case where the first conductivity type is p-type and the second conductivity type is n-type. In addition, n - Indicates that the impurity concentration is lower than n, n + Indicates that the impurity concentration is higher than n. Similarly, p - Indicates that the impurity concentration is lower than p, p + Indicates that the impurity concentration is higher than p.

[0040] <Embodiment 1>

[0041] Figure 1 Is a top view showing a semiconductor device as an RC-IGBT (Reverse Conducting IGBT). In addition, Figure 2 Is a top view showing other structures of the semiconductor device as the RC-IGBT of the present Embodiment 1. For Figure 1 The semiconductor device 100 shown, the IGBT region 10 and the diode region 20 are arranged in a striped pattern, and may sometimes be simply referred to as "striped type" in the following description. For Figure 2 The semiconductor device 100 shown, a plurality of diode regions 20 are provided longitudinally and laterally, and the IGBT region 10 is provided around the diode region 20. In the following description, it may sometimes be simply referred to as "island type".

[0042] <Overall planar structure of strip type>

[0043] In Figure 1 the semiconductor device 100 includes an IGBT region 10 and a diode region 20 within one semiconductor device. The IGBT region 10 and the diode region 20 each extend from one end side of the semiconductor device 100 to the other end side, and are alternately arranged in a striped pattern in a direction orthogonal to the extending direction of the IGBT region 10 and the diode region 20. Figure 1 In, 3 IGBT regions 10 and 2 diode regions 20 are shown, showing a structure in which all the diode regions 20 are sandwiched by the IGBT regions 10. However, the number of the IGBT region 10 and the diode region 20 is not limited to this. The number of the IGBT regions 10 can be more than 3 or less than 3, and the number of the diode regions 20 can be more than 2 or less than 2. In addition, it can also be a structure in which Figure 1 the positions of the IGBT region 10 and the diode region 20 are interchanged, or a structure in which all the IGBT regions 10 are sandwiched by the diode regions 20. In addition, it can also be a structure in which one IGBT region 10 and one diode region 20 are adjacent to each other.

[0044] As Figure 1 shown, a pad region 40 is adjacently provided to the IGBT region 10 on the lower side of the paper surface. The pad region 40 is a region where a control pad 41 for controlling the semiconductor device 100 is provided. In the following description, the IGBT region 10 and the diode region 20 are sometimes collectively referred to as a cell region. Around the region where the cell region and the pad region 40 are combined, a terminal region 30 is provided to maintain the breakdown voltage of the semiconductor device 100. A known breakdown voltage maintaining structure can be appropriately provided in the terminal region 30. In the breakdown voltage maintaining structure, for example, an FLR (Field Limiting Ring) that surrounds the cell region by a p-type terminal well layer of a p-type semiconductor and a VLD (Variation of Lateral Doping) that surrounds the cell region by a p-type well layer with a concentration gradient can be provided on the surface side of the semiconductor device 100. In addition, the number of the annular p-type terminal well layers for the FLR and the concentration distribution for the VLD can be appropriately selected according to the breakdown voltage design of the semiconductor device 100. In addition, a p-type terminal well layer can be provided over almost the entire area of the pad region 40, and IGBT cells and diode cells can be provided in the pad region 40.

[0045] The control pad 41 includes, for example, at least any one of a current sensing pad 41a, a Kelvin emitter pad 41b, a gate pad 41c, and temperature sensing diode pads 41d and 41e. In addition, in this specification, for example, at least any one of A, B, C... and Z refers to any one of all combinations in which one or more are extracted from the group of A, B, C... and Z.

[0046] The current sensing pad 41a is a control pad for detecting the current flowing in the cell region of the semiconductor device 100. The current sensing pad 41a is electrically connected to the cell region so that when a current flows in the cell region of the semiconductor device 100, a current that is one fraction to one ten-thousandth of the current flowing through the entire cell region flows to an IGBT cell or a diode cell in a part of the cell region.

[0047] The Kelvin emitter pad 41b and the gate pad 41c are control pads to which a gate drive voltage for controlling the on / off of the semiconductor device 100 is applied. The Kelvin emitter pad 41b is electrically connected to the p-type base layer of the IGBT cell. The gate pad 41c is electrically connected to the gate trench electrode of the IGBT cell. The Kelvin emitter pad 41b and the p-type base layer may also be electrically connected via a p + type contact layer. The temperature sensing diode pads 41d and 41e are control pads electrically connected to the anode and cathode of the temperature sensing diode provided in the semiconductor device 100. The voltage between the anode and cathode of the temperature sensing diode (not shown) provided in the cell region is measured via the temperature sensing diode pads 41d and 41e, and the temperature of the semiconductor device 100 is measured based on this voltage.

[0048] <Overall planar structure of island type>

[0049] Figure 2 In this case, the semiconductor device 100 includes an IGBT region 10 and a diode region 20 in one semiconductor device. A plurality of diode regions 20 are arranged and configured in the longitudinal and transverse directions within the semiconductor device 100, and the periphery of the diode region 20 is surrounded by the IGBT region 10. In other words, a plurality of diode regions 20 are provided in an island shape within the IGBT region 10. Figure 2 In this case, a structure is shown in which the diode regions 20 are arranged in a matrix of 4 columns in the left-right direction and 2 rows in the up-down direction on the paper surface. However, the number and arrangement of the diode regions 20 are not limited to this, and a structure in which one or more diode regions 20 are dispersedly provided within the IGBT region 10 and the periphery of each diode region 20 is surrounded by the IGBT region 10 may be adopted.

[0050] As Figure 2As shown, a pad region 40 is disposed adjacent to the lower side of the paper surface of the IGBT region 10. The pad region 40 is a region where control pads 41 for controlling the semiconductor device 100 are provided. In the description herein, the IGBT region 10 and the diode region 20 are also collectively referred to as a cell region. Around the region where the cell region and the pad region 40 are combined, a terminal region 30 is provided to maintain the breakdown voltage of the semiconductor device 100. A known breakdown voltage maintaining structure can also be appropriately provided in the terminal region 30. In the breakdown voltage maintaining structure, for example, on the surface side of the semiconductor device 100, an FLR that surrounds the region where the cell region and the pad region 40 are combined by a p-type terminal well layer of a p-type semiconductor, and a VLD that surrounds the cell region by a p-type well layer with a concentration gradient can be provided. In addition, the number of circular p-type terminal well layers for the FLR and the concentration distribution for the VLD can be appropriately selected according to the breakdown voltage design of the semiconductor device 100. In addition, a p-type terminal well layer can be provided over almost the entire area of the pad region 40, and IGBT cells and diode cells can be provided in the pad region 40.

[0051] The control pad 41 includes, for example, at least any one of a current sensing pad 41a, a Kelvin emitter pad 41b, a gate pad 41c, and temperature sensing diode pads 41d, 41e.

[0052] The current sensing pad 41a is a control pad for detecting the current flowing in the cell region of the semiconductor device 100. The current sensing pad 41a is electrically connected to the cell region such that when a current flows in the cell region of the semiconductor device 100, a current that is one fraction to one ten-thousandth of the current flowing through the entire cell region flows to an IGBT cell or a diode cell in a part of the cell region.

[0053] The Kelvin emitter pad 41b and the gate pad 41c are control pads to which a gate drive voltage for controlling the on / off of the semiconductor device 100 is applied. The Kelvin emitter pad 41b is electrically connected to the p-type base layer and the n + -type source layer of the IGBT cell. The gate pad 41c is electrically connected to the gate trench electrode of the IGBT cell. The Kelvin emitter pad 41b and the p-type base layer can also be electrically connected via a p + -type contact layer. The temperature sensing diode pads 41d, 41e are control pads electrically connected to the anode and the cathode of the temperature sensing diode provided in the semiconductor device 100. The voltage between the anode and the cathode of the temperature sensing diode (not shown) provided in the cell region is measured via the temperature sensing diode pads 41d, 41e, and the temperature of the semiconductor device 100 is measured based on this voltage.

[0054] <IGBT Region 10>

[0055] Figure 3 is a partially enlarged top view showing the structure of the IGBT region 10 of a semiconductor device as an RC-IGBT. Specifically, Figure 3 is a view showing an enlarged area surrounded by the dashed line 82 in the semiconductor device 100 shown by Figure 1 and Figure 2

[0056] In addition, Figure 4 and Figure 5 are cross-sectional views showing the structure of the IGBT region 10 of a semiconductor device as an RC-IGBT. Specifically, Figure 4 is Figure 3 a cross-sectional view taken along the single-dot chain line A-A of the semiconductor device 100 shown by Figure 5 and Figure 3 is a cross-sectional view taken along the single-dot chain line B-B of the semiconductor device 100 shown by

[0057] As shown in Figure 3 Figure 1 in the semiconductor device 100, the active trench gate 11 and the dummy trench gate 12 are provided in a striped pattern in the IGBT region 10. In the semiconductor device 100 of Figure 2 the active trench gate 11 and the dummy trench gate 12 extend along the length direction of the IGBT region 10, and the length direction of the IGBT region 10 corresponds to the length direction of the active trench gate 11 and the dummy trench gate 12. On the other hand, in the semiconductor device 100 of

[0058] there is no particular distinction between the length direction and the width direction in the IGBT region 10, and the left-right direction of the drawing paper can also correspond to the length direction of the active trench gate 11 and the dummy trench gate 12, and the up-down direction of the drawing paper can also correspond to the length direction of the active trench gate 11 and the dummy trench gate 12.

[0058] The active trench gate 11 is formed by providing a gate trench electrode 11a in a trench of the semiconductor substrate via a gate trench insulating film 11b. The dummy trench gate 12 is formed by providing a dummy trench electrode 12a in a trench of the semiconductor substrate via a dummy trench insulating film 12b. The gate trench electrode 11a of the active trench gate 11 is electrically connected to the Figure 1 and Figure 2 gate pads 41c. The dummy trench electrode 12a of the dummy trench gate 12 is electrically connected to an emitter electrode provided on the surface of the semiconductor device 100.

[0059] As shown in Figure 3 + type source layer 13 is provided in contact with the gate trench insulating film 11b on both sides in the width direction of the active trench gate 11. n +The n-type source layer 13 is also referred to as an n + + type emitter layer according to the semiconductor device. The n + + type source layer 13 is a semiconductor layer having an n-type impurity such as arsenic or phosphorus, and the concentration of the n-type impurity is, for example, 1.0E+17 / cm 3 3 to 1.0E+20 / cm 3 3 . The n + + type source layer 13 is alternately arranged with the p + + type contact layer 14 along the extending direction of the active trench gate 11. In addition, the p + + type contact layer 14 is arranged in contact with the dummy trench insulating film 12b between two adjacent dummy trench gates 12. The p + + type contact layer 14 is a semiconductor layer having a p-type impurity such as boron or aluminum, and the concentration of the p-type impurity is, for example, 1.0E+15 / cm 3 3 to 1.0E+20 / cm 3 3 .

[0060] As Figure 3 shown, in the IGBT region 10 of the semiconductor device 100, three dummy trench gates 12 are arranged beside three active trench gates 11 arranged. Moreover, it is configured that beside the three dummy trench gates 12 arranged, three active trench gates 11 different from the above three active trench gates 11 are arranged. The IGBT region 10 is configured to alternately arrange a group of active trench gates 11 and a group of dummy trench gates 12 like this. Figure 3 In, the number of active trench gates 11 included in a group of one active trench gate 11 is three, but it may be 1 or more. In addition, the number of dummy trench gates 12 included in a group of one dummy trench gate 12 may also be 1 or more, and the number of dummy trench gates 12 may also be 0. That is, it may also be that all the trench gates provided in the IGBT region 10 are active trench gates 11.

[0061] Figure 4 is a cross-sectional view taken along the dash-dot line A-A in Figure 3 of the semiconductor device 100, and is a cross-sectional view of the IGBT region 10. The semiconductor device 100 has an n - - type drift layer 1 formed of a semiconductor substrate. The n - - type drift layer 1 is a semiconductor layer having an n-type impurity such as arsenic or phosphorus, and the concentration of the n-type impurity is, for example, 1.0E+12 / cm 3 3 to 1.0E+15 / cm 3 3 . In addition, the concentration of the n-type impurity in the above n + + type source layer 13 is higher than the concentration of the n-type impurity in the n - - type drift layer 1.

[0062] Figure 4 In this case, the semiconductor substrate ranges from the n + -type source layer 13 and the p + -type contact layer 14 to the p-type collector layer 16. The p-type collector layer 16 is also referred to as a p-type drain layer depending on the semiconductor device. Figure 4 In this case, the upper end of the paper surface of the n + -type source layer 13 and the p + -type contact layer 14 is referred to as the surface of the semiconductor substrate, and the lower end of the paper surface of the p-type collector layer 16 is referred to as the back surface of the semiconductor substrate. The semiconductor device 100 has an n - -type drift layer 1 in the IGBT region 10 of the cell region and between the surface and the back surface on the opposite side of the surface. In addition, the semiconductor substrate may be constituted by including at least any one of, for example, a wafer and an epitaxial growth layer. In addition, the semiconductor substrate may include a wide bandgap semiconductor (silicon carbide (SiC), gallium nitride (GaN), diamond) capable of stable operation at high temperatures.

[0063] As Figure 4 shown, in the IGBT region 10, an n-type carrier accumulation layer 2 having a higher concentration of n-type impurities than the n - -type drift layer 1 is provided on the surface side of the n-type drift layer 1. The n-type carrier accumulation layer 2 is a semiconductor layer having, as n-type impurities, for example, arsenic or phosphorus, and the concentration of the n-type impurities is, for example, 1.0E+13 / cm - to 1.0E+17 / cm 3 . In addition, the semiconductor device 100 may be a structure in which the n-type carrier accumulation layer 2 is not provided, but the n 3 . By providing the n-type carrier accumulation layer 2, the conduction loss when current flows in the IGBT region 10 can be reduced. The n-type carrier accumulation layer 2 and the n Figure 4 shown n-type carrier accumulation layer 2 region may also be provided with an n - -type drift layer 1. The n-type carrier accumulation layer 2 and the n - -type drift layer 1 may be collectively referred to as a drift layer.

[0064] The n-type carrier accumulation layer 2 is formed by ion-implanting n-type impurities into the semiconductor substrate constituting the n - -type drift layer 1 and then diffusing the implanted n-type impurities into the semiconductor substrate serving as the n - -type drift layer 1 by annealing.

[0065] A p-type base layer 15 is provided on the surface side of the n-type carrier accumulation layer 2. In Figure 4 this example, the p-type base layer 15 is selectively indirectly provided through the n-type carrier accumulation layer 2 on the n -on the p-type drift layer 1, but may also be selectively provided directly on the n - -type drift layer 1. The p-type base layer 15 is a semiconductor layer having a p-type impurity such as boron or aluminum, and the concentration of the p-type impurity is, for example, 1.0E+12 / cm 3 to 1.0E+19 / cm 3 . The p-type base layer 15 is in contact with the gate trench insulating film 11b of the active trench gate 11. Figure 4 In the example of, the p-type base layer 15 is also in contact with the dummy trench insulating film 12b of the dummy trench gate 12.

[0066] In a region of a part of the surface side of the p-type base layer 15, an n + -type source layer 13 in contact with the gate trench insulating film 11b of the active trench gate 11 is selectively provided, and a p + -type contact layer 14 is selectively provided in the remaining region of the surface side of the p-type base layer 15. The n + -type source layer 13 and the p + -type contact layer 14 constitute the surface of the semiconductor substrate. In addition, the p + -type contact layer 14 is a region where the concentration of the p-type impurity is higher than that of the p-type base layer 15. When it is necessary to distinguish between the p + -type contact layer 14 and the p-type base layer 15, they may also be called separately and independently. When it is not necessary to distinguish, the p + -type contact layer 14 and the p-type base layer 15 may be collectively referred to as the p-type base layer.

[0067] In addition, on the back side of the n - -type drift layer 1 of the semiconductor device 100, an n-type buffer layer 3 having a higher concentration of n-type impurities than that of the n - -type drift layer 1 is provided. The n-type buffer layer 3 is provided to suppress the breakdown of the depletion layer extending from the p-type base layer 15 to the back side when the semiconductor device 100 is in the off state. The n-type buffer layer 3 may be formed, for example, by implanting phosphorus (P) or protons (H + ), or may be formed by implanting both phosphorus (P) and protons (H + ). The concentration of the n-type impurity in the n-type buffer layer 3 is, for example, 1.0E+12 / cm 3 to 1.0E+18 / cm 3 . In addition, the semiconductor device 100 may be a structure in which the n-type buffer layer 3 is not provided, but an n Figure 4 -type drift layer 1 is provided in the region of the n-type buffer layer 3 shown in - . The n-type buffer layer 3 and the n - -type drift layer 1 may also be collectively referred to as the drift layer.

[0068] On the back side of the n-type buffer layer 3 of the semiconductor device 100, a p-type collector layer 16 is provided. That is, the p-type collector layer 16 is provided between the n-type drift layer 1 and the back surface. The p-type collector layer 16 is a semiconductor layer having a p-type impurity such as boron or aluminum, and the concentration of the p-type impurity is, for example, 1.0E+16 / cm - to 1.0E+20 / cm 3 3 . The p-type collector layer 16 forms the back surface of the semiconductor substrate. It is also possible that the p-type collector layer 16 is provided not only in the IGBT region 10 but also in the terminal region 30 as a p-type terminal collector layer 16a described later. In addition, a part of the p-type collector layer 16 may extend from the IGBT region 10 to the diode region 20 and be provided.

[0069] As Figure 4 shown, in the IGBT region 10 of the semiconductor device 100, trenches are provided that penetrate the p-type base layer 15 from the surface of the semiconductor substrate and reach the n - -type drift layer 1. By providing gate trench electrodes 11a in a plurality of trenches via a gate trench insulating film 11b, an active trench gate 11 is formed. The gate trench electrode 11a faces the n - -type drift layer 1 via the gate trench insulating film 11b. In addition, by providing dummy trench electrodes 12a in a plurality of trenches via a dummy trench insulating film 12b, a dummy trench gate 12 is formed. The dummy trench electrode 12a faces the n - -type drift layer 1 via the dummy trench insulating film 12b.

[0070] The gate trench insulating film 11b of the active trench gate 11 is in contact with the p-type base layer 15 and the n + -type source layer 13. When a gate drive voltage is applied to the gate trench electrode 11a, a channel is formed in the p-type base layer 15 in contact with the gate trench insulating film 11b of the active trench gate 11.

[0071] As Figure 4 shown, an interlayer insulating film 4 is provided on the gate trench electrode 11a of the active trench gate 11. A barrier metal 5 is provided on the region of the surface of the semiconductor substrate where the interlayer insulating film 4 is not provided and on the interlayer insulating film 4. The barrier metal 5 may be, for example, a conductor containing titanium (Ti), specifically, it may be titanium nitride, or it may be TiSi in which titanium and silicon (Si) are alloyed. As Figure 4 shown, the barrier metal 5 makes an ohmic contact with the n + -type source layer 13, the p + -type contact layer 14, and the dummy trench electrode 12a, and makes an ohmic contact with the n + -type source layer 13, the p + ​The type contact layer 14 and the dummy trench electrode 12a are electrically connected. On the other hand, the barrier metal 5 is electrically insulated from the gate trench electrode 11a through the interlayer insulating film 4.

[0072] An electrode containing aluminum, i.e., the emitter electrode 6, is provided on the barrier metal 5. The emitter electrode 6 can also be formed of an aluminum alloy such as an aluminum-silicon alloy (Al-Si based alloy), or can be an electrode composed of a multilayer metal film having a plating film formed thereon by electroless plating or electroplating on an electrode formed of an aluminum alloy. The plating film formed by electroless plating or electroplating can be, for example, a nickel (Ni) plating film. Additionally, the barrier metal 5 may not be provided, and the emitter electrode 6 may be provided on the n + -type source layer 13, p + -type contact layer 14, and the dummy trench electrode 12a. Additionally, the emitter electrode 6 may be provided only on the n + -type source layer 13 and other n-type semiconductor layers. The barrier metal 5 and the emitter electrode 6 may also be collectively referred to as the emitter electrode.

[0073] In addition, Figure 4 shows a structure in which the interlayer insulating film 4 is not provided on the dummy trench electrode 12a of the dummy trench gate 12, but in Figure 4 the cross-sectional portion, the interlayer insulating film 4 may be provided on the dummy trench electrode 12a of the dummy trench gate 12. In Figure 4 the cross-sectional portion where the interlayer insulating film 4 is provided on the dummy trench electrode 12a of the dummy trench gate 12, in other cross-sectional portions, the emitter electrode 6 may be electrically connected to the dummy trench electrode 12a.

[0074] A collector electrode 7 is provided on the back side of the p-type collector layer 16. The collector electrode 7 can also be composed of an aluminum alloy or a multilayer of an aluminum alloy and a plating film, similar to the emitter electrode 6. The collector electrode 7 can also have a structure different from that of the emitter electrode 6. The collector electrode 7 makes an ohmic contact with the p-type collector layer 16 and is electrically connected to the p-type collector layer 16.

[0075] Figure 5 is a cross-sectional view taken along the dash-dot line B-B in Figure 3 of the semiconductor device 100 and is a cross-sectional view of the IGBT region 10. Different from the cross-sectional portion taken along the dash-dot line A-A shown in Figure 4 , for Figure 5 the cross-sectional portion taken along the dash-dot line B-B, there is no n + -type source layer 13 that contacts the active trench gate 11 and is provided on the surface side of the semiconductor substrate. In other words, Figure 3 the n +The type source layer 13 is selectively provided on the surface side of the p-type base layer. Additionally, the p-type base layer mentioned here may also include the p-type base layer 15 and the p + type contact layer 14.

[0076] <Diode region 20>

[0077] Figure 6 It is a partial enlarged top view showing the structure of the diode region 20 of the semiconductor device as an RC-IGBT. Specifically, Figure 6 it is a diagram showing an enlarged view of the region surrounded by the dashed line 83 of the semiconductor device 100 shown by Figure 1 and Figure 2 .

[0078] Additionally, Figure 7 and Figure 8 are cross-sectional views showing the structure of the diode region 20 of the semiconductor device as an RC-IGBT. Specifically, Figure 7 it is Figure 6 a cross-sectional view taken along the single dotted line C-C of the semiconductor device 100 shown by Figure 8 and is Figure 6 a cross-sectional view taken along the single dotted line D-D of the semiconductor device 100 shown by

[0079] The diode trench gate 21 extends along the surface of the semiconductor device 100 from one end side of the diode region 20 in the cell region toward the opposite end side. The diode trench gate 21 is constituted by disposing a diode trench electrode 21a in the trench of the diode region 20 via a diode trench insulating film 21b. The diode trench electrode 21a faces the n - type drift layer 1 via the diode trench insulating film 21b.

[0080] A p + type contact layer 24a and a p-type anode layer 25 having a lower concentration of p-type impurities than that are provided between two adjacent diode trench gates 21. The p + type contact layer 24a is a semiconductor layer having, as p-type impurities, for example, boron or aluminum, and the concentration of the p-type impurities is, for example, 1.0E+15 / cm 3 to 1.0E+20 / cm 3 . The p-type anode layer 25 is a semiconductor layer having, as p-type impurities, for example, boron or aluminum, and the concentration of the p-type impurities is, for example, 1.0E+12 / cm 3 to 1.0E+19 / cm 3 . The p + type contact layer 24a and the p-type anode layer 25 are alternately provided in the length direction of the diode trench gate 21.

[0081] Figure 7is a cross-sectional view taken along the dash-dot line C-C in Figure 6 and is a cross-sectional view of the diode region 20. The semiconductor device 100 also has an n-type drift layer 1 made of a semiconductor substrate in the diode region 20 in the same manner as in the IGBT region 10. - The n-type drift layer 1 of the diode region 20 - is continuously and integrally formed with the n-type drift layer 1 of the IGBT region 10 and is formed on the same semiconductor substrate. -

[0082] Figure 7 In + the range of the semiconductor substrate extends from the p-type contact layer 24a to the n-type cathode layer 26. + Figure 7 In + the upper end of the p-type contact layer 24a on the paper surface is referred to as the surface of the semiconductor substrate, and the lower end of the n-type cathode layer 26 on the paper surface is referred to as the back surface of the semiconductor substrate. The surface of the diode region 20 and the surface of the IGBT region 10 are included in the same plane, and the back surface of the diode region 20 and the back surface of the IGBT region 10 are included in the same plane. +

[0083] As Figure 7 shown, in the diode region 20, similar to the IGBT region 10, an n-type carrier accumulation layer 2 is provided on the surface side of the n-type drift layer 1, and an n-type buffer layer 3 is provided on the back surface side of the n-type drift layer 1. The n-type carrier accumulation layer 2 and the n-type buffer layer 3 provided in the diode region 20 may have the same structure as the n-type carrier accumulation layer 2 and the n-type buffer layer 3 provided in the IGBT region 10. In addition, it is not necessarily required to provide the n-type carrier accumulation layer 2 in the IGBT region 10 and the diode region 20. For example, there may be a structure in which the n-type carrier accumulation layer 2 is provided in the IGBT region 10 but not in the diode region 20. In addition, similar to the IGBT region 10, the n-type drift layer 1, the n-type carrier accumulation layer 2, and the n-type buffer layer 3 may be collectively referred to as the drift layer. - - -

[0084] A p-type anode layer 25 is provided on the surface side of the n-type carrier accumulation layer 2. Figure 7 In the example of - the p-type anode layer 25 is selectively indirectly provided on the n-type drift layer 1 through the n-type carrier accumulation layer 2, but it may also be selectively directly provided on the n-type drift layer 1. The p-type anode layer 25 is provided on the n-type drift layer 1 - -Between the type drift layer 1 and the surface. It is also possible to form the p-type anode layer 25 and the p-type base layer 15 simultaneously by making the concentration of the p-type impurities in the p-type anode layer 25 the same as the concentration of the p-type impurities in the p-type base layer 15 of the IGBT region 10. Additionally, it is also possible to configure such that the concentration of the p-type impurities in the p-type anode layer 25 is lower than the concentration of the p-type impurities in the p-type base layer 15 of the IGBT region 10, thereby reducing the amount of holes injected into the diode region 20 during diode operation. By reducing the amount of injected holes during diode operation, the recovery loss during diode operation can be reduced.

[0085] On the surface side of the p-type anode layer 25, a p-type contact layer 24a serving as a first contact layer is provided. + type contact layer 24a. + The p-type contact layer 24a is provided on at least a part of the p-type anode layer 25. + The concentration of the p-type impurities in the p-type contact layer 24a may be the same as or different from the concentration of the p-type impurities in the p-type contact layer 14 of the IGBT region 10. + type contact layer 14. + The p-type contact layer 24a constitutes the surface of the semiconductor substrate. Additionally, + the p-type contact layer 24a is a region where the concentration of the p-type impurities is higher than that of the p-type anode layer 25. When it is necessary to distinguish between the p-type contact layer 24a and the p-type anode layer 25, they can be separately referred to, and when there is no need to distinguish, the p-type contact layer 24a and the p-type anode layer 25 can be collectively referred to as the p-type anode layer. + type contact layer 24a and the p-type anode layer 25, they can be separately referred to, and when there is no need to distinguish, the p-type contact layer 24a and the p-type anode layer 25 can be collectively referred to as the p-type anode layer. + type contact layer 24a and the p-type anode layer 25 are collectively referred to as the p-type anode layer.

[0086] On the back side of the n-type buffer layer 3 of the semiconductor device 100, an n-type cathode layer 26 is provided. That is, + type cathode layer 26 is provided. + The n-type cathode layer 26 is provided between the n-type drift layer 1 and the back surface. - type drift layer 1 and the back surface. + The n-type cathode layer 26 is a semiconductor layer having an n-type impurity such as arsenic or phosphorus, and the concentration of the n-type impurity is, for example, 1.0E+16 / cm 3 ~1.0E+21 / cm 3 . + The n-type cathode layer 26 is provided on a part or all of the diode region 20. + The n-type cathode layer 26 constitutes the back surface of the semiconductor substrate. Additionally, although not shown, it is also possible to selectively inject p-type impurities into a part of the region where the n-type cathode layer 26 is formed to provide a p-type cathode layer as a p-type semiconductor. + type cathode layer 26 is formed to provide a p-type cathode layer as a p-type semiconductor.

[0087] As Figure 7As shown, in the diode region 20 of the semiconductor device 100, there is a trench that penetrates the p-type anode layer 25 from the surface of the semiconductor substrate and reaches the n - -type drift layer 1. By disposing a diode trench electrode 21a in the trench of the diode region 20 via a diode trench insulating film 21b, a diode trench gate 21 is formed. The diode trench electrode 21a faces the n - -type drift layer 1 via the diode trench insulating film 21b.

[0088] As Figure 7 shown, a first silicon burr 52 containing oxygen is disposed between the p-type anode layer 25 and the emitter electrode 6. Figure 7 In the example of, the first silicon burr 52 is disposed in contact with the p + -type contact layer 24a and the emitter electrode 6. In addition, a silicon layer 51 containing oxygen is disposed between the p-type anode layer 25 and the emitter electrode 6. Figure 7 In the example of, it is disposed above the diode trench electrode 21a and the p + -type contact layer 24a. The first silicon burr 52 penetrates the silicon layer 51 in the thickness direction of the silicon layer 51 and protrudes toward the emitter electrode 6.

[0089] Above the p-type anode layer 25 and above the silicon layer 51, an emitter electrode 6 is disposed. The emitter electrode 6 disposed in the diode region 20 and the emitter electrode 6 disposed in the IGBT region 10 are formed continuously. Alternatively, the silicon layer 51 may not be provided, and the diode trench electrode 21a and the p + -type contact layer 24a may be in ohmic contact with the emitter electrode 6.

[0090] In addition, Figure 7 shows a structure in which an interlayer insulating film 4 is not provided above the diode trench electrode 21a of the diode trench gate 21, but in Figure 4 the cross-sectional portion of, the interlayer insulating film 4 may be provided above the diode trench electrode 21a. In Figure 7 the cross-sectional portion of, when the interlayer insulating film 4 is provided above the diode trench electrode 21a of the diode trench gate 21, in other cross-sectional portions, the emitter electrode 6 may be electrically connected to the diode trench electrode 21a. Figure 7

[0091] A collector electrode 7 is disposed on the back side of the n + -type cathode layer 26. Similar to the emitter electrode 6, the collector electrode 7 in the diode region 20 and the collector electrode 7 in the IGBT region 10 are formed continuously. The collector electrode 7 is in ohmic contact with the n + -type cathode layer 26 and is electrically connected to the n + -type cathode layer 26. +

[0092] Figure 8 is a cross-sectional view taken along the dash-dot line D-D in Figure 6 and is a cross-sectional view of the diode region 20. Different from the cross-sectional portion along the dash-dot line C-C shown in Figure 7 , in the cross-sectional portion along the dash-dot line D-D in Figure 8 , a p + -type contact layer 24a is not provided between the p-type anode layer 25 and the silicon layer 51, and the p-type anode layer 25 is the surface of the semiconductor substrate. In other words, Figure 7 the p + -type contact layer 24a shown in

[0093] <Structure of the boundary region between the IGBT region 10 and the diode region 20>

[0094] Figure 9 is a cross-sectional view showing the structure of the boundary region between the IGBT region 10 and the diode region 20 of a semiconductor device as an RC-IGBT. Specifically, Figure 9 is Figure 1 and Figure 2 a cross-sectional view taken along the dash-dot line E-E in the semiconductor device 100 shown in

[0095] As shown in Figure 9 , the p-type collector layer 16 provided on the back side of the IGBT region 10 and the n + -type cathode layer 26 provided on the back side of the diode region 20 are adjacent in the in-plane direction of the semiconductor substrate. Moreover, the p-type collector layer 16 is provided so as to extend from the boundary between the IGBT region 10 and the diode region 20 only by a distance U1 to the diode region 20 side.

[0096] In this way, by providing the p-type collector layer 16 to extend into the diode region 20, the distance between the n + -type cathode layer 26 in the diode region 20 and the active trench gate 11 can be increased. Therefore, even when a gate drive voltage is applied to the gate trench electrode 11a during the operation of the freewheeling diode, current flowing from the channel formed adjacent to the active trench gate 11 in the IGBT region 10 to the n + -type cathode layer 26 can be suppressed. The distance U1 can be, for example, 100 μm. In addition, depending on the use of the semiconductor device 100 as an RC-IGBT, the distance U1 can also be zero or a distance smaller than 100 μm.

[0097] As shown in Figure 9As shown, a first silicon burr 52 and a silicon layer 51 are also provided in the boundary region. The first silicon burr 52 penetrates the silicon layer 51 in the thickness direction of the silicon layer 51 and protrudes toward the emitter electrode 6.

[0098] <Terminal Region 30>

[0099] Figure 10 and Figure 11 is a cross-sectional view showing the structure of the terminal region of the semiconductor device 100 as an RC-IGBT. Specifically, Figure 10 is Figure 1 and Figure 2 a cross-sectional view taken along the single dotted line F-F shown, and is a cross-sectional view from the IGBT region 10 to the terminal region 30. Additionally, Figure 11 is Figure 1 a cross-sectional view taken along the single dotted line G-G shown, and is a cross-sectional view from the diode region 20 to the terminal region 30.

[0100] As Figure 10 and Figure 11 shown, the terminal region 30 of the semiconductor device 100 has an n - -type drift layer 1 between the front and back surfaces of the semiconductor substrate. The front and back surfaces of the terminal region 30 are each included in the same plane as the front and back surfaces of the IGBT region 10 and the diode region 20. Additionally, the n - -type drift layer 1 of the terminal region 30 has the same structure as the n - -type drift layer 1 of each of the IGBT region 10 and the diode region 20 and is continuously formed integrally.

[0101] On the surface side of the n - -type drift layer 1, that is, between the front surface of the semiconductor substrate and the n - -type drift layer 1, a p-type terminal well layer 31 is selectively provided. The p-type terminal well layer 31 is a semiconductor layer having a p-type impurity such as boron or aluminum, and the concentration of this p-type impurity is, for example, 1.0E+14 / cm 3 ~1.0E+19 / cm 3 . The p-type terminal well layer 31 is provided so as to surround the cell region including the IGBT region 10 and the diode region 20. The p-type terminal well layer 31 is provided in a plurality of rings, and the number of p-type terminal well layers 31 provided is appropriately selected according to the breakdown voltage design of the semiconductor device 100. Additionally, an n + -type channel stopper layer 32 is provided on the further outer edge side of the p-type terminal well layer 31, and the n + -type channel stopper layer 32 surrounds the p-type terminal well layer 31 in a plan view.

[0102] In the n -A p-type terminal collector layer 16a is provided between the drift layer 1 of the type and the back surface of the semiconductor substrate. The p-type terminal collector layer 16a is continuously and integrally formed with the p-type collector layer 16 of the IGBT region 10 provided in the cell region. Therefore, the p-type collector layer can also be referred to as including the p-type terminal collector layer 16a.

[0103] As Figure 1 In the structure where the semiconductor device 100 shown is provided adjacent to the diode region 20 and the terminal region 30, as Figure 11 shown, the p-type terminal collector layer 16a is provided such that only the end portion on the diode region 20 side extends into the diode region 20 by a distance U2. According to such a structure, the distance between the n + type cathode layer 26 of the diode region 20 and the p-type terminal well layer 31 can be increased, and thus, the situation where the p-type terminal well layer 31 operates as the anode of the diode can be suppressed. The distance U2 can be, for example, 100 μm.

[0104] A collector electrode 7 is provided on the back surface of the semiconductor substrate. The collector electrode 7 is continuously and integrally formed from the cell region including the IGBT region 10 and the diode region 20 to the terminal region 30.

[0105] On the other hand, an emitter electrode 6 continuous from the cell region and a terminal electrode 6a separated from the emitter electrode 6 in structure are provided on the surface of the semiconductor substrate in the terminal region 30. The emitter electrode 6 and the terminal electrode 6a are electrically connected via a semi-insulating film 33. The semi-insulating film 33 can be, for example, sinSiN (semi-insulating Silicon Nitride). The terminal electrode 6a is electrically connected to the p-type terminal well layer 31 and the n + type channel stopper layer 32 via contact holes of the interlayer insulating film 4 provided on the surface of the terminal region 30. In addition, a terminal protective film 34 covering the emitter electrode 6, the terminal electrode 6a, and the semi-insulating film 33 is provided in the terminal region 30. The terminal protective film 34 is, for example, polyimide.

[0106] As Figure 9 shown, a first silicon burr 52 and a silicon layer 51 are also provided in the boundary region. The first silicon burr 52 penetrates the silicon layer 51 in the thickness direction of the silicon layer 51 and protrudes to the emitter electrode 6. In addition, the barrier metal 5 can be the same as the diode region 20 and is not provided in the IGBT region 10 or the like.

[0107] <Manufacturing method of RC-IGBT>

[0108] Figures 12 to 18 is a cross-sectional view showing a manufacturing method of a semiconductor device as an RC-IGBT.Figures 12 to 16 is a diagram showing the process of the structure on the surface side of the boundary region mainly forming the semiconductor device 100 Figure 9 , and Figure 17 and Figure 18 is a diagram showing the process of the structure on the back side of the boundary region mainly forming the semiconductor device 100 Figure 9 .

[0109] First, as shown in (a) of Figure 12 , prepare a semiconductor substrate constituting the n - -type drift layer 1. The semiconductor substrate can also be, for example, an FZ wafer manufactured by the FZ (Floating Zone) method or an MCZ wafer manufactured by the MCZ (Magnetic-field applied Czochralski) method, or an n-type wafer containing n-type impurities. The concentration of the n-type impurities contained in the semiconductor substrate is appropriately selected according to the breakdown voltage of the manufactured semiconductor device. For example, in a semiconductor device with a breakdown voltage of 1200V, the concentration of the n-type impurities is adjusted so that the specific resistance of the n - -type drift layer 1 constituting the semiconductor substrate becomes about 40 to 120 Ω·cm. As shown in (a) of Figure 12 , in the process of preparing the semiconductor substrate, the entire semiconductor substrate becomes the n - -type drift layer 1. By injecting p-type or n-type impurity ions from the surface side or the back side of such a semiconductor substrate and then diffusing them in the semiconductor substrate through heat treatment or the like, a p-type or n-type semiconductor layer is appropriately formed to manufacture the semiconductor device 100

[0110] As shown in (a) of Figure 12 , the semiconductor substrate constituting the n - -type drift layer 1 has regions that become the IGBT region 10 and the diode region 20. In addition, although not shown, regions such as the terminal region 30 are provided around the regions that become the IGBT region 10 and the diode region 20. Hereinafter, the manufacturing method of the structures of the IGBT region 10 and the diode region 20 of the semiconductor device 100 will be mainly described, but for the terminal region 30 and the like of the semiconductor device 100, they can also be manufactured by a known manufacturing method. For example, when forming an FLR having a p-type terminal well layer 31 as a breakdown voltage holding structure in the terminal region 30, p-type impurity ions can be injected before processing the IGBT region 10 and the diode region 20 of the semiconductor device 100 to form the FLR. Or, p-type impurity ions can be injected simultaneously with the ion injection of p-type impurities into the IGBT region 10 or the diode region 20 of the semiconductor device 100 to form the FLR

[0111] Next, asFigure 12 As shown in (b) thereof, an n-type carrier accumulation layer 2 is formed by injecting an n-type impurity such as phosphorus (P) from the surface side of the semiconductor substrate. Further, a p-type base layer 15 and a p-type anode layer 25 are formed by injecting a p-type impurity such as boron (B) from the surface side of the semiconductor substrate. The n-type carrier accumulation layer 2, the p-type base layer 15, and the p-type anode layer 25 are formed by diffusing the impurity ions by heat treatment after injecting the impurity ions into the semiconductor substrate. Since the ion implantation of the n-type impurity and the p-type impurity is performed after a mask treatment is performed on the surface of the semiconductor substrate, various layers are selectively formed on the surface side of the semiconductor substrate. The n-type carrier accumulation layer 2, the p-type base layer 15, and the p-type anode layer 25 are formed in the IGBT region 10 and the diode region 20, and are connected to the p-type terminal well layer 31 in the terminal region 30.

[0112] The mask treatment is a process of forming a mask on the semiconductor substrate by applying a resist on the semiconductor substrate, forming an opening in a predetermined region of the resist using photolithography technology, performing ion implantation or etching through the opening in a predetermined region of the semiconductor substrate. Through the above mask treatment and ion implantation, the n-type carrier accumulation layer 2, the p-type base layer 15, and the p-type anode layer 25 are selectively formed on the surface side of the IGBT region 10 and the diode region 20. Similarly, the p-type terminal well layer 31 is selectively formed in the terminal region 30.

[0113] The p-type impurities of the p-type base layer 15 and the p-type anode layer 25 may also be ion implanted simultaneously. In this case, the depths and the p-type impurity concentrations of the p-type base layer 15 and the p-type anode layer 25 are the same as each other. Further, the depths and the p-type impurity concentrations of the p-type base layer 15 and the p-type anode layer 25 may be made different from each other by ion implanting the p-type impurities of the p-type base layer 15 and the p-type anode layer 25 separately using a mask treatment.

[0114] Figure 12 The p-type impurities of the p-type terminal well layer 31 and the p-type anode layer 25 in the terminal region 30 not shown in (b) thereof may also be ion implanted simultaneously. In this case, the depths and the p-type impurity concentrations of the p-type terminal well layer 31 and the p-type anode layer 25 are the same as each other. Or, the depths and the p-type impurity concentrations of the p-type terminal well layer 31 and the p-type anode layer 25 may be made different from each other by ion implanting the p-type impurities of the p-type terminal well layer 31 and the p-type anode layer 25 separately using a mask treatment. Or, the p-type impurity concentrations of the p-type terminal well layer 31 and the p-type anode layer 25 can also be made different from each other by simultaneously ion implanting the p-type impurities of the p-type terminal well layer 31 and the p-type anode layer 25 using masks with different opening ratios. In this case, either one or both of the masks may be a grid-shaped mask and the opening ratios of the masks may be made different.

[0115] Similarly, by simultaneously ion-implanting p-type impurities into the p-type terminal well layer 31, the p-type base layer 15, and the p-type anode layer 25 using masks with different opening ratios, the p-type impurity concentrations in the p-type base layer 15 and the p-type anode layer 25 can also be made different from each other. The p-type terminal well layer 31, the p-type base layer 15, and the p-type anode layer 25 can also be formed by simultaneously ion-implanting p-type impurities.

[0116] Next, as shown in (a) of Figure 13 , an n-type source layer 13 is selectively formed on the surface side of the p-type base layer 15 in the IGBT region 10 through mask processing and n-type impurity implantation. The implanted n-type impurity can also be, for example, arsenic (As) or phosphorus (P). Additionally, a p-type contact layer 14 is selectively formed on the surface side of the p-type base layer 15 in the IGBT region 10 through mask processing and p-type impurity implantation, and a p-type contact layer 24a is selectively formed on the surface side of the p-type anode layer 25 in the diode region 20. + The implanted p-type impurity can also be, for example, boron (B) or aluminum (Al), etc. + +

[0117] Next, as shown in (b) of Figure 13 , a trench 8 is formed that penetrates the p-type base layer 15 and the p-type anode layer 25 from the surface side of the semiconductor substrate and reaches the n-type drift layer 1. In the IGBT region 10, the sidewall of the trench 8 that penetrates the n-type source layer 13 includes a part of the n-type source layer 13. In the IGBT region 10, the sidewall of the trench 8 that penetrates the p-type contact layer 14 includes a part of the p-type contact layer 14. In the diode region 20, the sidewall of the trench 8 that penetrates the p-type contact layer 24a includes a part of the p-type contact layer 24a. - + + + + + +

[0118] For example, the trench 8 is formed by depositing an oxide film such as SiO2 on the semiconductor substrate and then using mask processing to form an opening in the oxide film at the part where the trench 8 is to be formed and using the oxide film with the opening as a mask to etch the semiconductor substrate. Figure 13 In (b) of

[0119] Next, as shown in (b) of Figure 14As shown in (a) of the figure, the semiconductor substrate is heated in an oxygen-containing environment to form an oxide film 9 on the inner wall of the trench 8 and the surface of the semiconductor substrate. The oxide film 9 formed in the trench 8 of the IGBT region 10 is the gate trench insulating film 11b of the active trench gate 11 and the dummy trench insulating film 12b of the dummy trench gate 12. In addition, the oxide film 9 formed in the trench 8 of the diode region 20 is the diode trench insulating film 21b. The oxide film 9 formed on the surface of the semiconductor substrate is removed in subsequent processes except for the part formed in the trench 8.

[0120] Next, as shown in Figure 14 (b) of the figure, polysilicon doped with n-type or p-type impurities is deposited on the oxide film 9 in the trench 8 by CVD (chemical vapor deposition) or the like to form a gate trench electrode 11a, a dummy trench electrode 12a, and a diode trench electrode 21a.

[0121] Next, as shown in Figure 15 (a) of the figure, an interlayer insulating film 4 is formed on the gate trench electrode 11a of the active trench gate 11 in the IGBT region 10. The interlayer insulating film 4 can also be SiO2, for example. Through mask processing, a contact hole is formed in the insulating film that becomes the deposited interlayer insulating film 4 and the oxide film 9 formed on the surface of the semiconductor substrate is removed to form Figure 15 (a) of the interlayer insulating film 4 and the like. The contact hole of the interlayer insulating film 4 is formed on the n + -type source layer 13, the p + -type contact layer 14, the p + -type contact layer 24a, the dummy trench electrode 12a, and the diode trench electrode 21a.

[0122] Next, as shown in Figure 15 (b) of the figure, a barrier metal 5 is formed on the surface of the semiconductor substrate in the IGBT region 10 and on the interlayer insulating film 4, and a silicon layer 51 containing oxygen is formed on the surface of the semiconductor substrate in the diode region 20. The barrier metal 5 is formed by depositing titanium nitride using PVD (physical vapor deposition) or CVD. The silicon layer 51 is formed by plasma processing or WET processing in an oxygen-containing environment. The oxygen density of the silicon layer 51 formed in this way is lower than that of the silicon layer formed by thermal diffusion or CVD. The oxygen density of the silicon layer 51 can be adjusted according to the oxygen concentration in the environment during the process and the type of process for forming the silicon layer 51. In addition, the thickness of the silicon layer 51 is preferably less than half of the height of the predetermined first silicon burr 52 formed in the subsequent process.

[0123] Next, by sputtering aluminum silicon (for example, an aluminum silicon alloy), as shown in Figure 16As shown in (a) of [description], a conductive film 6b containing silicon and aluminum is formed on the barrier metal 5 and the silicon layer 51. By adjusting the growth temperature of this sputtering, the conductive film 6b is formed, and a first silicon burr 52 containing oxygen is formed between the p-type anode layer 25 and the conductive film 6b. The higher the growth temperature of the sputtering, the easier it is for the first silicon burr 52 to be generated at the silicon substrate interface, the easier it is for mutual diffusion to occur between the aluminum silicon and the silicon layer 51, and the easier it is to form alloy spikes (in other words, aluminum spikes). Therefore, the growth temperature of the sputtering is appropriately set considering these factors. In addition, mutual diffusion also occurs between the first silicon burr 52 and aluminum. Therefore, the first silicon burr 52 usually contains aluminum and has p-type conductivity.

[0124] In addition, if the flow rate of the sputtering ambient gas (such as argon or hydrogen) is adjusted, the oxygen on the surface of the silicon layer 51 is reduced, and the aluminum silicon of the first silicon burr 52 acquires oxygen. Based on the above, by adjusting the processing temperature and processing environment of the sputtering, the oxygen concentration contained in the first silicon burr 52 can be adjusted.

[0125] In the first embodiment, the first silicon burr 52 penetrates the silicon layer 51 in the thickness direction of the silicon layer 51. However, the silicon layer 51 does not need to remain. For example, it can also be removed as needed after the formation of the first silicon burr 52.

[0126] Next, Figure 16 In (b) of [description], although the specific patterning is not shown, the emitter electrode 6 is formed by patterning the conductive film 6b using etching or the like.

[0127] Next, as Figure 17 shown in (a) of [description], the back side of the semiconductor substrate is ground to thin the semiconductor substrate to a designed predetermined thickness. The thickness of the ground semiconductor substrate can be, for example, 80 μm to 200 μm.

[0128] Next, as Figure 17 shown in (b) of [description], an n-type impurity is implanted from the back side of the semiconductor substrate to form an n-type buffer layer 3. And a p-type impurity is implanted from the back side of the semiconductor substrate to form a p-type collector layer 16. The n-type buffer layer 3 can also be formed in the IGBT region 10, the diode region 20, the terminal region 30, etc., or can be formed only in the IGBT region 10 or the diode region 20. The n-type buffer layer 3 can be formed by implanting, for example, phosphorus (P) ions, or can be implanted with protons (H +)It can also be formed by implanting both protons and phosphorus. Protons can be implanted from the back surface of the semiconductor substrate to a relatively deep position with a relatively low acceleration energy. In addition, by changing the acceleration energy, the depth of the implanted protons can be changed relatively easily. Therefore, when forming the n-type buffer layer 3 using protons, if multiple implantations are performed while changing the acceleration energy, a thicker n-type buffer layer 3 can be formed in the thickness direction of the semiconductor substrate compared to forming it using phosphorus.

[0129] In addition, compared with protons, phosphorus can increase the activation rate as an n-type impurity. Therefore, if the n-type buffer layer 3 is formed using phosphorus, even for a thinned semiconductor substrate, breakdown of the depletion layer can be suppressed. In order to further thin the semiconductor substrate, it is preferable to form the n-type buffer layer 3 by implanting both protons and phosphorus. At this time, protons are implanted to a deeper position from the back surface than phosphorus.

[0130] The p-type collector layer 16 can also be formed by implanting, for example, boron (B). The p-type collector layer 16 is also formed in the terminal region 30, and the p-type collector layer 16 in the terminal region 30 becomes the p-type terminal collector layer 16a. After ion implantation from the back surface side of the semiconductor substrate, the back surface is irradiated with a laser for laser annealing, so that the implanted boron is activated to form the p-type collector layer 16. At this time, the phosphorus implanted to a relatively shallow position from the back surface of the semiconductor substrate is also activated simultaneously. On the other hand, protons are activated at a relatively low annealing temperature such as 350°C to 500°C. Therefore, except for the process for activating protons after the protons are implanted, attention needs to be paid to preventing the entire semiconductor substrate from becoming a temperature higher than 350°C to 500°C. Laser annealing can make only the vicinity of the back surface of the semiconductor substrate become high temperature. Therefore, it can be used for the activation of n-type and p-type impurities even after protons are implanted.

[0131] Next, as shown in (a) of Figure 18 , an n + -type cathode layer 26 is formed on the back surface side of the diode region 20. The n + -type cathode layer 26 can be formed by implanting, for example, arsenic (As) or phosphorus (P). As shown in (a) of Figure 18 , through a mask process, n-type impurities are selectively implanted from the back surface side so that the boundary between the p-type collector layer 16 and the n + -type cathode layer 26 is located at a position at a distance U1 from the boundary between the IGBT region 10 and the diode region 20 toward the diode region 20 side. The implantation amount of the n-type impurities for forming the n + -type cathode layer 26 is larger than the implantation amount of the p-type impurities for forming the p-type collector layer 16. Figure 18 In (a) of + , the depths from the back surface of the p-type collector layer 16 and the n+ The depth of the n-type cathode layer 26 may also be greater than the depth of the p-type collector layer 16. In the region where the n + -type cathode layer 26 is formed, it is necessary to implant an n-type impurity into the region where the p-type impurity has been implanted and finally become n-type. Therefore, in all regions where the n + -type cathode layer 26 is formed, the concentration of the n-type impurity is higher than the concentration of the implanted p-type impurity.

[0132] Next, as shown in Figure 18 (b) of FIG., a collector electrode 7 is formed on the back surface of the semiconductor substrate. The collector electrode 7 is formed over the entire surface of the IGBT region 10, the diode region 20, the terminal region 30, etc. on the back surface. In addition, the collector electrode 7 may be formed over the entire surface of the back surface of the n-type wafer serving as the semiconductor substrate. The collector electrode 7 may also be formed by depositing an aluminum-silicon alloy (Al-Si based alloy), titanium (Ti), etc. by PVD such as sputtering or evaporation, or by laminating multiple metals such as an aluminum-silicon alloy, titanium, nickel, or gold. Alternatively, the collector electrode 7 may be formed by further forming a metal film by electroless plating or electroplating on the metal film formed by PVD.

[0133] The semiconductor device 100 is manufactured through the above-described processes. A plurality of semiconductor devices 100 are manufactured in a state of being integrated in a matrix on a semiconductor substrate such as an n-type wafer. Therefore, the semiconductor devices 100 are individually cut by laser cutting or blade cutting.

[0134] Figure 19 is a flowchart showing the main processes for forming the structure on the surface side of the semiconductor device in the manufacturing method of the semiconductor device described above. In step S1, by performing Figures 12 to 14 and Figure 15 (a) of FIG., a semiconductor substrate including an n - -type drift layer 1 and a p-type anode layer 25 and provided with an interlayer insulating film 4 having contact holes is prepared. In step S2, by performing Figure 15 (b) of FIG., a silicon layer 51 containing oxygen is formed. In step S3, by performing Figure 16 (a) of FIG., in other words, sputtering of aluminum-silicon, a conductive film 6b containing silicon and aluminum is formed, and a first silicon burr 52 containing oxygen is formed. In step S4, by performing Figure 16 (b) of FIG., the conductive film 6b is patterned to form an emitter electrode 6. In addition, the conductive film 6b, in other words, the emitter electrode 6, may be a single-layer film or a multi-layer film. According to the above, the structure on the surface side of the semiconductor device is formed.

[0135] <Summary of Embodiment 1>

[0136] In the semiconductor device of Embodiment 1 as described above, a first silicon burr 52 containing oxygen is provided between the p-type anode layer 25 and the emitter electrode 6. With such a structure, the mutual diffusion of silicon in the p-type anode layer 25 and aluminum in the emitter electrode 6 can be suppressed by the first silicon burr 52. Therefore, the uneven diffusion profile of the p-type anode layer 25 can be suppressed. In addition, by adjusting the oxygen contained in the first silicon burr 52, the resistance value of the first silicon burr 52 can be adjusted. As a result, the resistance between the emitter electrode 6 and the p-type anode layer 25 can be adjusted. In addition, alloy spikes can be suppressed by the first silicon burr 52.

[0137] In addition, in Embodiment 1, the first silicon burr 52 penetrates the silicon layer 51 in the thickness direction of the silicon layer 51. With such a structure, the oxygen contained in the first silicon burr 52 can be easily adjusted through the silicon layer 51, and the resistance between the emitter electrode 6 and the p-type anode layer 25 can be easily adjusted.

[0138] In addition, in Embodiment 1, the first silicon burr 52 protrudes to the emitter electrode 6. With such a structure, the contact area between the first silicon burr 52 and the emitter electrode 6 can be increased. Therefore, the contact resistance can be reduced.

[0139] <Embodiment 2>

[0140] Figure 20 It is a cross-sectional view showing the structure of the boundary region between the IGBT region 10 and the diode region 20 of the semiconductor device of Embodiment 2.

[0141] In Embodiment 2, the plurality of first silicon burrs 52 include first silicon burrs 52a and 52b with different particle sizes. As an example, the particle size of the first silicon burr 52a located at the grain boundary 6c of the emitter electrode 6 is larger than that of the first silicon burr 52b located outside the grain boundary 6c. In addition, the oxygen concentration of the first silicon burr 52a located at the grain boundary 6c of the emitter electrode 6 is higher than that of the first silicon burr 52b located outside the grain boundary 6c.

[0142] In addition, the particle size of the emitter electrode 6 becomes equal to or less than the thickness of the emitter electrode 6. In addition, the emitter electrode 6 may be a single-layer film as in Embodiment 1 or a multi-layer film.

[0143] Next, the manufacturing method will be described. By adjusting Figure 19 the temperature of step S3 (in other words, sputtering for forming the conductive film 6b, etc.), the particle sizes of the plurality of first silicon burrs 52 between the emitter electrode 6 and the p-type anode layer 25 are adjusted to the same degree. In Figure 19After the process of step S3, heat treatment is performed. If the temperature and time of this heat treatment are adjusted, the movement of the first silicon burr 52 along the grain boundary 6c of the emitter electrode 6 is promoted. As a result, the particle size of the first silicon burr 52a located at the grain boundary 6c of the emitter electrode 6 is larger than that of the first silicon burr 52b located outside the grain boundary 6c. In addition, if Figure 19 the processing environment, temperature, and time of the heat treatment after the process of step S3 are adjusted, the movement of the first silicon burr 52 and oxygen along the grain boundary 6c of the emitter electrode 6 is promoted.

[0144] Figure 21 FIG. is a diagram showing the results of analyzing and evaluating the oxygen concentration of the first silicon burrs and the like by EDS (Energy Dispersive X-ray Spectroscopy) in a representative structure using the above manufacturing method of Embodiment 2. In addition, the unit of the numerical value is atm%. As can be seen from the results, according to the above manufacturing method, the oxygen concentration of the first silicon burr 52a located at the grain boundary 6c of the emitter electrode 6 is higher than that of the first silicon burr 52b located outside the grain boundary 6c.

[0145] <Summary of Embodiment 2>

[0146] According to the semiconductor device of Embodiment 2 as described above, since the particle sizes of the plurality of first silicon burrs 52 are different, the resistance between the emitter electrode 6 and the p-type anode layer 25 can be adjusted with high precision.

[0147] In addition, in Embodiment 2, the particle size of the first silicon burr 52a located at the grain boundary 6c of the emitter electrode 6 is larger than that of the first silicon burr 52b located outside the grain boundary 6c. According to such a structure, by adjusting the grain boundary 6c of the emitter electrode 6, the resistance between the emitter electrode 6 and the p-type anode layer 25 can be adjusted.

[0148] In addition, in Embodiment 2, the oxygen concentration of the first silicon burr 52a located at the grain boundary 6c of the emitter electrode 6 is higher than that of the first silicon burr 52b located outside the grain boundary 6c. According to such a structure, by adjusting the grain boundary 6c of the emitter electrode 6, the resistance between the emitter electrode 6 and the p-type anode layer 25 can be adjusted.

[0149] <Embodiment 3>

[0150] Figure 22 FIG. is a cross-sectional view showing the structure of the boundary region between the IGBT region 10 and the diode region 20 of the semiconductor device of Embodiment 3.

[0151] In Embodiment 3, the particle size of the emitter electrode 6 is larger than the thickness of the emitter electrode 6, and the upper parts of a plurality of grain boundaries 6c of the emitter electrode 6 are cut off by the upper surface of the emitter electrode 6. Embodiment 3 is the same as Embodiment 2 except for this point. Such a structure can be achieved by adjusting the temperature and time of step S3 (in other words, sputtering for forming the conductive film 6b, etc.) to adjust the particle size and thickness of the emitter electrode 6. Figure 19 This can be achieved by adjusting the temperature and time of step S3 (in other words, sputtering for forming the conductive film 6b, etc.) to adjust the particle size and thickness of the emitter electrode 6.

[0152] In the semiconductor device according to Embodiment 3, since the particle size of the emitter electrode 6 is larger than the thickness of the emitter electrode 6, the lateral component in the extending direction of the grain boundary 6c can be reduced, and the longitudinal component can be increased. As a result, the movement of the first silicon burr 52 along the grain boundary 6c of the emitter electrode 6 can be promoted, and thus, it is easy to increase the particle size of the first silicon burr 52a located at the grain boundary 6c of the emitter electrode 6.

[0153] <Embodiment 4>

[0154] Figure 23 FIG. is a cross-sectional view showing the structure of the boundary region between the IGBT region 10 and the diode region 20 of the semiconductor device according to Embodiment 4.

[0155] In the semiconductor device described so far, the barrier metal 5 is not provided in the diode region 20. In contrast, in the semiconductor device according to Embodiment 4, instead of the silicon layer 51, the barrier metal 5 that is in ohmic contact with the diode trench electrode 21a and the p + -type contact layer 24a is provided between the p-type anode layer 25 and the emitter electrode 6. Moreover, the first silicon burr 52 penetrates through the barrier metal 5 in the thickness direction of the barrier metal 5.

[0156] Next, the manufacturing method will be described. First, when the barrier metal 5 is formed in the IGBT region 10, the barrier metal 5 is also formed in the diode region 20. Next, an etching process or the like is performed on the barrier metal 5 in the diode region 20 to form a hole reaching the surface of the semiconductor substrate. Then, by performing Figure 19 step S3 (in other words, sputtering for forming the conductive film 6b, etc.), the first silicon burr 52 is formed on the surface of the semiconductor substrate ( Figure 23 in the example of the p + -type contact layer 24a) exposed from the hole of the barrier metal 5.

[0157] In the semiconductor device according to Embodiment 4, the first silicon burr 52 penetrates through the barrier metal 5 in the thickness direction of the barrier metal 5. According to such a structure, even if the barrier metal 5 is provided in the diode region 20, the resistance between the emitter electrode 6 and the p-type anode layer 25 can be adjusted.

[0158] <Embodiment 5>

[0159] Figure 24 It is a cross-sectional view showing the structure of the boundary region between the IGBT region 10 and the diode region 20 of the semiconductor device of this Embodiment 5.

[0160] In this Embodiment 5, similar to Embodiment 1, the diode region 20 including the p-type anode layer 25 that functions as a diode and is provided with the diode trench gate 21 is defined on the semiconductor substrate. Moreover, in this Embodiment 5, in the cross-section along the width direction of the diode trench gate 21, the p + -type contact layer 24a is locally provided on the p-type anode layer 25. In addition, the width direction of the diode trench gate 21 is a direction substantially perpendicular to the extending direction of the diode trench gate 21 (the direction from the Figure 24 near side of the paper surface to the depth side of the paper surface).

[0161] In this Embodiment 5, from the p + -type contact layer 24a, the ratio per unit area of the first silicon burr 52 in the p-type anode layer 25 is larger than the ratio per unit area of the first silicon burr 52 in the p + -type contact layer 24a. In addition, the former ratio is the ratio of the area or number of the first silicon burrs 52 provided between the p-type anode layer 25 exposed from the p + -type contact layer 24a and the emitter electrode 6 to the area of the p-type anode layer 25 in a plan view. The latter ratio is the ratio of the area or number of the first silicon burrs 52 provided between the p + -type contact layer 24a and the emitter electrode 6 to the area of the p + -type contact layer 24a in a plan view.

[0162] In addition, the above structure is formed by adjusting the mask pattern when forming the p + -type contact layer 24a and appropriately selecting the p-type impurities of the p + -type contact layer 24a.

[0163] According to the semiconductor device of this Embodiment 5 as described above, in the cross-section along the width direction of the diode trench gate 21, the p + -type contact layer 24a is locally provided on the p-type anode layer 25. According to such a structure, the resistance between the emitter electrode 6 and the p-type anode layer 25 in the region where the p + -type contact layer 24a is not provided can be adjusted.

[0164] In addition, in this Embodiment 5, from the p +The ratio per unit area of the first silicon burr 52 in the p-type anode layer 25 where the p-type contact layer 24a is exposed is larger than the ratio per unit area of the first silicon burr 52 in the p + -type contact layer 24a. With such a structure, in the region of the p-type anode layer 25 where the p + -type contact layer 24a is not provided, the resistance between the emitter electrode 6 and the p-type anode layer 25 can be reduced.

[0165] <Embodiment 6>

[0166] Figure 25 It is a cross-sectional view showing the structure of the boundary region between the IGBT region 10 and the diode region 20 of the semiconductor device of this Embodiment 6.

[0167] The semiconductor substrate of this Embodiment 6 further includes an n + -type impurity layer 53 locally provided on the p-type anode layer 25. Similar to the p + -type contact layer 24a, Figure 25 for example, the n + -type impurity layer 53 is locally provided on the p-type anode layer 25 in a cross-section along the width direction of the diode trench gate 21. In addition, the n + -type impurity layer 53 may have the same concentration as the n + -type source layer 13, or may have a different concentration from the n + -type source layer 13.

[0168] In this Embodiment 6, the ratio per unit area of the first silicon burr 52 in the n + -type impurity layer 53 is larger than the ratio per unit area of the first silicon burr 52 in the p-type anode layer 25 exposed from the n + -type impurity layer 53. In addition, the former ratio is the ratio of the area or number of the first silicon burr 52 provided between the n + -type impurity layer 53 and the emitter electrode 6 in a plan view to the area of the n + -type impurity layer 53 in a plan view. The latter ratio is the ratio of the area or number of the first silicon burr 52 provided between the p-type anode layer 25 exposed from the n + -type impurity layer 53 and the emitter electrode 6 in a plan view to the area of the p-type anode layer 25 in a plan view. The p-type anode layer 25 exposed from the n + -type impurity layer 53 may include the p + -type contact layer 24, or may not include the p + -type contact layer 24.

[0169] In addition, the above structure adjusts the mask pattern when forming the n + -type impurity layer 53 and appropriately selects the n+ It is formed by the n-type impurities of the type impurity layer 53.

[0170] According to the semiconductor device of the sixth embodiment as described above, the semiconductor substrate further includes an n- + type impurity layer 53 that is locally provided on the p-type anode layer. According to such a structure, it is possible to adjust the resistance between the emitter electrode 6 and the p-type anode layer 25 in the region where the n- + type impurity layer 53 is provided.

[0171] In addition, in the sixth embodiment, the ratio of the first silicon burr 52 per unit area in the n- + type impurity layer 53 is larger than the ratio of the first silicon burr 52 per unit area in the p-type anode layer 25 exposed from the n- + type impurity layer 53. According to such a structure, in the region where the n- + type impurity layer 53 is provided, it is possible to reduce the resistance between the emitter electrode 6 and the p-type anode layer 25.

[0172] <Embodiment 7>

[0173] Figure 26 It is a cross-sectional view showing the structure of the boundary region between the IGBT region 10 and the diode region 20 of the semiconductor device of the seventh embodiment.

[0174] In the seventh embodiment, similar to the first embodiment, a diode region 20 including a p-type anode layer 25 and functioning as a diode and provided with a diode trench gate 21, and an IGBT region 10 functioning as an IGBT and provided with a trench gate are defined on the semiconductor substrate. In addition, the trench gate mentioned here may be an active trench gate 11 or a dummy trench gate 12.

[0175] Here, generally, the first silicon burr 52 is not provided on the diode trench gate 21. Considering this situation, in the semiconductor device of the seventh embodiment, the interval between the diode trench gates 21 is larger than the interval between the trench gates, and the number of the diode trench gates 21 is reduced. According to such a structure, it is possible to increase the number of the first silicon burrs 52 provided in the diode region 20, and thus, it is possible to reduce the resistance between the emitter electrode 6 and the p-type anode layer 25.

[0176] <Embodiment 8>

[0177] Figure 27 It is a cross-sectional view showing the structure of the boundary region between the IGBT region 10 and the diode region 20 of the semiconductor device of the eighth embodiment.

[0178] The semiconductor substrate of the eighth embodiment further includes an n-type Schottky layer 54 Schottky-connected to the emitter electrode 6. Additionally, in Figure 27 , the n-type Schottky layer 54 is directly disposed on the n - -type drift layer 1, but it may also be indirectly disposed on the n - -type drift layer 1. Moreover, in the eighth embodiment, a second silicon burr 55 containing oxygen is disposed between the n-type Schottky layer 54 and the emitter electrode 6.

[0179] According to the semiconductor device of the eighth embodiment thus configured, the characteristics of the Schottky junction can be adjusted by the second silicon burr 55 containing oxygen.

[0180] <Eighth Embodiment 9>

[0181] Figure 28 FIG. is a cross-sectional view showing the structure of a boundary region between the IGBT region 10 and the diode region 20 of the semiconductor device of the ninth embodiment.

[0182] In the description so far, the diode region 20 that includes the p-type anode layer 25 and functions as a diode and is provided with the diode trench gate 21 is defined on the semiconductor substrate. In contrast, in the ninth embodiment, the diode region 20 that includes the p-type anode layer 25 and functions as a diode but is not provided with the diode trench gate 21 is defined on the semiconductor substrate. According to the semiconductor device of the ninth embodiment thus configured, there is no step difference caused by the diode trench gate 21, and thus, the first silicon burr 52 can be stably formed.

[0183] <Eighth Embodiment 10>

[0184] Figure 29 FIG. is a cross-sectional view showing the structure of a boundary region between the IGBT region 10 and the diode region 20 of the semiconductor device of the tenth embodiment.

[0185] In the tenth embodiment, the p-type anode layer 25 is disposed on the n - -type drift layer of the diode region 20, and the p + -type contact layer 24 is not provided. The tenth embodiment is the same as the ninth embodiment except for this point. According to such a structure, similar to the first embodiment, the mutual diffusion of the silicon of the p-type anode layer 25 and the aluminum of the emitter electrode 6 can be suppressed, and alloy spikes can be suppressed by the first silicon burr 52.

[0186] <Eighth Embodiment 11>

[0187] Figure 30 FIG. is a cross-sectional view showing the structure of a boundary region between the IGBT region 10 and the diode region 20 of the semiconductor device of the eleventh embodiment.

[0188] In the present Embodiment 11, similar to Embodiment 1, a diode region 20 including a p-type anode layer 25 and functioning as a diode and an IGBT region 10 functioning as an IGBT are defined on a semiconductor substrate. Moreover, similar to the semiconductor substrate of Embodiment 1, the semiconductor substrate of the present Embodiment 11 includes a p-type base layer 15 as a base layer, an n + -type source layer 13 as an emitter layer, and a p + -type contact layer 14 as a second contact layer.

[0189] In addition, in the present Embodiment 11, similar to Embodiment 1, an emitter electrode 6 is provided above the p-type anode layer 25 and above at least any one of the p-type base layer 15, the n + -type source layer 13, and the p + -type contact layer 14. Moreover, in the present Embodiment 11, a third silicon burr 56 containing oxygen is provided between at least any one of the above layers and the emitter electrode 6. In addition, it is also possible that a third silicon burr 56 is provided in the Figure 4 and Figure 5 IGBT region 10.

[0190] According to the semiconductor device of the present Embodiment 11, the resistance between at least any one of the above layers in the IGBT region 10 and the emitter electrode 6 can be adjusted by the third silicon burr 56 containing oxygen.

[0191] <Variation>

[0192] The semiconductor devices of Embodiments 1 to 6 and 8 to 10 are RC-IGBTs in which an IGBT region 10 and a diode region 20 are defined, but it is also possible to have a single diode having no IGBT region 10 and having a diode region 20. In addition, a silicon layer 51 is provided in some of Embodiments 1 to 11, but it is also possible not to provide the silicon layer 51.

[0193] In addition, the embodiments and the variations can be freely combined or appropriately deformed and omitted.

[0194] Hereinafter, the various aspects of the present disclosure are collectively described as appendices.

[0195] (Appendix 1)

[0196] A semiconductor device, comprising:

[0197] A semiconductor substrate including a drift layer of a first conductivity type and an anode layer of a second conductivity type provided on at least a part of the drift layer;

[0198] An electrode, which is disposed above the anode layer and contains aluminum; and

[0199] A first silicon burr, which is disposed between the anode layer and the electrode and contains oxygen.

[0200] (Supplementary Note 2)

[0201] In the semiconductor device described in Supplementary Note 1, wherein,

[0202] The semiconductor substrate further includes: a first contact layer of the second conductivity type, which is disposed on at least a part of the anode layer and has an impurity concentration of the second conductivity type higher than that of the anode layer.

[0203] (Supplementary Note 3)

[0204] In the semiconductor device described in Supplementary Note 1 or 2, wherein,

[0205] A silicon layer is further provided, which is disposed between the anode layer and the electrode and contains oxygen,

[0206] The first silicon burr penetrates through the silicon layer in the thickness direction of the silicon layer.

[0207] (Supplementary Note 4)

[0208] In the semiconductor device described in any one of Supplementary Notes 1 to 3, wherein,

[0209] The first silicon burr protrudes toward the electrode.

[0210] (Supplementary Note 5)

[0211] In the semiconductor device described in any one of Supplementary Notes 1 to 4, wherein,

[0212] The particle sizes of the plurality of first silicon burrs are different.

[0213] (Supplementary Note 6)

[0214] In the semiconductor device described in any one of Supplementary Notes 1 to 5, wherein,

[0215] The particle size of the first silicon burr located at the grain boundary of the electrode is larger than the particle size of the first silicon burr located outside the grain boundary.

[0216] (Supplementary Note 7)

[0217] In the semiconductor device described in any one of Supplementary Notes 1 to 5, wherein,

[0218] The oxygen concentration of the first silicon burr located at the grain boundary of the electrode is higher than the oxygen concentration of the first silicon burr located outside the grain boundary.

[0219] (Supplementary Note 8)

[0220] In the semiconductor device according to any one of Supplementary Notes 1 to 7, wherein,

[0221] The particle size of the electrode is larger than the thickness of the electrode.

[0222] (Supplementary Note 9)

[0223] In the semiconductor device according to Supplementary Note 1 or 2, wherein,

[0224] A barrier metal is further provided between the anode layer and the electrode,

[0225] The first silicon burr penetrates the barrier metal in the thickness direction of the barrier metal.

[0226] (Supplementary Note 10)

[0227] In the semiconductor device according to any one of Supplementary Notes 2 to 9, wherein,

[0228] A diode region that includes the anode layer and functions as a diode and is provided with a diode trench gate is defined on the semiconductor substrate,

[0229] In a cross-section along the width direction of the diode trench gate, the first contact layer is partially provided on the anode layer.

[0230] (Supplementary Note 11)

[0231] In the semiconductor device according to Supplementary Note 10, wherein,

[0232] The ratio per unit area of the first silicon burr provided between the anode layer exposed from the first contact layer and the electrode is larger than the ratio per unit area of the first silicon burr provided between the first contact layer and the electrode.

[0233] (Supplementary Note 12)

[0234] In the semiconductor device according to any one of Supplementary Notes 1 to 11, wherein,

[0235] The semiconductor substrate further includes an impurity layer of the first conductivity type that is partially provided on the anode layer.

[0236] (Supplementary Note 13)

[0237] In the semiconductor device according to Supplementary Note 12, wherein,

[0238] The ratio per unit area of the first silicon burrs provided between the impurity layer and the electrode is greater than the ratio per unit area of the first silicon burrs provided between the anode layer exposed from the impurity layer and the electrode.

[0239] (Supplementary Note 14)

[0240] In the semiconductor device according to any one of Supplementary Notes 1 to 13, wherein,

[0241] A diode region that includes the anode layer and functions as a diode and is provided with diode trench gates, and an IGBT region that functions as an IGBT and is provided with trench gates are defined on the semiconductor substrate.

[0242] The interval between the diode trench gates is greater than the interval between the trench gates.

[0243] (Supplementary Note 15)

[0244] In the semiconductor device according to any one of Supplementary Notes 1 to 14, wherein,

[0245] The semiconductor substrate further includes: a Schottky layer of the first conductivity type that is selectively provided on the drift layer and is Schottky-connected to the electrode.

[0246] A second silicon burr is further provided, which is provided between the Schottky layer and the electrode and contains oxygen.

[0247] (Supplementary Note 16)

[0248] In the semiconductor device according to any one of Supplementary Notes 1 to 13, wherein,

[0249] A diode region that includes the anode layer and functions as a diode and is not provided with diode trench gates is defined on the semiconductor substrate.

[0250] (Supplementary Note 17)

[0251] In the semiconductor device according to any one of Supplementary Notes 1 to 13, wherein,

[0252] A diode region that includes the anode layer and functions as a diode, and an IGBT region that functions as an IGBT are defined on the semiconductor substrate.

[0253] The semiconductor substrate further includes: a base layer of the second conductivity type that is selectively provided on the drift layer of the IGBT region, and an emitter layer of the first conductivity type and a second contact layer of the second conductivity type having a higher impurity concentration than the base layer, which are selectively provided on the base layer.

[0254] The electrode is disposed above the anode layer and above at least any one of the base layer, the emitter layer, and the second contact layer.

[0255] A third silicon burr is further provided, which is disposed between the at least any one layer and the electrode and contains oxygen.

[0256] (Supplementary Note 18)

[0257] A method for manufacturing a semiconductor device, comprising the following steps:

[0258] A step of preparing a semiconductor substrate, the semiconductor substrate including a drift layer of a first conductivity type and an anode layer of a second conductivity type provided on at least a part of the drift layer;

[0259] A step of forming a silicon layer containing oxygen on the upper surface of the semiconductor substrate;

[0260] A step of forming a conductive film containing silicon and aluminum on the silicon layer and forming a first silicon burr containing oxygen between the anode layer and the conductive film; and

[0261] A step of forming an electrode by patterning the conductive film.

Claims

1. A semiconductor device, characterized in that: have: A semiconductor substrate comprising: a drift layer of a first conductivity type, and an anode layer of a second conductivity type disposed on at least a portion of the drift layer; an electrode disposed above the anode layer and comprising aluminum; and The first silicon burr is disposed between the anode layer and the electrode and contains oxygen.

2. The semiconductor device according to claim 1, wherein: The semiconductor substrate further includes: a first contact layer of the second conductivity type provided on at least a portion of the anode layer and having a higher concentration of impurities of the second conductivity type than that of the anode layer.

3. The semiconductor device according to claim 1 or 2, characterized in that: further comprising a silicon layer disposed between the anode layer and the electrode and containing oxygen, The first silicon burr penetrates the silicon layer in a thickness direction of the silicon layer.

4. The semiconductor device according to any one of claims 1 to 3, wherein: The first silicon burr protrudes toward the electrode.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that The grain sizes of the plurality of first silicon burrs are different.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that A grain size of the first silicon burr located at a grain boundary of the electrode is larger than a grain size of the first silicon burr located outside the grain boundary.

7. The semiconductor device according to any one of claims 1 to 5, characterized in that The oxygen concentration of the first silicon burrs located at the grain boundary of the electrode is greater than the oxygen concentration of the first silicon burrs located outside the grain boundary.

8. The semiconductor device according to any one of claims 1 to 7, wherein: The particle size of the electrode is greater than the thickness of the electrode.

9. The semiconductor device according to claim 1 or 2, characterized in that: further comprising a barrier metal disposed between the anode layer and the electrode, The first silicon burr penetrates the barrier metal in a thickness direction of the barrier metal.

10. The semiconductor device according to any one of claims 2 to 9, characterized in that A diode region including the anode layer and functioning as a diode and provided with a diode trench gate is defined in the semiconductor substrate. In a cross section along a width direction of the diode trench gate, the first contact layer is partially provided on the anode layer.

11. The semiconductor device according to claim 10, wherein: A ratio per unit area of ​​the first silicon burr provided between the anode layer exposed from the first contact layer and the electrode is greater than a ratio per unit area of ​​the first silicon burr provided between the first contact layer and the electrode.

12. The semiconductor device according to any one of claims 1 to 11, characterized in that: The semiconductor substrate further includes an impurity layer of the first conductivity type partially provided on the anode layer.

13. The semiconductor device according to claim 12, wherein: A ratio per unit area of ​​the first silicon burr provided between the impurity layer and the electrode is greater than a ratio per unit area of ​​the first silicon burr provided between the anode layer exposed from the impurity layer and the electrode.

14. The semiconductor device according to any one of claims 1 to 13, wherein: A diode region including the anode layer and functioning as a diode and provided with a diode trench gate, and an IGBT region functioning as an IGBT and provided with a trench gate are defined in the semiconductor substrate. The intervals between the diode trench gates are greater than the intervals between the trench gates.

15. The semiconductor device according to any one of claims 1 to 14, characterized in that: The semiconductor substrate further includes: a Schottky layer of the first conductivity type selectively disposed on the drift layer and connected to the Schottky electrode, A second silicon burr is also provided, which is disposed between the Schottky layer and the electrode and contains oxygen.

16. The semiconductor device according to any one of claims 1 to 13, characterized in that: A diode region including the anode layer and functioning as a diode and not provided with a diode trench gate is defined in the semiconductor substrate.

17. The semiconductor device according to any one of claims 1 to 13, characterized in that: A diode region including the anode layer and functioning as a diode and an IGBT region functioning as an IGBT are defined on the semiconductor substrate. The semiconductor substrate further includes: a base layer of the second conductivity type selectively disposed on the drift layer of the IGBT region, and an emitter layer of the first conductivity type selectively disposed on the base layer and a second contact layer of the second conductivity type having a higher impurity concentration of the second conductivity type than that of the base layer. The electrode is disposed above the anode layer and above at least one of the base layer, the emitter layer, and the second contact layer. A third silicon burr is further provided, which is provided between the at least one layer and the electrode and contains oxygen.

18. A method for manufacturing a semiconductor device, characterized in that: The following processes are available: A step of preparing a semiconductor substrate, the semiconductor substrate comprising: a drift layer of a first conductivity type, and an anode layer of a second conductivity type provided on at least a portion of the drift layer; forming a silicon layer containing oxygen on the upper surface of the semiconductor substrate; forming a conductive film including silicon and aluminum on the silicon layer, and forming a first silicon burr including oxygen between the anode layer and the conductive film; and A step of forming electrodes by patterning the conductive film.

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