Semiconductor device

Abstract

This semiconductor device is provided with a transistor section and a diode section, and is provided with: a plurality of trench sections provided on the front surface of a semiconductor substrate; a drift region of a first conductivity type provided on the semiconductor substrate; and a front surface-side electrode that is provided above the semiconductor substrate. The transistor portion may have a base region of a second conductivity type, an emitter region of a first conductivity type, a contact region of the second conductivity type, a trench contact, and a first plug region of the second conductivity type. The diode portion may have an anode region of a second conductivity type, and a second plug region of the second conductivity type. The second plug region may be in contact with the front surface-side electrode at a position shallower than the first plug region in a depth direction of the semiconductor substrate.

Description

Technical Field

[0001] The present invention relates to a semiconductor device. Background Art

[0002] In Patent Document 1, a semiconductor device is described in which "groove contact portions 60 are provided in each of the mesa portions 71 and 81" and "the plug region 19 is provided at the bottom of the groove contact portions 60 in each of the mesa portions 71 and 81". In Patent Document 2, a semiconductor device is described in which "groove contact portions and plug regions are discretely provided in the diode portion". In Patent Document 3, a semiconductor device is described in which "the anode contact layer 28 is locally formed on the surface layer portion of the anode layer 30".

[0003] Prior Art Documents Patent Documents Patent Document 1: Japanese Unexamined Patent Application Publication No. 2023 - 135082 Patent Document 2: Japanese Unexamined Patent Application Publication No. 2023 - 19322 Patent Document 3: International Publication No. 2014 / 125584 Summary of the Invention

[0004] Technical Problem It is desired to improve the Vf - Err characteristics of the semiconductor device.

[0005] Technical Solution In a first aspect of the present invention, there is provided a semiconductor device including a transistor portion and a diode portion, comprising: a plurality of groove portions provided on the front surface of a semiconductor substrate; a drift region of a first conductivity type provided in the semiconductor substrate; and a front - side electrode provided above the semiconductor substrate. The transistor portion may have: a base region of a second conductivity type provided above the drift region; an emitter region of a first conductivity type provided above the base region and having a doping concentration higher than that of the drift region; a contact region of a second conductivity type provided above the base region and having a doping concentration higher than that of the base region; a groove contact portion provided on the front surface of the semiconductor substrate; and a first plug region of a second conductivity type provided below the groove contact portion and having a doping concentration higher than that of the base region. The diode portion may have: an anode region of a second conductivity type provided above the drift region; and a second plug region of a second conductivity type having a doping concentration higher than that of the anode region. The second plug region may contact the front - side electrode at a position shallower than the first plug region in the depth direction of the semiconductor substrate.

[0006] In the above - mentioned semiconductor device, the second plug region may contact the front - side electrode on the front surface of the semiconductor substrate.

[0007] In any of the above semiconductor devices, the lower end of the trench contact portion provided in the diode portion may be shallower than the lower end of the trench contact portion provided in the transistor portion.

[0008] In any of the above semiconductor devices, in the diode portion, the second plug region may be alternately provided with the anode region in the trench extending direction of the plurality of trench portions.

[0009] In any of the above semiconductor devices, in the trench extending direction, the width of the first plug region provided in the transistor portion may be larger than the width of the second plug region provided in the diode portion.

[0010] In any of the above semiconductor devices, the lower end of the first plug region may be deeper than the lower end of the emitter region in the depth direction of the semiconductor substrate.

[0011] In any of the above semiconductor devices, the lower end of the first plug region may be at the same depth as or shallower than the lower end of the emitter region in the depth direction of the semiconductor substrate.

[0012] In any of the above semiconductor devices, the doping concentration of the anode region may be lower than the doping concentration of the base region.

[0013] In any of the above semiconductor devices, the doping concentration of the anode region may be 1E16 cm -3 or more and 1E18 cm -3 or less.

[0014] In any of the above semiconductor devices, the lower end of the trench contact portion may be shallower than the lower end of the emitter region in the depth direction of the semiconductor substrate.

[0015] In any of the above semiconductor devices, the transistor portion may have: a main region having the emitter region; and a boundary region provided closer to the diode portion than the main region. The boundary region may have: a first boundary portion including the contact region on the front surface of the semiconductor substrate; and a second boundary portion provided closer to the diode portion than the first boundary portion and including the anode region.

[0016] In any of the above semiconductor devices, the trench contact portion may not be provided in the boundary region.

[0017] In any of the above semiconductor devices, the width of the contact region provided in the first boundary portion in the trench extending direction may be larger than the width of the contact region provided in the main region in the trench extending direction.

[0018] In any of the above semiconductor devices, the second boundary portion may include the second plug region.

[0019] In any of the above semiconductor devices, in the trench extending direction of the plurality of trench portions, the width of the second plug region provided in the second boundary portion may be smaller than the width of the first plug region.

[0020] In any of the above semiconductor devices, the diode portion may have a cathode region of a first conductivity type having a doping concentration higher than that of the drift region on the back surface of the semiconductor substrate. The cathode region may include a first cathode portion of a first conductivity type and a second cathode portion of a second conductivity type.

[0021] In any of the above semiconductor devices, the first cathode portion and the second cathode portion may be alternately and repeatedly arranged in a preset direction.

[0022] In any of the above semiconductor devices, the semiconductor device may include an accumulation region of a first conductivity type, which is provided above the drift region in the transistor portion and has a doping concentration higher than that of the drift region.

[0023] In any of the above semiconductor devices, an interlayer insulating film may be provided above the semiconductor substrate, and the interlayer insulating film is provided with a contact hole for electrically connecting the front side electrode to the semiconductor substrate. The second plug region may be provided along the shape of the contact hole in a top view.

[0024] It should be noted that the above description of the invention does not list all the features of the present invention. In addition, sub-combinations of these feature groups can also form inventions. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1A is a diagram showing an example of the upper surface of the semiconductor device 100.

[0026] Figure 1B is a diagram showing an example of the a-a' cross section of the semiconductor device 100.

[0027] Figure 1C is a diagram showing an example of the b-b' cross section of the semiconductor device 100.

[0028] Figure 1D is a diagram showing an example of the c-c' cross section of the semiconductor device 100.

[0029] Figure 1E is a diagram showing an example of the d-d' cross section of the semiconductor device 100.

[0030] Figure 2This is a diagram showing a modified example of the a-a' cross-section of the semiconductor device 100.

[0031] Figure 3 This is a diagram showing a modified example of the upper surface of the semiconductor device 100.

[0032] Figure 4 This is a diagram showing the Vf-If characteristics of the semiconductor device 100.

[0033] Figure 5 This is a diagram showing the Vf-Err characteristics of the semiconductor device 100.

[0034] Symbol Explanation 10... semiconductor substrate, 12... emitter region, 14... base region, 15... contact region, 16... storage region, 17... well region, 18... drift region, 19... first plug region, 20... buffer region, 21... front surface, 22... collector region, 23... back surface, 24... collector electrode, 25... connection portion, 29... second plug region, 30... dummy trench portion, 31... extension portion, 32... dummy insulating film, 33... connection portion, 34... dummy conductive portion, 38... interlayer insulating film, 40... gate trench portion, 41... extension portion, 42... gate insulating film, 43... connection portion, 44... gate conductive portion, 50... gate metal layer, 52... emitter electrode, 53... front-side electrode, 54... contact hole, 55... contact hole, 56... contact hole, 60... trench contact portion, 70... transistor portion, 71... mesa portion, 75... main region, 80... diode portion, 81... mesa portion, 82... cathode region, 84... anode region, 90... boundary region, 100... semiconductor device, 181... first cathode portion, 182... second cathode portion, 190... first boundary portion, 191... mesa portion, 290... second boundary portion, 291... mesa portion Detailed Embodiments

[0035] Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention described in the claims. In addition, not all combinations of the features described in the embodiments are necessarily required for the technical solution of the invention.

[0036] In this specification, one side in the direction parallel to the depth direction of the semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". One of the two main surfaces of the substrate, layer, or other component is referred to as the upper surface, and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction when mounting the semiconductor device.

[0037] In this specification, the orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis are sometimes used to explain technical matters. The orthogonal coordinate axes only determine the relative positions of the components and do not limit a specific direction. For example, the Z-axis is not limited to representing the height direction relative to the ground. It should be noted that the +Z-axis direction and the -Z-axis direction are opposite to each other. When not recording positive and negative but recording as the Z-axis direction, it means the direction parallel to the +Z-axis and -Z-axis.

[0038] In this specification, the orthogonal axes parallel to the upper surface and the lower surface of the semiconductor substrate are denoted as the X-axis and the Y-axis. In addition, the axis perpendicular to the upper surface and the lower surface of the semiconductor substrate is denoted as the Z-axis. In this specification, the direction of the Z-axis is sometimes called the depth direction. In addition, in this specification, the direction parallel to the upper surface and the lower surface of the semiconductor substrate, including the X-axis and the Y-axis, is sometimes called the horizontal direction.

[0039] When denoted as P+ type or N+ type in this specification, it means that the doping concentration is higher than that of the P-type or N-type. When denoted as P- type or N- type, it means that the doping concentration is lower than that of the P-type or N-type.

[0040] Figure 1A An example of the upper surface of the semiconductor device 100 is shown. The semiconductor device 100 in this example includes a transistor portion 70 and a diode portion 80. For example, the semiconductor device 100 is a reverse-conducting IGBT (RC-IGBT: Reverse Conducting IGBT, reverse-conducting insulated gate bipolar transistor).

[0041] The transistor portion 70 is a region obtained by projecting the collector region 22 provided on the back surface 23 side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The back surface 23 will be described later. The transistor portion 70 includes transistors such as IGBTs. In this example, the transistor portion 70 is an IGBT. It should be noted that the transistor portion 70 may also be other transistors such as MOSFETs.

[0042] The transistor portion 70 in this example includes a main region 75 having an emitter region 12 and a boundary region 90 provided closer to the diode portion 80 than the main region 75. The main region 75 is a region that operates as a transistor when the semiconductor device 100 operates. On the mesa surface 71 of the main region 75, on the front surface 21 of the semiconductor substrate 10, the emitter region 12 and the contact region 15 are alternately provided in the extending direction. The front surface 21 will be described later.

[0043] The diode section 80 is a region obtained by projecting the cathode region 82 provided on the back surface 23 side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The diode section 80 includes diodes such as a free wheel diode (FWD) provided adjacent to the transistor section 70 on the front surface of the semiconductor substrate 10. On the back surface of the semiconductor substrate 10, a P+-type collector region may be provided in a region other than the cathode region.

[0044] The boundary region 90 does not have an emitter region 12. That is, the boundary region 90 is a region that does not operate as a transistor when the semiconductor device 100 operates. By providing the boundary region 90 that does not perform transistor operation between the main region 75 and the diode section 80, hole injection during the reverse recovery operation of the semiconductor device 100 can be suppressed. The boundary region 90 has a first boundary portion 190 and a second boundary portion 290.

[0045] The first boundary portion 190 includes a contact region 15 on the front surface 21 of the semiconductor substrate 10. In the first boundary portion 190, the contact region 15 is provided so as to extend from the base region 14 at the negative side end of the trench extension direction (in this example, the Y-axis direction) to the base region 14 at the positive side end of the trench extension direction. The first boundary portion 190 may be provided on the table surface portion closest to the main region 75 among one or more table surface portions included in the boundary region 90. The first boundary portion 190 may be provided over a plurality of table surface portions. The first boundary portion 190 in this example has one table surface portion 191.

[0046] The second boundary portion 290 is provided closer to the diode section 80 than the first boundary portion 190 and includes an anode region 84 on the front surface 21 of the semiconductor substrate 10. The second boundary portion 290 may be provided over a plurality of table surface portions. The second boundary portion 290 in this example has two table surface portions 291, but may also have three or more table surface portions 291.

[0047] In this figure, a region around the active portion of the semiconductor device 100 is shown, and other regions are omitted. For example, an edge termination structure portion may be provided in the region on the negative side in the Y-axis direction of the semiconductor device 100 in this example. The edge termination structure portion alleviates the electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure portion has, for example, a guard ring, a field plate, a reduced surface electric field, and a structure combining these. It should be noted that in this example, although the edge on the negative side in the Y-axis direction is described for convenience, the same applies to other edges of the semiconductor device 100.

[0048] The semiconductor substrate 10 is a substrate formed of a semiconductor material. The semiconductor substrate 10 may be a silicon substrate or a silicon carbide substrate. The semiconductor substrate 10 in this example is a silicon substrate.

[0049] The semiconductor device 100 of this example has an emitter region 12, a base region 14, a contact region 15, a well region 17, a dummy trench portion 30, a gate trench portion 40, and an anode region 84 on the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 of this example has a first plug region 19 and a second plug region 29 inside the semiconductor substrate 10. In addition, the semiconductor device 100 of this example has an emitter electrode 52 and a gate metal layer 50 disposed above the front surface 21 of the semiconductor substrate 10.

[0050] The emitter region 12 is a first-conductivity-type region that is disposed above the base region 14 and has a doping concentration higher than that of the drift region 18 described later. As an example, the emitter region 12 is N+. An example of the dopant of the emitter region 12 is arsenic (As). The emitter region 12 is disposed on the front surface 21 of the mesa portion 71 in a manner that contacts the gate trench portion 40. The emitter region 12 may extend from one of the two trench portions sandwiching the mesa portion 71 to the other trench portion along the trench arrangement direction (in this example, the X-axis direction).

[0051] In addition, the emitter region 12 may or may not contact the dummy trench portion 30. In this example, the emitter region 12 contacts the dummy trench portion 30.

[0052] The base region 14 is a second-conductivity-type region that is disposed above the drift region 18. As an example, the base region 14 is P-. The doping concentration of the base region 14 may be 1E16 cm -3 above, or may also be 5E18 cm -3 below. The base region 14 may be disposed at both ends in the Y-axis direction of the mesa portion 71 on the front surface 21 of the semiconductor substrate 10. It should be noted that Figure 1A only one end in the Y-axis direction of the base region 14 is shown.

[0053] The contact region 15 is a second-conductivity-type region that is disposed above the base region 14 and has a doping concentration higher than that of the base region 14. As an example, the contact region 15 is P+. The doping concentration of the contact region 15 may be 1E21 cm -3 above, or may also be 1E22 cm -3 below.

[0054] The contact region 15 of this example is disposed on the front surface 21 of the mesa portion 71 and the mesa portion 191. That is, the contact region 15 of this example is disposed in the main region 75 and the first boundary portion 190. The contact region 15 may extend from one of the two trench portions sandwiching the mesa portion 71 and the mesa portion 191 to the other trench portion along the trench arrangement direction (in this example, the X-axis direction).

[0055] The width Wp2 in the trench extension direction of the contact region 15 provided in the first boundary portion 190 is larger than the width Wp1 in the trench extension direction of the contact region 15 provided in the main region 75. On the mesa portion 71 of the main region 75, the contact regions 15 and the emitter regions 12 are alternately provided in the trench extension direction. The contact region 15 is provided so as to extend in the trench extension direction on the mesa portion 191 of the first boundary portion 190.

[0056] The contact region 15 may or may not be in contact with the gate trench portion 40 or the dummy trench portion 30. In this example, the contact region 15 is in contact with the dummy trench portion 30 and the gate trench portion 40.

[0057] The well region 17 is a region of a second conductivity type provided above the drift region 18. The well region 17 is an example of a well region provided on the peripheral side of the active portion. As an example, the well region 17 is of P+ type. The well region 17 is formed from the end of the active portion on the side where the gate metal layer 50 is provided within a preset range. The diffusion depth of the well region 17 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. A part of the gate trench portion 40 and the dummy trench portion 30 on the side closer to the gate metal layer 50 is formed within the well region 17. The bottom of the end portion in the extension direction of the gate trench portion 40 and the dummy trench portion 30 may be covered by the well region 17.

[0058] The anode region 84 is a region of a second conductivity type provided above the drift region 18. As an example, the anode region 84 is of P- type. The doping concentration of the anode region 84 may be lower than the doping concentration of the base region 14 or may be the same as the doping concentration of the base region 14. In one example, the doping concentration of the anode region 84 is 1E16 cm -3 or more and 1E18 cm -3 or less. By making the doping concentration of the anode region 84 lower than the doping concentration of the base region 14, the reverse recovery loss Err of the semiconductor device 100 can be reduced.

[0059] The first plug region 19 is a region of a second conductivity type in the transistor portion 70 having a doping concentration higher than the doping concentration of the base region 14 provided below the trench contact portion 60. As an example, the first plug region 19 is of P+ type. The doping concentration of the first plug region 19 may be the same as the doping concentration of the contact region 15 or may be higher than the doping concentration of the contact region 15. In this example, the doping concentration of the first plug region 19 is the same as the doping concentration of the contact region 15. In one example, the doping concentration of the first plug region 19 is 1E21 cm -3 or more and 1E22 cm -3 or less.

[0060] The second plug region 29 is a region of a second conductivity type having a doping concentration higher than that of the anode region 84. As an example, the second plug region 29 is of P+ type. The doping concentration of the second plug region 29 may be the same as or different from that of the first plug region 19. In this example, the doping concentration of the second plug region 29 is the same as that of the first plug region 19.

[0061] In the diode section 80, the second plug region 29 and the anode region 84 are alternately arranged in the trench extending direction of the plurality of trench sections. That is, the second plug region 29 is selectively arranged in the trench extending direction (the Y-axis direction in this example).

[0062] In the trench extending direction, the width W19 of the first plug region 19 provided in the transistor section 70 is larger than the width W29 of the second plug region 29 provided in the diode section 80. The first plug region 19 may be arranged so as to entirely cover the lower part of the contact hole 54 in a plan view. That is, the first plug region 19 may be continuously arranged in the extending direction of the contact hole 54 (the Y-axis direction in this example). Thereby, the extraction of holes via the first plug region 19 becomes easy, and the latch-up of the semiconductor device 100 can be suppressed. It should be noted that in the case simply referred to as a plan view in this specification, it means observing from the upper surface side of the semiconductor substrate 10.

[0063] The second plug region 29 may be provided in the second boundary portion 290. That is, the second boundary portion 290 may include the second plug region 29. In addition, in the trench extending direction, the width of the second plug region 29 provided in the second boundary portion 290 may be smaller than the width of the first plug region 19 provided in the mesa portion 71. Thereby, the hole injection during the reverse recovery operation of the semiconductor device 100 can be suppressed.

[0064] The first plug region 19 and the second plug region 29 may be formed simultaneously by the same ion implantation process. As an example, the manufacturing method of the semiconductor device 100 sequentially includes: a stage of forming the contact hole 54 in the interlayer insulating film 38 of the transistor section 70 and the diode section 80; a stage of etching the semiconductor substrate 10 exposed through the opening of the contact hole 54 in the transistor section 70; and a stage of performing ion implantation to form the first plug region 19 and the second plug region 29. The interlayer insulating film 38 will be described later. It should be noted that the following stage may also be performed: first forming the contact hole 54 in the transistor section 70, and after etching the semiconductor substrate 10, forming the contact hole 54 in the diode section 80 and performing ion implantation.

[0065] The emission electrode 52 is provided above the gate trench section 40, the dummy trench section 30, the emission region 12, the base region 14, the contact region 15, the well region 17, the connection portion 25, and the anode region 84. In addition, the gate metal layer 50 is provided above the well region 17 and the connection portion 25.

[0066] The emission electrode 52 and the gate metal layer 50 are formed of a metal-containing material. At least a part of the emission electrode 52 may be formed of a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). At least a part of the gate metal layer 50 may be formed of a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). The emission electrode 52 and the gate metal layer 50 may have a barrier metal layer formed of titanium or a titanium compound or the like under the region formed of aluminum or the like. The emission electrode 52 and the gate metal layer 50 are provided in a separated manner from each other.

[0067] The emission electrode 52 and the gate metal layer 50 are provided above the semiconductor substrate 10 with an interlayer insulating film 38 therebetween. In Figure 1A the interlayer insulating film 38 is omitted. The contact hole 54, the contact hole 55, and the contact hole 56 are provided to penetrate through the interlayer insulating film 38.

[0068] The contact hole 54 is formed above each of the regions of the emission region 12, the contact region 15, and the anode region 84 in the transistor portion 70 and the diode portion 80. The contact hole 54 is not provided above the well regions 17 provided at both ends in the Y-axis direction. Thus, one or more contact holes 54 are formed in the interlayer insulating film. The one or more contact holes 54 may be provided to extend along the extending direction of the trenches of the plurality of trench portions.

[0069] The emission electrode 52 is electrically connected to the semiconductor substrate 10 via the contact hole 54. Below the contact hole 54, a trench contact portion 60 provided on the front surface 21 of the semiconductor substrate 10 may be formed.

[0070] The trench contact portion 60 electrically connects the emission electrode 52 and the semiconductor substrate 10. The trench contact portion 60 is provided continuously with the contact hole 54. The trench contact portion 60 of this example is provided on the mesa portion 71 and is not provided on the mesa portions 81, 191, and 291. That is, the trench contact portion 60 is not provided in the diode portion 80 and the boundary region 90.

[0071] The trench contact portion 60 has a conductive material filled in the contact hole 54. The trench contact portion 60 is provided between two adjacent trench portions among the plurality of trench portions. The trench contact portion 60 may have the same material as the emission electrode 52. The detailed situation of the trench contact portion 60 will be described later.

[0072] The contact hole 55 electrically connects the gate metal layer 50 and the gate conductive portion in the gate trench portion 40 via the connection portion 25. A trench contact portion 60 may be formed inside the contact hole 55.

[0073] The contact hole 56 connects the emission electrode 52 and the dummy conductive portion in the dummy trench portion 30. A trench contact portion 60 may be formed inside the contact hole 56.

[0074] The connection portion 25 is connected to a front-side metal layer such as the emission electrode 52 or the gate metal layer 50. In one example, the connection portion 25 is provided between the gate metal layer 50 and the gate conductive portion. The connection portion 25 in this example is provided to extend in the X-axis direction and can be electrically connected to the gate conductive portion. The connection portion 25 may be provided between the emission electrode 52 and the dummy conductive portion. The connection portion 25 is a conductive material such as polysilicon doped with impurities. The connection portion 25 in this example is polysilicon doped with N-type impurities (N+). The connection portion 25 is provided above the front surface 21 of the semiconductor substrate 10 with an insulating film such as an oxide film interposed therebetween.

[0075] The gate trench portion 40 is an example of a plurality of trench portions extending along a preset extension direction on the front surface 21 side of the semiconductor substrate 10. The gate trench portion 40 is arranged at a preset interval along a preset arrangement direction (the X-axis direction in this example). The gate trench portion 40 is an example of a MOS gate structure included in the semiconductor device 100. The gate trench portion 40 in this example has two extension portions 41 and a connection portion 43. The two extension portions 41 extend along an extension direction parallel to the front surface 21 of the semiconductor substrate 10 and perpendicular to the arrangement direction (the Y-axis direction in this example), and the connection portion 43 connects the two extension portions 41.

[0076] Preferably, at least a part of the connection portion 43 is formed in a curved shape. By connecting the ends of the two extension portions 41 of the gate trench portion 40, the electric field concentration at the ends of the extension portions 41 can be alleviated. At the connection portion 43 of the gate trench portion 40, the gate metal layer 50 can be electrically connected to the gate conductive portion via the connection portion 25.

[0077] The dummy trench portion 30 is an example of a plurality of trench portions extending along a preset extension direction on the front surface 21 side of the semiconductor substrate 10. The dummy trench portion 30 is a trench portion electrically connected to the emission electrode 52. The dummy trench portion 30 is arranged at a preset interval along a preset arrangement direction (the X-axis direction in this example) in the same manner as the gate trench portion 40.

[0078] The dummy trench portion 30 in this example has two extension portions 31 and a connection portion 33, similar to the gate trench portion 40. The two extension portions 31 extend along an extension direction (the Y-axis direction in this example) parallel to the front surface 21 of the semiconductor substrate 10 and perpendicular to the arrangement direction, and the connection portion 33 connects the two extension portions 31. The dummy trench portion 30 may have an I shape on the front surface 21 of the semiconductor substrate 10. That is, the dummy trench portion 30 may have only one extension portion 31 without the connection portion 33.

[0079] The transistor portion 70 in this example has a structure in which one gate trench portion 40 and two dummy trench portions 30 are repeatedly arranged. That is, the transistor portion 70 in this example has the gate trench portion 40 and the dummy trench portion 30 at a ratio of 1:2. For example, the transistor portion 70 has two extension portions 31 between two extension portions 41.

[0080] However, the ratio of the gate trench portion 40 to the dummy trench portion 30 is not limited to this example. The ratio of the gate trench portion 40 may be larger than the ratio of the dummy trench portion 30, or the ratio of the dummy trench portion 30 may be larger than the ratio of the gate trench portion 40. The ratio of the gate trench portion 40 to the dummy trench portion 30 may be 1:1 or 2:3. In addition, the transistor portion 70 may also have a structure in which all the trench portions are gate trench portions 40 and there is no dummy trench portion 30.

[0081] Figure 1B Shows Figure 1A An example of the a-a' cross-section. The a-a' cross-section is the XZ plane passing through the second plug region 29 in the diode portion 80. The semiconductor device 100 in this example has a semiconductor substrate 10, an interlayer insulating film 38, an emission electrode 52, a trench contact portion 60, and a collector electrode 24 in the a-a' cross-section. The collector electrode 24 is an example of a back-side metal layer provided in contact with the back surface 23 of the semiconductor substrate 10. The emission electrode 52 and the trench contact portion 60 are examples of a front-side electrode 53 provided above the semiconductor substrate 10. The front-side electrode 53 may include a metal layer such as a barrier metal layer.

[0082] The drift region 18 is a region of the first conductivity type provided in the semiconductor substrate 10. As an example, the drift region 18 is an N-type. The drift region 18 may be a region remaining in the semiconductor substrate 10 without forming other doped regions. That is, the doping concentration of the drift region 18 may be the doping concentration of the semiconductor substrate 10.

[0083] The buffer region 20 is a region of the first conductivity type provided closer to the back surface 23 side of the semiconductor substrate 10 than the drift region 18. The doping concentration of the buffer region 20 is higher than that of the drift region 18. As an example, the buffer region 20 is of N type. The buffer region 20 can function as a field stop layer that prevents the depletion layer extending from the lower surface side of the base region 14 from reaching the collector region 22 of the second conductivity type. It should be noted that the buffer region 20 can be omitted.

[0084] The collector region 22 is provided below the buffer region 20 in the transistor section 70. The collector region 22 has the second conductivity type. As an example, the collector region 22 is of P+ type.

[0085] The cathode region 82 is a region of the first conductivity type provided on the back surface 23 of the semiconductor substrate 10 in the diode section 80 and having a doping concentration higher than that of the drift region 18. As an example, the cathode region 82 is of N+ type.

[0086] The collector electrode 24 is formed on the back surface 23 of the semiconductor substrate 10. The collector electrode 24 is formed of a conductive material such as metal. The material of the collector electrode 24 can be the same as or different from the material of the emitter electrode 52.

[0087] The storage region 16 is a region of the first conductivity type provided above the drift region 18 and having a doping concentration higher than that of the drift region 18. As an example, the storage region 16 is of N type. However, the storage region 16 may not be provided.

[0088] The storage region 16 is provided in contact with the gate trench portion 40. The storage region 16 may or may not be in contact with the dummy trench portion 30. The storage region 16 can be provided in multiple layers in the depth direction of the semiconductor substrate 10. In this example, two layers of the storage region 16 are provided. By providing the storage region 16, the carrier injection enhancement effect (IE effect) can be improved and the on-voltage of the transistor section 70 can be reduced.

[0089] One or more gate trench portions 40 and one or more dummy trench portions 30 are provided on the front surface 21. Each trench portion is provided from the front surface 21 to the drift region 18. In the region where at least any one of the emitter region 12, the base region 14, the contact region 15, the storage region 16, and the anode region 84 is provided, each trench portion also penetrates these regions and reaches the drift region 18. The trench portions penetrating the doped regions are not limited to being manufactured in the order of forming the doped regions first and then forming the trench portions. A method of forming the doped regions between the trench portions after forming the trench portions is also included in the method of the trench portions penetrating the doped regions.

[0090] The gate trench portion 40 has a gate trench formed in the front surface 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed so as to cover the inner wall of the gate trench. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench at a position closer to the inside than the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 and the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The gate trench portion 40 is covered with an interlayer insulating film 38 on the front surface 21.

[0091] The gate conductive portion 44 includes a region facing the base region 14 that is adjacent to the mesa portion 71 side across the gate insulating film 42 in the depth direction of the semiconductor substrate 10. If a preset voltage is applied to the gate conductive portion 44, a channel composed of an inversion layer of electrons is formed on the surface layer of the interface in the base region 14 that contacts the gate trench.

[0092] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench formed on the front surface 21 side, a dummy insulating film 32, and a dummy conductive portion 34. The dummy insulating film 32 is formed so as to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and at a position closer to the inside than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 and the semiconductor substrate 10. The dummy trench portion 30 may be covered with the interlayer insulating film 38 on the front surface 21.

[0093] The interlayer insulating film 38 is provided above the semiconductor substrate 10. The interlayer insulating film 38 in this example is provided in contact with the front surface 21. An emission electrode 52 is provided above the interlayer insulating film 38. One or more contact holes 54 are provided in the interlayer insulating film 38 for electrically connecting the front-side electrode 53 and the semiconductor substrate 10.

[0094] The lower end D1 of the trench contact portion 60 is shallower than the lower end D12 of the emitter region 12 in the depth direction of the semiconductor substrate 10. That is, the trench contact portion 60 does not penetrate the emitter region 12 and terminates inside the emitter region 12. The distance from the front surface 21 of the semiconductor substrate 10 to the lower end D1 of the trench contact portion 60 can be 0.3 μm or more and can also be 0.5 μm or less. Thereby, the influence on the threshold value of the semiconductor device 100 is reduced, and the miniaturization of the semiconductor device 100 becomes easy.

[0095] The first plug region 19 is provided so as to cover the bottom of the trench contact portion 60. Thereby, it becomes easy to extract holes from the first plug region 19 to the trench contact portion 60, and latching of the semiconductor device 100 can be suppressed.

[0096] The lower end of the first plug region 19 is located at the same depth as the lower end D12 of the emitter region 12 or at a shallower position than the lower end D12 of the emitter region 12 in the depth direction of the semiconductor substrate 10. That is, the first plug region 19 does not have a protrusion protruding into the base region 14. In this example, the lower end of the first plug region 19 is provided at the same depth as the lower end D12 of the emitter region 12. Thus, by making the depth of the lower end of the first plug region 19 the same as or shallower than the lower end D12 of the emitter region 12, the doping concentration of the base region 14 becomes uniform, the influence on the threshold value of the semiconductor device 100 is reduced, and the miniaturization of the semiconductor device 100 becomes easy.

[0097] The second plug region 29 contacts the front side electrode 53 at a shallower position than the first plug region 19 in the depth direction of the semiconductor substrate 10. In this example, the first plug region 19 contacts the front side electrode 53 on the side wall of the trench contact portion 60 below the front surface 21 of the semiconductor substrate 10, and the second plug region contacts the front side electrode 53 on the front surface 21 of the semiconductor substrate 10. Thus, since the front side electrode 53 and the semiconductor substrate 10 can be connected near the front surface 21 with a high doping concentration in the diode portion 80, the forward voltage Vf of the diode portion 80 can be reduced, and an increase in the reverse recovery loss Err of the semiconductor device 100 can be suppressed.

[0098] In this example, the trench contact portion 60 is provided in the main region 75, and the trench contact portion 60 is not provided in the diode portion 80, the first boundary portion 190, and the second boundary portion 290. Thus, the amount of hole injection from the anode region 84 increases, and the forward voltage Vf of the diode portion 80 can be reduced.

[0099] Figure 1C Shows Figure 1A An example of the b-b' cross section. The b-b' cross section is the XZ plane that does not pass through the second plug region 29 in the diode portion 80. Use Figure 1C To illustrate the points different from Figure 1B .

[0100] In Figure 1C The cross section shown, the second plug region 29 is not provided in the diode portion 80 and the second boundary portion 290. Thus, by having a region where the second plug region 29 is not provided, an increase in the reverse recovery loss Err can be suppressed.

[0101] In Figure 1C The cross section shown, the contact region 15 is formed to the same depth as the emitter region 12. The contact region 15 can be formed to a position deeper than the emitter region 12. Thus, it becomes easy to extract holes from the base region 14, and latching of the semiconductor device 100 can be suppressed.

[0102] Figure 1D ShowsFigure 1A An example of the c-c' cross-section. The c-c' cross-section is the YZ cross-section passing through the contact hole 54 in the transistor section 70. The semiconductor device 100 in this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, a trench contact portion 60, and a collector electrode 24 in the c-c' cross-section.

[0103] The first plug region 19 in this example is provided in the transistor section 70 so as to entirely cover the bottom of the trench contact portion 60. Thus, it becomes easy to extract holes from the first plug region 19 to the trench contact portion 60, and latch-up of the semiconductor device 100 can be suppressed. However, there may be a portion of the bottom of the trench contact portion 60 that is not covered by the first plug region 19.

[0104] Figure 1E Shown Figure 1A An example of the d-d' cross-section. The d-d' cross-section is the YZ cross-section passing through the contact hole 54 in the diode section 80. Use Figure 1E To explain the points different from Figure 1D This.

[0105] The trench contact portion 60 is not provided in the diode section 80. The second plug region 29 is provided on the front surface 21 of the semiconductor substrate 10 in the diode section 80. Thus, since the doping concentration in the front surface 21 where the emitter electrode 52 is electrically connected to the semiconductor substrate 10 becomes high and the injection amount of holes increases, the forward voltage Vf of the diode section 80 can be reduced.

[0106] The second plug region 29 is alternately provided with the anode region 84 in the extending direction of the contact hole 54. That is, the second plug region 29 is selectively provided in the extending direction of the contact hole 54 (the Y-axis direction in this example). Thus, the forward voltage Vf of the diode section 80 can be reduced, and an increase in the reverse recovery loss Err can be suppressed.

[0107] The cathode region 82 in this example has a first cathode portion 181 and a second cathode portion 182. The first cathode portion 181 is a region of a first conductivity type having a doping concentration higher than that of the drift region 18. The doping concentration of the first cathode portion 181 may be higher than that of the buffer region 20. In one example, the first cathode portion 181 is of N+ type.

[0108] The second cathode portion 182 is a region of a second conductivity type provided adjacent to the first cathode portion 181 on the back surface 23 of the semiconductor substrate 10. That is, the second cathode portion 182 may be in direct contact with the first cathode portion 181. In one example, the second cathode portion 182 is of P+ type. The doping concentration of the second cathode portion 182 may be the same as or different from the doping concentration of the collector region 22.

[0109] The first cathode portion 181 can be formed by further implanting an N-type dopant after implanting a P-type dopant through an ion implantation process for forming the second cathode portion 182. Conversely, the second cathode portion 182 can be formed by further implanting a P-type dopant after implanting an N-type dopant through an ion implantation process for forming the first cathode portion 181.

[0110] The first cathode portion 181 and the second cathode portion 182 are alternately and repeatedly arranged in a preset direction. The first cathode portion 181 and the second cathode portion 182 can be alternately arranged in the trench arrangement direction (in this example, the X-axis direction), or can be alternately arranged in the trench extension direction (in this example, the Y-axis direction). In this example, the first cathode portion 181 and the second cathode portion 182 are alternately arranged in the trench extension direction. The first cathode portion 181 and the second cathode portion 182 can be arranged in a striped shape in a top view. Thereby, the trade-off between the forward voltage Vf of the diode portion 80 and the reverse recovery loss Err of the semiconductor device 100 can be adjusted.

[0111] Figure 2 It is a diagram showing a modified example of the a-a' cross section of the semiconductor device 100. In Figure 2 the modified example, the difference from Figure 1B the example is that the trench contact portion 60 is provided in the diode portion 80, the first boundary portion 190, and the second boundary portion 290. Use Figure 2 to explain the difference from Figure 1B the above.

[0112] In Figure 2 the example shown, the lower end of the first plug region 19 is deeper in the depth direction of the semiconductor substrate 10 than the lower end of the emitter region 12. That is, the first plug region 19 is provided so as to protrude into the base region 14. Thereby, it becomes easy to extract holes from the base region 14, and the latch-up of the semiconductor device 100 can be suppressed.

[0113] The lower end D2 of the trench contact portion 60 provided in the diode portion 80 is shallower than the lower end D1 of the trench contact portion 60 provided in the transistor portion 70. In one example, the distance from the front surface 21 of the semiconductor substrate 10 to the lower end D2 of the trench contact portion 60 in the diode portion 80 is 0 μm or more and 0.1 μm or less. Thereby, since the front side electrode 53 and the semiconductor substrate 10 can be connected near the front surface 21 with a high doping concentration in the diode portion 80, the forward voltage Vf of the diode portion 80 can be reduced, and an increase in the reverse recovery loss Err of the semiconductor device 100 can be suppressed.

[0114] The trench contact portion 60 of the diode portion 80 can be formed by filling a conductive material in a region where the front surface 21 of the semiconductor substrate 10 is slightly etched due to the operation of forming the contact hole 54 in the diode portion 80. That is, it can be formed without the need for an additional step for forming the trench contact portion 60 in the diode portion 80.

[0115] Figure 3 FIG. is a diagram showing a modified example of the upper surface of the semiconductor device 100. Use Figure 3 For Figure 1A different points are described.

[0116] In a plan view, the second plug region 29 can be provided along the shape of the contact hole 54. In the present specification, the second plug region 29 being provided along the shape of the contact hole 54 means that in the ion implantation step for forming the second plug region 29, dopants are implanted into the region of the semiconductor substrate 10 exposed through the opening of the contact hole 54. Therefore, the dopants diffuse through a thermal annealing step or the like after the ion implantation step, and even when the region where the contact hole 54 is provided and the region where the second plug region 29 is provided do not completely coincide in a plan view, embodiments where the second plug region 29 is provided along the shape of the contact hole 54 can be included.

[0117] In Figure 3 a modified example, in the main region 75, one contact hole 54 is provided so as to extend in the trench extending direction, and in the second boundary portion 290 and the diode portion 80, a plurality of contact holes 54 are selectively provided in the trench extending direction. That is, in the trench extending direction, the length of the contact hole 54 in the second boundary portion 290 and the diode portion 80 is shorter than the length of the contact hole 54 in the main region 75.

[0118] By providing the second plug region 29 along the shape of the contact hole 54, when selectively forming the second plug region 29, it is possible to eliminate the need for an additional resist mask or the like. As a result, the number of manufacturing steps when manufacturing the semiconductor device 100 is reduced, and the manufacturing cost of the semiconductor device 100 is lowered.

[0119] Figure 4 FIG. is a diagram showing the Vf-If characteristics of the semiconductor device 100 of this example and a semiconductor device of a comparative example. The Vf-If characteristics of this example are represented by a solid line, and the Vf-If characteristics of the comparative example are represented by a dotted line. The horizontal axis represents the forward voltage Vf, the vertical axis represents the forward current If, and the values of the vertical axis and the horizontal axis are normalized.

[0120] In the present specification, the semiconductor device of the comparative example refers to a semiconductor device in which the second plug region contacts the front side electrode at the same depth position as the first plug region or a deeper position in the depth direction of the semiconductor substrate. In Figure 4In [the figure], the Vf-If characteristics for a comparative example are shown, where the first plug region and the second plug region of the comparative example are in contact with the front-side electrode at the same depth. The difference between the semiconductor device 100 of this example and the semiconductor device of the comparative example is that the second plug region 29 is in contact with the front-side electrode 53 at a position shallower than the first plug region 19.

[0121] The value of the forward voltage Vf for allowing the same forward current If to flow through the semiconductor device 100 of this example is smaller than that of the semiconductor device of the comparative example. That is, compared with the semiconductor device of the comparative example, the forward voltage Vf of the semiconductor device 100 of this example is reduced. By making the second plug region 29 in contact with the front-side electrode 53 at a position shallower than the first plug region 19, the semiconductor device 100 of this example electrically connects the front-side electrode 53 and the semiconductor substrate 10 near the front surface 21 where the doping concentration is higher than that of the comparative example, can improve the hole injection from the anode region 84, and can reduce the forward voltage Vf.

[0122] Figure 5 It is a diagram showing the Vf-Err characteristics of the semiconductor device 100 of this example and the semiconductor device of the comparative example. The Vf-Err characteristics of this example are represented by a solid line, and the Vf-Err characteristics of the comparative example are represented by a dashed line. The horizontal axis represents the forward voltage Vf, and the vertical axis represents the reverse recovery loss Err. The values of the vertical axis and the horizontal axis are normalized.

[0123] For the semiconductor device of the comparative example, four data points with the doping concentration of the anode region changed are represented by white circles. Qp1, Qp2, Qp3, and Qp4 respectively represent the doping concentrations of the anode region. The doping concentration of Qp1 is the lowest, the doping concentrations of Qp2 and Qp3 increase in sequence, and the doping concentration of Qp4 is the highest. It can be seen that Figure 5 in the semiconductor device of the comparative example, if the doping concentration of the anode region is increased, there is a tendency that the forward voltage Vf decreases and the reverse recovery loss Err increases.

[0124] In Figure 5 the Vf-Err characteristics of the semiconductor device 100 of this example in the case where the doping concentration of the anode region 84 is Qp3 are represented by a cross mark. In the semiconductor device of the comparative example, if the doping concentration of the anode region is increased from Qp3 to Qp4, the forward voltage Vf decreases by 13.8%. On the other hand, for the semiconductor device 100 of this example, even if the doping concentration of the anode region 84 is Qp3, the forward voltage Vf also decreases by 13.8%. Therefore, the semiconductor device 100 of this example can reduce the forward voltage Vf without increasing the doping concentration of the anode region 84.

[0125] In addition, in the semiconductor device of the comparative example, if the doping concentration of the anode region is increased from Qp3 to Qp4, the reverse recovery loss Err increases by 12%. On the other hand, the increase amount of the reverse recovery loss Err of the semiconductor device 100 in this example remains at 6.9%. That is, compared with the case where the doping concentration is increased from Qp3 to Qp4, the increase amount of the reverse recovery loss Err can be reduced by 5.1%. Therefore, compared with the case of increasing the doping concentration of the anode region 84, the semiconductor device 100 in this example can improve the Vf-Err characteristics.

[0126] As described above, the present invention has been described using the embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious that various changes or improvements can be made to the above embodiments by those skilled in the art. It can be clearly understood from the description of the claims that the embodiments with such changes or improvements can also be included in the technical scope of the present invention.

[0127] It should be noted that the execution order of each process such as the actions, sequences, steps, and stages in the device, system, program, and method shown in the claims, the specification, and the drawings can be implemented in any order as long as it is not specifically stated as "before...", "prior to...", etc., and as long as the output of the previous process is not used in the subsequent process. Regarding the action flow in the claims, the specification, and the drawings, even if it is described using "first," "next," etc. for convenience, it does not mean that it must be implemented in that order.

Claims

1. A semiconductor device, characterized in that: The semiconductor device includes a transistor portion and a diode portion, and includes: A plurality of groove portions are disposed on the front surface of the semiconductor substrate; A drift region of a first conductivity type, which is disposed on the semiconductor substrate; and a front side electrode disposed above the semiconductor substrate, The transistor portion has: A base region of a second conductivity type, which is disposed above the drift region; An emitter region of the first conductivity type, which is disposed above the base region and has a doping concentration higher than that of the drift region; A contact region of the second conductivity type, which is disposed above the base region and has a doping concentration higher than that of the base region; A trench contact portion, which is disposed on the front surface of the semiconductor substrate; as well as A first plug region of the second conductivity type is below the trench contact portion and has a doping concentration higher than that of the base region. The diode unit has: An anode region of the second conductivity type, which is disposed above the drift region; as well as The second plug region of the second conductivity type has a doping concentration higher than that of the anode region, The second plug region is in contact with the front-side electrode at a position shallower than the first plug region in the depth direction of the semiconductor substrate.

2. The semiconductor device according to claim 1, wherein: The second plug region is in contact with the front-side electrode on the front surface of the semiconductor substrate.

3. The semiconductor device according to claim 1, wherein: A lower end of the trench contact portion provided in the diode portion is shallower than a lower end of the trench contact portion provided in the transistor portion.

4. The semiconductor device according to claim 1, wherein: In the diode portion, the second plug regions are arranged alternately with the anode regions in a trench extending direction of the plurality of trench portions.

5. The semiconductor device according to claim 4, wherein: In the trench extending direction, the width of the first plug region provided in the transistor portion is greater than the width of the second plug region provided in the diode portion.

6. The semiconductor device according to claim 1, wherein: A lower end of the first plug region is deeper than a lower end of the emitter region in a depth direction of the semiconductor substrate.

7. The semiconductor device according to claim 1, wherein: A lower end of the first plug region is located at the same depth as or shallower than a lower end of the emitter region in a depth direction of the semiconductor substrate.

8. The semiconductor device according to claim 1, wherein: The doping concentration of the anode region is lower than the doping concentration of the base region.

9. The semiconductor device according to claim 1, wherein: The doping concentration of the anode region is 1E16 cm -3 Above and 1E18cm -3 the following.

10. The semiconductor device according to claim 1, wherein: A lower end of the trench contact portion is shallower than a lower end of the emitter region in a depth direction of the semiconductor substrate.

11. The semiconductor device according to any one of claims 1 to 10, characterized in that The transistor portion has: a main region having the emission region; and a boundary region disposed closer to the diode portion than the main region, The boundary region has: A first boundary portion including the contact region on the front surface of the semiconductor substrate; and The second boundary portion is provided closer to the diode portion than the first boundary portion and includes the anode region.

12. The semiconductor device according to claim 11, wherein: The trench contact is not provided in the boundary region.

13. The semiconductor device according to claim 11, wherein: The width of the contact region provided in the first boundary portion in the trench extending direction is greater than the width of the contact region provided in the main region in the trench extending direction.

14. The semiconductor device according to claim 11, wherein: The second boundary portion includes the second plug region.

15. The semiconductor device according to claim 14, wherein: In a groove extending direction of the plurality of groove portions, a width of the second plug region provided at the second boundary portion is smaller than a width of the first plug region.

16. The semiconductor device according to any one of claims 1 to 10, characterized in that The diode portion includes a cathode region of the first conductivity type having a doping concentration higher than that of the drift region on the back surface of the semiconductor substrate. The cathode region includes a first cathode portion of a first conductivity type and a second cathode portion of a second conductivity type.

17. The semiconductor device according to claim 16, wherein: The first cathode portions and the second cathode portions are alternately and repeatedly arranged in a predetermined direction.

18. The semiconductor device according to any one of claims 1 to 10, characterized in that The semiconductor device includes a first conductivity type accumulation region provided above the drift region in the transistor portion and having a doping concentration higher than that of the drift region.

19. The semiconductor device according to any one of claims 1 to 10, characterized in that An interlayer insulating film is provided above the semiconductor substrate, wherein the interlayer insulating film is provided with a contact hole for electrically connecting the front-side electrode and the semiconductor substrate. The second plug region is disposed along the shape of the contact hole in a plan view.

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