Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, relates to the technical field of semiconductors, and prevents notches from being formed below a first channel region and a second channel region. The semiconductor device comprises a silicon-based substrate, an N-type gate-all-around transistor, a P-type gate-all-around transistor, a first etching blocking structure and a second etching blocking structure. A first channel region included in the N-type gate-all-around transistor and a second channel region included in the P-type gate-all-around transistor are made of the same material, and the material of the first channel region and the material of the second channel region are different from the material of the silicon-based substrate. The first etch stop structure is at least partially disposed in the silicon-based substrate below the second channel region. The surface of the first etching blocking structure is flush with the surface of the silicon-based substrate, and the first etching blocking structure and the silicon-based substrate are made of different materials. The second etch stop structure is at least partially disposed within the silicon-based substrate below the first channel region. And an etching inhibitor is doped in the second etching blocking structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a semiconductor device and a manufacturing method thereof. Background Art

[0002] The gate stack included in a gate-all-around transistor is formed not only on the top and sidewalls of a channel, but also on the bottom of the channel. Therefore, compared with a planar transistor and a fin field-effect transistor, the gate-all-around transistor has advantages such as higher gate control ability. Based on this, when the transistors included in a semiconductor device adopt gate-all-around transistors, the working performance of the semiconductor device can be improved. In addition, in the actual application process, a channel region made of a non-silicon material such as silicon-germanium or germanium may be adopted to meet different working requirements.

[0003] However, the yield of a semiconductor device including a channel region made of a non-silicon material formed by using the existing manufacturing method is relatively low, which is not conducive to improving the working performance of the semiconductor device. Summary of the Invention

[0004] The purpose of the present invention is to provide a semiconductor device and a manufacturing method thereof, which are used to prevent an etchant for releasing a first channel region and a second channel region from forming notches under the first channel region and the second channel region under the etching blocking action of a first etching blocking structure and a second etching blocking structure, increase the yield of the semiconductor device, reduce the parasitic capacitance of the semiconductor device, and are conducive to improving the yield of the semiconductor device.

[0005] To achieve the above purpose, in a first aspect, the present invention provides a semiconductor device, which includes: a silicon-based substrate, an N-type gate-all-around transistor, a P-type gate-all-around transistor, a first etching blocking structure, and a second etching blocking structure. The N-type gate-all-around transistor and the P-type gate-all-around transistor are arranged on the silicon-based substrate at intervals in a direction parallel to the surface of the silicon-based substrate. The materials of a first channel region included in the N-type gate-all-around transistor and a second channel region included in the P-type gate-all-around transistor are the same, and the materials of the first channel region and the second channel region are different from the material of the silicon-based substrate. The first etching blocking structure is at least partially disposed in the silicon-based substrate under the second channel region. The surface of the first etching blocking structure is flush with the surface of the silicon-based substrate, and the material of the first etching blocking structure is different from that of the silicon-based substrate. The second etching blocking structure is at least partially disposed in the silicon-based substrate under the first channel region. The second etching blocking structure is doped with an etching inhibitor.

[0006] In the case of adopting the above technical solution, in the semiconductor device provided by the present invention, the materials of the first channel region included in the N-type gate-all-around transistor and the second channel region included in the P-type gate-all-around transistor are the same. In this case, in the actual manufacturing process, the same process can be adopted and the first channel region and the second channel region can be manufactured simultaneously based on the same channel layer to improve the manufacturing efficiency of the semiconductor device and reduce the manufacturing cost of the semiconductor device. Secondly, the materials of the first channel region and the second channel region are different from the material of the silicon-based substrate. At this time, corresponding semiconductor materials can be selected to manufacture the first channel region and the second channel region according to different actual application scenarios to improve the applicability of the semiconductor device provided by the present invention in different application scenarios. For example: non-silicon semiconductor materials such as silicon germanium or germanium can be used to manufacture the first channel region and the second channel region to improve the conduction performance of the first channel region and the second channel region.

[0007] In addition, the semiconductor device provided by the present invention further includes a first etch stop structure at least partially disposed in the silicon-based substrate under the second channel region, and a second etch stop structure at least partially disposed in the silicon-based substrate under the first channel region. Wherein, the surface of the first etch stop structure is flush with the surface of the silicon-based substrate, and the material of the first etch stop structure is different from that of the silicon-based substrate. At this time, the first etch stop structure can have a certain etch selectivity ratio with the silicon-based substrate at least through the difference in material types. And the second etch stop structure is doped with an etch inhibitor. Based on this, even in the actual manufacturing process, the material of the sacrificial layer selected for releasing the first channel region and the second channel region is the same as or similar to the material of the silicon-based substrate, the first etch stop structure can also have an etch blocking effect on the etchant through the difference in its own material, and the second etch stop structure is doped with an etch inhibitor, so as to prevent notches from appearing in the directions of the first channel region and the second channel region after releasing the first channel region and the second channel region, reduce the parasitic capacitance of the semiconductor device, and improve the working performance of the semiconductor device.

[0008] In one example, the first etch stop structure includes a doped semiconductor portion, and the conduction type of the doped semiconductor portion is N-type.

[0009] In one example, the material of the doped semiconductor portion is the same as the material of the second channel region.

[0010] In one example, the thickness of the doped semiconductor portion is greater than or equal to 15 nm and less than or equal to 50 nm.

[0011] In one example, the doping concentration of the N-type impurities in the doped semiconductor portion is greater than or equal to 1E18 cm -3 and less than or equal to 1E19 cm -3 .

[0012] In one example, the material of the doped semiconductor portion includes Si 1-x Ge x , and the material of the second channel region includes Si 1- y Ge y , and the absolute value of the difference between x and y is less than or equal to 15%.

[0013] In one example, the second etch stop structure is a P-type doped semiconductor region.

[0014] In one example, the etch inhibitor includes boron.

[0015] In a second aspect, the present invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device includes: First, provide a silicon-based substrate. Next, form a first etch stop structure and a second etch stop structure in the silicon-based substrate. The surface of the first etch stop structure is flush with the surface of the silicon-based substrate, and the material of the first etch stop structure is different from that of the silicon-based substrate. The second etch stop structure is doped with an etch inhibitor. Next, form an N-type ring gate transistor and a P-type ring gate transistor disposed on the silicon-based substrate at intervals along a direction parallel to the surface of the silicon-based substrate. The first channel region included in the N-type ring gate transistor and the second channel region included in the P-type ring gate transistor are made of the same material, and the materials of the first channel region and the second channel region are different from the material of the silicon-based substrate. The first etch stop structure is at least partially disposed in the silicon-based substrate below the second channel region. The second etch stop structure is at least partially disposed in the silicon-based substrate below the first channel region.

[0016] In one example, forming the first etch stop structure in the silicon-based substrate includes: forming a first mask structure on the silicon-based substrate. The first mask structure is used to expose at least a portion of the silicon-based substrate located below the second channel region. Next, under the protection of the first mask structure, form a groove in the silicon-based substrate. Next, form a first etch stop structure filled in the groove.

[0017] In one example, an ion implantation process is used to form the second etch stop structure in the silicon-based substrate.

[0018] In one example, an N-type gate-all-around transistor and a P-type gate-all-around transistor are formed on a silicon-based substrate at intervals in a direction parallel to the surface of the silicon-based substrate, including: forming a first fin structure and a second fin structure with the same structure and arranged at intervals on the silicon-based substrate. Along the thickness direction of the silicon-based substrate, both the first fin structure and the second fin structure include sacrificial layers and channel layers stacked alternately. Among the alternately stacked sacrificial layers and channel layers, the bottommost film layer is a sacrificial layer. The material of the first etch stop structure is different from that of the sacrificial layer. Next, a second mask structure is formed across the first fin structure and the second fin structure. Next, the portions of the first fin structure exposed outside the second mask structure are processed to form a first source / drain region included in the N-type gate-all-around transistor; and the portions of the second fin structure exposed outside the second mask structure are processed to form a second source / drain region included in the P-type gate-all-around transistor. Next, at least part of the second mask structure is removed. Next, under the etching blocking action of the first etch stop structure and the second etch stop structure, the remaining sacrificial layers in the first fin structure and the second fin structure are removed, so that the remaining channel layers in the first fin structure form a first channel region, and the remaining channel layers in the second fin structure form a second channel region.

[0019] In one example, the material of the sacrificial layer includes Si 1-z Ge z , where z is greater than or equal to 0 and less than or equal to 5%.

[0020] For the beneficial effects of the second aspect and its various implementation manners in the present invention, reference may be made to the analysis of the beneficial effects in the first aspect and its various implementation manners, which will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0022] Figure 1 A longitudinal cross-sectional schematic diagram of a partial structure of a semiconductor device provided for the related art;

[0023] Figure 2 A schematic structural diagram of a semiconductor device provided in an embodiment of the present invention during the manufacturing process Figure 1 ;

[0024] Figure 3 A schematic structural diagram of a semiconductor device provided in an embodiment of the present invention during the manufacturing process Figure 2 ;

[0025] Figure 4 A schematic structural diagram of a semiconductor device provided in an embodiment of the present invention during the manufacturing processFigure 3 ;

[0026] Figure 5 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 4 ;

[0027] Figure 6 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 5 ;

[0028] Figure 7 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 6 ;

[0029] Figure 8 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 7 ;

[0030] Figure 9 Parts (1) and (2) in are schematic diagrams of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 8 and Figure 9 ;

[0031] Figure 10 Parts (1) and (2) in are schematic diagrams of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 10 and Figure 10 One;

[0032] Figure 11 Parts (1) and (2) in are schematic diagrams of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 10 Two and Figure 10 Three;

[0033] Figure 12 Parts (1) and (2) in are schematic diagrams of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 10 Four and Figure 10 Five;

[0034] Figure 13 Parts (1) and (2) in are schematic diagrams of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 10 Six and Figure 10 Seven;

[0035] Figure 14 Parts (1) and (2) in are schematic diagrams of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 10 Eight and Figure 10 Nine;

[0036] Figure 15 Parts (1) and (2) in it are respectively schematic diagrams of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process. Figure 2 Ten and Figure 2 Eleven.

[0037] Reference numerals: 11 is a silicon-based substrate, 12 is an N-type ring-gate transistor, 13 is a P-type ring-gate transistor, 14 is a first channel region, 15 is a second channel region, 16 is a first etching stop structure, 17 is a second etching stop structure, 18 is a first source / drain region, 19 is a second source / drain region, 20 is a first gate stack structure, 21 is a second gate stack structure, 22 is a shallow trench isolation structure, 23 is an interlayer dielectric layer, 24 is a gate sidewall, 25 is a first mask structure, 26 is a groove, 27 is a first fin structure, 28 is a second fin structure, 29 is a sacrificial layer, 30 is a channel layer, 31 is a second mask structure, 32 is a notch. Detailed implementation manners

[0038] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are only exemplary and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present invention.

[0039] Various schematic structural diagrams according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, where for clearer expression, some details are enlarged and some details may be omitted. The shapes of various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are only exemplary. In practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art can design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0040] In the context of the present invention, when a layer / component is referred to as being "on" another layer / component, the layer / component can be directly on the other layer / component, or there can be an intermediate layer / component between them. Additionally, if a layer / component is "on" another layer / component in one orientation, then when the orientation is reversed, the layer / component can be "under" the other layer / component. In order to make the technical problems, technical solutions, and beneficial effects to be solved by the present invention clearer and more understandable, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0041] In addition, the terms "first" and "second" are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality of" means two or more, unless otherwise specifically defined. "Several" means one or more, unless otherwise specifically defined.

[0042] In the description of the present invention, it should be noted that, unless otherwise clearly specified and defined, the terms "mounted", "connected", and "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0043] The gate stack included in the gate-all-around transistor is formed not only on the top and sidewalls of the channel but also on the bottom of the channel. Therefore, compared with the planar transistor and the fin field-effect transistor, the gate-all-around transistor has advantages such as higher gate control ability. Based on this, when the transistors included in a semiconductor device adopt gate-all-around transistors, the operating performance of the semiconductor device can be improved.

[0044] In addition, in the actual application process, non-silicon semiconductor materials such as silicon-germanium or germanium may be used to fabricate the channel region included in the gate-all-around transistor on a silicon-based substrate to meet different working requirements. For example, compared with silicon materials, high-mobility semiconductor materials such as silicon-germanium or germanium have higher carrier mobilities. The channel region fabricated using the above high-mobility semiconductor materials has higher conduction characteristics, which is beneficial to improving the driving performance of the semiconductor device.

[0045] However, the yield of semiconductor devices including a channel region made of a non-silicon material formed by using existing manufacturing methods is relatively low, which is not conducive to improving the working performance of semiconductor devices. Specifically, since the material of the channel region manufactured by using the above non-silicon semiconductor material is different from that of the silicon-based substrate, there is a certain etching selectivity ratio between the two. Moreover, in the manufacturing process of a gate-all-around transistor, it is necessary to release the channel region by selectively etching a sacrificial layer. Therefore, the material of the sacrificial layer is different from that of the channel region. Based on this, in the actual manufacturing process, a material the same as or similar to the silicon material is usually selected to manufacture the sacrificial layer, so as to reduce the types of semiconductor materials used in the process of manufacturing semiconductor devices and the lattice difference between different film layers on the premise of ensuring the above-mentioned selective etching, which is conducive to improving the yield and formation quality of semiconductor devices. However, when the material of the sacrificial layer is the same as or similar to that of the silicon-based substrate, as Figure 1 shown, in the process of selectively etching the sacrificial layer to release the channel region, the etchant will not only remove the sacrificial layer, but also affect the silicon-based substrate 11 with the same or similar material, thereby forming a notch 32 in the silicon-based substrate 11. Although the existence of this notch 32 can change the parasitic channel leakage in the gate-all-around transistor, it will also increase the parasitic capacitance of the gate-all-around transistor, affecting the frequency characteristics of the gate-all-around transistor.

[0046] Regarding the above technical problems, those skilled in the art can prevent the appearance of notches during the release of the channel region by introducing a bottom dielectric isolation technology, and can also prevent parasitic channel leakage. However, the process of this technical solution is relatively complex and there is also a self-heating risk, which is not conducive to improving the working performance of semiconductor devices.

[0047] To solve the above technical problems, an embodiment of the present invention provides a semiconductor device and a manufacturing method thereof. Among them, in the semiconductor device provided by the embodiment of the present invention, at least a first etching barrier structure is provided in the silicon-based substrate located below the second channel region, and at least a second etching barrier structure is provided in the silicon-based substrate located below the first channel region. Moreover, the surface of the first etching barrier structure is flush with the surface of the silicon-based substrate, and the material of the first etching barrier structure is different from that of the silicon-based substrate. Moreover, the second etching barrier structure is doped with an etching inhibitor so that the two have an etching barrier effect on the etchant during the etching of the sacrificial layer, preventing notches from appearing in the directions of the first channel region and the second channel region after they are released, reducing the parasitic capacitance of the semiconductor device, and improving the working performance of the semiconductor device.

[0048] In a first aspect, an embodiment of the present invention provides a semiconductor device. As Figure 15As shown, the semiconductor device includes: a silicon-based substrate 11, an N-type surrounding gate transistor 12, a P-type surrounding gate transistor 13, a first etch stop structure 16, and a second etch stop structure 17. The N-type surrounding gate transistor 12 and the P-type surrounding gate transistor 13 are disposed on the silicon-based substrate 11 at intervals in a direction parallel to the surface of the silicon-based substrate 11. The first channel region 14 included in the N-type surrounding gate transistor 12 and the second channel region 15 included in the P-type surrounding gate transistor 13 are made of the same material, and the materials of the first channel region 14 and the second channel region 15 are different from the material of the silicon-based substrate 11. The first etch stop structure 16 is at least partially disposed in the silicon-based substrate 11 under the second channel region 15. The surface of the first etch stop structure 16 is flush with the surface of the silicon-based substrate 11, and the material of the first etch stop structure 16 is different from that of the silicon-based substrate 11. The second etch stop structure 17 is at least partially disposed in the silicon-based substrate 11 under the first channel region 14. The second etch stop structure 17 is doped with an etch inhibitor.

[0049] In the case of adopting the above technical solution, in the semiconductor device provided by the embodiment of the present invention, the first channel region included in the N-type surrounding gate transistor and the second channel region included in the P-type surrounding gate transistor are made of the same material. In this case, in the actual manufacturing process, as Figures 2 to 15 shown, the first channel region 14 and the second channel region 15 can be simultaneously manufactured by using the same process and based on the same channel layer 30, so as to improve the manufacturing efficiency of the semiconductor device and reduce the manufacturing cost of the semiconductor device. Secondly, the materials of the first channel region 14 and the second channel region 15 are different from the material of the silicon-based substrate 11. At this time, corresponding semiconductor materials can be selected to manufacture the first channel region 14 and the second channel region 15 according to different actual application scenarios, so as to improve the applicability of the semiconductor device provided by the embodiment of the present invention in different application scenarios. For example: non-silicon semiconductor materials such as silicon-germanium or germanium can be used to manufacture the first channel region 14 and the second channel region 15 to improve the conduction performance of the first channel region 14 and the second channel region 15. In addition, as Figure 15As shown in the figure, the semiconductor device provided by the embodiment of the present invention further includes a first etching stop structure 16 at least partially disposed in the silicon-based substrate 11 under the second channel region 15, and a second etching stop structure 17 at least partially disposed in the silicon-based substrate 11 under the first channel region 14. Among them, the surface of the first etching stop structure 16 is flush with the surface of the silicon-based substrate 11, and the material of the first etching stop structure 16 is different from that of the silicon-based substrate 11. At this time, the first etching stop structure 16 can have a certain etching selectivity ratio with the silicon-based substrate 11 at least through the difference in material types. And the second etching stop structure 17 is doped with an etching inhibitor. Based on this, even in the actual manufacturing process, if the material of the sacrificial layer 29 selected for releasing the first channel region 14 and the second channel region 15 is the same as or similar to the material of the silicon-based substrate 11, the first etching stop structure 16 can also have an etching blocking effect on the etchant during the etching of the sacrificial layer 29 through the difference in its own material and the doping of the etching inhibitor in the second etching stop structure 17, preventing notches from appearing in the directions of the first channel region 14 and the second channel region 15 after releasing them, reducing the parasitic capacitance of the semiconductor device, and improving the working performance of the semiconductor device.

[0050] In the actual application process, the embodiment of the present invention does not specifically limit the type of the silicon-based substrate, which can be a silicon substrate or a silicon-on-insulator substrate including a silicon substrate, etc.

[0051] For N-type and P-type gate-all-around transistors, the embodiment of the present invention does not specifically limit the number and distribution of N-type and P-type gate-all-around transistors, as long as the N-type and P-type gate-all-around transistors are arranged on the silicon-based substrate at intervals in a direction parallel to the surface of the silicon-based substrate.

[0052] In terms of structure, as Figure 15 shown in part (1) of the figure, the N-type gate-all-around transistor 12 may include a first channel region 14, a first source / drain region 18, and a first gate stack structure 20. The first channel region 14 is disposed between the first source / drain regions 18, and both ends of the first channel region 14 are electrically connected to the first source / drain regions 18 respectively. The first channel region 14 may include at least one layer of nanostructures, and each layer of nanostructures has a gap with the silicon-based substrate 11. When the first channel region 14 includes multiple layers of nanostructures, different layers of nanostructures are spaced apart in the thickness direction of the silicon-based substrate 11. The first gate stack structure 20 surrounds the outer periphery of each layer of nanostructures included in the first channel region 14. The first gate stack structure 20 may include a first gate dielectric layer and a first gate electrode. The first gate dielectric layer at least surrounds the outer periphery of each layer of nanostructures included in the first channel region 14. The first gate electrode is disposed on the first gate dielectric layer.

[0053] Among them, the material of the first source / drain region can include any semiconductor material such as silicon, silicon germanium, or germanium, as long as it can be applied to the semiconductor device provided in the embodiments of the present invention. The material of the first channel region can include any semiconductor material different from the silicon-based substrate. The material of the first gate dielectric layer can include any insulating material such as HfO2, ZrO2, TiO2, or Al2O3. The material of the first gate can include any conductive material such as TiN, TaN, or TiSiN.

[0054] As for the P-type gate-all-around transistor, as shown in part (2) of Figure 15 the P-type gate-all-around transistor 13 can include a second channel region 15, second source / drain regions 19, and a second gate stack structure 21. The second channel region 15 is disposed between the second source / drain regions 19, and both ends of the second channel region 15 are electrically connected to the second source / drain regions 19 respectively. The second channel region 15 can include at least one layer of nanostructures, and there is a gap between each layer of nanostructures and the silicon-based substrate 11. When the second channel region 15 includes multiple layers of nanostructures, different layers of nanostructures are spaced apart along the thickness direction of the silicon-based substrate 11. The second gate stack structure 21 surrounds the outer periphery of each layer of nanostructures included in the second channel region 15. The second gate stack structure 21 can include a second gate dielectric layer and a second gate. The second gate dielectric layer at least surrounds the outer periphery of each layer of nanostructures included in the second channel region 15. The second gate is disposed on the second gate dielectric layer.

[0055] In addition, the materials of the respective structures in the P-type gate-all-around transistor can refer to the materials of the corresponding structures included in the N-type gate-all-around transistor in the foregoing text, and will not be elaborated herein. Specifically, the material of the first source / drain region can be the same as or different from the material of the second source / drain region. The material of the first gate stack structure can be the same as or different from the material of the second gate stack structure.

[0056] The materials of the first channel region and the second channel region can be set according to actual needs and are not specifically limited herein. Exemplarily, the materials of the first channel region and the second channel region can include silicon germanium or germanium. At this time, the germanium content in the materials of the first channel region and the second channel region can be determined according to the performance requirements of the semiconductor device in the actual application scenario.

[0057] For the first etch stop structure, in terms of the formation position, the first etch stop structure can be disposed only in the silicon-based substrate under the second channel region. Or, as shown in Figure 15As shown in part (2) of the figure, the first etching stop structure 16 can also be disposed within the silicon-based substrate 11 below the second channel region 15 and the second source / drain region 19. Alternatively, the setting range of the first etching stop structure 16 within the silicon-based substrate 11 can also be larger than the orthographic projection range of the P-type gate-all-around transistor 13 on the silicon-based substrate 11, so as to reduce the process precision requirements for manufacturing the first etching stop structure 16 and reduce the manufacturing difficulty and yield of the semiconductor device.

[0058] In terms of materials, the material of the first etching stop structure can include any material different from the silicon-based substrate, as long as it can be applied to the semiconductor device provided by the embodiments of the present invention.

[0059] Exemplarily, the material of the first etching stop structure includes a semiconductor material.

[0060] Wherein, when the material of the first etching stop structure includes a semiconductor material, the conduction type of the first etching stop structure can be intrinsic type to reduce the parasitic channel leakage of the P-type gate-all-around transistor and further improve the working performance of the semiconductor device. Alternatively, the first etching stop structure can also include a doped semiconductor portion, and the conduction type of the doped semiconductor portion is N-type to improve the applicability of the semiconductor device in different application scenarios.

[0061] Wherein, when the first etching stop structure includes a doped semiconductor portion, the doping concentration of the N-type impurity in the doped semiconductor portion can be set according to actual needs and is not specifically limited herein. For example: the doping concentration of the N-type impurity in the doped semiconductor portion can be greater than or equal to 1E18 cm -3 and less than or equal to 1E19 cm -3 .

[0062] When the material of the first etching stop structure includes a semiconductor material, the type of the semiconductor material for manufacturing the first etching stop structure can be the same as or similar to the material of the second channel region, so as to reduce the type of the semiconductor material used in the process of manufacturing the semiconductor device and reduce the lattice difference between different film layers while ensuring that the above etching stop effect can be achieved, which is beneficial to further improving the yield and formation quality of the semiconductor device.

[0063] Exemplarily, taking the first etching stop structure including a doped semiconductor portion as an example for illustration: the material of the doped semiconductor portion can include Si 1-x Ge x , the material of the second channel region can include Si 1-y Ge y , and the absolute value of the difference between x and y can be less than or equal to 15%. Wherein, both x and y are greater than 0 and less than or equal to 1.

[0064] As for the thickness of the first etch stop structure, it can be determined according to the type of material of the first etch stop structure and the requirements for the etch stopping effect of the first etch stop structure in the actual application scenario, and no specific limitation is made here.

[0065] Exemplarily, the thickness of the doped semiconductor portion can be greater than or equal to 15 nm and less than or equal to 50 nm. For example, the thickness of the doped semiconductor portion can be 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, or 50 nm, etc.

[0066] For the second etch stop structure, in terms of the formation position, the second etch stop structure can be disposed only in the silicon-based substrate under the first channel region. Or, as Figure 15 shown in part (1) of, the second etch stop structure 17 can also be disposed in the silicon-based substrate 11 under the first channel region 14 and the first source / drain region 18. Alternatively, the setting range of the second etch stop structure 17 in the silicon-based substrate 11 can also be larger than the orthographic projection range of the N-type gate-all-around transistor 12 on the silicon-based substrate 11, so as to reduce the process precision requirements for manufacturing the second etch stop structure 17 and reduce the manufacturing difficulty and yield of the semiconductor device.

[0067] In terms of the structure, the second etch stop structure can include a P-type doped semiconductor region. At this time, at least part of the second etch stop structure can be manufactured through the doping process, reducing the manufacturing difficulty of the semiconductor device.

[0068] As for the type of etch inhibitor doped in the second etch stop structure, it can be set according to the material of the sacrificial layer, the type of etchant used for selectively etching the sacrificial layer, and the actual application scenario. Exemplarily, the etch inhibitor can include P-type impurities (such as boron, etc.).

[0069] In some cases, such as Figure 8 and Figure 15As shown, the semiconductor device provided by an embodiment of the present invention may further include at least one of a shallow trench isolation structure 22, a gate sidewall 24, and an interlayer dielectric layer 23. Among them, the shallow trench isolation structure 22 is formed on the silicon-based substrate 11, used to define the active region of the silicon-based substrate 11, reduce the leakage risk, and further improve the yield and working performance of the semiconductor device. The above-mentioned gate sidewall 24 is disposed on both sides of the first gate stack structure 20 and the second gate stack structure 21 along the length direction to reduce the leakage between the first gate stack structure 20 and the second gate stack structure 21 and other conductive structures. The above-mentioned interlayer dielectric layer 23 is disposed on the N-type gate-all-around transistor 12 and the P-type gate-all-around transistor 13, and the top of the interlayer dielectric layer 23 is flush with the tops of the first gate stack structure 20 and the second gate stack structure 21 respectively, so that the first source / drain region 18 and the second source / drain region 19 are not affected by the etching and cleaning operations for removing at least part of the second mask structure and the sacrificial layer, thereby improving the yield of the semiconductor device.

[0070] As for the materials of the shallow trench isolation structure, the gate sidewall, and the interlayer dielectric layer, it may include any one of insulating materials such as silicon oxide, silicon oxynitride, or silicon nitride oxynitride, and specific limitations are not made here.

[0071] In a second aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor device. The manufacturing process will be described below according to Figures 2 to 15 the perspective view or cross-sectional view of the operations shown. Specifically, the method for manufacturing the semiconductor device includes the following steps:

[0072] First, a silicon-based substrate is provided. The type of the silicon-based substrate can refer to the foregoing, and details are not described here again.

[0073] Next, as Figures 2 to 5 shown, a first etching stop structure 16 and a second etching stop structure 17 are formed in the silicon-based substrate 11. The surface of the first etching stop structure 16 is flush with the surface of the silicon-based substrate 11, and the material of the first etching stop structure 16 is different from that of the silicon-based substrate 11. The second etching stop structure 17 is doped with an etching inhibitor.

[0074] Among them, the specific structures and materials of the above-mentioned first etching stop structure and second etching stop structure, as well as information such as the type of the etching inhibitor, can refer to the foregoing, and details are not described here again.

[0075] As for the manufacturing process of the first etching stop structure and the second etching stop structure, it can be determined according to their specific structures, and specific limitations are not made here.

[0076] Exemplarily, forming the first etching stop structure in the silicon-based substrate may include the steps: as Figure 3As shown, at least processes such as photolithography are adopted to form a first mask structure 25 on the silicon-based substrate 11. The first mask structure 25 is used to expose at least the part of the silicon-based substrate 11 located below the second channel region 15. Specifically, the first mask structure 25 can be a photoresist mask or a hard mask structure made of materials such as silicon nitride. The range of the silicon-based substrate 11 exposed by the first mask structure 25 is the same as the range of the first etch stop structure 16 formed subsequently within the silicon-based substrate 11. Therefore, the mask pattern of the first mask structure 25 can be determined according to the range of the first etch stop structure 16 described above, which will not be elaborated here. Next, as Figure 4 shown, under the protection of the first mask structure 25, processes such as dry etching or wet etching are adopted to form a groove 26 within the silicon-based substrate 11. Among them, when the groove 26 is formed by processes such as dry etching, an oxide layer may be formed on the surface of the groove 26. At this time, the wet etching process can be used to remove this oxide layer. Next, as Figure 5 shown, processes such as epitaxy and planarization can be adopted to form the first etch stop structure 16 filled in the groove.

[0077] In one example, as Figure 2 shown, the ion implantation process can be adopted to form a second etch stop structure 17 within the silicon-based substrate 11.

[0078] It should be noted that the embodiments of the present invention do not specifically limit the sequence of forming the first etch stop structure and the second etch stop structure within the silicon-based substrate. It can be to form the first etch stop structure first and then the second etch stop structure. Or, it can also be to form the second etch stop structure first and then the first etch stop structure.

[0079] Next, as Figures 6 to 15 shown, N-type gate-all-around transistors 12 and P-type gate-all-around transistors 13 are formed on the silicon-based substrate 11 at intervals along the direction parallel to the surface of the silicon-based substrate 11. The first channel region 14 included in the N-type gate-all-around transistor 12 and the second channel region 15 included in the P-type gate-all-around transistor 13 are made of the same material, and the materials of the first channel region 14 and the second channel region 15 are different from the material of the silicon-based substrate 11. The first etch stop structure 16 is at least partially disposed within the silicon-based substrate 11 located below the second channel region 15. The second etch stop structure 17 is at least partially disposed within the silicon-based substrate 11 located below the first channel region 14.

[0080] Among them, information such as the structures and materials of the N-type gate-all-around transistor and the P-type gate-all-around transistor can be referred to the above, which will not be elaborated here. In addition, the embodiments of the present invention do not specifically limit the manufacturing processes of the N-type gate-all-around transistor and the P-type gate-all-around transistor, which can be determined according to their structures.

[0081] Exemplarily, forming the N-type and P-type gate-all-around transistors disposed on the silicon-based substrate at intervals in a direction parallel to the surface of the silicon-based substrate may include the steps:

[0082] As Figure 6 and Figure 7 shown, first fin structures 27 and second fin structures 28 that are identical in structure and disposed at intervals are formed on the silicon-based substrate 11. Along the thickness direction of the silicon-based substrate 11, both the first fin structures 27 and the second fin structures 28 include sacrificial layers 29 and channel layers 30 that are alternately stacked. Among the alternately stacked sacrificial layers 29 and channel layers 30, the film layer at the bottom layer is the sacrificial layer 29. The material of the first etch stop structure 16 is different from the material of the sacrificial layer 29.

[0083] Specifically, the above-mentioned channel layers are used to fabricate the first channel region and the second channel region. Therefore, the materials of the channel layers included in the first fin structures and the channel layers included in the second fin structures may refer to the materials of the first channel region and the second channel region described above, which will not be elaborated here. Secondly, the number of layers of the channel layers included in the first fin structures and the channel layers included in the second fin structures may refer to the number of layers of the nanostructures included in the first channel region and the second channel region described above.

[0084] As for the sacrificial layer, the first channel region and the second channel region will be released by removing part of the sacrificial layer subsequently. Therefore, the thickness of the sacrificial layer can be determined according to the spacing between different nanostructures in the first channel region and the second channel region and the spacing between the nanostructures and the silicon-based substrate in the actual application scenario. As for the material of the sacrificial layer, the material of the sacrificial layer may be the same as or similar to the material of the silicon-based substrate.

[0085] Exemplarily, the material of the sacrificial layer may include Si 1-z Ge z , where z is greater than or equal to 0 and less than or equal to 5%. For example: the material of the sacrificial layer may include Si, Si 0.95 Ge 0.05 or Si 0.098 Ge 0.002 etc.

[0086] In addition, among the alternately stacked sacrificial layers and channel layers, the film layer at the bottom layer is the sacrificial layer. The film layer at the top layer may be the sacrificial layer or the channel layer.

[0087] In the actual manufacturing process, as Figure 6 shown, processes such as epitaxy may be used to form the alternately stacked sacrificial layers 29 and channel layers 30 along the thickness direction of the silicon-based substrate 11. Then, processes such as photolithography and etching are used to pattern the above-mentioned sacrificial layers 29 and channel layers 30, as well as part of the silicon-based substrate 11, to form the first fin portion and the second fin portion. Next, asFigure 7 As shown, processes such as deposition and etching can be used to form a shallow trench isolation structure 22 for defining an active region between adjacent first fin portions and second fin portions. The top height of the shallow trench isolation structure 22 is less than or equal to the bottom height of the sacrificial layer 29 located at the bottom layer. Wherein, the portions of the first fin portion and the second fin portion exposed outside the shallow trench isolation structure 22 are the first fin-like structure 27 and the second fin-like structure 28 respectively.

[0088] Next, as Figure 8 and Figure 9 shown, a second mask structure 31 spanning the first fin-like structure 27 and the second fin-like structure 28 is formed.

[0089] In the actual manufacturing process, a mask material covering the silicon-based substrate can be formed by a deposition process. Then, processes such as photolithography and etching are used to selectively etch the mask material to form the above-mentioned second mask structure. As for the material of the second mask structure, it can be set according to actual needs as long as it can play a mask protection role in the subsequent process.

[0090] Exemplarily, the above-mentioned second mask structure may include a sacrificial gate. The material of the sacrificial gate may include materials such as polysilicon that are easy to remove. Secondly, the above-mentioned second mask structure may also include a gate oxide layer and a sacrificial gate located on the gate oxide layer. The material of the gate oxide layer may include materials such as silicon oxide. Or, the second mask structure may also include a sacrificial gate and gate sidewalls, and the gate sidewalls are located on both sides of the sacrificial gate along the length direction.

[0091] Next, as Figure 10 and Figure 11 shown, the portion of the first fin-like structure exposed outside the second mask structure 31 is processed to form the first source / drain region 18 included in the N-type surrounding gate transistor 12; and the portion of the second fin-like structure 28 exposed outside the second mask structure 31 is processed to form the second source / drain region 19 included in the P-type surrounding gate transistor 13.

[0092] In the actual manufacturing process, taking the formation of the first source / drain region as an example for illustration: Processes such as ion implantation can be used to directly dope the portion of the first fin-like structure exposed outside the second mask structure to form the first source / drain region. Or, processes such as wet etching or dry etching can also be used to selectively remove the portion of the first fin-like structure exposed outside the second mask structure; next, processes such as epitaxy are used to form the first source / drain region on both sides of the remaining first fin-like structure. Wherein, the formation method of the second source / drain region can refer to the formation process of the first source / drain region, which will not be elaborated here. In addition, the embodiments of the present invention do not specifically limit the manufacturing sequence of the first source / drain region and the second source / drain region, and can be set according to actual needs.

[0093] Next, as Figure 12 shown, processes such as deposition and planarization can be used to form an interlayer dielectric layer 23 on the silicon-based substrate 11. The top of the interlayer dielectric layer 23 is flush with the top of the second mask structure 31. The material of the interlayer dielectric layer 23 can be referred to the previous text and will not be elaborated here.

[0094] Next, as Figure 13 shown, processes such as dry etching or wet etching can be used to remove at least part of the second mask structure.

[0095] It should be noted that the removal range of the second mask structure can be determined according to its own structure. For example: when the second mask structure only includes a sacrificial gate, or only includes a sacrificial gate and a gate oxide layer, the second mask structure can be completely removed. When the second mask structure includes a sacrificial gate and a gate sidewall, only part of the second mask structure can be removed.

[0096] Next, as Figure 14 shown, processes such as dry etching or wet etching can be used. Under the etching blocking effect of the first etching blocking structure 16 and the second etching blocking structure 17, the remaining sacrificial layers in the first fin structure and the second fin structure are removed, so that the remaining channel layer in the first fin structure forms a first channel region 14, and the remaining channel layer in the second fin structure forms a second channel region 15.

[0097] Next, as Figure 15 shown, processes such as atomic layer deposition are used to form a first gate stack structure 20 included in the N-type surrounding gate transistor 12 and a second gate stack structure 21 included in the P-type surrounding gate transistor 13.

[0098] Among them, the specific structures and materials of the first gate stack structure and the second gate stack structure can be referred to the previous text and will not be elaborated here.

[0099] It should be noted that the above N-type surrounding gate transistor and P-type surrounding gate transistor can be formed in various ways. How to form the above N-type surrounding gate transistor and P-type surrounding gate transistor is not the main feature of the present invention. Therefore, in this specification, only a brief introduction is given so that those of ordinary skill in the art can easily implement the present invention. Those of ordinary skill in the art can fully conceive other ways to fabricate the above N-type surrounding gate transistor and P-type surrounding gate transistor.

[0100] For the beneficial effects of the second aspect and its various implementation manners in the embodiments of the present invention, reference can be made to the analysis of the beneficial effects in the first aspect and its various implementation manners, which will not be elaborated here.

[0101] In the above description, technical details such as the composition and etching of each layer are not elaborated in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of the desired shape. Additionally, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as the methods described above. Moreover, although the embodiments are described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0102] The embodiments of the present invention have been described above. However, these embodiments are merely for clearer illustration and not for limiting the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: Silicon-based substrate, An N-type gate-all-around transistor and a P-type gate-all-around transistor are arranged on the silicon-based substrate at intervals along a direction parallel to the surface of the silicon-based substrate; a first channel region included in the N-type gate-all-around transistor and a second channel region included in the P-type gate-all-around transistor are made of the same material, and a material of the first channel region and a material of the second channel region are different from a material of the silicon-based substrate; a first etch stop structure, at least partially disposed in the silicon-based substrate below the second channel region; The surface of the first etch stop structure is flush with the surface of the silicon-based substrate, and the first etch stop structure and the silicon-based substrate are made of different materials; and a second etch barrier structure, at least partially disposed in the silicon-based substrate below the first channel region; the second etch barrier structure is doped with an etch inhibitor.

2. The semiconductor device according to claim 1, wherein: The first etch stop structure includes a doped semiconductor portion, and the conductivity type of the doped semiconductor portion is N type.

3. The semiconductor device according to claim 2, characterized in that The material of the doped semiconductor portion is the same as that of the second channel region; And / or, the thickness of the doped semiconductor portion is greater than or equal to 15 nm and less than or equal to 50 nm; and / or, the doping concentration of the N-type impurities in the doped semiconductor portion is greater than or equal to 1E18 cm -3 , and less than or equal to 1E19cm -3 .

4. The semiconductor device according to claim 2, characterized in that The material of the doped semiconductor portion includes Si 1- x Ge x , the material of the second channel region includes Si 1-y Ge y , the absolute value of the difference between x and y is less than or equal to 15%.

5. The semiconductor device according to claim 1, wherein: The second etch stop structure is a P-type doped semiconductor region; and / or, the etch inhibitor comprises boron; And / or, the second etch stop structure is integrally continuous with the silicon-based substrate.

6. A method for manufacturing a semiconductor device, characterized in that: include: Provide a silicon-based substrate; forming a first etch stop structure and a second etch stop structure in the silicon-based substrate; The surface of the first etch barrier structure is flush with the surface of the silicon-based substrate, and the first etch barrier structure and the silicon-based substrate are made of different materials; the second etch barrier structure is doped with an etching inhibitor; An N-type gate-all-around transistor and a P-type gate-all-around transistor are formed on the silicon-based substrate and are spaced apart from each other in a direction parallel to the surface of the silicon-based substrate; a first channel region included in the N-type gate-all-around transistor and a second channel region included in the P-type gate-all-around transistor are made of the same material, and a material of the first channel region and a material of the second channel region are different from a material of the silicon-based substrate; The first etch stop structure is at least partially disposed in the silicon-based substrate below the second channel region; The second etch stop structure is at least partially disposed in the silicon-based substrate below the first channel region.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: Forming the first etch stop structure in the silicon-based substrate includes: forming a first mask structure on the silicon-based substrate; the first mask structure is used to expose at least a portion of the silicon-based substrate located below the second channel region; Under the protection of the first mask structure, forming a groove in the silicon-based substrate; The first etch stop structure filled in the groove is formed.

8. The method for manufacturing a semiconductor device according to claim 6, wherein: The second etching stop structure is formed in the silicon-based substrate by using an ion implantation process.

9. The method for manufacturing a semiconductor device according to claim 6, wherein: The forming of an N-type gate-all-around transistor and a P-type gate-all-around transistor spaced apart on the silicon-based substrate in a direction parallel to the surface of the silicon-based substrate comprises: A first fin structure and a second fin structure having the same structure and arranged at intervals are formed on a silicon-based substrate; along the thickness direction of the silicon-based substrate, the first fin structure and the second fin structure both include sacrificial layers and channel layers that are alternately stacked; among the sacrificial layers and channel layers that are alternately stacked, the film layer located at the bottom is the sacrificial layer; the material of the first etch stop structure is different from the material of the sacrificial layer; forming a second mask structure spanning the first fin structure and the second fin structure; Processing the portion of the first fin structure exposed outside the second mask structure to form a first source / drain region included in the N-type all-around gate transistor; and processing the portion of the second fin structure exposed outside the second mask structure to form a second source / drain region included in the P-type all-around gate transistor; removing at least a portion of the second mask structure; Under the etching blocking effect of the first etching blocking structure and the second etching blocking structure, the remaining sacrificial layer in the first fin-shaped structure and the second fin-shaped structure is removed so that the remaining channel layer in the first fin-shaped structure forms the first channel region, and the remaining channel layer in the second fin-shaped structure forms the second channel region.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: The material of the sacrificial layer includes Si 1-z Ge z , z is greater than or equal to 0 and less than or equal to 5%.

Images