Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, relates to the technical field of semiconductors, and aims to facilitate the miniaturization of the semiconductor device and improve the integration level of the semiconductor device. The semiconductor device includes a semiconductor substrate, a first transistor, a second transistor, and a first isolation structure. The first isolation structure is arranged between the source and drain regions included in the second transistor and the source and drain regions and / or channel regions included in the first transistor. Wherein the length of the active structure included in the second transistor is smaller than that of the active structure included in the first transistor, and / or the width of the active structure included in the second transistor is smaller than that of the active structure included in the first transistor. At least one pair of two adjacent source-drain contact structures which respectively belong to the first transistor and the second transistor and are positioned on the same side along the length direction of the gate stack structure are arranged at intervals, and the source-drain contact structures included in the first transistor and the second transistor are positioned in a vertical space of an area in which the first transistor and the second transistor are positioned.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular, to a semiconductor device and a manufacturing method thereof. Background Art

[0002] A three-dimensional stacked complementary transistor includes an N-type transistor and a P-type transistor stacked vertically, eliminating the lateral pitch between the N-type transistor and the P-type transistor, which allows for further increasing the effective channel width, thus facilitating the improvement of the working performance and integration degree of the semiconductor device.

[0003] However, the source-drain contact structure of the existing three-dimensional stacked complementary transistor needs to occupy additional wiring space, which is not conducive to the miniaturization of the semiconductor device. Summary of the Invention

[0004] The purpose of the present invention is to provide a semiconductor device and a manufacturing method thereof. By making the length and / or width of the active structure included in the second transistor be respectively smaller than the length and / or width of the active structure included in the first transistor, the source-drain contact structures included in the first transistor and the second transistor are both located in the vertical space of the region where the first transistor and the second transistor are located, without occupying additional layout area, which is conducive to the miniaturization of the semiconductor device and improves the integration degree of the semiconductor device.

[0005] To achieve the above purpose, in a first aspect, the present invention provides a semiconductor device, which includes: a semiconductor substrate, a first transistor, a second transistor, and a first isolation structure. The first transistor and the second transistor are arranged at intervals in the thickness direction of the semiconductor substrate on the semiconductor substrate, and the second transistor is located above the first transistor. The first isolation structure is disposed between the source-drain region included in the second transistor and the source-drain region and / or channel region included in the first transistor. Wherein, along the length direction of the gate stack structure included in the first transistor and the second transistor, the length of the active structure included in the second transistor is smaller than the length of the active structure included in the first transistor, and / or, along the width direction of the channel region included in the first transistor and the second transistor, the width of the active structure included in the second transistor is smaller than the width of the active structure included in the first transistor. The active structure includes a channel region and source-drain regions located on both sides of the channel region along the length direction. At least a pair of adjacent two source-drain contact structures belonging to the first transistor and the second transistor and located on the same side along the length direction of the gate stack structure are arranged at intervals, and the source-drain contact structures included in the first transistor and the second transistor are both located in the vertical space of the region where the first transistor and the second transistor are located.

[0006] In the case of adopting the above technical solution, the first transistor and the second transistor included in the semiconductor device are spaced apart along the thickness direction of the semiconductor substrate, and the first isolation structure is disposed between the source-drain regions included in the second transistor and the source-drain regions and / or channel regions included in the first transistor to prevent leakage. Obviously, the first transistor and the second transistor can form a three-dimensional stacked complementary transistor (CFET device) to improve the integration degree of the semiconductor device.

[0007] In addition, when the length of the active structure included in the second transistor is less than the length of the active structure included in the first transistor along the length direction of the gate stack structures included in the first transistor and the second transistor, at least a pair of two adjacent source-drain contact structures that respectively belong to the first transistor and the second transistor and are located on the same side along the length direction of the gate stack structure can be spaced apart at least along the length direction of the gate stack structure by the length difference between the active structures included in the first transistor and the second transistor. In other words, it can be made such that the source-drain contact structures included in the first transistor and the second transistor are both located in the vertical space of the regions where the first transistor and the second transistor are located, and there is no need to adopt a structure such as an L-shaped structure to physically insulate these two spaced-apart source-drain contact structures, which is beneficial to the miniaturization of the semiconductor device. Similarly, when the width of the active structure included in the second transistor is less than the width of the active structure included in the first transistor along the width direction of the channel regions included in the first transistor and the second transistor, it can be made such that they are spaced apart at least along the width direction of the channel region by the width difference between the active structures included in the first transistor and the second transistor. This is also beneficial to making the layout and routing of all the source-drain contact structures included in the first transistor and the second transistor not additionally occupy the layout area outside the device on the premise of physically insulating these two source-drain contact structures, thereby improving the integration degree of the semiconductor device.

[0008] In one example, in the first transistor and the second transistor, two source-drain contact structures that are located on the same side along the length direction of the gate stack structure and are spaced apart both extend in a direction perpendicular to the surface of the semiconductor substrate.

[0009] In one example, the semiconductor device further includes an insulating dielectric layer. The insulating dielectric layer covers the second transistor and the part of the first transistor that is exposed outside the second transistor. And the source-drain contact structures corresponding to the first transistor and the second transistor include a first connection portion; the first connection portion is located above one of the source-drain regions included in the first transistor and is electrically connected to one of the source-drain regions included in the first transistor and one of the source-drain regions included in the second transistor that are located on the same side along the length direction of the gate stack structure at the same time. The first connection portion penetrates through the part of the insulating dielectric layer that covers above one of the source-drain regions included in the first transistor and is at the same setting height as the second transistor.

[0010] In one example, the first connection portion extends in a direction perpendicular to the surface of the semiconductor substrate.

[0011] In one example, the semiconductor device further includes an insulating dielectric layer. The insulating dielectric layer covers the second transistor and the portion of the first transistor that is exposed outside the second transistor. Moreover, the source-drain contact structures corresponding to the first transistor and the second transistor include a second connection portion and a third connection portion. The second connection portion and the third connection portion are disposed on the same side of the first transistor and the second transistor along the length direction of the gate stack structure, and the second connection portion and the third connection portion are spaced apart. The second connection portion penetrates through the portion of the insulating dielectric layer that covers the other one of the source-drain regions included in the first transistor and is at the same setting height as the second transistor, and is electrically connected to the other one of the source-drain regions included in the first transistor. The third connection portion penetrates through the portion of the insulating dielectric layer that covers the other one of the source-drain regions included in the second transistor, and is electrically connected to the other one of the source-drain regions included in the second transistor.

[0012] In one example, when the length of the active structure included in the second transistor is less than the length of the active structure included in the first transistor, the length of the channel region included in the second transistor is less than the length of the channel region included in the first transistor, and / or the length of the source-drain region included in the second transistor is less than or equal to the length of the source-drain region included in the first transistor.

[0013] In one example, the midline of the channel region included in the second transistor along the length direction of the gate stack structure coincides with the midline of the channel region included in the first transistor along the length direction of the gate stack structure.

[0014] In one example, one side wall of the channel region included in the second transistor along the width direction is aligned with one side wall of the channel region included in the first transistor along the width direction. Alternatively, the midline of the channel region included in the second transistor along the width direction coincides with the midline of the channel region included in the first transistor along the width direction.

[0015] In one example, the second transistor is a comb-shaped field effect transistor.

[0016] In one example, the first transistor is a gate-all-around transistor. The channel region included in the second transistor has multiple layers of nanostructures that are spaced apart along the thickness direction of the semiconductor substrate, and a connection portion disposed on one side of the multiple layers of nanostructures along the width direction. Moreover, the number of layers of nanostructures included in the channel region of the second transistor is less than the number of layers of nanostructures included in the channel region of the first transistor.

[0017] In one example, the first transistor and / or the second transistor is a gate-all-around transistor.

[0018] In one example, the semiconductor device further includes a second isolation structure. The second isolation structure is disposed between the gate stack structure included in the first transistor and the gate stack structure included in the second transistor.

[0019] In a second aspect, the present invention further provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device includes: First, a fin structure is formed on a semiconductor substrate. Along the thickness direction of the semiconductor substrate, the fin structure includes a first fin portion, a semiconductor isolation layer, and a second fin portion arranged in sequence. Next, the second fin portion is selectively etched so that the length of the remaining second fin portion is less than the length of the first fin portion, and / or the width of the remaining second fin portion is less than the width of the first fin portion. Next, a first transistor is formed based on the first fin portion by using semiconductor manufacturing processes. Next, the semiconductor isolation layer is removed; and a first isolation structure is formed at least on the source / drain regions included in the first transistor. Next, a second transistor is formed based on the second fin portion by using semiconductor manufacturing processes. Next, a source / drain contact structure is formed in electrical contact with the source / drain regions included in the first transistor and the second transistor. At least a pair of two adjacent source / drain contact structures that belong to the first transistor and the second transistor respectively and are located on the same side along the length direction of the gate stack structure are spaced apart, and the source / drain contact structures included in the first transistor and the source / drain contact structures included in the second transistor are both located in the vertical space of the regions where the first transistor and the second transistor are located.

[0020] In one example, forming the first transistor, the first isolation structure, and the second transistor includes: forming a mask structure across the fin structure; and etching away the portion of the fin structure exposed outside the mask structure. Next, source / drain regions included in the first transistor are epitaxially formed on both sides of the remaining first fin portion. Next, a first isolation structure is formed at least on the source / drain regions included in the first transistor. Next, source / drain regions included in the second transistor are epitaxially formed on both sides of the remaining second fin portion. Next, the mask structure is removed; and the remaining first fin portion and the remaining second fin portion are respectively formed into channel regions. Next, a gate stack structure is formed on the outer periphery of the channel regions.

[0021] In one example, after forming the fin structure on the semiconductor substrate and before forming the mask structure across the fin structure, the second fin portion is selectively etched so that the width of the remaining second fin portion is less than the width of the first fin portion.

[0022] In one example, after etching away the portion of the fin structure exposed outside the mask structure and before epitaxially forming the source / drain regions included in the second transistor on both sides of the remaining second fin portion, the second fin portion is selectively etched so that the length of the remaining second fin portion is less than the length of the first fin portion.

[0023] In one example, the second fin portion includes at least one layer of semiconductor stack, and each layer of semiconductor stack includes a sacrificial layer and a channel layer located on the sacrificial layer. Moreover, after forming a fin structure on a semiconductor substrate and before selectively etching the second fin portion, the manufacturing method of the semiconductor device further includes: performing selective epitaxy on one side of the second fin portion in the width direction to form a connection portion. Each channel layer included in the second fin portion is electrically connected through the connection portion.

[0024] In one example, after forming a mask structure spanning the fin structure and before etching away the portion of the fin structure exposed outside the mask structure, the manufacturing method of the semiconductor device further includes: removing the remaining semiconductor isolation layer. Next, a second isolation structure is formed between the remaining first fin portion and the remaining second fin portion.

[0025] For the beneficial effects of the second aspect and its various implementation manners in the present invention, reference can be made to the analysis of the beneficial effects in the first aspect and its various implementation manners, which will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0027] Figure 1 is a schematic structural diagram of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 1 ;

[0028] Figure 2 is a schematic structural diagram of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 2 ;

[0029] Figure 3 is a schematic structural diagram of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 3 ;

[0030] Figure 4 is a schematic structural diagram of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 4 ;

[0031] Figure 5 is a schematic structural diagram of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 5 ;

[0032] Figure 6 is a schematic structural diagram of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 6 ;

[0033] Figure 7Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 7 ;

[0034] Figure 8 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 8 ;

[0035] Figure 9 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 9 ;

[0036] Figure 10 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 10 ;

[0037] Figure 11 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 11 One;

[0038] Figure 12 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 12 Two;

[0039] Figure 13 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 13 Three;

[0040] Figure 14 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 14 Four;

[0041] Figure 15 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 15 Five;

[0042] Figure 16 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 16 Six;

[0043] Figure 17 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 17 Seven;

[0044] Figure 18 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 18 Eight;

[0045] Figure 19 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 19 Nine;

[0046] Figure 20 Schematic of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 20 Ten;

[0047] Figure 21 Schematic of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 21 Eleven;

[0048] Figure 22 Schematic of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 22 Twelve;

[0049] Figure 23 Schematic of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 23 Thirteen;

[0050] Figure 24 Schematic of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 24 Fourteen;

[0051] Figure 25 Schematic of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 25 Fifteen;

[0052] Figure 26 Schematic of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 26 Sixteen;

[0053] Figure 27 Schematic of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 27 Seventeen;

[0054] Figure 28 Schematic of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 28 Eighteen;

[0055] Figure 29 Schematic of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 29 Nineteen;

[0056] Figure 30 Schematic of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 30 Ten;

[0057] Figure 31 Schematic of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 31 Eleven;

[0058] Figure 32 Structural schematic of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 32 Twelve;

[0059] Figure 33 Structural schematic of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure 33 Thirteen.

[0060] Reference numerals: 11 is a semiconductor substrate, 12 is a first transistor, 13 is a second transistor, 14 is a first isolation structure, 15 is a source / drain region, 16 is a channel region, 17 is a gate stack structure, 18 is a source / drain contact structure, 19 is a second isolation structure, 20 is a shallow trench isolation structure, 21 is an insulating dielectric layer, 22 is a fin structure, 23 is a first fin portion, 24 is a semiconductor isolation layer, 25 is a second fin portion, 26 is a mask structure, 27 is a gate sidewall, 28 is a sacrificial gate, 29 is a sacrificial layer, 30 is a channel layer, 31 is a connection portion, 32 is a first connection portion, 33 is a second connection portion, 34 is a third connection portion. Detailed implementation manners

[0061] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily obscuring the concepts of the present invention.

[0062] Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and in order to express more clearly, some details are enlarged and some details may be omitted. The shapes of various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary. In practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art can design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0063] In the context of the present invention, when a layer / component is referred to as being "on" another layer / component, the layer / component can be directly on the other layer / component, or there can be an intermediate layer / component between them. Additionally, if a layer / component is "on" another layer / component in one orientation, then when the orientation is reversed, the layer / component can be "under" the other layer / component. In order to make the technical problems, technical solutions, and beneficial effects to be solved by the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely used to explain the present invention and are not used to limit the present invention.

[0064] In addition, the terms "first" and "second" are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality of" means two or more unless otherwise specifically defined. "Several" means one or more unless otherwise specifically defined.

[0065] In the description of the present invention, it should be noted that unless otherwise clearly specified and limited, the terms "mounted", "connected" and "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0066] The three-dimensional stacked complementary transistor includes an N-type transistor and a P-type transistor stacked vertically, eliminating the lateral spacing between the N-type transistor and the P-type transistor, which allows for further increasing the effective channel width, thus facilitating the improvement of the working performance and integration degree of the semiconductor device.

[0067] However, in existing three-dimensional stacked complementary transistors, the channel regions and source / drain regions of the upper and lower transistors have the same length and width. In order to lead out at least a pair of adjacent source / drain contact structures included in the upper and lower transistors respectively, the source / drain contact structures need to adopt structures such as a quasi-L shape to prevent physical insulation between two adjacent source / drain contact structures on the same side. However, such a design requires additional layout area and is not conducive to the miniaturization of semiconductor devices. Although the introduction of the existing buried power rail BPR structure will reduce the area occupied by layout and wiring, the buried power rail technology requires additional steps such as bonding, increasing the manufacturing cost of semiconductor devices and being not conducive to the large-scale mass production of semiconductor devices.

[0068] To solve the above technical problems, an embodiment of the present invention provides a semiconductor device and a manufacturing method thereof. Among them, in the semiconductor device provided by the embodiment of the present invention, a first transistor and a second transistor are arranged at intervals in the thickness direction of a semiconductor substrate on the semiconductor substrate. Moreover, the length and / or width of the active structure included in the second transistor are respectively smaller than the length and / or width of the active structure included in the first transistor, so that the source / drain contact structures included in the first transistor and the second transistor are both located in the vertical space of the regions where the first transistor and the second transistor are located, without additional occupation of layout area, facilitating the miniaturization of semiconductor devices and improving the integration degree of semiconductor devices.

[0069] In a first aspect, embodiments of the present invention provide a semiconductor device. As Figures 27 to 33 shown, the semiconductor device includes: a semiconductor substrate 11, a first transistor 12, a second transistor 13, and a first isolation structure 14. The first transistor 12 and the second transistor 13 are arranged at intervals in the thickness direction of the semiconductor substrate 11 on the semiconductor substrate 11, and the second transistor 13 is located above the first transistor 12. The first isolation structure 14 is disposed between the source-drain region 15 included in the second transistor 13 and the source-drain region 15 and / or the channel region 16 included in the first transistor 12. Wherein, along the length direction of the gate stack structure 17 included in the first transistor 12 and the second transistor 13, the length of the active structure included in the second transistor 13 is less than the length of the active structure included in the first transistor 12, and / or, along the width direction of the channel region 16 included in the first transistor 12 and the second transistor 13, the width of the active structure included in the second transistor 13 is less than the width of the active structure included in the first transistor 12. The active structure includes a channel region 16 and source-drain regions 15 located on both sides of the channel region 16 along the length direction. At least a pair of adjacent two source-drain contact structures 18 belonging to the first transistor 12 and the second transistor 13 and located on the same side along the length direction of the gate stack structure 17 are arranged at intervals, and the source-drain contact structures 18 included in the first transistor 12 and the second transistor 13 are both located in the vertical space of the regions where the first transistor 12 and the second transistor 13 are located.

[0070] In the case of adopting the above technical solution, as Figures 27 to 33 shown, the first transistor 12 and the second transistor 13 included in the semiconductor device are distributed at intervals in the thickness direction of the semiconductor substrate 11, and the first isolation structure 14 is disposed between the source-drain region 15 included in the second transistor 13 and the source-drain region 15 and / or the channel region 16 included in the first transistor 12 to prevent leakage. Obviously, the first transistor 12 and the second transistor 13 can form a three-dimensional stacked complementary transistor (CFET device) to improve the integration of the semiconductor device. In addition, as Figures 27 to 33As shown, when the length of the active structure included in the second transistor 13 is less than the length of the active structure included in the first transistor 12 along the length direction of the gate stack structure 17 included in the first transistor 12 and the second transistor 13, at least a pair of two adjacent source-drain contact structures 18 that belong to the first transistor 12 and the second transistor 13 respectively and are located on the same side along the length direction of the gate stack structure 17 can be spaced apart at least along the length direction of the gate stack structure 17 due to the length difference between the active structures included in the first transistor 12 and the second transistor 13. In other words, it can be made such that the source-drain contact structures 18 included in the first transistor 12 and the second transistor 13 are both located within the vertical space of the regions where the first transistor 12 and the second transistor 13 are located, without the need to use structures such as an L-shaped structure to physically insulate these two spaced-apart source-drain contact structures 18, which is beneficial for the miniaturization of semiconductor devices. Similarly, when the width of the active structure included in the second transistor 13 is less than the width of the active structure included in the first transistor 12 along the width direction of the channel region 16 included in the first transistor 12 and the second transistor 13, it can be spaced apart at least along the width direction of the channel region 16 due to the width difference between the active structures included in the first transistor 12 and the second transistor 13, which is also beneficial for ensuring that the layout and wiring of all the source-drain contact structures 18 included in the first transistor 12 and the second transistor 13 do not additionally occupy the layout area outside the device perimeter on the premise of physically insulating these two source-drain contact structures 18, thereby improving the integration degree of semiconductor devices.

[0071] In actual application processes, the semiconductor substrate can be a semiconductor substrate such as a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a silicon-on-insulator substrate on which no structures are formed.

[0072] Exemplarily, the above-mentioned semiconductor substrate can also be a semiconductor substrate on which some structures are formed. For example: in the case of applying the semiconductor device provided by the embodiments of the present invention to semiconductor devices located in the second layer or higher layers in an integrated circuit, the above-mentioned semiconductor substrate can include a semiconductor substrate, lower-layer devices formed on the semiconductor substrate, and an interlayer dielectric layer for isolating the lower-layer devices, etc.

[0073] In some cases, as Figures 27 to 33 shown, the semiconductor device provided by the embodiments of the present invention may further include an insulating dielectric layer 21. The insulating dielectric layer 21 covers the second transistor 13 and the portion of the first transistor 12 that is exposed outside the second transistor 13, and the top of the insulating dielectric layer 21 is flush with the top of the gate stack structure 17 included in the second transistor 13 to protect the source-drain region 15 from the etching and cleaning operations for removing structures such as the sacrificial gate 28, thereby improving the yield of semiconductor devices.

[0074] As for the material of the insulating dielectric layer, it may include any one of insulating materials such as silicon oxide, silicon oxynitride, or silicon nitride oxynitride, and no specific limitation is made here.

[0075] For the first transistor and the second transistor, in terms of the device type, the embodiments of the present invention do not specifically limit the device types of the first transistor and the second transistor, as long as they can be formed on the semiconductor substrate.

[0076] Exemplarily, the first transistor and / or the second transistor may be a fin field effect transistor or a gate-all-around transistor.

[0077] Optionally, as Figures 27 to 32 shown, the first transistor 12 and the second transistor 13 may both be gate-all-around transistors to improve the gate control ability of the two, which is beneficial to improving the driving performance of the semiconductor device.

[0078] Optionally, as Figure 28 shown, the second transistor 13 may be a comb-shaped field effect transistor. At this time, the second transistor 13 further includes a connecting portion 31 for electrically connecting different layer nanostructures spaced apart along the thickness direction of the semiconductor substrate 11, which is beneficial to increasing the conduction area of the channel region 16 included in the second transistor 13 and improving the electrical performance of the second transistor 13. Based on this, the first transistor 12 is a gate-all-around transistor; the channel region 16 included in the second transistor 13 has multiple layer nanostructures spaced apart along the thickness direction of the semiconductor substrate 11, and a connecting portion 31 provided on one side of the multiple layer nanostructures along the width direction. And, the number of layers of the nanostructures included in the channel region 16 of the second transistor 13 may be less than the number of layers of the nanostructures included in the channel region 16 of the first transistor 12 to improve the vertical integration degree of the semiconductor device and facilitate the miniaturization of the semiconductor device.

[0079] Of course, in the case where the second transistor is a comb-shaped field effect transistor, the height of the channel region of the second transistor may also be equal to or greater than the height of the channel region of the first transistor. As for the heights of the channel regions included in the first transistor and the second transistor, they can be determined according to the requirements for the electrical characteristics of these two transistors in the actual application scenario, and no specific limitation is made here.

[0080] In terms of the structure, the specific structures of the first transistor and the second transistor can be set according to their own device types and actual requirements, and no specific limitation is made here.

[0081] Exemplarily, when the first transistor and / or the second transistor is a fin field-effect transistor, the fin field-effect transistor may include a channel region, source / drain regions, a gate stack structure, and source / drain contact structures. The source / drain regions are disposed on two sides of the channel region along the length direction, the gate stack structure is disposed on the top and sidewalls of the channel region. The source / drain contact structures are disposed above the source / drain regions and are electrically connected to the source / drain regions.

[0082] Exemplarily, when the first transistor and / or the second transistor is a gate-all-around transistor, the gate-all-around transistor may include a channel region, source / drain regions, a gate stack structure, and source / drain contact structures. The source / drain regions are disposed on two sides of the channel region along the length direction, the gate stack structure surrounds the outer periphery of the channel region. The source / drain contact structures are disposed above the source / drain regions and are electrically connected to the source / drain regions. Specifically, the channel region may include only one layer of nanostructures; or, as Figures 27 to 32 shown, the channel region 16 may also include multiple layers of nanostructures that are spaced apart along the thickness direction of the semiconductor substrate 11. The embodiments of the present invention do not specifically limit the number of layers of nanostructures in the channel region 16 included in the first transistor 12 and the second transistor 13. Specifically, the materials of the different layers of nanostructures included in the channel region 16 may be the same or different.

[0083] It should be noted that it may be that the source region included in the second transistor and the source region included in the first transistor are on the same side along the length direction of the gate stack structure; or, it may also be that the drain region included in the second transistor and the source region included in the first transistor are on the same side along the length direction of the gate stack structure.

[0084] In addition, as Figure 31 shown, in the first transistor 12 and the second transistor 13, each pair of adjacent two source / drain contact structures 18 on the same side along the length direction of the gate stack structure 17 are spaced apart. Or, as Figure 32 shown, in the first transistor 12 and the second transistor 13, only a pair of adjacent two source / drain contact structures 18 on the same side along the length direction of the gate stack structure 17 are spaced apart, while another pair of adjacent two source / drain contact structures 18 on the same side along the length direction of the gate stack structure 17 are electrically connected.

[0085] Exemplarily, as Figure 32 and Figure 33As shown, the source-drain contact structure 18 corresponding to the first transistor 12 and the second transistor 13 may include a first connection portion 32; the first connection portion 32 is located above one of the source-drain regions 15 included in the first transistor 12, and is simultaneously electrically connected to one of the source-drain regions 15 included in the first transistor 12 and one of the source-drain regions 15 included in the second transistor 13 that are located on the same side along the length direction of the gate stack structure 17. The first connection portion 32 penetrates through a portion of the insulating dielectric layer 21 that covers one of the source-drain regions 15 included in the first transistor 12 and is at the same setting height as the second transistor 13. In an actual application process, it may be that the drain region among the source-drain regions 15 included in the first transistor 12 and the drain region among the source-drain regions 15 included in the second transistor 13 are located on the same side along the length direction of the gate stack structure 17, and the first connection portion 32 is simultaneously electrically connected to the drain region included in the first transistor 12 and the drain region included in the second transistor 13, and is used to output a voltage. Of course, it may also be determined according to actual requirements which one of the source-drain regions 15 included in the first transistor 12 and which one of the source-drain regions 15 included in the second transistor 13 the first connection portion 32 is electrically connected to, and no specific limitation is made here.

[0086] Exemplarily, such as Figure 32 and Figure 33As shown, the source-drain contact structure 18 corresponding to the first transistor 12 and the second transistor 13 may further include a second connection portion 33 and a third connection portion 34. The second connection portion 33 and the third connection portion 34 are disposed on the same side of the first transistor 12 and the second transistor 13 along the length direction of the gate stack structure 17, and the second connection portion 33 and the third connection portion 34 are spaced apart. The second connection portion 33 penetrates through the insulating dielectric layer 21 and covers a portion of the other one of the source-drain regions 15 included in the first transistor 12 and is at the same set height as the second transistor 13, and is electrically connected to the other one of the source-drain regions 15 included in the first transistor 12. The third connection portion 34 penetrates through the insulating dielectric layer 21 and covers a portion of the other one of the source-drain regions 15 included in the second transistor 13, and is electrically connected to the other one of the source-drain regions 15 included in the second transistor 13. In an actual application process, it may be that the source region in the source-drain region 15 included in the first transistor 12 is electrically connected to the second connection portion 33, or it may be that the source region in the source-drain region 15 included in the second transistor 13 is electrically connected to the third connection portion 34. One of the second connection portion 33 and the third connection portion 34 is used for grounding, and the other is used for connecting to a power supply; specifically, which one of the second connection portion 33 and the third connection portion 34 is grounded and which one is connected to the power supply can be determined according to the conduction types of the first transistor 12 and the second transistor 13, and no specific limitation is made here. Of course, it can also be determined according to actual requirements which one of the source-drain regions 15 included in the first transistor 12 the second connection portion 33 is electrically connected to, and which one of the source-drain regions 15 included in the second transistor 13 the third connection portion 34 is electrically connected to, and no specific limitation is made here.

[0087] As for the specific morphologies of the two source-drain contact structures located on the same side along the length direction of the gate stack structure in the first transistor and the second transistor, they can be determined according to their positional relationships. If they are electrically connected together, they can be of a covering type or other structures. Of course, as Figure 32 and Figure 33 shown, the first connection portion 32 can also extend in a direction perpendicular to the surface of the semiconductor substrate.

[0088] As Figure 31 and Figure 32 shown, if the two source-drain contact structures 18 located on the same side along the length direction of the gate stack structure are spaced apart, they can both extend in a direction perpendicular to the surface of the semiconductor substrate. At this time, the source-drain contact structure 18 can be simplified, and at the same time, the source-drain contact structure 18 can be obtained only by etching to form contact holes and forming conductive materials filled in the contact holes, without pre-burying conductive materials for leading out the source-drain regions 15, simplifying the manufacturing process of the semiconductor device and facilitating cost reduction.

[0089] In terms of materials, in the first transistor and the second transistor, the materials of the source / drain regions and the channel region can include any one of semiconductor materials such as silicon, silicon germanium, or germanium, and no specific limitation is made here. The materials of the source / drain regions can be the same as or different from those of the channel region. Additionally, the materials of the channel regions included in the first transistor and the second transistor can be the same or different. The materials of the source / drain regions included in the first transistor and the second transistor can be the same or different.

[0090] The gate stack structures included in the first transistor and the second transistor can include: a gate dielectric layer disposed on the outer periphery of the channel region, and a gate electrode located on the gate dielectric layer. Among them, the material of the gate dielectric layer included in the first transistor and / or the second transistor can be an insulating material such as HfO2, ZrO2, TiO2, or Al2O3. The material of the gate electrode included in the first transistor and / or the second transistor can be a conductive material such as TiN, TaN, or TiSiN. The materials of the gate stack structures included in the first transistor and the second transistor can be the same or different.

[0091] In some cases, such as Figure 31 and Figure 32 as shown, the semiconductor device provided by the embodiment of the present invention may further include a gate sidewall 27. The gate sidewall 27 is disposed on both sides of the gate stack structures 17 included in the first transistor 12 and the second transistor 13 along the length direction, and is used to separate the gate stack structures 17 from other adjacent conductive structures, reducing the leakage risk. The material of the gate sidewall 27 can include any one of insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0092] In terms of device size, it can be that only along the length direction of the gate stack structures included in the first transistor and the second transistor, the length of the active structure included in the second transistor is less than the length of the active structure included in the first transistor.

[0093] Or, it can also be that only along the width direction of the channel regions included in the first transistor and the second transistor, the width of the active structure included in the second transistor is less than the width of the active structure included in the first transistor.

[0094] Or, as Figures 27 to 33 shown, it can also be that while the length of the active structure included in the second transistor 13 is less than the length of the active structure included in the first transistor 12, the width of the active structure included in the second transistor 13 is also less than the width of the active structure included in the first transistor 12. At this time, in the first transistor 12 and the second transistor 13, at least a pair of adjacent two source / drain contact structures 18 located on the same side along the length direction of the gate stack structure 17 can be spaced apart in two directions to further reduce the leakage risk between them.

[0095] Specifically, when the length of the active structure included in the second transistor is smaller than the length of the active structure included in the first transistor, only the length of the channel region included in the second transistor may be smaller than the length of the channel region included in the first transistor; or only the length of the source and drain region included in the second transistor may be smaller than the length of the source and drain region included in the first transistor; or, while the length of the channel region included in the second transistor is smaller than the length of the channel region included in the first transistor, the length of the source and drain region included in the second transistor is less than or equal to the length of the source and drain region included in the first transistor.

[0096] The difference between the lengths of the active structures included in the first transistor and the second transistor can be set according to manufacturing accuracy and actual needs, and is not limited here.

[0097] In addition, when the length of the active structure included in the second transistor is smaller than the length of the active structure included in the first transistor, as Figure 31 and Figure 32 As shown, the center line of the channel region 16 included in the second transistor 13 along the length direction of the gate stack structure 17 may coincide with the center line of the channel region 16 included in the first transistor 12 along the length direction of the gate stack structure 17. At this time, the second fin 25 used to manufacture the second transistor 13 may be selectively etched along the direction from the source and drain region 15 to the channel region 16, so that the second fin 25 is narrowed, so that the length of the active structure included in the second transistor 13 is smaller than the length of the active structure included in the first transistor 12, and there is no need to additionally manufacture a mask to cover one side of the second fin 25, which is conducive to simplifying the manufacturing process of the semiconductor device.

[0098] Alternatively, a side wall of the channel region included in the second transistor along the length direction of the gate stack structure may be aligned with a side wall of the channel region included in the first transistor along the length direction of the gate stack structure. In this case, if in the first transistor and the second transistor, only one pair of two adjacent source-drain contact structures located on the same side along the length direction of the gate stack structure are arranged at intervals, and another pair of two adjacent source-drain contact structures located on the same side along the length direction of the gate stack structure are electrically connected, then the two source-drain contact structures electrically connected together may be arranged on the side where the side walls of the channel region of the first transistor and the second transistor are aligned in the length direction, and the two source-drain contact structures spaced apart may be arranged on the side where the side walls of the channel region of the first transistor and the second transistor are staggered in the length direction, so as to further reduce the leakage risk of both and reduce the manufacturing difficulty of the two source-drain contact structures spaced apart.

[0099] When the width of the active structure included in the second transistor is smaller than the width of the active structure included in the first transistor, as Figure 28 and Figure 29 ,as well as Figure 33As shown, it may be that one side wall of the channel region 16 included in the second transistor 13 along the width direction is aligned with one side wall of the channel region 16 included in the first transistor 12 along the width direction. At this time, the manufacturing difficulty of the mask structure for selectively etching the second fin 25 used to manufacture the second transistor 13 is relatively low, based on reducing the manufacturing difficulty of semiconductor devices. At the same time, it is also beneficial that at least a pair of adjacent source-drain contact structures 18, which are located on the same side and spaced apart along the length direction of the gate stack structure 17 in the first transistor 12 and the second transistor 13, can have a larger spacing along the width direction of the channel region 16, which is beneficial to reducing the leakage risk between the two, and is beneficial to reducing the manufacturing difficulty of manufacturing these two spaced-apart source-drain contact structures 18.

[0100] Or, as Figure 30 shown, it may also be that the midline of the channel region 16 included in the second transistor 13 along the width direction coincides with the midline of the channel region 16 included in the first transistor 12 along the width direction.

[0101] In one example, as Figure 31 and Figure 32 shown, the semiconductor device may further include a second isolation structure 19. The second isolation structure 19 is disposed between the gate stack structure 17 included in the first transistor 12 and the gate stack structure 17 included in the second transistor 13 to reduce the electrical interference between the first transistor 12 and the second transistor 13 and improve the electrical performance of the semiconductor device. The material of the second isolation structure 19 may include any insulating material such as silicon oxide or silicon nitride.

[0102] For the first isolation structure, in the embodiments of the present invention, the material and thickness of the first isolation structure are not specifically limited, as long as the first isolation structure can electrically isolate the source-drain region included in the second transistor from the source-drain region and / or the channel region included in the first transistor.

[0103] Specifically, the setting position of the first isolation structure can be determined according to the lengths of the active structures included in the first transistor and the second transistor, and no specific limitation is made here. Specifically, if the length of the active structure included in the second transistor is less than the length of the active structure included in the first transistor, the first isolation structure is at least disposed between the source-drain region included in the second transistor and the channel region included in the first transistor (and may also be disposed between the source-drain region included in the second transistor and the source-drain region included in the first transistor).

[0104] If the length of the active structure included in the second transistor is equal to the length of the active structure included in the first transistor, the first isolation structure is disposed between the source-drain region included in the second transistor and the source-drain region included in the first transistor.

[0105] In some cases, such as Figures 27 to 33As shown in the figure, the semiconductor device provided by an embodiment of the present invention may further include a shallow trench isolation structure 20. The shallow trench isolation structure 20 is formed on the semiconductor substrate 11 and is used to define the active region of the semiconductor substrate 11, reduce the leakage risk, and further improve the yield and working performance of the semiconductor device.

[0106] As for the material of the shallow trench isolation structure, it may include any one of insulating materials such as silicon oxide, silicon oxynitride, or silicon nitride oxynitride, and no specific limitation is made here.

[0107] In a second aspect, an embodiment of the present invention provides a manufacturing method of a semiconductor device. The manufacturing process will be described below according to Figures 1 to 33 the cross-sectional views of the operations shown. Specifically, the manufacturing method of the semiconductor device includes the following steps: First, as Figures 1 to 3 shown, a fin structure 22 is formed on the semiconductor substrate 11. Along the thickness direction of the semiconductor substrate 11, the fin structure 22 includes a first fin portion 23, a semiconductor isolation layer 24, and a second fin portion 25 arranged in sequence. Next, as Figures 4 to 23 shown, the second fin portion 25 is selectively etched so that the length of the remaining second fin portion 25 is less than the length of the first fin portion 23, and / or the width of the remaining second fin portion 25 is less than the width of the first fin portion 23. Next, as Figures 24 to 30 shown, using semiconductor manufacturing processes, a first transistor 12 is manufactured based on the first fin portion 23. Next, as Figures 24 to 30 shown, the semiconductor isolation layer 24 is removed; and a first isolation structure 14 is formed at least on the source / drain regions 15 included in the first transistor 12. Next, as Figures 24 to 30 shown, using semiconductor manufacturing processes, a second transistor 13 is manufactured based on the second fin portion 25. Next, as Figures 31 to 33 shown, a source / drain contact structure 18 that is in electrical contact with the source / drain regions 15 included in the first transistor 12 and the second transistor 13 is formed. At least a pair of adjacent two source / drain contact structures 18 that respectively belong to the first transistor 12 and the second transistor 13 and are located on the same side along the length direction of the gate stack structure 17 are spaced apart, and the source / drain contact structures 18 included in the first transistor 12 and the source / drain contact structures 18 included in the second transistor 13 are both located in the vertical space of the regions where the first transistor 12 and the second transistor 13 are located.

[0108] It should be noted that the structure of the semiconductor device formed by the manufacturing method provided in the second aspect of the embodiment of the present invention is the same as the structure of the semiconductor device provided in the first aspect. Therefore, for the beneficial effects of the second aspect and its various implementation manners in the embodiment of the present invention, reference can be made to the analysis of the beneficial effects in the first aspect and its various implementation manners, and details are not described here again.

[0109] In the actual manufacturing process, in the above fin structure, the first fin portion is used to manufacture the first transistor. Therefore, the specific structure of the first fin portion can be determined according to the device type and structure of the first transistor.

[0110] Exemplarily, when the first transistor is a fin field-effect transistor, the first fin portion can be a single-layer strip-shaped semiconductor structure; or, it can also be a strip-shaped semiconductor structure including multiple semiconductor layers. Moreover, the material and width of the first fin portion are the same as the material and width of the channel region included in the first transistor respectively.

[0111] Exemplarily, when the first transistor is a gate-all-around transistor, the first fin portion can include at least one semiconductor stack. Each semiconductor stack includes sacrificial layers and channel layers stacked alternately. In the alternately stacked sacrificial layers and channel layers, the bottom layer and the top layer are sacrificial layers. Among them, the channel layers included in the first fin portion are used to manufacture the nanostructures in the channel region included in the first transistor. Therefore, the width of the first fin portion and the material of the channel layers included in the first fin portion can be determined according to the material and width of the channel region included in the first transistor. As for the sacrificial layers included in the first fin portion, the sacrificial layers of the first fin portion covered by the mask structure need to be removed subsequently to release the channel region included in the first transistor. Moreover, when selectively removing the sacrificial layers included in the first fin portion, the second fin portion (or the channel layers included in the second fin portion) will be retained. Therefore, the material of the sacrificial layers included in the first fin portion can be any semiconductor material different from the channel layers included in the first fin portion and the second fin portion (or the channel layers included in the second fin portion). For example: when the materials of the channel layers included in the first fin portion and the second fin portion are silicon, the material of the sacrificial layers included in the first fin portion can be silicon-germanium or germanium.

[0112] Similarly, the second fin portion is used to manufacture the second transistor. Therefore, the specific structure of the second fin portion can be determined according to the device type and structure of the second transistor.

[0113] Exemplarily, when the second transistor is a fin field-effect transistor, the second fin portion can be a single-layer strip-shaped semiconductor structure; or, it can also be a strip-shaped semiconductor structure including multiple semiconductor layers. Moreover, the material and width of the second fin portion are the same as the material and width of the channel region included in the second transistor respectively.

[0114] Exemplarily, in the case where the second transistor is a gate-all-around transistor, the second fin may include at least one semiconductor stack. Each semiconductor stack includes a sacrificial layer and a channel layer located on the sacrificial layer. Among them, the channel layer included in the second fin is used to fabricate nanostructures in the channel region included in the second transistor. Therefore, the material of the channel layer included in the second fin can be determined according to the material of the channel region included in the second transistor. As for the sacrificial layer included in the first fin, the sacrificial layer of the second fin covered by the mask structure needs to be removed subsequently to release the channel region included in the second transistor. Moreover, when selectively removing the sacrificial layer included in the second fin, the first fin (or the channel layer included in the first fin) will be retained. Therefore, the material of the sacrificial layer included in the second fin can be any semiconductor material different from the channel layer included in the second fin and the first fin (or the channel layer included in the first fin). Additionally, in the case where both the first transistor and the second transistor are gate-all-around transistors, the materials of the sacrificial layers included in the first fin and the second fin can be the same to reduce the limitation of the epitaxial critical thickness and facilitate improving the formation quality of semiconductor devices. Of course, the materials of the two can also be different.

[0115] As for the semiconductor isolation layer included in the fin structure, this semiconductor isolation layer plays a pre-occupation role. Subsequently, by removing the semiconductor isolation layer not covered by the mask structure and after forming the source / drain regions included in the first transistor, at least a first isolation structure is formed on the source / drain regions included in the first transistor. Therefore, the thickness of the semiconductor isolation layer can be determined according to the thickness requirement of the first isolation structure. As for the material of the semiconductor isolation layer, it can be any semiconductor material different from the first fin and the second fin, and no specific limitation is made here.

[0116] Exemplarily, as Figure 1 shown, processes such as epitaxy can be used to form the sacrificial layer 29 and the channel layer 30 for fabricating the first fin and the second fin along the thickness direction of the semiconductor substrate 11, and the semiconductor isolation layer 24 is formed. Then, as Figure 2 shown, processes such as photolithography and etching are used to pattern the above-mentioned sacrificial layer 29, channel layer 30, semiconductor isolation layer 24, and part of the semiconductor substrate 11 to form a Fin structure. Next, as Figure 3 shown, processes such as deposition and etching can be used to form a shallow trench isolation structure 20 for defining an active region between adjacent Fin structures. The top height of the shallow trench isolation structure 20 is less than or equal to the bottom height of the sacrificial layer 29 at the bottom layer. Among them, the part of the Fin structure exposed outside the shallow trench isolation structure 20 is the fin structure 22.

[0117] It should be noted that when the manufactured semiconductor device does not include the above-mentioned shallow trench isolation structure, only the sacrificial layer, the channel layer, and the semiconductor isolation layer can be patterned. And a fin structure can be directly obtained after the patterning process.

[0118] Exemplarily, if the manufactured second transistor is a comb-shaped field effect transistor, after forming the fin structure, as Figure 4 and Figure 5 shown, processes such as dry etching or wet etching can be used to selectively etch the second fin portion 25 to reduce the width of the second fin portion 25. Then, as Figure 6 shown, processes such as deposition are used to form a mask on the side of the second fin portion 25 that has been etched. And as Figure 7 and Figure 8 shown, under the protection of the corresponding mask, an etching process is used to narrow the width of the second fin portion 25; then processes such as epitaxy are used to selectively epitaxially grow one side of the second fin portion 25 in the width direction to form a connection portion 31. Each channel layer 30 included in the second fin portion 25 is electrically connected through the connection portion 31. The material of the connection portion 31 can include any one of semiconductor materials such as silicon, silicon germanium, or germanium. As Figure 9 shown, after forming the connection portion 31, processes such as dry etching or wet etching can be used to remove the corresponding mask.

[0119] Exemplarily, if the width of the active structure included in the second transistor in the manufactured semiconductor device is smaller than the width of the active structure included in the first transistor, after forming the fin structure (or after forming the connection portion), as Figures 10 to 12 shown, under the protection of the corresponding mask, processes such as dry etching or wet etching can be used to selectively etch the second fin portion 25 so that the width of the remaining second fin portion 25 is smaller than the width of the first fin portion 23. Among them, the mask can be any mask with a protective function such as a photoresist mask. After reducing the width of the second fin portion 25, processes such as dry etching or wet etching can be used to remove the mask.

[0120] As Figures 13 to 15 shown, deposition and etching processes can be used to form a mask structure 26 spanning the fin structure 22. The specific structure and material of the mask structure 26 can be set according to actual requirements as long as it can play a mask protection role in the subsequent process.

[0121] Exemplarily, as Figure 5 shown, the mask structure 26 can include a sacrificial gate 28. The material of the sacrificial gate 28 can include materials such as polysilicon that are easy to remove.

[0122] Exemplarily, the above mask structure may also include a gate oxide layer and a sacrificial gate located on the gate oxide layer. The material of the gate oxide layer may include materials such as silicon oxide.

[0123] In one example, after forming the mask structure, the manufacturing method of the semiconductor device further includes: as Figure 16 shown, using processes such as dry etching or wet etching to remove the remaining semiconductor isolation layer. Next, as Figure 17 shown, using processes such as deposition and etching to form a second isolation structure 19 between the remaining first fin 23 and the remaining second fin 25.

[0124] It should be noted that while manufacturing the second isolation structure, gate sidewalls can be formed on both sides of the mask structure along the length direction to improve the manufacturing efficiency of the semiconductor device. Or, alternatively, the gate sidewalls can be formed first and then the second isolation structure can be manufactured.

[0125] Next, as Figure 18 shown, using processes such as dry etching or wet etching to etch away the part of the fin structure exposed outside the mask structure 26 (if the second isolation structure 19 is formed at this time, selective etching of the second isolation structure 19 is also required).

[0126] Exemplarily, if the length of the active structure included in the second transistor in the manufactured semiconductor device is less than the length of the active structure included in the first transistor, then after etching away the part of the fin structure exposed outside the mask structure, as Figure 19 shown, using processes such as deposition and etching to form a mask at least for shielding the remaining first fin 23. Then, as Figure 20 shown, under the protection of this mask and using processes such as dry etching or wet etching, selectively etch the second fin 25 so that the length of the remaining second fin 25 is less than the length of the first fin 23. Then, as Figure 21 shown, remove this mask.

[0127] Next, as Figure 22 shown, using processes such as epitaxy to epitaxially form source / drain regions 15 included in the first transistor 12 on both sides of the remaining first fin.

[0128] Or, in the actual manufacturing process, under the protection of the mask structure, only the second fin and the second isolation structure can be selectively etched. Then, using processes such as ion implantation to dope the part of the first fin exposed outside to form the source / drain regions included in the first transistor.

[0129] Next, as Figure 23As shown, processes such as deposition and etching can be used to form a first isolation structure 14 at least on the source / drain regions 15 included in the first transistor 12.

[0130] Next, as Figure 24 shown, processes such as epitaxy can be used to epitaxially form the source / drain regions 15 included in the second transistor 13 on both sides of the remaining second fin portions.

[0131] Next, as Figure 25 shown, processes such as deposition and planarization can be used to form an insulating dielectric layer 21 covering the semiconductor substrate 11. The top of the insulating dielectric layer 21 is flush with the top of the mask structure 26. The material of the insulating dielectric layer 21 can refer to the previous text and will not be elaborated here.

[0132] Next, as Figure 26 shown, processes such as dry etching or wet etching can be used to remove the mask structure.

[0133] Next, as Figure 26 shown, the remaining first fin portion and the remaining second fin portion are respectively formed into channel regions 16.

[0134] The specific implementation manner of this operation can be set according to the device types of the first transistor and the second transistor, as well as the actual requirements. Exemplarily, in the case where the first transistor and the second transistor are fin field-effect transistors, after removing the mask structure, the remaining first fin portion forms the channel region included in the first transistor. The remaining second fin portion forms the channel region included in the second transistor.

[0135] Exemplarily, in the case where the first transistor and / or the second transistor is a gate-all-around transistor, after removing the mask structure, the remaining sacrificial layer also needs to be removed to release the channel region.

[0136] Next, as Figures 27 to 30 shown, processes such as atomic layer deposition can be used to form a gate stack structure 17 on the outer periphery of the channel region 16.

[0137] Next, as Figures 31 to 33 shown, a source / drain contact structure 18 is formed in electrical contact with the source / drain regions 15 included in the first transistor 12 and the second transistor 13.

[0138] Specifically, processes such as photolithography and etching can be used to etch the insulating dielectric layer to form contact holes. Then, processes such as physical vapor deposition can be used to form the source / drain contact structure filled in the contact holes.

[0139] In the above description, no detailed explanations are given for the technical details such as the composition and etching of each layer. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of the required shapes. Additionally, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as the methods described above. Moreover, although the embodiments are described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0140] The embodiments of the present invention have been described above. However, these embodiments are only for clearer illustration and not for limiting the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor substrate, a first transistor, a second transistor and a first isolation structure; The first transistor and the second transistor are arranged on the semiconductor substrate at intervals along the thickness direction of the semiconductor substrate, and the second transistor is located above the first transistor; the first isolation structure is arranged between the source and drain region included in the second transistor and the source and drain region and / or the channel region included in the first transistor; Wherein, along the length direction of the gate stack structure included in the first transistor and the second transistor, the length of the active structure included in the second transistor is smaller than the length of the active structure included in the first transistor, and / or, along the width direction of the channel region included in the first transistor and the second transistor, the width of the active structure included in the second transistor is smaller than the width of the active structure included in the first transistor; the active structure includes a channel region, and the source and drain regions located on both sides of the channel region along the length direction; At least one pair of adjacent source-drain contact structures belonging to the first transistor and the second transistor respectively and located on the same side along the length direction of the gate stack structure are arranged at intervals, and the source-drain contact structures included in the first transistor and the second transistor are both located in the vertical space of the area where the first transistor and the second transistor are located.

2. The semiconductor device according to claim 1, wherein: In the first transistor and the second transistor, the two source-drain contact structures located on the same side along the length direction of the gate stack structure and arranged at intervals both extend in a direction perpendicular to the surface of the semiconductor substrate.

3. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises an insulating dielectric layer; the insulating dielectric layer covers the second transistor and covers a portion of the first transistor exposed outside the second transistor; The source-drain contact structure corresponding to the first transistor and the second transistor includes a first connecting portion; the first connecting portion is located above one of the source and drain regions included in the first transistor, and is simultaneously electrically connected to one of the source and drain regions included in the first transistor and one of the source and drain regions included in the second transistor located on the same side along the length direction of the gate stack structure; the first connecting portion penetrates the insulating dielectric layer and covers a portion above one of the source and drain regions included in the first transistor, and is at the same setting height as the second transistor.

4. The semiconductor device according to claim 3, characterized in that The first connection portion extends in a direction perpendicular to a surface of the semiconductor substrate.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that: The semiconductor device further comprises an insulating dielectric layer; the insulating dielectric layer covers the second transistor and covers a portion of the first transistor exposed outside the second transistor; The source-drain contact structure corresponding to the first transistor and the second transistor includes a second connection portion and a third connection portion; the second connection portion and the third connection portion are arranged on the same side of the first transistor and the second transistor along the length direction of the gate stack structure, and the second connection portion and the third connection portion are spaced apart; The second connecting portion penetrates a portion of the insulating dielectric layer covering the other of the source and drain regions included in the first transistor and at the same height as the second transistor, and is electrically connected to the other of the source and drain regions included in the first transistor; The third connection portion penetrates a portion of the insulating dielectric layer covering the other one of the source and drain regions included in the second transistor, and is electrically connected to the other one of the source and drain regions included in the second transistor.

6. The semiconductor device according to claim 1, wherein: In the case where the length of the active structure included in the second transistor is smaller than the length of the active structure included in the first transistor, The length of the channel region included in the second transistor is smaller than the length of the channel region included in the first transistor; and / or the length of the source and drain region included in the second transistor is smaller than or equal to the length of the source and drain region included in the first transistor.

7. The semiconductor device according to claim 6, characterized in that A midline of a channel region included in the second transistor along a length direction of the gate stack structure coincides with a midline of a channel region included in the first transistor along the length direction of the gate stack structure.

8. The semiconductor device according to claim 1, wherein: A side wall of the channel region included in the second transistor along the width direction is aligned with a side wall of the channel region included in the first transistor along the width direction; Alternatively, a center line of a channel region included in the second transistor along the width direction coincides with a center line of a channel region included in the first transistor along the width direction.

9. The semiconductor device according to claim 1, wherein: The second transistor is a comb field effect transistor.

10. The semiconductor device according to claim 9, characterized in that The first transistor is a gate-all-around transistor; the second transistor includes a channel region having a multilayer nanostructure distributed at intervals along the thickness direction of the semiconductor substrate, and a connecting portion arranged on one side of the multilayer nanostructure along the width direction; The number of layers of the nanostructure in the channel region included in the second transistor is smaller than the number of layers of the nanostructure in the channel region included in the first transistor.

11. The semiconductor device according to claim 1, wherein: The first transistor and / or the second transistor is a gate-all-around transistor; And / or, the semiconductor device further includes a second isolation structure; the second isolation structure is disposed between the gate stack structure included in the first transistor and the gate stack structure included in the second transistor.

12. A method for manufacturing a semiconductor device, characterized in that: include: forming a fin structure on a semiconductor substrate; Along the thickness direction of the semiconductor substrate, the fin-shaped structure includes a first fin portion, a semiconductor isolation layer and a second fin portion which are arranged in sequence; Selectively etching the second fin so that the length of the remaining second fin is smaller than the length of the first fin, and / or the width of the remaining second fin is smaller than the width of the first fin; Using a semiconductor manufacturing process to form a first transistor based on the first fin; removing the semiconductor isolation layer; and forming a first isolation structure at least on the source and drain regions included in the first transistor; Using a semiconductor manufacturing process to form a second transistor based on the second fin; A source-drain contact structure is formed that is electrically in contact with the source-drain regions included in the first transistor and the second transistor; at least one pair of adjacent source-drain contact structures that belong to the first transistor and the second transistor, respectively, and are located on the same side along the length direction of the gate stack structure are arranged at intervals, and the source-drain contact structure included in the first transistor and the source-drain contact structure included in the second transistor are both located in the vertical space of the region where the first transistor and the second transistor are located.

13. The method for manufacturing a semiconductor device according to claim 12, wherein: Forming the first transistor, the first isolation structure and the second transistor includes: forming a mask structure spanning over the fin-shaped structure; and etching and removing a portion of the fin-shaped structure exposed outside the mask structure; epitaxially forming source and drain regions of the first transistor on both sides of the remaining first fin; forming the first isolation structure at least on the source and drain regions included in the first transistor; epitaxially forming source and drain regions of the second transistor on both sides of the remaining second fin; removing the mask structure; and forming the remaining first fin and the remaining second fin into channel regions respectively; A gate stack structure is formed at the periphery of the channel region.

14. The method for manufacturing a semiconductor device according to claim 13, wherein: After forming the fin-shaped structure on the semiconductor substrate and before forming the mask structure spanning the fin-shaped structure, the second fin is selectively etched so that the width of the remaining second fin is smaller than the width of the first fin.

15. The method for manufacturing a semiconductor device according to claim 13, wherein: After etching away the portion of the fin-shaped structure exposed outside the mask structure, and before epitaxially forming the source and drain regions included in the second transistor on both sides of the remaining second fin, the second fin is selectively etched so that the length of the remaining second fin is less than the length of the first fin.

16. The method for manufacturing a semiconductor device according to claim 12, wherein: The second fin includes at least one semiconductor stack, and each semiconductor stack includes a sacrificial layer and a channel layer located on the sacrificial layer; After forming the fin-shaped structure on the semiconductor substrate and before selectively etching the second fin, the method for manufacturing the semiconductor device further includes: selectively performing epitaxial growth on one side of the second fin along the width direction to form a connecting portion; each channel layer included in the second fin is electrically connected via the connecting portion.

17. The method for manufacturing a semiconductor device according to claim 13, wherein: After forming a mask structure spanning the fin-shaped structure, before etching away the portion of the fin-shaped structure exposed outside the mask structure, the method for manufacturing the semiconductor device further includes: removing the remaining semiconductor isolation layer; A second isolation structure is formed between the remaining first fins and the remaining second fins.

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