Sensing, storing and computing integrated three-dimensional integrated chip and preparation method and computing method thereof

Abstract

The invention discloses a sensing, storage and calculation integrated three-dimensional integrated chip, a preparation method of the sensing, storage and calculation integrated three-dimensional integrated chip and a calculation method of the sensing, storage and calculation integrated three-dimensional integrated chip. The sensing memory unit comprises a stacked resistive random access memory device group, a sensing device and a gating device; the stacked resistive random access memory device group comprises at least two resistive random access memory devices which are stacked in the thickness direction; the sensing device is used for receiving an external signal and converting the external signal into an input signal, and the output end of the sensing device is coupled with the top electrode of the stacked resistive random access memory device group; the gating device is configured to receive a control signal and switch on and off according to the control signal, and the gating device is coupled with the top electrode of the stacked resistive random access memory device group; wherein the stacked resistive random access memory device group is arranged between the sensing device and the gating device along the width direction, and the at least two resistive random access memory devices share one top electrode, so that the at least two resistive random access memory devices synchronously receive an input signal or are synchronously switched on and off.

Description

Technical Field

[0001] This application belongs to the technical field of microelectronic devices, and particularly relates to a sensing, storage, and computing integrated three-dimensional integrated chip, a preparation method thereof, and a computing method. Background Art

[0002] In traditional chips, the sensing function, storage function, and computing function are usually designed as independent modules. However, this architecture causes the system to have the defects of high power consumption and high latency, and it is difficult to meet the increasingly high performance requirements of terminal devices.

[0003] In response to this, some studies have proposed integrating the sensing, storage, and computing functions in a single chip to achieve optimization of power consumption and latency. However, this kind of chip still has the defects of high parasitic capacitance and large dynamic power consumption that need to be optimized. Summary of the Invention

[0004] The embodiments of this application provide a sensing, storage, and computing integrated three-dimensional integrated chip, a preparation method thereof, and a computing method. The sensing, storage, and computing integrated three-dimensional integrated chip realizes the writing of multiple weight values in the sensing, storage, and computing unit by stacking multiple resistive random access memory (RRAM) devices in the thickness direction, and the top electrodes of the multiple RRAM devices are shared to achieve synchronous storage or synchronous computing, thereby improving the performance of the chip.

[0005] In a first aspect, the embodiments of this application provide a sensing, storage, and computing integrated three-dimensional integrated chip, which integrates a sensing, storage, and computing unit array having multiple sensing, storage, and computing units. The sensing, storage, and computing unit includes a stacked RRAM device group, a sensing device, and a gating device: the stacked RRAM device group includes at least two RRAM devices stacked in the thickness direction of the sensing, storage, and computing integrated three-dimensional integrated chip; the sensing device is configured to receive an external signal and convert the external signal into an input signal, and the output end of the sensing device is coupled to the top electrode of the stacked RRAM device group; the gating device is configured to receive a control signal and switch on and off according to the control signal, and the gating device is coupled to the top electrode of the stacked RRAM device group; wherein, the stacked RRAM device group is disposed between the sensing device and the gating device along the width direction of the sensing, storage, and computing integrated three-dimensional integrated chip, and at least two RRAM devices are arranged sharing a top electrode, so that at least two RRAM devices receive input signals synchronously or switch on and off synchronously.

[0006] In some optional embodiments, the stacked RRAM device group includes a top electrode, a resistive switching layer, and at least two bottom electrodes. The top electrode is coupled to the at least two bottom electrodes through the resistive switching layer, and the resistive switching layer is configured to change the resistance value under the control of a voltage signal applied between the top electrode and the bottom electrodes.

[0007] In some alternative embodiments, at least two bottom electrodes are stacked in the thickness direction, and an insulating dielectric layer is provided between any two bottom electrodes. The top electrode extends at least in the thickness direction to connect the bottom electrodes, and the resistive switching layer extends at least in the thickness direction to separate the top electrode from each bottom electrode.

[0008] In some alternative embodiments, the gating device includes a substrate, an active region disposed on one side of the substrate, a drain electrode, a source electrode, and a gate electrode. The drain electrode and the source electrode are disposed on the side of the active region facing away from the substrate and are electrically isolated by a gate dielectric layer. The gate electrode is disposed between the drain electrode and the source electrode in the width direction and is spaced apart from the active region by the gate dielectric layer. Among them, the source electrode is electrically connected to the top electrode of the storage device.

[0009] In some alternative embodiments, the integrated sensing, storage, and computing three-dimensional integrated chip further includes:

[0010] A driving module for outputting a control signal to the gating device;

[0011] Bit lines extending in the row direction, and the bit lines are connected between the driving module and the drain electrodes of the respective gating devices;

[0012] Word lines extending in the column direction, and the word lines are connected between the driving module and the gate electrodes of the respective gating devices.

[0013] In some alternative embodiments, the integrated sensing, storage, and computing three-dimensional integrated chip further includes:

[0014] A first output line, and the first output line is electrically connected to the stacked resistive switching memory device group in each sensing, storage, and computing unit;

[0015] A second output line, and the second output line is electrically connected to the sensing devices in each sensing, storage, and computing unit.

[0016] In some alternative embodiments, the sensing device includes a photosensitive layer. The photosensitive layer is disposed on the side of the active region facing away from the substrate, and the photosensitive layer is coupled to the top electrode of the stacked resistive switching memory device group through the source electrode and the active region.

[0017] In a second aspect, an embodiment of the present application provides a method for manufacturing an integrated sensing, storage, and computing three-dimensional integrated chip. The manufacturing method includes:

[0018] Providing a gating device and a sensing device;

[0019] Depositing an insulating dielectric layer and a bottom electrode layer in sequence above the gating device;

[0020] Repeating the deposition of the insulating dielectric layer and the bottom electrode layer until N bottom electrode layers are obtained, and insulating dielectric layers are formed above and below each bottom electrode layer;

[0021] Etching the stacked structure of the insulating dielectric layer and the bottom electrode layer to form a through hole to expose the gating device;

[0022] Grow a resistive switching layer at the interface of the stacked structure on the inner wall of the through hole;

[0023] Deposit a top electrode layer inside the resistive switching layer to complete the preparation of the stacked resistive random access memory (RRAM) device group.

[0024] In some alternative embodiments, the thickness of the insulating dielectric layer is greater than or equal to 100 nm and less than or equal to 300 nm; and / or,

[0025] The material of the resistive switching layer includes at least one of oxides, nitrides, sulfides, and organic materials, and the thickness of the resistive switching layer is greater than or equal to 4 nm and less than or equal to 30 nm; and / or,

[0026] The material of the top electrode layer includes active metals; and / or,

[0027] The material of the bottom electrode layer includes inert materials.

[0028] In a third aspect, an embodiment of the present application provides a calculation method for a sensing-in-memory three-dimensional integrated chip, which is applied to the sensing-in-memory three-dimensional integrated chip provided in any embodiment of the first aspect. The calculation method includes:

[0029] Connect the select device to the sensing device, and the sensing device receives the sample signal and generates a first output current;

[0030] Disconnect the sensing device, connect the select device to the stacked RRAM device group, and write weights to each storage device respectively;

[0031] Disconnect the select device, connect the stacked RRAM device group to the sensing device, and the sensing device receives the sample signal and completes the calculation according to the weights of the storage devices to generate a second output current;

[0032] Compare the first output current with the second output current to determine whether the target image is a sample image, and complete image recognition.

[0033] The sensing-in-memory three-dimensional integrated chip provided by the embodiment of the present application realizes the integration of multiple storage devices in the sensing-in-memory unit in the form of stacking in the thickness direction. Among them, the resistive random access memory (RRAM) device is used as the storage device to realize in-memory computing and shorten the signal transmission time. Multiple RRAM devices share a top electrode to realize synchronous storage or computing. The sensing-in-memory three-dimensional integrated chip greatly improves the storage density in the form of stacking storage devices, and realizes the improvement of chip performance under the same area; at the same time, the stacked storage devices reduce the length of the device interconnection line, thereby reducing the parasitic capacitance and dynamic power consumption inside the sensing-in-memory unit. Description of the Drawings

[0034] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for the purpose of illustrating the preferred embodiments and are not considered to be a limitation of the present application. Also, in all the drawings, the same reference numerals are used to denote the same components. In the drawings:

[0035] Figure 1 Schematic diagram of an array of sense-in-memory three-dimensional integrated chips according to some embodiments of the present application;

[0036] Figure 2 Schematic diagram of the structure of a sense-in-memory unit according to some embodiments of the present application;

[0037] Figure 3 Schematic flowchart of a method for fabricating a sense-in-memory three-dimensional integrated chip according to some embodiments of the present application;

[0038] Figures 4a to 4g is Figure 3 Schematic diagram of the process structure of the shown fabrication method;

[0039] Figure 5 Schematic flowchart of a calculation method for a sense-in-memory three-dimensional integrated chip according to some embodiments of the present application;

[0040] Figure 6 Schematic diagram of a sub-process of the calculation method according to some embodiments of the present application.

[0041] The reference numerals in the specific embodiments are as follows:

[0042] 01, sense-in-memory unit;

[0043] 100, select device; 110, substrate; 121, epitaxial layer; 1221, first sub-region; 1222, second sub-region; 131, drain; 132, gate; 133, source; 140, gate dielectric layer; 150, isolation structure;

[0044] 200, sensing device; 210, photosensitive layer;

[0045] 300, stacked resistive memory device group; 301, resistive memory device; 310, top electrode; 320, resistive layer; 331, bottom electrode; 332, insulating dielectric layer;

[0046] Thickness direction Z; width direction X; length direction Y;

[0047] Word line WL; bit line BL; first output line C1; second output line C2. Specific embodiments

[0048] The embodiments of the technical solution of the present application will be described in detail below with reference to the accompanying drawings. The following embodiments are only used to illustrate the technical solution of the present application more clearly, so they are only examples and cannot be used to limit the protection scope of the present application.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the description of the specification, claims, and the above drawings of this application are intended to cover non-exclusive inclusion.

[0050] In the description of the embodiments of this application, technical terms such as "first" and "second" are only used to distinguish different objects and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity, specific order, or primary-secondary relationship of the indicated technical features. In the description of the embodiments of this application, the meaning of "plurality" is more than two, unless otherwise specifically defined.

[0051] Referring to "embodiments" herein means that the specific features, structures, or characteristics described in connection with the embodiments may be included in at least one embodiment of this application. The phrase appears in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art explicitly and implicitly understand that the embodiments described herein may be combined with other embodiments.

[0052] In the description of the embodiments of this application, the term "and / or" is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this article generally represents an "or" relationship between the associated objects before and after.

[0053] In the description of the embodiments of this application, the term "plurality" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0054] In the description of the embodiments of the present application, the orientation or positional relationship indicated by technical terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the embodiments of the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the embodiments of the present application.

[0055] In the description of the embodiments of the present application, unless otherwise clearly specified and limited, technical terms such as "installation", "connection", "connection", "fixation", etc. should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated into one; it can also be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, and can be the communication inside two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to specific circumstances.

[0056] With the rapid development of Internet of Things technology and artificial intelligence technology, the demand of terminal devices for real-time data processing is increasing continuously. The traditional von Neumann architecture with separated storage and computing has the defects of low data transfer efficiency and high power consumption, and it is difficult to meet the urgent needs of new scenarios such as edge computing for low latency and high energy efficiency.

[0057] In recent years, with the development of in-memory computing technology, some research has integrated sensing, storage and computing functions into a single chip to form a sensing-storage-computing integrated chip, effectively reducing power consumption and latency and achieving the improvement of the overall system performance.

[0058] However, the two-dimensional integrated sensing-storage-computing integrated chip is limited by the single-chip area and cannot provide sufficient storage capacity and computing power when processing complex real-time tasks. Traditional devices such as static random access memory and dynamic random access memory occupy a large area, restricting the storage density. At the same time, in the two-dimensional integrated structure, the increasing length and density of interconnections lead to the increase of parasitic capacitance and resistance load, which has a negative impact on the signal transmission speed and limits the energy efficiency ratio of the chip.

[0059] In response to this, related research has proposed 3D NAND technology to improve the storage and computing capabilities by introducing multiple storage devices into the sensing-storage-computing chip in a vertically stacked form. However, the form of directly stacking the storage device with the insulating structure results in too large chip thickness and prone to defects such as warping. At the same time, the increase in production cost brought about by the complexity of its process has also become an obstacle to large-scale production.

[0060] To solve the problems of the prior art, embodiments of the present application provide a sensing, storage, and computing integrated three-dimensional integrated chip, a preparation method thereof, and a computing method. The sensing, storage, and computing integrated three-dimensional integrated chip realizes the writing of multiple weight values in the sensing, storage, and computing unit by stacking multiple resistive random access memory (RRAM) devices in the thickness direction, and the top electrodes of the multiple RRAM devices are shared to realize synchronous storage or synchronous computing, thereby improving the chip performance. First, the sensing, storage, and computing integrated three-dimensional integrated chip provided by the embodiments of the present application will be introduced below.

[0061] In a first aspect, please refer to Figure 1 and Figure 2 , embodiments of the present application provide a sensing, storage, and computing integrated three-dimensional integrated chip, which integrally includes a sensing, storage, and computing unit array having multiple sensing, storage, and computing units 01. The sensing, storage, and computing unit 01 includes a stacked RRAM device group 300, a sensing device 200, and a gating device 100: The stacked RRAM device group 300 includes at least two RRAM devices 301 stacked in the thickness direction of the sensing, storage, and computing integrated three-dimensional integrated chip; the sensing device 200 is configured to receive an external signal and convert the external signal into an input signal, and an output end of the sensing device 200 is coupled to a top electrode 310 of the stacked RRAM device group 300; the gating device 100 is configured to receive a control signal and switch on and off according to the control signal, and the gating device 100 is coupled to the top electrode 310 of the stacked RRAM device group 300; wherein, the stacked RRAM device group 300 is disposed between the sensing device 200 and the gating device 100 along the width direction of the sensing, storage, and computing integrated three-dimensional integrated chip, and at least two RRAM devices 301 are provided with a shared top electrode 310, so that at least two RRAM devices 301 synchronously receive the input signal or synchronously switch on and off.

[0062] As a non-volatile memory device, the RRAM device 301 can switch between two conduction modes, namely, a high resistance state and a low resistance state, in response to a voltage excitation, thereby realizing the integration of the storage function and the computing function. Optionally, the RRAM device 301 is selected from a metal oxide RRAM device 301, an organic RRAM device 301, a two-dimensional material RRAM device 301, a ferroelectric RRAM device 301, a spin RRAM device 301, and an electrolyte RRAM device 301.

[0063] The sensing device 200 refers to an element that can directly sense an external physical signal on the chip and convert it into an electrical signal, where the external physical signal includes temperature, light, sound, pressure, etc. Optionally, the external signal is an optical signal, the input signal is a photocurrent, and the sensing device 200 includes a photodiode, and the photodiode is configured to sense the optical signal and convert it into an electrical signal. Exemplarily, the photodiode is one of a PIN photodiode, a PN junction photodiode, and a Schottky photodiode.

[0064] The gating device 100 is a component that controls the current path through its own on / off state to activate the selected sense-compute unit 01. Optionally, the gating device 100 is one of a metal-semiconductor field-effect transistor, a magnetoresistive tunnel junction, a diode, a threshold switch, and a two-terminal gating device 100. Exemplarily, the gating device 100 is a metal-semiconductor field-effect transistor. In some embodiments, to reduce the system power consumption, the metal-semiconductor field-effect transistor is designed with a low threshold voltage for driving. For example, the threshold voltage is not higher than 5V.

[0065] Thus, the sense-compute-in-memory three-dimensional integrated chip realizes the monolithic integration of multiple memories in the form of stacking in the thickness direction, and further realizes the writing of multiple weight values and improves the storage density of the sense-compute-in-memory three-dimensional integrated chip. The sense-compute-in-memory three-dimensional integrated chip uses the resistive random access memory device 301 to implement in-memory computing, reduces the signal transmission time, and improves the signal transmission speed. The design of sharing the top electrode 310 by multiple resistive random access memory devices 301 enables multiple resistive random access memory devices 301 to perform weight writing or calculation operations synchronously, further improving the real-time data processing ability of the chip under the same area. Compared with the form of direct stacking, the chip thickness is significantly reduced, the process is simplified and the cost is optimized, and it has greater potential for large-scale production. In addition, compared with a planar structure chip with the same computing power, the stacking form of the sense-compute-in-memory three-dimensional integrated chip reduces the length of the interconnections inside the chip, thereby reducing the dynamic power consumption and parasitic capacitance inside the chip to achieve performance optimization.

[0066] According to some embodiments of the present application, the stacked resistive random access memory device group 300 includes a top electrode 310, a resistive switching layer 320, and at least two bottom electrodes 331. The top electrode 310 is coupled to the at least two bottom electrodes 331 through the resistive switching layer 320. The resistive switching layer 320 is configured to change the resistance value under the control of the voltage signals applied between the top electrode 310 and the bottom electrodes 331.

[0067] It can be understood that the at least two bottom electrodes 331 can be individually applied with voltage excitation, so as to achieve independent weight writing and subsequent calculation operations in the case of sharing the top electrode 310.

[0068] Optionally, the thickness of the resistive switching layer 320 is greater than or equal to 4nm. It can be understood that the thickness direction of the resistive switching layer 320 is different from the thickness direction of the sense-compute-in-memory three-dimensional integrated chip. Specifically, the thickness direction of the resistive switching layer 320 refers to the direction that is perpendicular to both the contact surface between the top electrode 310 and the resistive switching layer 320 and the contact surface between the bottom electrode 331 and the resistive switching layer 320.

[0069] Further optionally, the thickness of the resistive switching layer 320 is less than or equal to 30nm.

[0070] Optionally, the resistive change layer 320 is selected from at least one of metal oxides, chalcogenides, perovskite materials, organic materials, and nitrides. Among them, the metal oxides include hafnium oxide, tantalum pentoxide, titanium dioxide, bismuth ferrite, etc. Exemplarily, the resistive change layer 320 is made of hafnium oxide.

[0071] Thus, when the sense-storage-compute unit 01 performs a weight writing or computing operation, the top electrode 310 responds to the control signal of the selection device 100 or the input signal of the sensing device 200, so that multiple resistive memory devices 301 synchronously receive the voltage signal excitation of the top electrode 310 and respectively perform weight writing or computing operations to achieve storage functions or computing functions.

[0072] According to some embodiments of the present application, at least two bottom electrodes 331 are stacked along the thickness direction, and an insulating dielectric layer 332 is provided between any two bottom electrodes 331. The top electrode 310 extends at least along the thickness direction to connect to each bottom electrode 331, and the resistive change layer 320 extends at least along the thickness direction to space the top electrode 310 from each bottom electrode 331. Optionally, the resistive change layer 320 is inclined with respect to the thickness direction, which is convenient for processing on the inner wall of the through hole formed by etching on the one hand, and can provide a more easily adherent basis for the subsequent preparation of the top electrode 310 on the other hand.

[0073] Optionally, the top electrode 310 is inclined with respect to the thickness direction, which is convenient for processing and preparing by forms such as deposition and simultaneously forming a coupling with each bottom electrode 331.

[0074] It can be understood that the insulating dielectric layer 332 is used to block the lateral leakage current between two adjacent bottom electrodes 331 along the thickness direction. The insulating dielectric layer 332 can form device isolation between the resistive memory devices 301 so that each resistive memory device 301 can be independently controlled to turn on and off by adjusting the voltage of the bottom electrode 331.

[0075] Optionally, the thickness of the insulating dielectric layer 332 is greater than or equal to 100 nm. Among them, the thickness of the insulating dielectric layer 332 refers to the minimum length of the insulating dielectric layer 332 in the thickness direction of the sense-storage-compute integrated three-dimensional integrated chip.

[0076] Further optionally, the thickness of the insulating dielectric layer 332 is less than or equal to 300 nm.

[0077] Optionally, the top electrode 310 is made of an active metal material, and the bottom electrode 331 is made of an inert material.

[0078] Thus, multiple bottom electrodes 331 stacked along the thickness direction can form multiple resistive memory devices 301 with the top electrode 310 through sharing the resistive change layer 320, improving the storage density of the sense-storage-compute unit 01 while controlling the thickness of the chip, reducing the parasitic capacitance and contributing to the thermal management of the chip.

[0079] According to some embodiments of the present application, the gating device 100 includes a substrate 110, an active region disposed on one side of the substrate 110, a drain 131, a source 133, and a gate 132. The drain 131 and the source 133 are disposed on the side of the active region away from the substrate 110 and are electrically isolated by a gate dielectric layer 140. The gate 132 is disposed between the drain 131 and the source 133 in the width direction and is spaced apart from the active region by the gate dielectric layer 140. Among them, the source 133 is electrically connected to the top electrode 310 of the storage device.

[0080] Optionally, the drain 131 and the gate 132 of the gating device 100 are respectively connected to a row gating signal and a column gating signal, and the chip can select a target sense-compute unit 01 according to the row gating signal and the column gating signal and perform operations such as weight writing, calculation, or image acquisition.

[0081] Specifically, the active region includes an epitaxial layer 121 doped with ions of a first conductivity type and a well region disposed in the epitaxial layer 121 and doped with ions of a second conductivity type. Exemplarily, the first conductivity type is P-type and the second conductivity type is N-type.

[0082] Optionally, the well region includes a first sub-region 1221 coupled to the drain 131 and a second sub-region 1222 coupled to the source 133. Exemplarily, the orthographic projection of the drain 131 on the substrate 110 falls within the orthographic projection range of the first sub-region 1221 on the substrate 110, and the orthographic projection of the source 133 on the substrate 110 falls within the orthographic projection range of the second sub-region 1222 on the substrate 110.

[0083] Further optionally, the doping concentration of the second sub-region 1222 is greater than the doping concentration of the first sub-region 1221, or the doping concentration of the second sub-region 1222 is equal to the doping concentration of the first sub-region 1221.

[0084] Further optionally, the orthographic projection of the top electrode 310 on the substrate 110 falls within the orthographic projection range of the source 133 on the substrate 110.

[0085] Even more optionally, the orthographic projection of the stacked resistive memory device group 300 on the substrate 110 falls within the orthographic projection range of the source 133 on the substrate 110.

[0086] It can be understood that an insulating dielectric layer 332 is disposed between the stacked resistive memory device group 300 and the source 133 to electrically isolate the bottom electrode 331 of the resistive memory region from the source 133 of the gating device 100.

[0087] It can be understood that the gating device 100 further includes an isolation structure 150, which is disposed around in the horizontal plane to achieve electrical isolation between different sense-calculate units 01, so as to achieve the gating or turning off of the target sense-calculate unit 01. Specifically, the isolation structure 150 is disposed on both sides of the active region along the width direction of the sense-calculate integrated three-dimensional chip, and at the same time, the isolation structure 150 is also disposed on both sides of the active region along the length direction of the sense-calculate integrated three-dimensional chip.

[0088] Therefore, the gating device 100 selects a transistor. When the drain 131 and the gate 132 of the transistor sense a control signal, the sense-calculate unit 01 where the transistor is located is turned on to perform operations such as image acquisition, weight writing, or calculation. The sense-calculate integrated three-dimensional chip realizes the call of different sense-calculate units 01 through the gating device 100.

[0089] According to some embodiments of the present application, the sense-calculate integrated three-dimensional chip further includes:

[0090] A driving module for outputting a control signal to the gating device 100;

[0091] Bit lines extending in the row direction, and the bit lines are connected between the driving module and the drains 131 of the respective gating devices 100;

[0092] Word lines extending in the column direction, and the word lines are connected between the driving module and the gates 132 of the respective gating devices 100.

[0093] Optionally, the driving module includes a word line driving unit and a bit line driving unit. The word line driving unit is connected to the gates 132 of the respective gating devices 100 through the word lines, and the bit line driving unit is connected to the drains 131 of the respective gating devices 100 through the bit lines.

[0094] Optionally, the width direction of the sense-calculate integrated three-dimensional chip is the row direction, the length direction of the sense-calculate integrated three-dimensional chip is the column direction, and multiple sense-calculate units 01 are arranged in a matrix array.

[0095] Exemplarily, there are xy sense-calculate units 01 and they are distributed in x rows and y columns. There are x bit lines and they are respectively electrically connected to the sense-calculate units 01 in x rows. There are y word lines and they are respectively electrically connected to the sense-calculate units 01 in y columns. Among them, the bit lines are used to control the conduction states of the drains 131 of y sense-calculate units 01 in the same row, and the word lines are used to control the switching states of the gates 132 of x sense-calculate units 01 in the same column.

[0096] Optionally, the select device 100 includes a passivation layer covering the drain 131 and the gate 132. A first via is formed in the passivation layer above the drain 131, and a first conductive metal is deposited in the first via to form a bit line. A second via is formed in the passivation layer above the gate 132, and a second conductive metal is deposited in the second via to form a word line. Along the thickness direction of the integrated sensing, computing, and storage three-dimensional integrated chip, the word line and the bit line are insulated from each other through the passivation layer.

[0097] Thus, the driving module can transmit control signals through the word line and the bit line and select the corresponding sensing, computing, and storage unit 01 to turn it on, thereby realizing operations such as image acquisition, weight writing, or calculation.

[0098] According to some embodiments of the present application, the integrated sensing, computing, and storage three-dimensional integrated chip further includes:

[0099] A first output line electrically connected to the resistive random access memory device group 300 in each sensing, computing, and storage unit 01;

[0100] A second output line electrically connected to the sensing device 200 in each sensing, computing, and storage unit 01.

[0101] Optionally, the first output line includes at least two writing sub-lines, and the at least two writing sub-lines are connected to the bottom electrodes 331 of at least two resistive random access memory devices 301 in each sensing, computing, and storage unit 01 in a one-to-one correspondence to perform weight writing operations on the respective resistive random access memory devices 301 within the same sensing, computing, and storage unit 01.

[0102] Exemplarily, the resistive random access memory device group 300 includes two resistive random access memory devices 301, the first output line includes two writing sub-lines, one of the writing sub-lines is electrically connected to the bottom electrode 331 close to the active region in each sensing, computing, and storage unit 01, and the other writing word line is electrically connected to the bottom electrode 331 far from the active region in each sensing, computing, and storage unit 01.

[0103] Optionally, the integrated sensing, computing, and storage three-dimensional integrated chip further includes a first inverter, and the first inverter is connected to the output end of the first output line and is used to generate a first output voltage as a calculation result.

[0104] Optionally, the integrated sensing, computing, and storage three-dimensional integrated chip further includes a second inverter, and the second inverter is connected to the output end of the second output line and is used to generate a second output voltage as an image acquisition result. By comparing the first output voltage and the second output voltage, the integrated sensing, computing, and storage three-dimensional integrated chip can complete an image recognition task.

[0105] Thus, the integrated sensing, storage, and computing three-dimensional integrated chip can output the total current as the acquisition result and the computing result in the acquisition mode and the computing mode respectively, and complete the recognition task according to the comparison between the computing result and the acquisition result. It can be understood that the recognition task can be tasks such as image recognition and speech recognition.

[0106] According to some embodiments of the present application, the sensing device 200 includes a photosensitive layer 210. The photosensitive layer 210 is disposed on a side of the active region away from the substrate 110. The photosensitive layer 210 is coupled to the top electrode 310 of the stacked resistive random access memory device group 300 through the source electrode 133 and the active region.

[0107] Optionally, at least a part of the positive projection of the photosensitive layer 210 on the substrate 110 falls within the positive projection range of the second sub-region 1222 on the substrate 110.

[0108] Further optionally, the positive projection of the photosensitive layer 210 on the substrate 110 falls within the positive projection range of the second sub-region 1222 on the substrate 110.

[0109] Optionally, the photosensitive layer 210 is adjacent to the source electrode 133 of the gating device 100 along the width direction of the integrated sensing, storage, and computing three-dimensional integrated chip, or the photosensitive layer 210 is spaced apart from the source electrode 133 of the gating device 100 along the width direction of the integrated sensing, storage, and computing three-dimensional integrated chip and is isolated by the gate dielectric layer 140.

[0110] Optionally, the photosensitive layer 210 is selected from at least one of silicon, gallium arsenide, indium phosphide, mercury cadmium telluride (HgCdTe, MCT), and organic semiconductor materials.

[0111] Thus, the sensing device 200 can receive an external optical signal and generate a photocurrent. The photocurrent can directly output the image acquisition result through the second output line, or the photocurrent can be transmitted to the top electrode 310 of the stacked resistive random access memory device group 300 through the second sub-region 1222 and the source electrode 133 and output the computing result through each resistive random access memory device 301 and the first output line.

[0112] In a second aspect, please refer to Figure 3 and Figures 4a to 4g , embodiments of the present application provide a method for manufacturing an integrated sensing, storage, and computing three-dimensional integrated chip. The manufacturing method includes:

[0113] S110. Provide a gating device and a sensing device;

[0114] S120. Deposit an insulating dielectric layer and a bottom electrode layer in sequence above the gating device;

[0115] S130. Repeat depositing the insulating dielectric layer and the bottom electrode layer until N bottom electrode layers are obtained, and insulating dielectric layers are formed above and below each bottom electrode layer;

[0116] S140. Etch the stacked structure of the insulating dielectric layer and the bottom electrode layer to form a via hole to expose the select device;

[0117] S150. Grow a resistive switching layer at the stacked structure interface on the inner wall of the via hole;

[0118] S160. Deposit a top electrode layer inside the resistive switching layer to complete the preparation of the stacked resistive random access memory device group.

[0119] Thus, compared with the three-dimensional integrated chip formed by the traditional stacked memory device, the present application significantly reduces the number of stacked layers, thereby improving the fabricability of the chip. For example, taking the preparation of two-layer resistive random access memory as an example, the related technology needs to prepare three insulating layers, two top electrode layers, two bottom electrode layers and two resistive switching layers, while the preparation method provided by the present application only needs to prepare three insulating layers and two bottom electrode layers, one top electrode layer and one resistive switching layer, and the top electrode layer and the resistive switching layer do not occupy space in the chip thickness direction, and this advantage will become more prominent as the number of stacked resistive random access memory devices increases.

[0120] According to some embodiments of the present application, step S110 includes:

[0121] S111. Provide a substrate and grow an epitaxial layer on one side of the substrate;

[0122] S112. Inject ions of the first conductivity type into the epitaxial layer;

[0123] S113. Inject ions of the second conductivity type into the surface of the epitaxial layer away from the substrate to form a well region located inside the epitaxial layer;

[0124] S114. Form a source electrode and a drain electrode on the surface of the epitaxial layer away from the substrate;

[0125] S115. Form a gate dielectric layer on the surface of the epitaxial layer away from the substrate;

[0126] S116. Form a gate electrode on the surface of the gate dielectric layer away from the substrate.

[0127] Optionally, step S110 further includes:

[0128] S117. Etch the gate dielectric layer to expose the second sub-region;

[0129] S118. Deposit a photosensitive layer above the second sub-region.

[0130] Optionally, in step S114, the source electrode and the drain electrode are prepared by a deposition process.

[0131] Further optionally, in step S114, a mask is set on the surface of the epitaxial layer away from the substrate and the source electrode and the drain electrode are directly deposited.

[0132] Optionally, in step S116, the gate is fabricated by a deposition process.

[0133] Further optionally, in step S116, a mask is disposed on the surface of the gate dielectric layer away from the substrate and the gate is directly deposited.

[0134] According to some embodiments of the present application, in step S120, the same mask is used to form the insulating dielectric layer and the bottom electrode layer.

[0135] According to some embodiments of the present application, in steps S120 and S130, the thickness of the insulating dielectric layer is greater than or equal to 100 nm and less than or equal to 300 nm.

[0136] Optionally, the material of the insulating dielectric layer includes at least one of silicon dioxide, silicon nitride, and polymer insulating materials.

[0137] According to some embodiments of the present application, in steps S120 and S130, the material of the bottom electrode layer includes inert materials.

[0138] Exemplarily, the material of the bottom electrode layer includes at least one of gold, platinum, and titanium nitride.

[0139] According to some embodiments of the present application, in step S140, the through hole formed by etching has an inverted conical structure. Specifically, please refer to Figure 4e , in the width direction of the integrated sensing and computing three-dimensional integrated chip, the opening size of the through hole on the side away from the substrate is larger than the opening size on the side close to the substrate, so as to facilitate the subsequent process implementation of growing the resistive switching layer and depositing the top electrode layer on the inner wall of the through hole.

[0140] Optionally, in step S140, a mask is set and the stacked structure of the insulating dielectric layer and the bottom electrode layer is etched to form a through hole and expose the source electrode.

[0141] Further optionally, the through hole is formed at the central position of the stacked structure of the insulating dielectric layer and the bottom electrode layer.

[0142] According to some embodiments of the present application, in step S150, the material of the resistive switching layer includes at least one of oxides, nitrides, sulfides, and organic compounds.

[0143] Optionally, the thickness of the resistive switching layer is greater than or equal to 4 nm and less than or equal to 30 nm.

[0144] Exemplarily, the resistive switching layer is a hafnium dioxide layer.

[0145] It can be understood that between two adjacent bottom electrodes, the resistive switching layer can be set to one layer or multiple layers. When the resistive switching layer is set to multiple layers, the materials of two directly adjacent resistive switching layers are set differently.

[0146] According to some embodiments of the present application, in step S160, the material of the top electrode layer includes an active metal.

[0147] Exemplarily, the material of the top electrode layer includes one of copper, silver, and lead.

[0148] According to some embodiments of the present application, the preparation method further includes:

[0149] S171. Prepare a passivation layer above the gate;

[0150] S172. Etch the passivation layer to form a first via to expose the drain, and deposit a first conductive metal in the first via to obtain a bit line;

[0151] S173. Etch the passivation layer to form a second via to expose the gate, and deposit a second conductive metal in the second via to obtain a word line.

[0152] In a third aspect, please refer to Figure 5 , an embodiment of the present application provides a calculation method for a sense-compute integrated three-dimensional integrated chip, which is applied to the sense-compute integrated three-dimensional integrated chip provided in any embodiment of the first aspect. The calculation method includes:

[0153] S210. Connect the select device and the sensing device, and the sensing device receives a sample signal and generates a first output current;

[0154] S220. Disconnect the sensing device, connect the select device and the stacked resistive random access memory (RRAM) device group, and write weights to each storage device respectively;

[0155] S230. Disconnect the select device, connect the stacked RRAM device group and the sensing device, and the sensing device receives a sample signal and completes the calculation according to the weights of the storage devices to generate a second output current;

[0156] S240. Compare the first output current with the second output current, determine whether the target image is a sample image, and complete image recognition.

[0157] According to some embodiments of the present application, step S210 includes:

[0158] S211. Provide a first voltage to the j-th column word line, and provide a second voltage lower than the first voltage or ground to the i-th row bit line;

[0159] S212. Provide a read signal to the second output line.

[0160] Thus, the selection and reading of a single sense-compute unit at the i-th row and j-th column are realized.

[0161] According to some embodiments of the present application, step S220 includes:

[0162] S221. Provide voltages to the bottom electrodes of each resistive memory device through the write sub-lines respectively;

[0163] S222. Provide a third voltage to the j-th column word line and provide a write signal or a rewrite signal to the i-th row bit line;

[0164] S223. Provide a read signal to the first output line.

[0165] Thus, the selection of a single sense-memory-computation unit at the i-th row and j-th column and the weight writing are realized. Among them, each bottom electrode that has been applied with a voltage excitation conducts simultaneously after the sense-memory-computation unit is selected, so that the weight writing operation can be performed simultaneously.

[0166] Optionally, in step S221, the driving module divides the system clock into N sub-periods through a time-slot allocation circuit, and each sub-period corresponds to the weight writing of one layer of resistive memory devices. The write voltage is sequentially loaded onto each bottom electrode through the write sub-lines.

[0167] According to some embodiments of the present application, please refer to Figure 6 , step S230 includes:

[0168] S231. The system clock generates a high-precision clock signal and is divided into time slots equal to the number of layers of the resistive memory device 301 through a frequency divider, and each time slot corresponds to one layer of resistive memory device;

[0169] S232. The logic control unit generates a hierarchical strobe signal sequence according to the time slot number, and the signal switching module dynamically distributes the strobe signal to the row strobe circuit of the target layer;

[0170] S233. Cyclically switch the resistive memory devices of each layer, complete feature extraction or inference operation, and generate a second output current.

[0171] Specifically, in step S233, the second output current is the accumulated value of the output currents of each sense-memory-computation unit in the array, and the output current of each sense-memory-computation unit is in turn the accumulated value of the output currents of each layer of resistive memories in the unit. Among them, the output current of a single resistive memory is the product of its own weight and the photocurrent. Thus, the second output current is obtained by the coupled calculation of the sense-memory-computation unit and the photocurrent and can be used to characterize the target image.

[0172] According to some embodiments of the present application, step S240 includes:

[0173] S241. Obtain a first output voltage and a second output voltage according to the first output current and the second output current;

[0174] S242. Normalize the first output voltage and the second output voltage to obtain a calculation result, compare the calculation result with a preset threshold value, and determine whether the target image is a sample image.

[0175] Optionally, in step S241, the operational amplifier is used to perform an inverting amplification operation on the first output current and the second output current to obtain the first output voltage and the second output voltage.

[0176] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application, and they should all be covered by the scope of the claims and the description of the present application. In particular, as long as there is no structural conflict, the technical features mentioned in each embodiment can be combined in any way. The present application is not limited to the specific embodiments disclosed in the text, but includes all technical solutions falling within the scope of the claims.

Claims

1. A three-dimensional integrated chip integrating sensing, storage and computing, characterized in that: A sensing storage and computing unit array is provided, comprising a plurality of sensing storage and computing units, wherein the sensing storage and computing unit comprises: A stacked resistive memory device group, comprising at least two resistive memory devices stacked in a thickness direction of the sensing-storage-computing integrated three-dimensional integrated chip; A sensing device, used for receiving an external signal and converting the external signal into an input signal, wherein an output end of the sensing device is coupled to a top electrode of the stacked resistive memory device group; A gating device, configured to receive a control signal and switch on and off according to the control signal, the gating device being coupled to a top electrode of the stacked resistive memory device group; Among them, the stacked resistive memory device group is arranged between the sensing device and the selection device along the width direction of the three-dimensional integrated chip of sensing, storage and computing, and at least two of the resistive memory devices share a top electrode setting so that at least two of the resistive memory devices can synchronously receive input signals or be synchronously turned on and off.

2. The sensing, storage and computing integrated three-dimensional integrated chip according to claim 1, characterized in that: The stacked resistive memory device group includes a top electrode, a resistive layer and at least two bottom electrodes, the top electrode is coupled to at least two bottom electrodes through the resistive layer, and the resistive layer is configured to achieve a change in resistance value under the control of a voltage signal applied to the top electrode and the bottom electrode.

3. The sensing, storage and computing integrated three-dimensional integrated chip according to claim 2, characterized in that: At least two of the bottom electrodes are stacked along the thickness direction and an insulating dielectric layer is provided between any two of the bottom electrodes. The top electrode at least extends along the thickness direction to connect the bottom electrodes. The resistive layer at least extends along the thickness direction to separate the top electrode and the bottom electrodes.

4. The sensing, storage and computing integrated three-dimensional integrated chip according to claim 1, characterized in that: The gating device includes a substrate, an active area arranged on one side of the substrate, and a drain, a source and a gate. The drain and the source are arranged on a side of the active area away from the substrate and are electrically isolated by a gate dielectric layer. The gate is arranged between the drain and the source along the width direction and is spaced from the active area by the gate dielectric layer, wherein the source is electrically connected to the top electrode of the storage device.

5. The sensing, storage and computing integrated three-dimensional integrated chip according to claim 4, characterized in that: The sensing, storage and computing integrated three-dimensional integrated chip also includes: A driving module, used for outputting a control signal to the gating device; A bit line extending in a row direction, wherein the bit line is connected between the driving module and the drain of each of the gating devices; The word line extends along the column direction, and the word line is connected between the driving module and the gate of each of the gating devices.

6. The sensing, storage and computing integrated three-dimensional integrated chip according to claim 5, characterized in that: The sensing, storage and computing integrated three-dimensional integrated chip also includes: A first output line, the first output line is electrically connected to the stacked resistive memory device group in each of the sensing, storage and computing units; A second output line, wherein the second output line is electrically connected to the sensing device in each of the sensing storage and computing units.

7. The sensing, storage and computing integrated three-dimensional integrated chip according to claim 4, characterized in that: The sensing device comprises a photosensitive layer, which is arranged on a side of the active region away from the substrate, and the photosensitive layer and a top electrode of the stacked resistive memory device group are coupled to the active region through the source electrode.

8. A method for preparing a three-dimensional integrated chip of sensing, storage and computing, characterized in that: The preparation method comprises: Provide gating devices and sensing devices; Depositing an insulating dielectric layer and a bottom electrode layer in sequence above the gating device; Repeatedly depositing insulating dielectric layers and bottom electrode layers until N bottom electrode layers are obtained and insulating dielectric layers are formed above and below each bottom electrode layer; Etching the stacked structure of the insulating dielectric layer and the bottom electrode layer to form a through hole to expose the gating device; Growing a resistive switching layer on the stack structure interface of the inner wall of the through hole; A top electrode layer is deposited inside the resistive switching layer to complete the preparation of the stacked resistive switching memory device group.

9. The method for preparing the sensing, storage and computing integrated three-dimensional integrated chip according to claim 8, characterized in that: The thickness of the insulating dielectric layer is greater than or equal to 100 nm and less than or equal to 300 nm; and / or, The material of the resistive layer includes at least one of oxide, nitride, sulfide, and organic matter, and the thickness of the resistive layer is greater than or equal to 4 nm and less than or equal to 30 nm; and / or, The material of the top electrode layer includes an active metal; and / or, The material of the bottom electrode layer includes an inert material.

10. A computing method for a sensing-storage-computing integrated three-dimensional integrated chip, applied to the sensing-storage-computing integrated three-dimensional integrated chip as claimed in any one of claims 1 to 8, characterized in that: The calculation methods include: The gating device is connected to the sensing device, and the sensing device receives the sample signal and generates a first output current; Disconnect the sensing device, connect the gating device and the stacked resistive memory device group, and write the weight to each memory device respectively; The gating device is disconnected, and the stacked resistive memory device group is connected to the sensing device, and the sensing device receives the sample signal and completes calculation according to the weight of the memory device to generate a second output current; The first output current is compared with the second output current to determine whether the target image is a sample image, thereby completing image recognition.

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