Electronic device

Abstract

The invention provides an electronic device. The electronic device comprises a substrate, an electronic unit and a joint unit, the substrate includes a first bump metal layer and a second bump metal layer, wherein the first bump metal layer and the second bump metal layer are arranged along a first direction. The electronic unit comprises a third bump metal layer and a fourth bump metal layer, the first bump metal layer is overlapped with the third bump metal layer, and the second bump metal layer is overlapped with the fourth bump metal layer. The bonding unit comprises a first bonding piece and a second bonding piece, the first bonding piece is arranged between the first bump metal layer and the third bump metal layer, and the second bonding piece is arranged between the second bump metal layer and the fourth bump metal layer. In the first direction, a ratio of a width of the third bump metal layer to a width of the first bump metal layer is greater than or equal to 0.3 and less than or equal to 0.9.

Description

Technical Field

[0001] The present invention relates to an electronic device, and particularly to an electronic device having tiny electronic units. Background Art

[0002] Due to the small size of tiny electronic units, the size of the contacts on the electronic units is also reduced accordingly, which in turn results in a large size difference between the contacts of the electronic units and the contacts of the substrate. When using solder to bond the electronic units and the substrate, the large contact size difference will cause a significant change in the thickness of the bonded contacts, and there is a risk of insufficient mechanical strength, thereby reducing the reliability of the electronic device. Summary of the Invention

[0003] The object of the present invention is to provide an electronic device.

[0004] The present invention provides an electronic device, which includes a substrate, an electronic unit, and a bonding unit. The substrate includes a first bump metal layer and a second bump metal layer, wherein the first bump metal layer and the second bump metal layer are arranged along a first direction. The electronic unit includes a third bump metal layer and a fourth bump metal layer, wherein the first bump metal layer overlaps with the third bump metal layer, and the second bump metal layer overlaps with the fourth bump metal layer. The bonding unit includes a first bonding member and a second bonding member, wherein the first bonding member is disposed between the first bump metal layer and the third bump metal layer, and the second bonding member is disposed between the second bump metal layer and the fourth bump metal layer. In the first direction, a ratio of a width of the third bump metal layer to a width of the first bump metal layer is greater than or equal to 0.3 and less than or equal to 0.9.

[0005] The present invention further provides an electronic device, which includes a substrate, an electronic unit, a bonding unit, and a connecting wire. The substrate includes a first bump metal layer and a wire, wherein the first bump metal layer and the wire are arranged along a first direction. The electronic unit includes a body, a second bump metal layer, and an electrode, the second bump metal layer and the electrode are respectively located on two sides of the body, and the first bump metal layer overlaps with the second bump metal layer. The bonding unit includes a bonding member, wherein the bonding member is disposed between the first bump metal layer and the second bump metal layer. The connecting wire electrically connects the electrode of the electronic unit and the wire of the substrate. In the first direction, a ratio of a width of the second bump metal layer to a width of the first bump metal layer is greater than or equal to 0.3 and less than or equal to 0.9. Description of the Drawings

[0006] Figures 1 to 3 It is a schematic diagram of the bonding process of the electronic device according to the first embodiment of the present invention.

[0007] Figure 4An upward view schematic diagram of the electronic unit according to the first embodiment of the present invention.

[0008] Figure 5 A top view schematic diagram of the substrate according to the first embodiment of the present invention.

[0009] Figures 6 to 8 A schematic diagram of the bonding process of the electronic device according to the second embodiment of the present invention.

[0010] Figures 9 to 11 A schematic diagram of the bonding process of the electronic device according to the third embodiment of the present invention.

[0011] Description of reference numerals: 1 - electronic device; 100 - body; 102, 104, 114, 202, 204, 226 - bump metal layer; 106, 108, 118, 214, 216 - solder; 110, 112, 206, 208, 228 - conductive pad; 116 - electrode; 120 - insulating layer; 122 - connecting wire; 200 - bottom plate; 210, 212, 218, 220, 230 - bonding member; 222, 224 - wire; BU - bonding unit; EU - electronic unit; OP1, OP2 - opening; PCx, PCy, NCx, NCy, PSx, NSx, PSy, NSy - width; SU - substrate; T1, T2, T3 - thickness; X, Y, V - direction. Detailed description of the embodiments

[0012] To enable those of ordinary skill in the art to further understand the present invention, the following specifically enumerate the embodiments of the present invention and, in conjunction with the accompanying drawings, detail the composition and the intended effects of the present invention. It should be noted that the accompanying drawings are all simplified schematic diagrams, and therefore, only the elements and combination relationships related to the present invention are shown to provide a clearer description of the basic structure or implementation method of the present invention, while the actual elements and layouts may be more complex. Additionally, for the convenience of description, the elements shown in the various drawings of the present invention are not drawn in an equal proportion according to the actual number, shape, and size of the implementation, and the detailed ratio can be adjusted according to the design requirements.

[0013] Throughout the specification and claims of the present invention, certain terms are used to refer to specific elements. Those of ordinary skill in the art should understand that electronic device manufacturers may use different names to refer to the same element. The present invention is not intended to distinguish elements that have the same function but different names. In the specification and claims of the present invention, terms such as "comprising" and "including" are open-ended terms and should therefore be interpreted as meaning "including but not limited to...".

[0014] The directional terms mentioned in the present invention, such as "upper", "lower", "front", "rear", "left", "right", etc., are only with reference to the directions in the attached drawings. Therefore, the directional terms used are for illustration purposes and not for limiting the present invention. In the attached drawings, each drawing shows the general characteristics of the methods, structures, and / or materials used in specific embodiments. However, these drawings should not be construed as defining or limiting the scope or nature covered by these embodiments. For example, for clarity, the relative sizes, thicknesses, and positions of each film layer, region, and / or structure may be reduced or enlarged.

[0015] It should be understood that when an element or film layer is referred to as being "on", "disposed on", or "connected to" another element or film layer, it can be directly on this other element or film layer or directly connected to this other element or film layer, or there may be intervening elements or film layers (non-direct situation) between the two. On the contrary, when an element is referred to as being "directly on", "directly disposed on", or "directly connected to" another element or film layer, there are no intervening elements or film layers between the two. In addition, the arrangement relationship between different elements can be interpreted according to the content of the attached drawings.

[0016] The term "same" is generally interpreted as being within 10% of the given value or range, or within 5%, 3%, 2%, 1%, or 0.5% of the given value or range.

[0017] The electrical connections or couplings described in the present invention can refer to either direct connections or indirect connections. In the case of a direct connection, the endpoints of the elements on two circuits are directly connected or connected to each other by a conductor segment. In the case of an indirect connection, there are switches, diodes, capacitors, inductors, resistors, other suitable elements, or combinations of the above elements between the endpoints of the elements on two circuits, but not limited thereto.

[0018] Although terms such as first, second, third... can be used to describe various components, the components are not limited to these terms. These terms are only used to distinguish a single component in the specification from other components. The same terms may not be used in the claims, and first, second, third... are replaced according to the order of element declarations in the claims. Therefore, in the specification of the present invention, the first component may be the second component in the claims.

[0019] It should be noted that in the following listed embodiments, without departing from the spirit of the present invention, the technical features in several different embodiments can be replaced, recombined, and mixed to complete other embodiments.

[0020] Comparisons of thickness, area, width, height, radius, etc. between different components in the present invention can be made by suitable instruments such as an optical microscope (OM), a scanning electron microscope (SEM), etc., and can be made using the same photo or more than one photo.

[0021] The electronic device of the present invention may include a display device, a backlight device, an antenna device, a sensing device, a wearable device, a vehicle-mounted device, or a splicing device, but is not limited thereto. The electronic device may be a bendable, flexible, or rollable electronic device. The display device may include a non-self-emitting display device or a self-emitting display device, but is not limited thereto. The display device may, for example, include liquid crystal, light-emitting diodes, fluorescence materials, phosphorescence materials, quantum dots (QD), other suitable display media, or a combination of the foregoing, but is not limited thereto. The antenna device may be an antenna device in a liquid crystal state or an antenna device not in a liquid crystal state, but is not limited thereto. The sensing device may be a sensing device for sensing capacitance, light, heat energy, or ultrasonic waves, but is not limited thereto.

[0022] The electronic device may include an electronic unit, and the electronic unit may include passive components or active components, such as capacitors, resistors, inductors, diodes, etc. The diodes may include light-emitting diodes or photodiodes, but are not limited thereto. The light-emitting diodes may, for example, include organic light-emitting diodes (OLED), mini light-emitting diodes (mini LED), micro light-emitting diodes (micro LED), or quantum dot light-emitting diodes (quantum dot LED), but are not limited thereto. The splicing device may, for example, be a display splicing device or an antenna splicing device, but is not limited thereto. It should be noted that the electronic device may be any permutation and combination of the foregoing, but is not limited thereto. In addition, the shape of the electronic device may be rectangular, circular, polygonal, a shape with curved edges, or other suitable shapes. The electronic device may have peripheral systems such as a driving system, a control system, a light source system, etc. to support the display device, the antenna device, the wearable device (such as including augmented reality or virtual reality), the vehicle-mounted device (such as including an automotive windshield), or the splicing device.

[0023] A direction V, a direction X, and a direction Y are marked in the following drawings. The direction V may be a normal direction or a top view direction, and the directions X and Y may be horizontal directions. As Figure 1, the direction V can be perpendicular to a surface (such as the upper surface or the lower surface) of a base plate 200, the direction X and the direction Y can be perpendicular to the direction V or parallel to the surface of the base plate 200, and the direction X can be perpendicular to the direction Y. The following drawings can describe the spatial relationship of the structure according to the directions V, X, and Y.

[0024] Please refer to Figures 1 to 5 , Figures 1 to 3 is a schematic diagram of the bonding process of the electronic device according to the first embodiment of the present invention. Figure 1 The state before the electronic unit and the substrate are bonded is shown. Figure 2 The state where the electronic unit and the substrate are in contact but no intermetallic compound (IMC) has been formed is shown. Figure 3 The state after the electronic unit and the substrate are bonded is shown. Figure 4 is a bottom view schematic diagram of the electronic unit according to the first embodiment of the present invention, while Figure 5 is a top view schematic diagram of the substrate according to the first embodiment of the present invention.

[0025] As Figure 1 shown, an electronic unit EU and a substrate SU can be provided first, but not limited thereto. In some embodiments, the electronic unit EU can be a micro light-emitting diode, but not limited thereto. In some embodiments, the electronic unit EU can be a flip chip LED, but not limited thereto. The electronic unit EU includes a body 100, a bump metal layer 102, and a bump metal layer 104, but not limited thereto. The body 100 can include semiconductor materials, such as P-type semiconductor materials and N-type semiconductor materials, but not limited thereto. The bump metal layer 102 and the bump metal layer 104 are disposed on the lower surface of the body 100, the bump metal layer 102 is electrically connected to one of the P-type semiconductor material and the N-type semiconductor material, and the bump metal layer 104 is electrically connected to the other of the P-type semiconductor material and the N-type semiconductor material, but not limited thereto. As Figure 4 and Figure 1 shown, the bump metal layer 102 and the bump metal layer 104 are arranged along the direction X, so the bump metal layer 102 can be disposed on one side of the bump metal layer 104 in the direction X.

[0026] In this embodiment, a solder 106 is disposed under the bump metal layer 102, and a solder 108 is disposed under the bump metal layer 104. In the present invention, the solder can include tin, indium, a combination of both, or other suitable elements, but not limited thereto. The atomic percentage (at%) range of tin (Sn) and indium (In) in the solder can be greater than 50% (i.e., (Sn at% + In at%) > 50%).

[0027] The substrate SU includes a basal substrate 200, a bump metal layer 202, a bump metal layer 204, a conductive pad 206, and a conductive pad 208, but is not limited thereto. The basal substrate 200 can be a flexible substrate or a rigid substrate, and a circuit layer can be provided on the basal substrate 200, but is not limited thereto. The circuit layer can include thin film transistors, wires, insulating layers, or a combination of the above, but is not limited thereto. In addition, the material of the basal substrate 200 can include glass, quartz, sapphire, polymers (such as polyimide (PI), polyethylene terephthalate (PET)), silicon, silicon carbide, gallium arsenide, other suitable materials, or a combination of the above, but is not limited thereto.

[0028] The bump metal layer 202 and the bump metal layer 204 are disposed on the basal substrate 200, such as Figure 5 and Figure 1 , the bump metal layer 202 and the bump metal layer 204 are arranged along the direction X. Therefore, the bump metal layer 202 can be disposed on one side of the bump metal layer 204 in the direction X. In the present invention, the bump metal layer can include a single-layer structure or a multi-layer structure, and the material of the bump metal layer can include titanium, nickel, gold, copper, palladium, platinum, aluminum, a combination of the above elements, or other suitable materials, but is not limited thereto. The bump metal layer can provide functions such as adhesion and diffusion barrier. The materials of the bump metal layer 102 and the bump metal layer 104 can be the same as or different from the materials of the bump metal layer 202 and the bump metal layer 204.

[0029] The conductive pad 206 is disposed on the bump metal layer 202 and is electrically connected to the bump metal layer 202, while the conductive pad 208 is disposed on the bump metal layer 204 and is electrically connected to the bump metal layer 204. In the present invention, the conductive pad can include a single-layer structure or a multi-layer structure, and the material of the conductive pad can include metal or other suitable materials, but is not limited thereto. In some embodiments, the solder 106 and the solder 108 can be tin, and the conductive pads 206 and 208 can be gold, but are not limited thereto. In some embodiments, the solder 106 and the solder 108 can be tin, and the conductive pads 206 and 208 can be nickel, but are not limited thereto. In some embodiments, the solder 106 and the solder 108 can be tin, and the conductive pads 206 and 208 can be copper, but are not limited thereto. In some embodiments, the solder 106 and the solder 108 can be indium, and the conductive pads 206 and 208 can be gold, but are not limited thereto.

[0030] Next, as Figure 2 shown, the solder 106 can be in direct contact with the conductive pad 206, and the solder 108 can be in direct contact with the conductive pad 208. Next, as Figure 3As shown, after bonding, the electronic device 1 may include a bonding unit BU. The bonding unit BU includes a bonding member 210 and a bonding member 212. The bonding member 210 is disposed between the bump metal layer 202 and the bump metal layer 102, and the bonding member 212 is disposed between the bump metal layer 204 and the bump metal layer 104. In some examples, the solder 106 and the conductive pad 206 may be melted and mixed to form the bonding member 210, and the solder 108 and the conductive pad 208 may be melted and mixed to form the bonding member 212. The bonding member 210 and the bonding member 212 are, for example, intermetallic compounds, but are not limited thereto. In other examples, the solder may be melted while the conductive pad is not melted, and when the conductive pad contacts the melted solder, they diffuse and mix with each other to form the bonding member, but are not limited thereto. After bonding, the bump metal layer 102, the bonding member 210, and the bump metal layer 202 may overlap in the direction V, and the bump metal layer 104, the bonding member 212, and the bump metal layer 204 may overlap in the direction V. In addition, the bump metal layers 102 and 104 of the electronic unit EU may be electrically connected to the bump metal layers 202 and 204 of the substrate SU through the bonding member 210 and the bonding member 212, respectively.

[0031] In this embodiment (as Figure 2 shown), the areas of the bump metal layer 102 and the bump metal layer 104, and the areas of the solder 106 and the solder 108 may be smaller than the areas of the bump metal layer 202 and the bump metal layer 204, and the areas of the conductive pad 206 and the conductive pad 208, but are not limited thereto. In some embodiments, the areas of the bump metal layer 102 and the bump metal layer 104, and the areas of the solder 106 and the solder 108 may be larger than the areas of the bump metal layer 202 and the bump metal layer 204, and the areas of the conductive pad 206 and the conductive pad 208, but are not limited thereto.

[0032] When the solder 106 and the solder 108 are disposed under the bump metal layers 102 and 104 with smaller areas and the areas of the solder 106 and the solder 108 are smaller than the areas of the conductive pad 206 and the conductive pad 208, in a well-wetted bonding state, the solder 106 and the solder 108 will spread on the conductive pad 206 and the conductive pad 208 with larger areas, reducing the thickness of the bonding member 210 and the bonding member 212 and risking insufficient mechanical strength, thereby reducing the reliability of the electronic device.

[0033] Therefore, the present invention proposes a dimension design of the bonding components on the electronic unit EU and the substrate SU to solve the above problems. In this embodiment, the sizes (such as area, length, or width) of the solder 106 and the solder 108 can be substantially the same as those of the bump metal layers 102 and 104, and the sizes of the conductive pads 206 and 208 can be substantially the same as those of the bump metal layers 202 and 204. Therefore, by designing the size of the bump metal layer, the sizes of the solder and the conductive pads can be further determined.

[0034] For example Figure 4 , in the X direction, the bump metal layer 102 has a width PCx and the bump metal layer 104 has a width NCx. In addition, in the Y direction, the bump metal layer 102 has a width PCy and the bump metal layer 104 has a width NCy. In the present invention, the definition of the tiny electronic unit EU can include that the widths of the width PCx, the width PCy, the width NCx, and the width NCy are each greater than 5 microns and less than or equal to 36 microns. In addition, the size of the bump metal layer 102 and the size of the bump metal layer 104 may not be the same. For example Figure 4 the width NCx can be greater than the width PCx, but not limited thereto. In some embodiments, the size of the bump metal layer 102 and the size of the bump metal layer 104 may be the same.

[0035] For example Figure 5 , in the X direction, the bump metal layer 202 has a width PSx and the bump metal layer 204 has a width NSx. In addition, in the Y direction, the bump metal layer 202 has a width PSy and the bump metal layer 204 has a width NSy. The size of the bump metal layer 202 and the size of the bump metal layer 204 may be the same, but not limited thereto. In some embodiments, the size of the bump metal layer 202 and the size of the bump metal layer 204 may not be the same.

[0036] The ratio of the width PCx of the bump metal layer 102 to the width PSx of the bump metal layer 202 is greater than or equal to 0.3 and less than or equal to 0.9. The ratio of the width NCx of the bump metal layer 104 to the width NSx of the bump metal layer 204 is greater than or equal to 0.3 and less than or equal to 0.9. In some other embodiments, the ratio of the width PCx of the bump metal layer 102 to the width PSx of the bump metal layer 202 is greater than or equal to 0.5 and less than or equal to 0.8, and the ratio of the width NCx of the bump metal layer 104 to the width NSx of the bump metal layer 204 is greater than or equal to 0.5 and less than or equal to 0.8.

[0037] A ratio of the width PCy of bump metal layer 102 to the width PSy of bump metal layer 202 is greater than or equal to 0.1 and less than or equal to 0.9. A ratio of the width NCy of bump metal layer 104 to the width NSy of bump metal layer 204 is greater than or equal to 0.1 and less than or equal to 0.9. In some other embodiments, the ratio of the width PCy of bump metal layer 102 to the width PSy of bump metal layer 202 is greater than or equal to 0.2 and less than or equal to 0.8, and the ratio of the width NCy of bump metal layer 104 to the width NSy of bump metal layer 204 is greater than or equal to 0.2 and less than or equal to 0.8.

[0038] A ratio of an area of bump metal layer 102 to an area of bump metal layer 202 is greater than or equal to 0.1 and less than or equal to 0.64, and a ratio of an area of bump metal layer 104 to an area of bump metal layer 204 is greater than or equal to 0.1 and less than or equal to 0.64.

[0039] In some embodiments, when any one of the width PCx and width PCy of bump metal layer 102 and the width NCx and width NCy of bump metal layer 104 is less than or equal to 5 microns, the electronic unit EU can be defined as an extremely tiny electronic unit. In this case, the ratio of the width PCx of bump metal layer 102 to the width PSx of bump metal layer 202, the ratio of the width NCx of bump metal layer 104 to the width NSx of bump metal layer 204, the ratio of the width PCy of bump metal layer 102 to the width PSy of bump metal layer 202, and the ratio of the width NCy of bump metal layer 104 to the width NSy of bump metal layer 204 are all greater than or equal to 0.33 and less than or equal to 0.75. In addition, the ratio of the area of bump metal layer 102 to the area of bump metal layer 202 is greater than or equal to 0.11 and less than or equal to 0.56, and the ratio of the area of bump metal layer 104 to the area of bump metal layer 204 is greater than or equal to 0.11 and less than or equal to 0.56.

[0040] Since the sizes of the solder and the conductive pads can be determined by designing the sizes of the bump metal layers, the proportional relationships between the widths and areas of the above-mentioned bump metal layers 102 and 104 and the widths and areas of bump metal layers 202 and 204 can be equivalent to the proportional relationships between the widths and areas of the solder 106 and 108 and the widths and areas of the conductive pads 206 and 208.

[0041] Furthermore, through the above-mentioned size design of the bump metal layers 102, 104, 202, and 204, the variation range of the thickness of the joint can be reduced. For example, after bonding Figure 3The thickness T1 of either the bonding member 210 or the bonding member 212 in [the above] may be greater than or equal to 0.3 micrometers and less than or equal to 6.4 micrometers. The bonding members 210 and 212 having this thickness range can provide sufficient mechanical strength and can improve the reliability of the electronic device 1.

[0042] In addition, in some embodiments, a part of the surface of the bump metal layer (such as the surface in contact with the conductive pad or solder) may be covered by the insulating layer. In this case, the width or area of the above-mentioned bump metal layer can be measured by measuring a part of the surface of the bump metal layer not covered by the insulating layer.

[0043] In some embodiments, the sizes (such as width or area) of the bump metal layer 102 and the bump metal layer 104 may be larger than the sizes of the bump metal layer 202 and the bump metal layer 204. When calculating the above ratio, the larger value (such as the width of the bump metal layer 102) can be used as the denominator, and the smaller value (such as the width of the bump metal layer 202) can be used as the numerator, and the same ratio range as above can be obtained.

[0044] From the above, it can be seen that in some embodiments, an electronic device 1 may include a substrate SU, an electronic unit EU, and a bonding unit BU. The substrate SU includes a bump metal layer 202 and a bump metal layer 204, and the bump metal layer 202 and the bump metal layer 204 are arranged along the direction X. The electronic unit EU includes a bump metal layer 102 and a bump metal layer 104, the bump metal layer 202 overlaps with the bump metal layer 102, and the bump metal layer 204 overlaps with the bump metal layer 104. The bonding unit BU includes a bonding member 210 and a bonding member 212, the bonding member 210 is disposed between the bump metal layer 202 and the bump metal layer 102, and the bonding member 212 is disposed between the bump metal layer 204 and the bump metal layer 104. In the direction X, the ratio of the width PCx of the bump metal layer 102 to the width PSx of the bump metal layer 202 is greater than or equal to 0.3 and less than or equal to 0.9. Although the electronic unit EU in the electronic device 1 is a tiny electronic unit (such as a micro light-emitting diode), the electronic unit EU and the substrate SU still have a high bonding strength, making the electronic device 1 have high reliability.

[0045] The content of the present invention is not limited to the above embodiments. Other embodiments of the present invention will be further disclosed below. However, for the sake of simplicity of description and highlighting the differences between the embodiments, the same reference numerals are used to label the same elements in the following text, and the repeated parts will not be described again.

[0046] Please refer to Figures 6 to 8 , Figures 6 to 8 which is a schematic diagram of the bonding process of the electronic device according to the second embodiment of the present invention, Figure 6 showing the state before the electronic unit and the substrate are bonded,Figure 7 shows the state where the electronic unit is in contact with the substrate but no intermetallic compound has been formed, while Figure 8 shows the state after the electronic unit is bonded to the substrate. In this embodiment, the positions of the solder and the conductive pads are different from those in the first embodiment. As Figure 6 , the electronic unit EU includes a conductive pad 110 and a conductive pad 112. The conductive pad 110 is disposed under the bump metal layer 102, while the conductive pad 112 is disposed under the bump metal layer 104. In addition, a solder 214 is disposed on the bump metal layer 202 of the substrate SU, and a solder 216 is disposed on the bump metal layer 204 of the substrate SU.

[0047] In some embodiments, the solders 214 and 216 may be tin, and the conductive pads 110 and 112 may be gold, but not limited thereto. In some embodiments, the solders 214 and 216 may be tin, and the conductive pads 110 and 112 may be nickel, but not limited thereto. In some embodiments, the solders 214 and 216 may be tin, and the conductive pads 110 and 112 may be copper, but not limited thereto. In some embodiments, the solders 214 and 216 may be indium, and the conductive pads 110 and 112 may be gold, but not limited thereto.

[0048] In this embodiment, the size of the bump metal layer 102 may be the same as the size of the bump metal layer 104. The sizes (such as area, length, or width) of the conductive pads 110 and 112 may be substantially the same as the sizes of the bump metal layer 102 and the bump metal layer 104, and the sizes of the solders 214 and 216 may be substantially the same as the sizes of the bump metal layer 202 and the bump metal layer 204. In addition, the areas of the bump metal layer 102 and the bump metal layer 104, as well as the areas of the conductive pads 110 and 112, may be smaller than the areas of the bump metal layer 202 and the bump metal layer 204, as well as the areas of the solders 214 and 216, but not limited thereto. However, in some embodiments, the areas of the bump metal layer 102 and the bump metal layer 104, as well as the areas of the conductive pads 110 and 112, may be larger than the areas of the bump metal layer 202 and the bump metal layer 204, as well as the areas of the solders 214 and 216, but not limited thereto.

[0049] Next, as Figure 7 shown, the solder 214 may be in direct contact with the conductive pad 110, and the solder 216 may be in direct contact with the conductive pad 112. Next, as Figure 8As shown, the bonding unit BU of the electronic device 1 after bonding includes a bonding member 218 and a bonding member 220. The bonding member 218 is disposed between the bump metal layer 202 and the bump metal layer 102, and the bonding member 220 is disposed between the bump metal layer 204 and the bump metal layer 104. In some examples, the solder 214 and the conductive pad 110 can be melted and mixed to form the bonding member 218, and the solder 216 and the conductive pad 112 can be melted and mixed to form the bonding member 220, and the bonding member 218 and the bonding member 220 are, for example, intermetallic compounds, but not limited thereto. In other examples, the solder can be melted while the conductive pad is not melted, and when the conductive pads come into contact with the melted solder, they diffuse and mix with each other to form the bonding member, but not limited thereto. After bonding, the bump metal layer 102, the bonding member 218, and the bump metal layer 202 can overlap in the direction V, and the bump metal layer 104, the bonding member 220, and the bump metal layer 204 can overlap in the direction V. In addition, the bump metal layers 102 and 104 of the electronic unit EU can be electrically connected to the bump metal layers 202 and 204 of the substrate SU through the bonding members 218 and 220.

[0050] When the solders 214 and 216 are disposed on the bump metal layers 202 and 204 with a larger area and the areas of the conductive pads 110 and 112 are smaller than the areas of the solders 214 and 216, the solders 214 and 216 will gather inward when melted, making the thickness of the bonding member 218 and the bonding member 220 larger than expected. When the bonding member 218 and the bonding member 220 are too thick, there is still a risk of being brittle and having insufficient mechanical strength, thereby reducing the reliability of the electronic device.

[0051] However, similar to the first embodiment, the bump metal layer 102, the bump metal layer 104, the bump metal layer 202, and the bump metal layer 204 of this embodiment also have the same width and area ratio design. Since the sizes of the solder and the conductive pad can be determined by designing the size of the bump metal layer, the proportional relationship between the widths and areas of the bump metal layers 102 and 104 and the widths and areas of the bump metal layers 202 and 204 can be equivalent to the proportional relationship between the widths and areas of the conductive pads 110 and 112 and the widths and areas of the solders 214 and 216. Through these designs, the variation range of the thickness of the joint can be reduced. For example, the thickness T2 of the bonding member 218 or the bonding member 220 in Figure 8 can be greater than or equal to 0.3 micrometers and less than or equal to 6.4 micrometers. The bonding members 218 and 220 with this thickness range can provide sufficient mechanical strength and improve the reliability of the electronic device 1.

[0052] Please refer to Figures 9 to 11 , Figures 9 to 11Schematic diagram of the bonding process of the electronic device according to the third embodiment of the present invention. Figure 9 The state before the electronic unit and the substrate are bonded is shown. Figure 10 The state after the electronic unit and the substrate are bonded is shown, and Figure 11 The state after the connection wire is formed is shown. The difference from the first embodiment is that the electronic unit in this embodiment is a vertical type light emitting diode. The electronic unit EU includes a body 100, a bump metal layer 114 and an electrode 116, but is not limited thereto. The bump metal layer 114 and the electrode 116 are respectively located on both sides of the body 100. For example, the electrode 116 is disposed on the upper surface of the body 100, and the bump metal layer 114 is disposed on the lower surface of the body 100, but is not limited thereto. The bump metal layer 114 can be electrically connected to one of the P-type semiconductor material and the N-type semiconductor material in the body 100, and the electrode 116 can be electrically connected to the other of the P-type semiconductor material and the N-type semiconductor material, but is not limited thereto. In addition, a solder 118 can be disposed on the lower surface of the bump metal layer 114, but is not limited thereto.

[0053] The substrate SU includes a bottom plate 200, a wire 222, a wire 224, a bump metal layer 226 and a conductive pad 228, but is not limited thereto. The wire 222 and the wire 224 are disposed on the bottom plate 200 and arranged along the direction X. Therefore, the wire 222 can be disposed on one side of the wire 224 in the direction X. The bump metal layer 226 is disposed on the wire 222. Therefore, the bump metal layer 226 and the wire 224 are also arranged along the direction X. In addition, the conductive pad 228 can be disposed on the upper surface of the bump metal layer 226, but is not limited thereto. The conductive pad 228 is electrically connected to the bump metal layer 226, and the bump metal layer 226 is electrically connected to the wire 222. Before bonding, the bump metal layer 226, the conductive pad 228, the solder 118 and the bump metal layer 114 can overlap in the direction V.

[0054] In some embodiments, the conductive pad 228 can be disposed on the lower surface of the bump metal layer 114, and the solder 118 can be disposed on the upper surface of the bump metal layer 226, but is not limited thereto.

[0055] Next, the solder 118 can be in direct contact with the conductive pad 228. Next, as Figure 10As shown, the bonding unit BU of the electronic device 1 after bonding may include a bonding member 230, and the bonding member 230 is disposed between the bump metal layer 226 and the bump metal layer 114. In some examples, the solder 118 and the conductive pad 228 may melt and mix to form the bonding member 230. In other examples, the solder may melt while the conductive pad does not melt, and when the conductive pad contacts the molten solder, they diffuse and mix with each other to form the bonding member, but this is not limited thereto. The bonding member 230 is, for example, an intermetallic compound, but this is not limited thereto. After bonding, the bump metal layer 114, the bonding member 230, and the bump metal layer 226 may overlap in the direction V. In addition, the bump metal layer 114 of the electronic unit EU may be electrically connected to the bump metal layer 226 and the wire 222 on the substrate SU through the bonding member 230.

[0056] Similar to the first embodiment, the bump metal layer 114 of the electronic unit EU and the bump metal layer 226 on the substrate SU in this embodiment also have the same width and area ratio design. The ratio relationship between the width and area of the bump metal layer 114 and the width and area of the bump metal layer 226 in this embodiment may be equivalent to the ratio relationship between the width and area of the bump metal layer 102 and the width and area of the bump metal layer 202 in the first embodiment. Since the sizes of the solder and the conductive pad can be determined by designing the size of the bump metal layer, the ratio relationship between the width and area of the bump metal layer 114 and the width and area of the bump metal layer 226 may be equivalent to the ratio relationship between the width and area of the solder 118 and the width and area of the conductive pad 228. Through these designs, the variation range of the thickness of the contact point can be reduced. For example, a thickness T3 of the bonding member 230 in Figure 10 after bonding may be greater than or equal to 0.3 micrometers and less than or equal to 6.4 micrometers. The bonding member 230 having this thickness range can provide sufficient mechanical strength and improve the reliability of the electronic device 1.

[0057] Next, as Figure 11 shown, an insulating layer 120 is formed on the substrate SU and the electronic unit EU, and the insulating layer 120 can cover the substrate SU and the electronic unit EU. The insulating layer 120 has an opening OP1 and an opening OP2. The opening OP1 can expose a part of the upper surface of the electrode 116 of the electronic unit EU, and the opening OP2 can expose a part of the upper surface of the wire 224. Next, a connecting wire 122 is formed on the insulating layer 120, and the connecting wire 122 can extend into the openings OP1 and OP2 and contact the electrode 116 and the wire 224. Therefore, the connecting wire 122 can electrically connect the electrode 116 of the electronic unit EU and the wire 224 of the substrate SU.

[0058] In some embodiments, the connecting wire 122, the electrodes 116 of the electronic unit EU, and the wires 222 and 224 of the substrate SU may include metals, transparent conductive materials, or other suitable conductive materials, but are not limited thereto.

[0059] As can be seen from the above, in this embodiment, an electronic device 1 may include a substrate SU, an electronic unit EU, a bonding unit BU, and a connecting wire 122. The substrate SU includes a bump metal layer 226 and a wire 224, wherein the bump metal layer 226 and the wire 224 are arranged along the direction X. The electronic unit EU includes a body 100, a bump metal layer 114, and electrodes 116. The bump metal layer 114 and the electrodes 116 are located on both sides of the body 100, respectively, and the bump metal layer 226 and the bump metal layer 114 overlap. The bonding unit BU includes a bonding member 230, wherein the bonding member 230 is disposed between the bump metal layer 226 and the bump metal layer 114. The connecting wire 122 is electrically connected to the electrode 116 of the electronic unit EU and the wire 224 of the substrate SU. In the direction X, the ratio of the width of the bump metal layer 114 to the width of the bump metal layer 226 is greater than or equal to 0.3 and less than or equal to 0.9.

[0060] In summary, in the electronic device of the present invention, by designing the sizes of the bump metal layers of the tiny electronic units and the bump metal layers on the substrate, the variation range of the thickness of the bonding member formed by melting and mixing the solder and the conductive pads can be reduced, so that the bonding member can provide sufficient mechanical strength and improve the reliability of the electronic device.

[0061] The above are only the embodiments of the present invention and are not intended to limit the present invention. For those of ordinary skill in the art, the present invention may have various changes and modifications. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. An electronic device, characterized in that, Comprising: A substrate including a first bump metal layer and a second bump metal layer, wherein the first bump metal layer and the second bump metal layer are arranged along a first direction; An electronic unit including a third bump metal layer and a fourth bump metal layer, wherein the first bump metal layer and the third bump metal layer overlap, and the second bump metal layer and the fourth bump metal layer overlap; and A bonding unit including a first bonding member and a second bonding member, wherein the first bonding member is disposed between the first bump metal layer and the third bump metal layer, and the second bonding member is disposed between the second bump metal layer and the fourth bump metal layer, wherein in the first direction, a ratio of a width of the third bump metal layer to a width of the first bump metal layer is greater than or equal to 0.3 and less than or equal to 0.

9.

2. The electronic device according to claim 1, wherein The ratio of the width of the third bump metal layer to the width of the first bump metal layer is greater than or equal to 0.5 and less than or equal to 0.

8.

3. The electronic device according to claim 1, characterized in that, In a second direction perpendicular to the first direction, a ratio of a width of the third bump metal layer to a width of the first bump metal layer is greater than or equal to 0.1 and less than or equal to 0.

9.

4. The electronic device according to claim 3, characterized in that, In the second direction, the ratio of the width of the third bump metal layer to the width of the first bump metal layer is greater than or equal to 0.2 and less than or equal to 0.

8.

5. The electronic device according to claim 1, characterized in that, A ratio of an area of the third bump metal layer to an area of the first bump metal layer is greater than or equal to 0.1 and less than or equal to 0.

64.

6. The electronic device according to claim 1, wherein When the width of the third bump metal layer is less than or equal to 5 microns, the ratio of the width of the third bump metal layer to the width of the first bump metal layer is greater than or equal to 0.33 and less than or equal to 0.

75.

7. The electronic device according to claim 6, wherein, The ratio of the area of the third bump metal layer to the area of the first bump metal layer is greater than or equal to 0.11 and less than or equal to 0.

56.

8. The electronic device according to claim 1, wherein, A thickness of the first bonding member or the second bonding member is greater than or equal to 0.3 microns and less than or equal to 6.4 microns.

9. The electronic device according to claim 1, wherein The electronic unit is a flip-chip light-emitting diode.

10. An electronic device, characterized in that, Comprising: A substrate including a first bump metal layer and a wire, wherein the first bump metal layer and the wire are arranged along a first direction; An electronic unit including a body, a second bump metal layer and an electrode, the second bump metal layer and the electrode are respectively located on two sides of the body, and the first bump metal layer and the second bump metal layer overlap; A bonding unit including a bonding member, wherein the bonding member is disposed between the first bump metal layer and the second bump metal layer; and A connecting wire electrically connecting the electrode of the electronic unit and the wire of the substrate, wherein in the first direction, a ratio of a width of the second bump metal layer to a width of the first bump metal layer is greater than or equal to 0.3 and less than or equal to 0.9.

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