Apparatus including interrupt tracking circuit

Abstract

An apparatus (10) and method are provided in which the apparatus includes an interrupt detection circuit (40) that detects an interrupt caused by at least one interrupt source (14), and an interrupt tracking circuit (44) that manages one or more hardware-managed linked list data structures to track a suspended interrupt detected by the interrupt detection circuit. A computer program including computer-readable code for manufacturing the apparatus, and a computer-readable storage medium are also provided.

Description

[0001] This technology relates to the field of data processing.

[0002] An interrupt controller in a data processing system detects interrupts triggered by one or more interrupt sources and signals the detected interrupts to a processor responsible for handling the interrupts.

[0003] In one example of this technology, an apparatus is provided, which includes:

[0004] An interrupt detection circuit for detecting interrupts triggered by at least one interrupt source; and

[0005] An interrupt tracking circuit for managing one or more hardware-managed linked list data structures to track pending interrupts detected by the interrupt detection circuit.

[0006] In another example of this technology, a system is provided, which includes:

[0007] The above-mentioned apparatus;

[0008] An interconnect circuit coupled to the apparatus; and

[0009] At least one processing element coupled to the interconnect circuit.

[0010] In another example of this technology, a method is provided, which includes:

[0011] Detecting interrupts triggered by at least one interrupt source using an interrupt detection circuit; and

[0012] Tracking pending interrupts detected by the interrupt detection circuit by hardware-managing one or more linked list data structures.

[0013] In another example of this technology, a computer program is provided, which includes computer-readable code for manufacturing an apparatus, the apparatus including:

[0014] An interrupt detection circuit for detecting interrupts triggered by at least one interrupt source; and

[0015] An interrupt tracking circuit for managing one or more hardware-managed linked list data structures to track pending interrupts detected by the interrupt detection circuit.

[0016] In another example of this technology, a computer-readable storage medium for storing the above computer program is provided.

[0017] Additional aspects, features, and advantages of this technology will be apparent from the following description of the examples read in conjunction with the accompanying drawings, in which:

[0018] Figure 1 and Figure 2 illustrates an example of a data processing system in which one or more CPUs are coupled to an interrupt controller and a memory via an interconnect;

[0019] Figure 3 and Figure 4 illustrates how a head pointer and a tail pointer managed by an interrupt tracking circuit can be used to track pending interrupts in a linked list data structure;

[0020] Figure 5 illustrates an example of an entry in a hardware-managed linked list data structure;

[0021] Figure 6 illustrates how an entry can be removed from a doubly linked list;

[0022] Figure 7 is a flowchart illustrating the tracking of interrupts by an interrupt controller;

[0023] Figure 8 is a flowchart illustrating a process for identifying a highest priority pending interrupt (HPPI); and

[0024] Figure 9 is a flowchart illustrating the removal of an interrupt from a doubly linked list.

[0025] Before discussing example embodiments with reference to the accompanying drawings, the following description of example embodiments and associated advantages is provided.

[0026] According to one example configuration, a device is provided that includes: an interrupt detection circuit for detecting interrupts triggered by at least one interrupt source; and an interrupt tracking circuit for managing one or more hardware-managed linked list data structures to track pending interrupts detected by the interrupt detection circuit.

[0027] The device (e.g., can be an interrupt controller (interrupt control circuit)) is responsible for detecting interrupts triggered by one or more interrupt sources (e.g., these can be peripheral devices), and is also responsible for signaling the interrupt to a processor (both virtual and physical processors) responsible for processing the interrupt. An interrupt can be a request to interrupt currently executing code to handle / respond to a specific event. For example, an interrupt can be used by a hardware device (e.g., a peripheral device) to indicate an electrical or physical state change that requires a timely response. Interrupts can also be used to implement computer multitasking, especially in real-time computing.

[0028] An interrupt controller may maintain one or more interrupt tracking structures (e.g., in a storage circuit such as a memory), which hold information about currently pending interrupts. These data structures are available for use by a processor responsible for handling interrupts to provide information about the interrupts to the processor. However, as the number of processors and the number of interrupts increase, the size of these interrupt tracking data structures also increases. For example, an interrupt tracking structure may include a large bit array indicating the pending and enabled status of a large number of interrupts. In such a particular implementation, identifying a pending interrupt that needs to be processed by a processor (e.g., determining the highest priority pending interrupt (HPPI)) requires scanning these large bit arrays. This process can be time-consuming and may result in reduced performance of the interrupt controller and increased implementation costs.

[0029] The present technology provides an improved method. Specifically, the apparatus of the present technology is arranged to track pending (e.g., unresolved) interrupts in a tracking structure in the form of a hardware-managed linked list. A linked list is an ordered list of entries (in this case, entries identifying pending interrupts), where each entry points to the next entry in the list. Thus, these successor pointers can be used to traverse the linked list without the need to scan a large data array to identify each entry. Therefore, tracking pending interrupts in the linked list allows a processor, interrupt controller, or other circuitry to quickly identify the next pending interrupt in a given order without scanning a large interrupt tracking structure.

[0030] The linked list data structures provided by the present technology are managed by hardware; specifically, they are managed by an interrupt tracking circuit, which is hardware within the apparatus. This means that the management of the linked list can be centrally performed by the apparatus itself without relying on processing circuitry within one or more processors of a system that executes software to manage the linked list.

[0031] Thus, the present technology provides a method of tracking interrupts by hardware, which reduces the performance cost associated with tracking interrupts and can be scaled to systems with different numbers of processors and different numbers of interrupts.

[0032] The present technology may be particularly advantageous in systems with a large number of interrupts because the number of interrupts in a given linked list can be significantly smaller than the total number of interrupts. For example, if an interrupt tracking table is used to track pending interrupts, the number of entries in the interrupt tracking table can be significantly larger than the number of entries in any given linked list, thus avoiding any long-running search operations.

[0033] In some examples, the interrupt tracking circuit includes a pointer storage circuit that stores, for each of one or more hardware-managed linked list data structures, a head pointer indicating the first entry in the hardware-managed linked list data structure and a tail pointer indicating the last entry in the hardware-managed linked list data structure.

[0034] The present technique can implement the one or more hardware-managed linked list data structures (also referred to herein as "hardware-managed linked lists" or simply "linked lists") in many ways. In a particular example, the linked list can be implemented using "head" and "tail" pointers maintained in a pointer storage circuit (provided by hardware) in the device. Specifically, the head pointer identifies the first entry (also referred to as the head entry) in a given linked list, and the tail pointer identifies the last entry (also referred to as the tail entry) in a given linked list; if multiple linked lists are provided, a head pointer and a tail pointer can be provided for each linked list.

[0035] The head pointer provides a simple and efficient way to identify the next pending interrupt in a given linked list (e.g., when determining which interrupt the given processor should handle next; the head pointer identifies the next interrupt in the linked list) without scanning the entire data array in a storage structure such as system memory. Thus, this avoids the performance cost and energy cost associated with scanning a large amount of data. Similarly, providing a tail pointer enables easy location of the end of the list (e.g., the tail pointer identifies the end of the list), such as when adding another interrupt to the end of the list. Providing the head pointer and the tail pointer in this way can also clearly indicate when a given list is empty; for example, when the head pointer of a given linked list indicates that the linked list is empty (e.g., if the head pointer is invalid), this can be interpreted as indicating that there are no pending interrupts in the linked list. Checking one pointer to determine if any interrupts are pending has a much lower performance cost than scanning the entire array in memory and only finding that none of the represented interrupts are pending.

[0036] In some examples, the one or more hardware-managed linked list data structures include at least one physical interrupt linked list that tracks physical interrupts and at least one virtual interrupt linked list that tracks virtual interrupts, and the interrupt tracking circuit includes a memory access circuit that maintains a pointer data structure in a memory accessible by the interrupt controller, and for each of the at least one virtual interrupt linked lists, the pointer data structure stores a head pointer indicating the first entry in the hardware-managed linked list data structure and a tail pointer indicating the last entry in the hardware-managed linked list data structure.

[0037] Thus, the head and tail pointers for one or more virtual interrupt lists may be stored in shared memory (e.g., as opposed to being stored in a pointer storage circuit as in the above example). This supports storing the state of a scalable number of virtual machines (VMs) in addition to physical interrupts (where the head / tail pointers may be stored, for example, in a pointer storage circuit in an interrupt controller).

[0038] In some examples, in response to identifying a given interrupt to be tracked, an interrupt tracking circuit:

[0039] i) Updates the next entry pointer in the last entry of a given hardware-managed linked list data structure to point to the entry corresponding to the given interrupt; and

[0040] ii) Updates the tail pointer of the given hardware-managed linked list data structure in the one or more hardware-managed linked list data structures to indicate the entry corresponding to the given interrupt.

[0041] Note that steps (i) and (ii) may be performed in any order, and may be performed in parallel or one after the other. Additionally, it should be noted that in some implementations, identifying a given interrupt to be tracked may refer to either the interrupt detection circuit detecting an interrupt (specifically, an enabled interrupt) or the interrupt tracking circuit determining that a previously disabled interrupt has been enabled, or both.

[0042] In this example, the tail pointer for a particular linked list maintained by hardware is used to add an interrupt to the list of pending interrupts to be tracked, thereby allowing support for a first-in, first-out (FIFO) scheme, which avoids interrupt starvation in a given list (e.g., the head pointer could simply be used to identify the next interrupt to be serviced and the location to insert more interrupts to be tracked; however, this could lead to interrupt starvation).

[0043] In some examples, a pointer storage circuit is configured to: store the interrupt identifier associated with the interrupt represented by the first entry of each hardware-managed linked list data structure in the one or more hardware-managed linked list data structures as the head pointer of the hardware-managed linked list data structure, and store the interrupt identifier associated with the interrupt represented by the last entry of each hardware-managed linked list data structure in the one or more hardware-managed linked list data structures as the tail pointer of the hardware-managed linked list data structure.

[0044] In some specific implementations, the head pointer and the tail pointer stored in the pointer storage circuit may take the form of address pointers; for example, the head pointer and the tail pointer can identify these entries by indicating the addresses storing the head entry and the tail entry of a given linked list. However, in this example, the head pointer and the tail pointer include interrupt identifiers. Specifically, the head pointer of a given linked list is the interrupt identifier of the interrupt at the head of the linked list, and the tail pointer of the given linked list is the interrupt identifier of the interrupt at the tail of the linked list (unless the linked list is empty, in which case, the head pointer and the tail pointer can store a certain default value to indicate that the list is empty).

[0045] Using interrupt identifiers as the head pointer and the tail pointer instead of address pointers allows the pointers to remain valid across virtualization and address translation boundaries and across physical machine boundaries (e.g., in the context of virtual machine (VM) migration); this is because the interrupt identifier remains the same regardless of the physical address and / or virtual address where the head entry and the tail entry of the saved list are located. For example, if the linked list data structure is moved from one area of the memory to another area (e.g., when a virtual machine is migrated from one CPU to another CPU), the physical address for each entry in the linked list will be updated, but the interrupt identifier will not necessarily be updated. Similarly, if the address translation for one or more entries changes (e.g., the virtual address changes), the interrupt identifier will not necessarily change. Therefore, using interrupt identifiers as the head pointer and the tail pointer allows the pointers to remain valid regardless of how the physical or virtual address of the entries changes.

[0046] In examples such as this, the interrupt tracking circuit can adopt a scheme for mapping the interrupt identifier to the address storing the corresponding entry in the memory (or other storage circuit); for example, this may involve calculating an offset relative to a base address based on the interrupt identifier or a part of the interrupt identifier. In addition, it should be noted that any pointers within a given entry in the linked list (as described below, these pointers can include, for example, pointers to the next entry in the list and optionally pointers to the previous entry in the list) can also be represented as interrupt identifiers.

[0047] In some examples, the interrupt tracking circuit is configured to: identify one of the multiple priority levels associated with each pending interrupt, and for each of the multiple priority levels, manage the corresponding hardware-managed linked list data structure to track the pending interrupts associated with that priority level.

[0048] Different interrupts may be associated with different priorities or levels of importance. In this example, a linked list is maintained for each of the multiple priority levels of pending interrupts. This simplifies the process for inserting a new interrupt into the tracking structure. For example, while it is possible to provide a single linked list that identifies the pending interrupts from multiple priority levels and is sorted by priority level (e.g., the highest priority pending interrupt (HPPI) is at the head of the list), adding a new pending interrupt with a given priority level to such a list would require searching the list to find the correct position to insert the interrupt based on the priority of the interrupt. In contrast, providing separate linked lists for each of the different priority levels simplifies the insertion of newly pending interrupts.

[0049] However, it should be understood that in an alternative embodiment, a single linked list may be provided to track all pending interrupts. For example, this may be an appropriate approach if there is only one priority level or level of importance, or if the number of pending interrupts to be tracked is small.

[0050] In some examples, the interrupt tracking circuit is configured to identify the next entry in a linked list data structure managed by a given hardware in each entry of the linked list data structure managed by the given hardware except for the last entry.

[0051] Thus, the linked list data structure (linked list) managed by the hardware can be a list of entries, where any given entry except for the last entry points to the next entry in the linked list.

[0052] In some examples, the interrupt tracking circuit is configured to manage the one or more linked list data structures managed by the hardware as a doubly linked list, where each entry in the linked list data structure managed by the given hardware except for the first entry and the last entry indicates the next entry in the linked list data structure managed by the given hardware and the previous entry in the linked list data structure managed by the given hardware.

[0053] In some examples, the linked list used in this technology may be provided as a singly linked list (e.g., in such a linked list, each entry except the last entry identifies the next entry but not the previous entry). However, implementing the linked list as a doubly linked list (e.g., in such a linked list, each entry except the first and last entries identifies both the next entry and the previous entry in the linked list) may be particularly advantageous. Specifically, when using a doubly linked list, this can simplify the "repair" of the list after an entry is removed. For example, when an entry is removed (e.g., when an interrupt is no longer pending and enabled), the entries on either side of the removed entry can be identified based on the successor and predecessor pointers in the entry, and the list can be repaired by updating the pointers in these identified entries. Thus, a doubly linked list can be "repaired" after an entry is removed without fully scanning the interrupt trace structure. Additionally, by simply detecting a cycle in the list, a particular implementation using a doubly linked list in this way can be robust to a malformed list, which would otherwise require some form of pointer chasing (e.g., hare and tortoise) algorithm.

[0054] In some examples, the interrupt trace circuit removes an entry representing a given interrupt from one or more hardware-managed linked list data structures in response to determining that the given interrupt is no longer pending, wherein removing the entry representing the given interrupt includes updating the previous entry in the hardware-managed linked list data structure to point to the entry after the entry removed from the hardware-managed linked list data structure.

[0055] In this way, the hardware-managed linked list data structure can be updated after an entry is removed, thus maintaining the list structure and sorting. Note that the above process applies to removing an entry from a singly linked list or from a doubly linked list; for example, in a singly linked list, an entry can be removed from the singly linked list simply by updating the previous entry to point to the entry after the removed entry. However, note that in a singly linked list, it may be necessary to traverse the list from the beginning to find the entry that points to the deleted entry.

[0056] Note that if an entry is removed from the head or tail of the linked list (or, in fact, if an entry is added to the head or tail of the linked list), it may also be necessary to update the head pointer and tail pointer of the linked list, providing the head pointer and tail pointer in such cases.

[0057] In some examples, the interrupt trace circuit is configured to manage the one or more hardware-managed linked list data structures as a doubly linked list, wherein each entry in the doubly linked list except the first and last entries indicates the next entry and the previous entry in the doubly linked list, and wherein removing the entry representing the given interrupt includes updating the next entry in the doubly linked list to point to the entry before the entry removed from the doubly linked list.

[0058] This allows entries to be removed from the doubly linked list, thus maintaining the list structure and sorting.

[0059] In some examples, the one or more hardware-managed linked list data structures are stored in shared memory.

[0060] Thus, while the head pointer and the tail pointer (if provided) may be provided in the storage circuitry within the device, and while the linked list is managed by the hardware of the interrupt circuitry, in this example, the linked list data structure itself is stored in shared memory accessible by the device (e.g., via an interconnect). This shared memory may also be accessible by one or more processors, including the processor responsible for processing pending interrupts. Note that if the format of the hardware-managed linked list data structure is standardized across physical machines, this enables writing the structures on one machine and reading them on different machines.

[0061] Storing the hardware-managed linked list data structure in memory reduces the circuit area required to implement the device (since the amount of storage space required within the device can be reduced compared to the amount of storage space required to store the linked list locally).

[0062] In some examples, the interrupt tracking circuit is configured to manage one or more interrupt tracking tables in shared memory to represent the one or more hardware-managed linked list data structures. In such examples, each interrupt tracking table includes entries for each of a plurality of interrupts, and the interrupt tracking circuit is configured to: manage the one or more hardware-managed linked list data structures by setting pointers to the next entry in the given hardware-managed linked list data structure in each entry of a given interrupt tracking table representing a pending interrupt to be tracked, except for the last entry.

[0063] In this example, the linked list is represented in memory using an interrupt tracking table (also referred to herein as an interrupt status table (IST)). Each interrupt tracking table may include a plurality of entries, each entry representing an interrupt (e.g., each entry may indicate the interrupt identifier of the interrupt), and providing information about the interrupt (e.g., including whether the interrupt is pending and enabled). The one or more linked lists are then represented by updating the entries in the interrupt tracking table; for example, an entry may be updated to include a pointer to the next entry in the list. Thus, the linked list provides an indication of the order of pending interrupts represented in one or more interrupt tracking tables.

[0064] Using the interrupt tracking table in this way reduces the number of memory accesses that need to be performed to update the linked list, since existing entries in the table can be updated rather than writing new entries to the list. Additionally, the use of the interrupt tracking table means that the storage required to manage the linked list scales naturally with the number of interrupts required.

[0065] In some examples, the interrupt trace circuit is configured to: manage multiple interrupt trace tables to represent the one or more hardware-managed linked list data structures; and the interrupt trace circuit is configured to: set a table identifier in each entry of a given interrupt trace table that represents a pending interrupt to be traced to identify which of the multiple interrupt trace tables contains the next entry in the given hardware-managed linked list data structure.

[0066] By setting a table identifier in each entry of the linked list, a given linked list can span multiple interrupt trace tables (e.g., including entries represented in multiple interrupt trace tables), thereby allowing the order associated with interrupts in multiple tables to be traced in a single linked list.

[0067] In some examples, each of the multiple interrupt trace tables represents a different class of interrupt.

[0068] Thus, in this example, providing a table identifier in the entries of a given linked list can allow the linked list to indicate the order in which multiple classes of interrupts are to be processed relative to each other. The manner in which interrupts can be classified can depend on the particular implementation, but in some examples, interrupts can be classified as private to a given processor or shared among multiple processors.

[0069] In some examples, a system is provided that includes the apparatus described in any of the above examples, as well as an interconnect circuit (also referred to herein as an interconnect) coupled to the apparatus, and at least one processing element coupled to the interconnect circuit.

[0070] The at least one processing element can include one or more processors responsible for processing the pending interrupts detected by the apparatus. Additionally, one or more processing elements can execute software to provide a virtual processor that can also be responsible for processing some or all of the pending interrupts. The one or more processing elements (PEs) and the apparatus can be arranged to communicate via the interconnect (interconnect circuit), and they can also access shared memory via the interconnect.

[0071] In some examples, at least one of the interrupt trace circuit and the at least one processing element is configured to identify the next-highest priority pending interrupt by identifying the highest-priority linked list data structure that contains at least one entry corresponding to the pending interrupt and identifying the next entry in the hardware linked list data structure.

[0072] Thus, providing one or more hardware-managed linked list data structures can provide a simple mechanism for determining the next-highest priority pending interrupt to be processed by a particular processing element.

[0073] The concepts described herein can be embodied in computer-readable code for fabricating an apparatus embodying the described concepts. For example, the computer-readable code can be used in one or more stages of a semiconductor design and fabrication process, including an electronic design automation (EDA) stage, to fabricate an integrated circuit including an apparatus embodying these concepts. The computer-readable code can additionally or alternatively enable the definition, modeling, simulation, verification, and / or testing of an apparatus embodying the concepts described herein.

[0074] For example, computer-readable code for fabricating an apparatus embodying the concepts described herein can be embodied in code represented in a hardware description language (HDL) that defines these concepts. For example, the code can define a register transfer level (RTL) abstraction of one or more logic circuits for use in defining an apparatus embodying these concepts. The code can define the HDL representation of one or more logic circuits of an apparatus in Verilog, SystemVerilog, Chisel, or VHDL (Very High-Speed Integrated Circuit Hardware Description Language), as well as an intermediate representation such as FIRRTL. The computer-readable code can provide a definition of the concepts or other behavioral representations of the concepts embodied using a system-level modeling language such as SystemC and SystemVerilog, which can be interpreted by a computer to enable simulation, functional, and / or formal verification and testing of the concepts.

[0075] Additionally or alternatively, the computer-readable code can embody a computer-readable representation of one or more netlists. One or more netlists can be generated by applying one or more logic synthesis processes to the RTL representation. Alternatively or additionally, one or more logic synthesis processes can generate a bitstream to be loaded into a field-programmable gate array (FPGA) from the computer-readable code to configure the FPGA to embody the described concepts. The FPGA can be deployed for the purpose of verifying and testing the concepts prior to fabricating an integrated circuit, or the FPGA can be directly deployed in a product.

[0076] The computer-readable code can include a mixture of code representations for fabricating an apparatus, such as a mixture including an RTL representation, a netlist representation, or one or more of another computer-readable definition used in a semiconductor design and fabrication process to fabricate an apparatus embodying the present invention. Alternatively or additionally, the concepts can be defined in a combination of a computer-readable definition for fabricating an apparatus in a semiconductor design and fabrication process and computer-readable code defining instructions that will be executed by the defined apparatus once fabricated.

[0077] Such computer-readable code can be provided on any known transient computer-readable medium (such as a wired or wireless transmission of the code over a network) or non-transient computer-readable media such as semiconductors, magnetic disks, or optical discs. An integrated circuit fabricated using the computer-readable code can include components such as one or more of the following: a central processing unit, a graphics processing unit, a neural processing unit, a digital signal processor, or other components that individually or jointly embody the concept.

[0078] Some specific examples will now be described with reference to the accompanying drawings. It should be understood that the claimed subject matter is not limited to these specific examples.

[0079] Figure 1 An example of a data processing system 2 (e.g., a system-on-chip) in which the present technology can be implemented is schematically shown. The data processing system 2 includes a plurality of processing elements (PEs) 4 (e.g., processing circuitry such as a central processing unit, a CPU; the processing circuitry may also be referred to as a “processor”). In this example, three processors 4 are shown, but it should be understood that the number of processors can vary. The processors communicate with each other and with a shared memory 8 via a cache-coherent interconnect 6 that supports a coherence protocol to maintain cache coherence of the data cached in the private cache of each processor 4.

[0080] An interrupt controller 10 is provided to receive incoming interrupt signals from the connected peripheral devices 14 (here they are examples of interrupt sources) and forward the incoming interrupt signals to the processors 4. In some cases, a processor also generates interrupts for other processors (referred to as inter-processor interrupts (IPIs)), so the processors 4 themselves can also act as interrupt sources. The peripheral devices can signal the interrupt to the interrupt controller 10 via dedicated wires 11 or by reusing an existing I / O (input / output) mechanism 12 (such as a memory-mapped I / O write operation). The latter is commonly referred to as message-signaled interrupt (MSI). The job of the interrupt controller is to prioritize the interrupts according to a configuration executed by software to ensure that higher-priority interrupts are presented to the processors before lower-priority interrupts. On modern multi-processor systems with more than a single processor, the interrupt controller may also have to route the interrupts to one or more designated processors and handle reprogramming of the routing configuration without losing interrupt signals.

[0081] Accordingly, the interrupt controller needs to be able to communicate with the processors to which it can forward interrupts. As Figure 1As shown, one way to achieve this is to use a dedicated communication protocol and an interrupt communication bus 16 in the system, which is specifically designed to carry interrupt signals from the interrupt controller 10 to the processor 4. The interrupt communication bus 16 is completely separate from the cache coherence interconnect 6 that is used to transfer memory transactions between the processor 4, the memory 8, and the interrupt controller 10 (the interrupt controller 10 may still have an interface to the cache coherence interconnect 6 to allow memory transactions for programming configuration information issued by the processor 4, which controls how the interrupt controller 10 forwards interrupts to the processor 4).

[0082] Alternatively, the interrupt controller may send an "interrupt occurred" signal to the processor via a bus to prompt the software executing on the processor to read an interrupt trace structure in memory to determine which interrupts are pending. This can reduce the number of bits that need to be provided in the bus because information such as the type of a given interrupt may not be needed when sending the "interrupt occurred" signal. Additionally, even when an interrupt is signaled via the interrupt bus, an interrupt trace structure may still be provided in the shared memory 8, which can be queried (e.g.,) by software to determine which interrupts are pending and enabled. In the present technology, these interrupt trace structures are implemented as hardware-managed linked list data structures.

[0083] Although a dedicated interrupt communication bus 16 and protocol are provided in the Figure 1 example, this is just one option for signaling interrupts to the processor. However, this approach may require a significant amount of design work, especially in large distributed systems and for multi-socket implementations. Figure 2Another way to provide an implementation of the data processing system 18 of the present technology is shown. In this example, a dedicated interrupt bus is not necessary because the existing cache coherence mechanism supported by the cache coherence interconnect 6 is used to distribute interrupts from the interrupt controller 10 to the processors 4, and the interrupt configuration and status are represented by a memory-based table 20 shared by the processors 4 and the interrupt controller 10. The interrupt tracking data structure 20 is stored in the memory and the cache coherence protocol of the cache coherence interconnect 6 is used to ensure consistency between the views of the shared tracking data structure seen by the interrupt controller 10 and the processors 4, which means that when an interrupt changes state due to a message or signal received by the interrupt controller 10, the interrupt controller can cause the interrupt to be delivered to the correct processor by simply updating the tracking data structure stored in the memory. This can be done by using the existing cache coherence interconnect mechanism supported by the interconnect 6 without the need for a dedicated interrupt bus 16. This greatly reduces the design effort involved in scaling the chip design according to different numbers of processors and interrupts, because scaling can be achieved by changing the size or number of the structures of the data stored in the memory without the need to extend the wiring of the dedicated interrupt distribution bus 16.

[0084] As Figure 1 shown, the system 18 includes at least one processor 4, an interrupt controller 10, a cache coherence interconnect 6, and a memory 8. Although only a single processor 4 is shown for simplicity, Figure 2 additional processors may be provided, and these additional processors may operate in the same manner as Figure 2 the processor 4 shown.

[0085] A given processor 4 includes processing circuitry 22 for performing data processing operations in response to instructions. For example, the processing circuitry 22 may include a processing pipeline having pipeline stages for fetching, decoding, and executing instructions. Any known pipeline design may be used for the processor 4. The processor 4 also includes a processor memory access circuit 26 that acts as an interface between the processor 4 and the cache coherence interconnect 6 and is responsible for issuing memory access requests and receiving responses to the memory access requests, as well as receiving / sending other messages, such as snoop requests and responses, according to the coherence protocol operated by the cache coherence interconnect 6.

[0086] The data processing system 18 also includes an interrupt controller 10 that includes interrupt detection circuitry 40 to detect interrupts triggered by interrupt sources such as the processor 4 or a peripheral device 14 (although not explicitly shown in Figure 2 but as Figure 1As shown, a dedicated interrupt wiring 11 can be used or a message-based method can be utilized to detect an interruption, in which an interruption is signaled in-band in a memory transaction for accessing the memory system 8 sent by a peripheral device). The interrupt tracking circuit 44 responds to the detection of a given interruption by the interrupt detection circuit 40 to control the tracking of pending interruptions using an interrupt tracking table 20 in the memory and pointers stored in a pointer storage circuit 48 provided in the interrupt tracking circuit 44. An interrupt controller memory access circuit 46 is provided to control access to the memory system for the interrupt controller 10 and manage the exchange of cache coherence messages between the interrupt controller 10 and the cache coherence interconnect 6.

[0087] One or more interrupt tracking tables 20 provided in the shared memory 8 are data arrays indicating the pending state and enabled state of each of a plurality of interruptions. When a given enabled interruption triggered by an interruption source is detected, the interrupt control circuit 44 signals the given enabled interruption to a given processor by controlling the interrupt controller memory access circuit 46 to issue one or more memory write requests to update the interrupt tracking table corresponding to the target interrupt processing context in which the interruption is to be processed; for example, these write requests may cause the pending and / or enabled state of the given interruption to be updated in the table.

[0088] According to the present technique, the interrupt tracking circuit 44 tracks the pending enabled interruptions detected by the interrupt detection circuit 40 by maintaining one or more hardware-managed linked list data structures. A linked list is a list of items, where each item except the last entry includes a "next" pointer pointing to the next entry in the list. In Figure 2 the system 18 shown, the entries in the linked list are represented in one or more interrupt tracking tables 20. Specifically, each entry in the interrupt tracking table that is also in the linked list will include a successor pointer, as described above. This allows the order of pending and enabled interruptions to be tracked.

[0089] In addition to controlling the interrupt controller memory access circuit 46 to issue write requests to update the entries in the interrupt tracking table 20, the interrupt tracking circuit 44 also updates the pointers stored in the pointer storage circuit 48. These pointers indicate the head (first) and tail (last) entries of each linked list maintained by the interrupt tracking circuit 44.

[0090] As described above, separate interrupt trace structures can be provided for different interrupt handling contexts. Each interrupt handling context can be a physical processor 4 implemented in hardware within the system or a virtual processor that is software executed on the physical processor 4 to simulate the behavior of different processors. At any given time, a given physical processor 4 can execute an active virtual processor (referred to as a "resident" virtual processor), but there can also be multiple inactive virtual processors waiting for an execution slot on the physical processor (these inactive virtual processors can be referred to as "non-resident" virtual processors). Each interrupt handling context can have a corresponding set of memory-based interrupt trace structures.

[0091] Figure 3 An example is shown of how a head pointer and a tail pointer in a pointer storage circuit and at least one interrupt trace table can be used to manage updates to a linked list data structure. Note that although the linked list data structure itself can be stored in a general memory storage that can also be used for other data, and the storage of the linked list in memory can depend on address allocation managed by software, updates to the linked list data structure of the present technology are managed by hardware and thus are performed without explicit software guidance.

[0092] As Figure 3 shown, the interrupt trace table 20 (also referred to herein as the interrupt status table (IST)) includes a plurality of entries (each entry is labeled as ISTE in Figure 3 ). A subset of the entries in the IST forms part of a set of hardware-managed linked lists, as indicated by the arrows (the arrows connect adjacent entries in a given linked list). Specifically, Figure 3 a doubly linked list is shown, where each entry (except the first and last entries) includes a "previous" pointer pointing to the previous entry in the list and a "next" pointer pointing to the next entry in the list (note that Figure 3 successor and predecessor pointers are not shown). Thus, the order of the entries in a given linked list can be determined by traversing the list in either direction using the successor or predecessor pointers.

[0093] Figure 3 An example of a pointer storage circuit 48 is also shown. In this example, the pointer storage circuit includes a set of pointers for each of a plurality of PEs (e.g., PE 0 and PE 1), and a set of pointers for "1 out of N interrupts" (e.g., the interrupts to be handled by any one of a given list of PEs).

[0094] For each linked list, the pointer storage circuit stores a head pointer 50 and a tail pointer 52; the head pointer 50 is a pointer to the first / next entry in the linked list, and the tail pointer 52 is a pointer to the last entry in the list.

[0095] As Figure 3 shown, multiple linked lists can be maintained by an interrupt tracking circuit. In this particular example, for each PE (and for one of the N interrupts), a linked list is maintained for each priority level (priority 0, priority 1, etc.). Thus, the HPPI can be determined by reading the head pointer for the highest priority level (e.g., priority 0). If this head pointer indicates that the associated list is empty, then the head pointer for the next highest priority pending interrupt can be read, and so on. Providing a separate linked list for each priority level is advantageous because it simplifies the operation of inserting a new interrupt into the list; for example, if an interrupt with priority 1 becomes pending and enabled, it can be simply inserted into a given position (e.g., at the tail) in the corresponding list. In contrast, if a single linked list is provided in priority order, inserting a new interrupt would involve searching the list to find the appropriate position to insert the interrupt.

[0096] Figure 4 Another example of how an IST can be used to maintain a linked list data structure is shown. Specifically, Figure 4 shown is how a single linked list can span multiple ISTs. To facilitate this, each pointer in the entries of the IST (e.g., each previous pointer and each next pointer) and each pointer in the pointer storage circuit includes a table identifier (table ID) indicating the IST in which the corresponding entry is stored.

[0097] As Figure 4 shown, a separate IST 20 can be provided for each class of interrupt. Thus, providing the table ID in each pointer allows a given linked list to span multiple tables, which in turn allows interrupts from different classes to be tracked in the same linked list. This avoids the need to check multiple linked lists (e.g., if a separate linked list is provided for each class) to determine which interrupt is the next one to be processed.

[0098] Figure 5 An example of an IST entry 54 is shown. In this example, each IST entry 54 contains an interrupt identifier (INTID) 56 for a particular interrupt, a field holding a previous (PREV) pointer 58 that points to the previous entry in the linked list, and a field holding a next (NXT) pointer 60 that points to the next entry in the linked list. In this example, the IST entry 54 is compatible with a doubly linked list data structure (because it provides fields for identifying both the previous entry and the next entry); however, in other embodiments, only the next pointer can be provided (i.e., the previous pointer can be omitted), thus providing a singly linked list.

[0099] In this example, each of the PREV pointer and the NXT pointer includes an INTID 62, 64 identifying the previous / next entry, and a table identifier (TAB ID) 66, 68 indicating the IST in which the previous / next entry is found. This allows the linked list to traverse multiple ISTs, as described above. It should be understood that in specific implementations where the linked list does not need to traverse multiple tables, the table identifiers 66, 68 may be omitted.

[0100] As explained above, the linked list data structure for tracking pending interrupts can be doubly-linked (where each entry except the first and last entries specifies both a previous entry and a next entry) or singly-linked (where each entry except the last entry specifies a next entry but not a previous entry). The structure of a singly-linked list makes it easy to find the next interrupt to service at a given priority; however, removing an entry involves traversing the list from the head to find the entry before the deleted entry so that its pointer can be updated.

[0101] Note that while the interrupt identifier (INTID) 56 of the IST entry 54 itself is explicitly shown in the Figure 5 example, this is just an option. In an alternative example, the interrupt identifier of the entry itself is not actually included in the IST entry because it is implicit based on the position of the entry in the table. Thus, for example, the IST entry could alternatively look like this:

[0102] entry0: [prev INTID,V], [data0], [next INTID,V]

[0103] entry1: [prev INTID,V], [data1], next INTID,V]

[0104] …

[0105] In this example, the interrupt identifier for entry 0 would be 0, but this identifier is not part of [data0] because any agent accessing the entry already knows that it is operating on INTID 0. Instead, [datax] contains metadata and status about the interrupt, such as the priority of the interrupt, masking, level / edge configuration bits, and / or PE target.

[0106] Figure 6 An example showing why a doubly-linked list data structure can be particularly advantageous is presented. Specifically, Figure 6Shows the steps involved in removing an entry from a doubly linked list. As shown, the doubly linked list includes a first entry 54a for an interrupt with identifier INT0 56a, a second entry 54b for an interrupt with identifier INT1 56b, and a third entry 54c for an interrupt with identifier INT2 56c. Since Figure 6 the entries shown in form part of the doubly linked list, each entry specifies both a PREV pointer 58 and an NXT pointer 60: in the entry 54a for INT0, the NXT pointer 60a identifies INT1 (indicating that the next entry is the entry 54b for INT1); in the entry 54b for INT1, the PREV pointer 58b identifies INT0 and the NXT pointer 60b identifies INT2; in the entry 54c for INT2, the PREV pointer 58c identifies INT1. The entry 54a for INT0 and the entry 54c for INT2 also include PREV and NXT pointers 58a, 60c respectively, but the contents of these pointers are shown as being irrelevant to this discussion.

[0107] Figure 6 Shows the process of removing the entry for interrupt INT1 from the doubly linked list. As shown at "B", the process involves disabling the entry for INT1; for example, the entry 54b for INT1 can be updated to store some state indicating that it is disabled. Then, as shown at C, the PREV and NXT pointers 58, 60 of the previous and subsequent entries 54a, 54c are updated to point to each other; the NXT pointer 60a in the entry for INT0 now identifies INT2, and the PREV pointer 58c in the entry for INT2 now identifies INT0. Thus, the entry for INT1 has been removed.

[0108] Figure 6 Also shows the advantage of the linked list being doubly linked. Specifically, as shown at B, after removing an entry, the doubly linked list can be "fixed" without having to traverse the list from the beginning to identify the entry before the removed entry. For example, since both the NXT pointer 60a of the entry 54a for INT0 and the PREV pointer 58c of the entry 54c for INT2 identify INT1, it is possible to identify that: since INT1 has been disabled / is no longer being tracked, the next entry after the entry 54a for INT0 is the entry 54c for INT2. Thus, the list can still be traversed between the removal of INT1 and the update of the PREV and NXT pointers.

[0109] Now turning to the flowchart, Figure 7 shows an example of a method for tracking pending interrupts; this method can be performed, for example, by the above-mentioned interrupt controller.

[0110] AtFigure 7 In the method, when a pending interruption is detected 62 and determined 66 to be enabled, or when a previously disabled interruption is enabled 64, the method includes locating 68 in the pointer storage circuit a pointer for the corresponding linked list data structure. For example, the corresponding linked list may depend on the priority level of the interruption. Note that if an interruption is detected 62 but determined 66 not to be enabled, the interruption is not tracked (as shown in step 70), unless and until the interruption is enabled in step 64.

[0111] For an interruption to be tracked (e.g., a pending, enabled interruption), the method further includes determining 72 (as described above) whether the corresponding linked list is empty (i.e., contains no entries). If the linked list is empty, the head pointer and the tail pointer are updated 74, 76 to add the INTID to the list. In this case, the INTID will be the only entry in the list, so there is no need to update its predecessor pointer and successor pointer.

[0112] On the other hand, if it is determined 72 that the corresponding linked list is not empty, the tail pointer of the list is read 78 to identify the entry at the current last position in the list. Then, the PREV pointer in the IST for the INTID (i.e., the new interruption to be tracked) can be set 80 to point to the entry currently identified by the tail pointer, and the NXT pointer of the entry currently identified by the tail pointer can be updated 82 to point to the INTID. The tail pointer is also updated 76 to identify the INTID.

[0113] In this way, a new pending interruption can be added to the doubly linked list data structure. In addition, it should be understood that the method is also applicable to a singly linked list, the only difference being that step 80 can be omitted.

[0114] Figure 8 A method for identifying the highest priority pending interruption (HPPI) using a linked list data structure managed by hardware is shown. The method can be performed, for example, by an interruption controller, by one of the above-mentioned PEs, or by software executed on one of these PEs. The method assumes that separate linked lists are managed for each priority level, where priority level 0 is the highest priority level, and "higher" priority interruptions preempt "lower" priority interruptions. For example, a higher priority interruption can be an interruption considered more important than a lower priority interruption, and a higher priority interruption can be allowed to interrupt the processing of a lower priority interruption, but not vice versa. However, it should be understood that the labeling of the priority levels is not subject to specific restrictions; for example, other specific implementations can label the lowest priority level as priority level 0.

[0115] The method includes step 84: reading the head pointer of the linked list of priority level 0. If 86 the head pointer indicates that the linked list is empty, then read 88 the head pointer of the linked list of the next priority level (e.g., priority level 1). Then repeat steps 86 and 88 until a head pointer is read that does not indicate that its corresponding linked list is empty. This allows identification of the highest-priority non-empty linked list.

[0116] Once the highest-priority non-empty linked list is identified, the method includes determining 90 that the interrupt identified by the head pointer is an HPPI. Then, assuming that the HPPI is identified such that it can be resolved by the PE, the method involves step 92: once the interrupt is taken, triggering an update to the head pointer such that it points to the next interrupt in the linked list (i.e., removing the interrupt being resolved by the PE from the list). Note that step 92 is optional; there may be various reasons at the PE such that even if the interrupt is identified as an HPPI, it will not ultimately be taken, in which case the head pointer of the list will not be updated.

[0117] Therefore, Figure 8 illustrates the ease of identifying an HPPI when implementing the present technology. Specifically, an HPPI can be identified simply by reading one or more head pointers in the pointer storage circuit, without the need to scan the entire IST (or multiple ISTs).

[0118] Figure 9 illustrates a method for removing an interrupt from a doubly-linked list data structure. As shown, the method involves determining 94 that a given interrupt INTID is no longer pending and enabled; for example, the interrupt source may have de-asserted the valid interrupt signal, or the interrupt may have been disabled.

[0119] When it is determined that INTID is no longer pending and enabled, the method includes step 96: locating INTID in the IST and updating the entry to indicate that INTID is no longer pending, or is disabled. The method also includes using the PREV pointer of the entry for INTID to locate 98 the previous entry in the list and updating 100 the NXT pointer of the identified entry to point to the entry after the entry for INTID. Similarly, the method includes the step of locating 102 the next entry in the list (i.e., the entry after INTID) and the step of updating 104 its PREV pointer.

[0120] Therefore, Figure 9 demonstrates how using a doubly-linked list makes it particularly simple to delete an entry from the list, because the PREV pointer in the entry to be deleted allows identification of the previous entry that needs to be updated.

[0121] As shown in the above example, it is advantageous to use one or more hardware-managed linked list data structures to track pending interrupts, as it avoids the need to scan large data arrays in memory to identify HPPI or update the pending and enabled states of interrupts. These advantages are provided for both the case of using a singly-linked list or a doubly-linked list, but the above example also shows that using a doubly-linked list is particularly advantageous as it simplifies the update operation of the list after removing an entry.

[0122] In this application, the phrase "configured to..." is used to mean that an element of a device has a configuration capable of performing the defined operation. In this context, "configuration" means an arrangement or manner of interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not mean that the device element needs to be changed in any way to provide the defined operation.

[0123] Further, the phrase "at least one of..." in this application is used to mean including any one of the following options or any combination of the following options. For example, "A; at least one of B and C" means A or B or C, or any combination of A, B, and C (such as A and B, or A and C, or B and C).

[0124] Although the exemplary embodiments of the present invention have been described in detail herein with reference to the accompanying drawings, it should be understood that the present invention is not limited to those exact embodiments, and various changes and modifications can be made by those skilled in the art without departing from the scope of the present invention as defined by the appended claims.

Claims

1. A device, the device comprising: an interrupt detection circuit for detecting an interrupt triggered by at least one interrupt source; and an interrupt tracking circuit for managing one or more hardware-managed linked list data structures to track pending interrupts detected by the interrupt detection circuit.

2. The device according to claim 1, wherein the interrupt tracking circuit includes a pointer storage circuit for storing, for each of the hardware-managed linked list data structures in at least one subset of the one or more hardware-managed linked list data structures, a head pointer indicating the first entry in the hardware-managed linked list data structure and a tail pointer indicating the last entry in the hardware-managed linked list data structure.

3. The device according to claim 1 or claim 2, wherein: the one or more hardware-managed linked list data structures include at least one physical interrupt linked list for tracking physical interrupts and at least one virtual interrupt linked list for tracking virtual interrupts; and the interrupt tracking circuit includes a memory access circuit for maintaining a pointer data structure in a memory accessible by an interrupt controller, and for each of the at least one virtual interrupt linked lists, the pointer data structure stores a head pointer indicating the first entry in the hardware-managed linked list data structure and a tail pointer indicating the last entry in the hardware-managed linked list data structure.

4. The device according to claim 2 or claim 3, wherein the interrupt tracking circuit, in response to identifying a given interrupt to be tracked, updates the next entry pointer in the last entry of the given hardware-managed linked list data structure to point to the entry corresponding to the given interrupt; and updates the tail pointer of the given hardware-managed linked list data structure in the one or more hardware-managed linked list data structures to indicate the entry corresponding to the given interrupt.

5. The device according to any one of claims 2 to 4, wherein the pointer storage circuit is configured to store, as the head pointer of the hardware-managed linked list data structure, an interrupt identifier associated with the interrupt represented by the first entry of each of the hardware-managed linked list data structures in the one or more hardware-managed linked list data structures, and to store, as the tail pointer of the hardware-managed linked list data structure, an interrupt identifier associated with the interrupt represented by the last entry of each of the hardware-managed linked list data structures in the one or more hardware-managed linked list data structures.

6. The device according to any of the preceding claims, wherein the interrupt tracking circuit is configured to: identify one of a plurality of priority levels associated with each pending interrupt; and for each of the plurality of priority levels, manage the corresponding hardware-managed linked list data structure to track the pending interrupts associated with the priority level.

7. The device according to any of the preceding claims, wherein The interrupt tracking circuit is configured to identify a next entry in the given hardware-managed linked list data structure in each entry of the given hardware-managed linked list data structure except the last entry.

8. The apparatus according to claim 7, wherein the interrupt tracking circuit is configured to manage the one or more hardware-managed linked list data structures as a doubly linked list, wherein each entry in the given hardware-managed linked list data structure except the first entry and the last entry indicates the next entry in the hardware-managed linked list data structure and the previous entry in the hardware-managed linked list data structure.

9. The apparatus according to claim 7 or claim 8, wherein the interrupt tracking circuit removes an entry representing the given interrupt from the one or more hardware-managed linked list data structures in response to determining that the given interrupt is no longer pending, wherein removing the entry representing the given interrupt includes updating the previous entry in the hardware-managed linked list data structure to point to the entry after the entry removed from the hardware-managed linked list data structure.

10. The apparatus according to claim 9, wherein: the interrupt tracking circuit is configured to manage the one or more hardware-managed linked list data structures as a doubly linked list, wherein each entry in the doubly linked list except the first entry and the last entry indicates the next entry in the doubly linked list and the previous entry in the doubly linked list; and removing the entry representing the given interrupt includes updating the next entry in the doubly linked list to point to the entry before the entry removed from the doubly linked list.

11. The apparatus according to any one of the preceding claims, wherein the one or more hardware-managed linked list data structures are stored in a shared memory.

12. The apparatus according to claim 11, wherein: the interrupt tracking circuit is configured to manage one or more interrupt tracking tables in the shared memory to represent the one or more hardware-managed linked list data structures; and each interrupt tracking table includes an entry for each of a plurality of interrupts, and the interrupt tracking circuit is configured to manage the one or more hardware-managed linked list data structures by setting a pointer to the next entry in the given hardware-managed linked list data structure in each entry of the given interrupt tracking table representing a pending interrupt to be tracked except the last entry.

13. The apparatus according to any one of the preceding claims, wherein: the interrupt tracking circuit is configured to manage a plurality of interrupt tracking tables to represent the one or more hardware-managed linked list data structures; and the interrupt tracking circuit is configured to set a table identifier in each entry of the given interrupt tracking table representing a pending interrupt to be tracked to identify which of the plurality of interrupt tracking tables contains the next entry in the given hardware-managed linked list data structure.

14. The apparatus according to claim 13, wherein: each of the plurality of interrupt tracking tables represents a different category of interrupt.

15. A system, the system comprising: The apparatus according to any one of the preceding claims; Interconnect circuitry coupled to the apparatus; And At least one processing element coupled to the interconnect circuitry.

16. The system according to claim 15, wherein At least one of the interrupt tracking circuit and the at least one processing element is configured to identify a second highest priority pending interrupt by: Identifying a highest priority linked list data structure that includes at least one entry corresponding to a pending interrupt; and Identifying a next entry in the hardware linked list data structure.

17. A method, the method comprising: Detecting, using the interrupt detection circuit, an interrupt triggered by at least one interrupt source; And Managing, by hardware, one or more linked list data structures to track pending interrupts detected by the interrupt detection circuit.

18. A computer program, the computer program comprising computer-readable code for fabricating an apparatus, the apparatus comprising: An interrupt detection circuit for detecting an interrupt triggered by at least one interrupt source; And An interrupt tracking circuit for managing one or more hardware-managed linked list data structures to track pending interrupts detected by the interrupt detection circuit.

19. A computer-readable storage medium for storing the computer program according to claim 18.

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