Semiconductor device

Abstract

Provided is a semiconductor device occupying a small area. The semiconductor device includes a transistor and a first insulating layer. The transistor includes a first conductive layer, a second conductive layer having a region overlapping the first conductive layer via a first insulating layer, and a semiconductor layer. The second conductive layer has a first opening in a region overlapping the first conductive layer. The first insulating layer has a second opening reaching the first conductive layer in a region overlapping the first opening. The semiconductor layer is in contact with a top surface of the first conductive layer, a side surface of the first insulating layer, and a side surface of the second conductive layer in the first opening and the second opening. The first insulating layer has an oxygen diffusion coefficient at 350 DEG C of 5 * 10-12 cm2 / sec or more.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device and a method for manufacturing the same. One aspect of the present invention relates to a transistor and a method for manufacturing the same. One aspect of the present invention relates to a display device including a semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. As an example of the technical field of one aspect of the present invention, semiconductor devices, display devices, light-emitting devices, power storage devices, storage devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), and driving methods or manufacturing methods of the above devices can be cited.

[0003] Note that in this specification and the like, a semiconductor device refers to a device that utilizes semiconductor characteristics, a circuit including semiconductor elements (transistors, diodes, photodiodes, etc.), and a device including such a circuit. In addition, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. For example, as examples of semiconductor devices, there are integrated circuits, chips having integrated circuits, and electronic components in which chips are housed in packages. In addition, storage devices, display devices, light-emitting devices, lighting devices, and electronic devices themselves are semiconductor devices, and sometimes all include semiconductor devices. Background Art

[0004] Semiconductor devices including transistors are widely used in electronic devices. In recent years, the uses of display devices have been diversifying. For example, display devices are used in portable information terminals, television devices (also referred to as television receivers), digital signage, and PIDs (public information displays). As display devices, for example, display devices including organic EL (electro luminescence) elements or light-emitting diodes (LEDs), display devices including liquid crystal elements, and electronic paper that performs display by an electrophoresis method can be cited.

[0005] In a display device, by reducing the occupied area of a transistor, the pixel size can be reduced, and thus the definition can be improved. In addition, by reducing the occupied area of a transistor, the aperture ratio can be increased. Therefore, micro transistors are required.

[0006] Devices that require high-definition display devices, such as those for virtual reality (VR), augmented reality (AR), substitutional reality (SR), and mixed reality (MR), are being actively developed.

[0007] A high-definition display device using an organic EL element is disclosed in Patent Document 1. [Prior Art Documents] [Patent Documents]

[0008] [Patent Document 1] International Patent Application Publication No. 2016 / 038508 Summary of the Invention Technical Problem to be Solved by the Invention

[0009] One of the objects of one embodiment of the present invention is to provide a micro transistor. One of the objects of one embodiment of the present invention is to provide a transistor with a short channel length. One of the objects of one embodiment of the present invention is to provide a transistor with a large on-state current. One of the objects of one embodiment of the present invention is to provide a transistor with good electrical characteristics. One of the objects of one embodiment of the present invention is to provide a semiconductor device with a small occupied area. One of the objects of one embodiment of the present invention is to provide a semiconductor device with a low wiring resistance. One of the objects of one embodiment of the present invention is to provide a semiconductor device or a display device with low power consumption. One of the objects of one embodiment of the present invention is to provide a transistor, a semiconductor device, or a display device with high reliability. One of the objects of one embodiment of the present invention is to provide a display device with high clarity. One of the objects of one embodiment of the present invention is to provide a manufacturing method for a semiconductor device or a display device with high productivity. One of the objects of one embodiment of the present invention is to provide a novel transistor, semiconductor device, display device, or their manufacturing methods.

[0010] Note that the description of these objects does not preclude the existence of other objects. One embodiment of the present invention does not need to achieve all of the above objects. Objects other than the above can be extracted from the description of the specification, drawings, and claims. Means for Solving the Technical Problem

[0011] One aspect of the present invention is a semiconductor device including a transistor and a first insulating layer. The transistor includes a first conductive layer, a second conductive layer having a region overlapping the first conductive layer with the first insulating layer therebetween, and a semiconductor layer. The second conductive layer has a first opening in the region overlapping the first conductive layer. The first insulating layer has a second opening reaching the first conductive layer in the region overlapping the first opening. The semiconductor layer is in contact with the top surface of the first conductive layer, the side surfaces of the first insulating layer, and the side surfaces of the second conductive layer in the first opening and the second opening. The oxygen diffusion coefficient of the first insulating layer at 350 °C is 5×10 -12 cm 2 / sec or more.

[0012] In the above semiconductor device, the oxygen diffusion coefficient is preferably calculated by thermal desorption spectroscopy or secondary ion mass spectrometry.

[0013] In the above semiconductor device, the semiconductor layer preferably contains a metal oxide.

[0014] The above semiconductor device preferably includes a second insulating layer and a third insulating layer. The second insulating layer is preferably located between the first insulating layer and the first conductive layer. The third insulating layer is preferably located between the first insulating layer and the second conductive layer. The first insulating layer preferably contains an oxide or an oxynitride. The second insulating layer and the third insulating layer preferably each contain a nitride or a nitrogen oxide.

[0015] The above semiconductor device preferably includes a fourth insulating layer. The fourth insulating layer is preferably located between the second insulating layer and the first conductive layer. The fourth insulating layer preferably has a region with a larger hydrogen content than the second insulating layer.

[0016] The above semiconductor device preferably includes a fifth insulating layer. The fifth insulating layer is preferably located between the third insulating layer and the second conductive layer. The fifth insulating layer preferably has a region with a larger hydrogen content than the third insulating layer.

[0017] One aspect of the present invention is a semiconductor device including a first transistor, a second transistor, and a first insulating layer. The first transistor includes a first conductive layer, a second conductive layer having a region overlapping the first conductive layer with the first insulating layer therebetween, and a first semiconductor layer. The second conductive layer has a first opening in the region overlapping the first conductive layer. The first insulating layer has a second opening reaching the first conductive layer in the region overlapping the first opening. The first semiconductor layer is in contact with the top surface of the first conductive layer, the side surfaces of the first insulating layer, and the side surfaces of the second conductive layer in the first opening and the second opening. The second transistor includes a third conductive layer on the first insulating layer, a second semiconductor layer, and a second insulating layer located between the third conductive layer and the second semiconductor layer. The second insulating layer is in contact with the top surface and the side surfaces of the third conductive layer. The oxygen diffusion coefficient of the first insulating layer is larger than the oxygen diffusion coefficient of the second insulating layer.

[0018] In the above semiconductor device, the diffusion coefficient of oxygen is preferably calculated by thermal desorption spectroscopy or secondary ion mass spectrometry.

[0019] One aspect of the present invention is a semiconductor device including a first transistor, a second transistor, and a first insulating layer. The first transistor includes a first conductive layer, a second conductive layer having a region overlapping the first conductive layer with the first insulating layer interposed therebetween, and a first semiconductor layer. The second conductive layer has a first opening in the region overlapping the first conductive layer. The first insulating layer has a second opening reaching the first conductive layer in the region overlapping the first opening. The first semiconductor layer contacts the top surface of the first conductive layer, the side surfaces of the first insulating layer, and the side surfaces of the second conductive layer in the first opening and the second opening. The second transistor includes a third conductive layer on the first insulating layer, a second semiconductor layer, and a second insulating layer located between the third conductive layer and the second semiconductor layer. The second insulating layer contacts the top surface and the side surfaces of the third conductive layer. The etching rate of an etchant for the first insulating layer is faster than the etching rate of the second insulating layer.

[0020] In the above semiconductor device, the etchant preferably contains hydrofluoric acid.

[0021] In the above semiconductor device, the first semiconductor layer and the second semiconductor layer preferably each contain a metal oxide.

[0022] In the above semiconductor device, the second conductive layer and the third conductive layer preferably contain different materials.

[0023] Alternatively, in the above semiconductor device, the second conductive layer and the third conductive layer preferably contain the same material.

[0024] The above semiconductor device preferably includes a third insulating layer and a fourth insulating layer. The third insulating layer is preferably located between the first insulating layer and the first conductive layer. The fourth insulating layer is preferably located between the first insulating layer and the second conductive layer. The fourth insulating layer is preferably located between the first insulating layer and the third conductive layer. The first insulating layer preferably contains an oxide or an oxynitride. The third insulating layer and the fourth insulating layer preferably each contain a nitride or a nitrogen oxide.

[0025] The above semiconductor device preferably includes a fifth insulating layer. The fifth insulating layer is preferably located between the third insulating layer and the first conductive layer. The fifth insulating layer preferably has a region with a larger hydrogen content than the third insulating layer.

[0026] The above semiconductor device preferably includes a sixth insulating layer. The sixth insulating layer is preferably located between the fourth insulating layer and the second conductive layer. The sixth insulating layer is preferably located between the fourth insulating layer and the third conductive layer. The sixth insulating layer preferably has a region with a larger hydrogen content than the fourth insulating layer. Advantages of the Invention

[0027] According to one aspect of the present invention, a micro transistor can be provided. According to one aspect of the present invention, a transistor with a short channel length can be provided. According to one aspect of the present invention, a transistor with a large on-state current can be provided. According to one aspect of the present invention, a transistor with good electrical characteristics can be provided. According to one aspect of the present invention, a semiconductor device with a small occupied area can be provided. According to one aspect of the present invention, a semiconductor device with a low wiring resistance can be provided. According to one aspect of the present invention, a semiconductor device or a display device with low power consumption can be provided. According to one aspect of the present invention, a transistor, a semiconductor device or a display device with high reliability can be provided. According to one aspect of the present invention, a display device with high clarity can be provided. According to one aspect of the present invention, a manufacturing method of a semiconductor device or a display device with high productivity can be provided. According to one aspect of the present invention, a novel transistor, semiconductor device, display device or their manufacturing methods can be provided.

[0028] Note that the description of these effects does not preclude the existence of other effects. One aspect of the present invention does not necessarily have all of the above effects. Effects other than the above can be extracted from the descriptions in the specification, drawings, and claims. Brief Description of the Drawings

[0029] Figure 1A is a top view showing an example of a semiconductor device. Figure 1B and Figure 1C is a cross-sectional view showing an example of a semiconductor device. Figure 2A and Figure 2B is a perspective view showing an example of a semiconductor device. Figure 3 is a cross-sectional view showing an example of a semiconductor device. Figure 4A is a top view showing an example of a semiconductor device. Figure 4B is a cross-sectional view showing an example of a semiconductor device. Figure 5A is a top view showing an example of a semiconductor device. Figure 5B and Figure 5C is a cross-sectional view showing an example of a semiconductor device. Figure 6A and Figure 6B is a cross-sectional view showing an example of a semiconductor device. Figure 7A is a top view showing an example of a semiconductor device. Figure 7B is a cross-sectional view showing an example of a semiconductor device. Figure 8A is a top view showing an example of a semiconductor device.Figure 8B and Figure 8C is a cross-sectional view showing an example of a semiconductor device. Figure 9A is a top view showing an example of a semiconductor device. Figure 9B and Figure 9C is a cross-sectional view showing an example of a semiconductor device. Figure 10A and Figure 10B is a cross-sectional view showing an example of a semiconductor device. Figures 11A to 11C is a cross-sectional view showing an example of a semiconductor device. Figure 12A and Figure 12B is a cross-sectional view showing an example of a semiconductor device. Figure 13A is a top view showing an example of a semiconductor device. Figure 13B and Figure 13C is a cross-sectional view showing an example of a semiconductor device. Figure 14A and Figure 14B is an equivalent circuit diagram of the semiconductor device. Figure 14C is a top view showing an example of a semiconductor device. Figure 15 is a cross-sectional view showing an example of a semiconductor device. Figure 16 is a perspective view showing an example of a semiconductor device. Figures 17A to 17D is a perspective view showing an example of a semiconductor device. Figure 18A and Figure 18B is an equivalent circuit diagram of the semiconductor device. Figure 18C is a top view showing an example of a semiconductor device. Figure 19 is a cross-sectional view showing an example of a semiconductor device. Figure 20 is a perspective view showing an example of a semiconductor device. Figures 21A to 21D is a perspective view showing an example of a semiconductor device. Figures 22A to 22D is a cross-sectional view showing an example of a manufacturing method of a semiconductor device. Figures 23A to 23C is a cross-sectional view showing an example of a manufacturing method of a semiconductor device. Figures 24A to 24C is a cross-sectional view showing an example of a manufacturing method of a semiconductor device. Figures 25A to 25CIt is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 26A and Figure 26B It is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 27A It is a perspective view showing an example of a display device. Figure 27B It is a block diagram showing an example of a display device. Figure 28A It is a circuit diagram of a latch circuit. Figure 28B It is a circuit diagram of an inverter circuit. Figure 29A and Figure 29B It is a circuit diagram of a pixel circuit. Figure 29C It is a cross-sectional view showing an example of a pixel circuit. Figure 30 It is a circuit diagram of a pixel circuit. Figure 31 It is a top view showing an example of the layout of a pixel. Figure 32 It is a top view showing an example of the layout of a pixel. Figure 33 It is a top view showing an example of the layout of a pixel. Figure 34 It is a cross-sectional view showing an example of the layout of a pixel. Figure 35A and Figure 35B It is a cross-sectional view showing an example of the layout of a pixel. Figures 36A to 36C It is a top view showing an example of the layout of a pixel. Figures 37A to 37C It is a top view showing an example of the layout of a pixel. Figure 38 It is a top view showing an example of the layout of a pixel. Figure 39 It is a top view showing an example of the layout of a pixel. Figure 40A and Figure 40B It is a top view showing an example of the layout of a pixel. Figure 41A and Figure 41B It is a top view showing an example of the layout of a pixel. Figure 42A and Figure 42B It is a top view showing an example of the layout of a pixel. Figure 43A and Figure 43B It is a cross-sectional view showing an example of a display device. Figure 44It is a cross-sectional view showing an example of a display device. Figures 45A to 45C It is a cross-sectional view showing an example of a display device. Figure 46A And Figure 46B It is a cross-sectional view showing an example of a display device. Figure 47 It is a cross-sectional view showing an example of a display device. Figure 48 It is a cross-sectional view showing an example of a display device. Figure 49 It is a cross-sectional view showing an example of a display device. Figure 50A And Figure 50B It is a cross-sectional view showing an example of a display device. Figures 51A to 51F It is a cross-sectional view showing an example of a manufacturing method of a display device. Figures 52A to 52D It is a diagram showing an example of an electronic device. Figures 53A to 53F It is a diagram showing an example of an electronic device. Figures 54A to 54G It is a diagram showing an example of an electronic device. Figure 55 It is an SEM image of a transistor according to an embodiment. Figure 56A And Figure 56B It is a STEM image of a transistor according to an embodiment. Figure 57 It is a diagram showing the Id-Vg characteristics of a transistor according to an embodiment. Figure 58A And Figure 58B It is a diagram showing the electrical characteristics of a transistor according to an embodiment. Figure 59 It is a diagram showing the electrical characteristics of a transistor according to an embodiment. Figure 60 It is a diagram showing the electrical characteristics of a transistor according to an embodiment. Figure 61 It is a diagram showing the reliability of a transistor according to an embodiment. Figure 62A And Figure 62B It is a photograph of the display state of an OLED panel according to an embodiment. Figure 63 It is a diagram showing the I-V characteristics of a sample according to an embodiment. Figure 64 It is a diagram showing the sheet resistance and carrier concentration of a sample according to an embodiment. Figure 65It is a diagram showing the Id-Vg characteristics of a transistor according to an embodiment. Figure 66 It is a diagram showing the electrical characteristics of a transistor according to an embodiment. Figure 67A It is a diagram showing the electrical characteristics of a transistor according to an embodiment. Figure 67B It is a diagram showing the Id-Vg characteristics of a transistor according to an embodiment. Figure 68 It is a diagram showing the Id-Vg characteristics of a transistor according to an embodiment. Figure 69A and Figure 69B It is a diagram showing the electrical characteristics of a transistor according to an embodiment. Figure 70 It is a diagram showing the electrical characteristics of a transistor according to an embodiment. Figure 71A It is a diagram showing the Id-Vg characteristics of a transistor according to an embodiment. Figure 71B It is a diagram showing the electrical characteristics of a transistor according to an embodiment. Figure 72 It is a diagram showing the reliability of a transistor according to an embodiment. Figure 73 It is a photograph of the display state of an OLED panel according to an embodiment. Figures 74A to 74C It is a cross-sectional view showing the structure of a sample according to an embodiment. Figure 75A and Figure 75B It is a diagram showing a cross-sectional TEM image and crystal orientation according to an embodiment. Figure 76A and Figure 76B It is a diagram showing a cross-sectional TEM image and crystal orientation according to an embodiment. Figure 77A and Figure 77B It is a diagram showing the Id-Vg characteristics of a transistor according to an embodiment. Figure 78 It is a diagram explaining a method for evaluating the off-state current of a transistor according to an embodiment. Figure 79A and Figure 79B It is a diagram showing the off-state current of a transistor according to an embodiment. Figure 80 It is a diagram showing the Id-Vg characteristics of a transistor according to an embodiment. Figure 81A and Figure 81B It is a TDS spectrum according to an embodiment. Figure 82 It is a diagram showing the diffusion coefficient of oxygen according to an embodiment. Figure 83A andFigure 83B It is a diagram showing the measurement result of TDS according to an embodiment. Figure 84A and Figure 84B It is a diagram showing the Id-Vg characteristics of a transistor according to an embodiment. Figure 85A and Figure 85B It is a diagram showing the Id-Vg characteristics of a transistor according to an embodiment. Figure 86A and Figure 86B It is a diagram showing the electrical characteristics of a transistor according to an embodiment. Figures 87A to 87F It is a TDS spectrum according to an embodiment. Figure 88 It is a TDS spectrum according to an embodiment. Figure 89 It is a diagram showing the measurement result of TDS according to an embodiment. Figure 90 It is a diagram showing the electrical characteristics of a transistor according to an embodiment. Figure 91A and Figure 91B It is a diagram showing the reliability of a transistor according to an embodiment. Figure 92 It is a diagram showing the drain breakdown voltage of a transistor according to an embodiment. Mode of implementing the invention

[0030] The embodiments will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and it is easily understandable to those of ordinary skill in the art that its mode and details can be transformed into various forms without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited only to the content described in the following embodiments shown.

[0031] Note that in the invention structure described below, the same parts or parts having the same function are denoted by the same reference numerals in different drawings, and repeated description is omitted. In addition, when indicating parts having the same function, the same hatching is sometimes used without particularly attaching reference numerals.

[0032] In addition, in this specification, etc., when a plurality of elements use the same reference numeral and it is necessary to distinguish them, sometimes reference numerals for identification such as “_1”, “[n]”, “[m, n]” are attached to the reference numeral. In addition, in the drawings, etc., in the case where reference numerals for identification such as “_1”, “[n]”, “[m, n]” are attached to the reference numeral, if it is not necessary to distinguish them in this specification, etc., sometimes reference numerals for identification such as “_1”, “[n]”, “[m, n]” are not attached.

[0033] In addition, for ease of understanding, the positions, sizes, ranges, etc. of the respective components shown in the drawings sometimes do not represent their actual positions, sizes, ranges, etc. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, ranges, etc. disclosed in the drawings.

[0034] In this specification and the like, for convenience, ordinal numbers such as "first" and "second" are added, and they do not limit the number of components or the order of components (for example, the process order or the stacking order). In addition, the ordinal numbers added to a component in a certain part of this specification may sometimes be inconsistent with the ordinal numbers added to the same component in other parts of this specification or in the claims.

[0035] In addition, depending on the situation or state, "film" and "layer" can be interchanged with each other. For example, "conductive layer" can be changed to "conductive film". In addition, "insulating film" can be changed to "insulating layer".

[0036] A transistor is a type of semiconductor device, and can perform functions such as amplifying current or voltage, and controlling switching operations such as conduction or non-conduction. The transistors in this specification and the like include IGFETs (Insulated Gate Field Effect Transistors) and thin film transistors (TFTs: Thin Film Transistors).

[0037] In cases where transistors with different polarities are used or the direction of the current in the circuit operation changes, etc., the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification and the like, the "source electrode" and "drain electrode" can be used interchangeably. Note that depending on the situation, the source electrode and drain electrode of the transistor can be appropriately renamed as the source terminal and drain terminal or the source electrode and drain electrode, etc.

[0038] In addition, "gate electrode" and "back gate electrode" can be interchanged. Therefore, in this specification and the like, "gate electrode" and "back gate electrode" can be used interchangeably. Note that depending on the situation, the gate electrode and back gate electrode of the transistor can be appropriately renamed as the gate electrode and back gate electrode, etc.

[0039] In this specification and the like, "electrically connected" includes cases where connection is made through "an element having a certain electrical function". Here, there are no particular limitations on the "element having a certain electrical function" as long as it can transmit and receive electrical signals between the connection objects. For example, the "element having a certain electrical function" includes switching elements such as transistors, resistive elements, coils, and other elements having various functions, in addition to electrodes or wirings.

[0040] In addition, in this specification and the like, unless otherwise specified, the off-state current refers to the leakage current between the source and the drain when the transistor is in the off state (also referred to as the non-conducting state or the cut-off state). Unless otherwise specified, in an n-channel transistor, the off state refers to a state where the voltage between the gate and the source (also denoted as Vgs or Vg) is lower than the threshold voltage (also denoted as Vth), and in a p-channel transistor, the off state refers to a state where the voltage between the gate and the source is higher than the threshold voltage.

[0041] In this specification and the like, "the top surface shapes are substantially the same" means that at least a part of the edges of each layer in the stack overlap. For example, it includes the case where the upper layer and the lower layer are processed by the same mask pattern or a part of the same mask pattern. However, in practice, there are cases where the edges do not overlap, and sometimes the upper layer is inside the lower layer or the upper layer is outside the lower layer, and this case can also be said to be "the top surface shapes are substantially the same". When the top surface shapes are the same or substantially the same, it can also be said that the ends are aligned or substantially aligned.

[0042] In this specification and the like, the conical shape means a shape in which at least a part of the side surface of the component is inclined with respect to the substrate surface or the surface to be formed. For example, it preferably has a region where the angle (also referred to as the cone angle) formed by the inclined side surface and the substrate surface or the surface to be formed is less than 90 degrees. Here, the side surface of the component, the substrate surface, and the surface to be formed do not necessarily have to be completely flat, and may be an approximately planar shape with a small curvature or an approximately planar shape with fine unevenness.

[0043] In this specification and the like, a device manufactured using a metal mask or an FMM (Fine Metal Mask, high-precision metal mask) is sometimes referred to as a device having an MM (Metal Mask) structure. In addition, in this specification and the like, a device not manufactured using a metal mask or an FMM is sometimes referred to as a device having an MML (Metal Mask Less) structure. Note that since a device with an MML structure can be manufactured without using a metal mask, it can exceed the upper limit of the resolution due to the alignment accuracy of the metal mask. In addition, a device with an MML structure does not require the equipment and the washing process of the metal mask required for the manufacture of the metal mask. In addition, a device with an MML structure can reduce the manufacturing cost, so it is suitable for mass production.

[0044] In this specification and the like, a structure in which light-emitting layers are respectively manufactured in light-emitting elements (also referred to as light-emitting devices) having different emission wavelengths is sometimes referred to as an SBS (Side By Side) structure. Since the SBS structure can optimize the materials and structures for each light-emitting element, the degree of freedom in the selection of materials and structures is increased, and it is easy to improve the brightness and reliability.

[0045] In this specification and the like, a hole or an electron is sometimes referred to as a "carrier". Specifically, a hole injection layer or an electron injection layer is sometimes referred to as a "carrier injection layer", a hole transport layer or an electron transport layer is sometimes referred to as a "carrier transport layer", and a hole blocking layer or an electron blocking layer is sometimes referred to as a "carrier blocking layer". Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier blocking layer cannot sometimes be clearly distinguished according to their cross-sectional shapes or characteristics, etc. In addition, sometimes a single layer has the functions of two or three of the carrier injection layer, carrier transport layer, and carrier blocking layer.

[0046] In this specification and the like, a light-emitting element includes an EL layer between a pair of electrodes. The EL layer includes at least a light-emitting layer. Here, as the layers included in the EL layer (also referred to as functional layers), there may be mentioned a light-emitting layer, a carrier injection layer (hole injection layer and electron injection layer), a carrier transport layer (hole transport layer and electron transport layer), and a carrier blocking layer (hole blocking layer and electron blocking layer), etc. In this specification and the like, a light-receiving element (also referred to as a light-receiving device) includes at least an active layer serving as a photoelectric conversion layer between a pair of electrodes. In this specification and the like, one of the pair of electrodes is sometimes denoted as a pixel electrode, and the other is denoted as a common electrode.

[0047] In this specification and the like, a sacrificial layer (which may also be referred to as a mask layer) is at least located above the light-emitting layer (more specifically, the layer that is processed into an island shape among the layers constituting the EL layer), and has a function of protecting the light-emitting layer in the manufacturing process.

[0048] In this specification and the like, disconnection refers to a phenomenon in which a layer, film, or electrode is disconnected due to the shape of the formation surface (for example, a step, etc.).

[0049] (Embodiment 1) In this embodiment, a semiconductor device according to one aspect of the present invention will be described with reference to FIGS. 1 to 21.

[0050] One aspect of the present invention is a semiconductor device including a transistor and a first insulating layer.

[0051] The transistor includes a first conductive layer, a second conductive layer having a region overlapping with the first conductive layer across a first insulating layer, a semiconductor layer, a gate insulating layer, and a gate electrode. The second conductive layer has a first opening in the region overlapping with the first conductive layer. The first insulating layer has a second opening reaching the first conductive layer in the region overlapping with the first opening. The semiconductor layer contacts the top surface of the first conductive layer, the side surfaces of the first insulating layer, and the side surfaces of the second conductive layer in the first opening and the second opening. A gate insulating layer is provided on the semiconductor layer, and a gate electrode is provided on the gate insulating layer. In this transistor, the first conductive layer is used as one of the source electrode and the drain electrode, and the second conductive layer is used as the other of the source electrode and the drain electrode. In this transistor, the source electrode, the layer having a channel formation region, and the drain electrode can be overlapped, so that the occupied area can be reduced. In addition, the region of the semiconductor layer in contact with the first insulating layer is used as the channel formation region. Thus, the channel length of the transistor can be made smaller than the limit resolution of the exposure apparatus, and a transistor with a large on-state current can be realized.

[0052] The semiconductor layer preferably contains a metal oxide. In addition, the first insulating layer preferably uses a material that releases oxygen. Thus, oxygen can be supplied from the first insulating layer to the semiconductor layer (especially, the channel formation region), so that the oxygen vacancies (V O : Oxygen Vacancy) in the semiconductor layer can be reduced.

[0053] In a transistor with a short channel length, the more oxygen supplied from the first insulating layer to the semiconductor layer, the better. In addition, the oxygen diffusion coefficient of the first insulating layer is preferably large. Specifically, the oxygen diffusion coefficient of the first insulating layer at 350 °C is preferably 5×10 -12 cm 2 / sec or more. Thus, the diffusion rate of oxygen in the first insulating layer increases, and oxygen can be effectively supplied to the semiconductor layer. Therefore, even a transistor with a short channel length can have excellent electrical characteristics and high reliability at the same time.

[0054] <Structural Example 1> A semiconductor device according to one embodiment of the present invention will be described. Figure 1A is a top view (also referred to as a plan view) of the semiconductor device 10. Figure 1B is a cross-sectional view of a cross-section along the Figure 1A indicated dash-dotted line A1 - A2, Figure 1C is a cross-sectional view of a cross-section along the dash-dotted line B1 - B2. Note that in Figure 1A , a part of the components of the semiconductor device 10 (such as an insulating layer) is omitted. Regarding the top view of the semiconductor device, similarly to Figure 1A , a part of the components is also omitted in the subsequent drawings.

[0055] Figure 2Aand Figure 2B It is a perspective view of the semiconductor device 10 . Figure 2B The normal direction of the substrate 102 surface is offset to show Figure 2A The components of a portion of the shown.

[0056] The semiconductor device 10 includes a transistor 100, a transistor 200, a capacitor 150, and an insulating layer 110. The transistor 100, the transistor 200, and the capacitor 150 are provided on a substrate 102. The transistor 100 and the transistor 200 have different structures. In addition, the transistor 100, the transistor 200, and the capacitor 150 can be formed by sharing some processes.

[0057] The transistor 100 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b. In the transistor 100, the conductive layer 104 is used as a gate electrode (also referred to as a first gate electrode). A portion of the insulating layer 106 is used as a gate insulating layer (also referred to as a first gate insulating layer). The conductive layer 112a is used as one of a source electrode and a drain electrode, and the conductive layer 112b is used as the other of the source electrode and the drain electrode. Each layer constituting the transistor 100 may have a single-layer structure or a stacked-layer structure. Note that in Figure 2A In FIG. 1 , the insulating layer 110 and the insulating layer 106 are shown through their outlines with dotted lines.

[0058] A conductive layer 112a is provided on the substrate 102, and an insulating layer 110 is provided on the conductive layer 112a. The insulating layer 110 is provided to cover the top surface and side surfaces of the conductive layer 112a. The insulating layer 110 has an opening 141 that reaches the conductive layer 112a. It can be said that the conductive layer 112a is exposed in the opening 141.

[0059] Conductive layer 112b is provided on insulating layer 110. Conductive layer 112b has a region overlapping conductive layer 112a via insulating layer 110. Conductive layer 112b has opening 143 in the region overlapping conductive layer 112a. Opening 143 is provided in a region overlapping opening 141.

[0060] The semiconductor layer 108 is disposed so as to cover the opening 141 and the opening 143. The semiconductor layer 108 has regions in contact with the top surface and the side surface of the conductive layer 112b, the side surface of the insulating layer 110, and the top surface of the conductive layer 112a. The semiconductor layer 108 is electrically connected to the conductive layer 112a through the opening 141 and the opening 143. The semiconductor layer 108 has a shape along the top surface and the side surface of the conductive layer 112b, the side surface of the insulating layer 110, and the top surface of the conductive layer 112a. The semiconductor layer 108 has a region overlapping with the conductive layer 112a with the insulating layer 110 therebetween. It can also be said that the insulating layer 110 has a region sandwiched between the conductive layer 112a and the semiconductor layer 108.

[0061] The region of the semiconductor layer 108 in contact with the conductive layer 112a is used as one of the source region and the drain region, and the region in contact with the conductive layer 112b is used as the other of the source region and the drain region. In the semiconductor layer 108, a channel formation region is provided between the source region and the drain region.

[0062] The insulating layer 106 is disposed so as to cover the opening 141 and the opening 143. The insulating layer 106 is disposed on the semiconductor layer 108, the conductive layer 112b, and the insulating layer 110. The insulating layer 106 has regions in contact with the top surface and the side surface of the semiconductor layer 108, the top surface and the side surface of the conductive layer 112b, and the top surface of the insulating layer 110. The insulating layer 106 has a shape along the top surface and the side surface of the semiconductor layer 108, the top surface and the side surface of the conductive layer 112b, and the top surface of the insulating layer 110.

[0063] The conductive layer 104 is disposed on the insulating layer 106 and includes a region in contact with the top surface of the insulating layer 106. The conductive layer 104 includes a region overlapping with the semiconductor layer 108 with the insulating layer 106 therebetween. The conductive layer 104 has a shape along the top surface shape of the insulating layer 106.

[0064] In the transistor 100, the heights of the source electrode and the drain electrode with respect to the surface of the substrate 102 of the formation surface are different from each other, and the drain current flows in a direction perpendicular or substantially perpendicular to the surface of the substrate 102. It can also be said that in the transistor 100, the drain current flows in the longitudinal direction or substantially longitudinal direction. Therefore, the transistor of one aspect of the present invention can be said to be a vertical channel type transistor, a vertical transistor, or a VFET (Vertical Field Effect Transistor).

[0065] The channel length of the transistor 100 can be controlled by the thickness of the insulating layer 110 (specifically, the insulating layer 110b) provided between the conductive layer 112a and the conductive layer 112b. Therefore, a transistor having a channel length shorter than the limit resolution of the exposure apparatus used to manufacture the transistor can be manufactured with high precision. In addition, the characteristic non-uniformity between multiple transistors 100 can be reduced. Therefore, the operation of the semiconductor device including the transistor 100 is stable, and the reliability can be improved. In addition, when the characteristic non-uniformity is reduced, the degree of freedom in circuit design is increased, and the operating voltage of the semiconductor device can also be reduced. Thereby, the power consumption of the semiconductor device can be reduced.

[0066] In the transistor 100, the source electrode, the layer having the channel formation region, and the drain electrode can be overlapped and provided, so that the occupied area can be significantly reduced as compared with a so-called planar transistor in which the layer having the channel formation region is arranged in a planar shape.

[0067] The conductive layer 112a, the conductive layer 112b, and the conductive layer 104 can all be used as wirings, and the transistor 100 can be provided in the region where these wirings overlap. That is, in a circuit including the transistor 100 and the wirings, the occupied areas of the transistor 100 and the wirings can be reduced. Therefore, the occupied area of the circuit can be reduced to realize a small semiconductor device.

[0068] The transistor 200 includes a conductive layer 204, a conductive layer 212a, a conductive layer 212b, an insulating layer 106, a semiconductor layer 208, an insulating layer 120, and a conductive layer 202. In the transistor 200, the conductive layer 204 is used as a gate electrode (also referred to as a first gate electrode). A part of the insulating layer 106 is used as a gate insulating layer (also referred to as a first gate insulating layer). The conductive layer 202 is used as a back gate electrode (also referred to as a second gate electrode), and a part of the insulating layer 120 is used as a back gate insulating layer (also referred to as a second gate insulating layer). The conductive layer 212a is used as one of the source electrode and the drain electrode, and the conductive layer 212b is used as the other of the source electrode and the drain electrode. Each layer constituting the transistor 200 can have a single-layer structure or a stacked structure. Note that the transistor 200 may not include the conductive layer 202. In addition, in Figure 2A the insulating layer 120 is omitted.

[0069] In the semiconductor layer 208, the entire region overlapping the gate electrode with the gate insulating layer interposed therebetween between the source electrode and the drain electrode is used as the channel formation region. The semiconductor layer 208 has a pair of regions 208L that sandwich the channel formation region and a pair of regions 208D outside thereof.

[0070] Regions 208L and 208D are regions containing impurity elements. As such impurity elements, one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, or noble gases, etc. can be used. As typical examples of noble gases, helium, neon, argon, krypton, and xenon can be cited. As impurity elements, one or more of boron, phosphorus, aluminum, magnesium, and silicon are particularly preferably used.

[0071] The conductive layer 204, the conductive layer 212a, and the conductive layer 212b are used as masks to supply (also referred to as add or implant) impurity elements to the semiconductor layer 208. Thereby, in the semiconductor layer 208, a region 208D is formed in a region that does not overlap with any of the conductive layer 204, the conductive layer 212a, the conductive layer 212b, and the insulating layer 106, and a region 208L is formed in a region that does not overlap with any of the conductive layer 204, the conductive layer 212a, and the conductive layer 212b and overlaps with the insulating layer 106.

[0072] The region of the semiconductor layer 208 that contacts the conductive layer 212a and the adjacent region 208D are used as one of the source region and the drain region. The region of the semiconductor layer 208 that contacts the conductive layer 212b and the adjacent region 208D are used as the other of the source region and the drain region.

[0073] A conductive layer 202 is provided on the insulating layer 110, and an insulating layer 120 is provided on the conductive layer 202. The insulating layer 120 is provided so as to cover the top surface and the side surfaces of the conductive layer 202. The insulating layer 120 has a portion that protrudes beyond the end of the conductive layer 202. The end of the insulating layer 120 contacts the top surface of the insulating layer 110.

[0074] A semiconductor layer 208 is provided on the insulating layer 120. The semiconductor layer 208 has a region that overlaps with the conductive layer 202 with the insulating layer 120 therebetween. The semiconductor layer 208 can use the same material as the semiconductor layer 108. In addition, the semiconductor layer 208 can be formed by the same process as the semiconductor layer 108. For example, a film that becomes the semiconductor layer 108 and the semiconductor layer 208 is formed and processed, whereby the semiconductor layer 108 and the semiconductor layer 208 can be formed.

[0075] An insulating layer 106 is provided on the semiconductor layer 208. A part of the insulating layer 106 is used as the gate insulating layer of the transistor 100, and another part of the insulating layer 106 is used as the gate insulating layer of the transistor 200. The insulating layer 106 has openings 147a and 147b in the region overlapping with the semiconductor layer 208.

[0076] A conductive layer 204, a conductive layer 212a, and a conductive layer 212b are provided on the insulating layer 106. The conductive layer 204 has a region overlapping with the semiconductor layer 208 with the insulating layer 106 therebetween. In addition, the conductive layer 204 has a region overlapping with the conductive layer 202 with the semiconductor layer 208 therebetween. The conductive layers 212a and 212b are provided so as to cover a part of the openings 147a and 147b. The conductive layer 212a is electrically connected to the semiconductor layer 208 through the opening 147a, and the conductive layer 212b is electrically connected to the semiconductor layer 208 through the opening 147b. The conductive layer 204, the conductive layer 212a, and the conductive layer 212b may use the same material as the conductive layer 104. In addition, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b may be formed by the same process as the conductive layer 104. For example, a film that becomes the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b is formed and processed, whereby the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b can be formed.

[0077] The transistor 200 is a planar transistor in which the semiconductor layer 208 is arranged in a planar shape. The transistor 200 is a so-called top-gate transistor having a gate electrode above the semiconductor layer 208. For example, by supplying an impurity element to the semiconductor layer 208 using the conductive layer 204 serving as a gate electrode, regions 208D serving as source regions and drain regions can be formed in a self-aligned manner. The transistor 200 can be said to be a TGSA (Top Gate Self-Aligned) type transistor.

[0078] The transistor 200 can control the channel length by the length of the conductive layer 204. Accordingly, the channel length of the transistor 200 is a value equal to or greater than the limit resolution of the exposure apparatus used in the manufacture of the transistor. That is, the channel length of the transistor 200 can be made larger than the channel length of the transistor 100. By increasing the channel length, a transistor with high saturation can be realized.

[0079] Note that in this specification and the like, the case where the current change in the saturation region in the Id-Vd characteristics of the transistor is small is sometimes expressed as "high saturation".

[0080] The transistor 100 with a short channel length and the transistor 200 with a long channel length can be formed on the same substrate in a manner where a part of the processes is common. For example, by using the transistor 100 for a transistor that is required to have a large on-state current and using the transistor 200 for a transistor that is required to have high saturation, a high-performance semiconductor device can be realized.

[0081] For example, when the semiconductor device according to one embodiment of the present invention is used in a pixel circuit of a display device, the occupied area of the pixel circuit can be reduced, and a high-definition display device can be realized. Further, for example, when the semiconductor device according to one embodiment of the present invention is used in a driving circuit of a display device (for example, one or both of a gate line driving circuit and a source line driving circuit), the occupied area of the driving circuit can be reduced, and thus a display device with a narrow border can be realized.

[0082] The capacitor element 150 includes a conductive layer 112b and a conductive layer 202 serving as a pair of electrodes, and an insulating layer 120. The conductive layer 112b serves as the other of the source electrode and the drain electrode of the transistor 100, and also serves as one of the pair of electrodes of the capacitor element 150. The conductive layer 202 serves as the back gate electrode of the transistor 200, and also serves as the other of the pair of electrodes of the capacitor element 150. The region between the conductive layer 112b and the conductive layer 202 sandwiching the insulating layer 120 serves as the dielectric of the capacitor element 150. By forming the conductive layer 112b and the conductive layer 202 in different processes, the capacitor element 150 including these conductive layers as a pair of electrodes can be formed. Further, by forming the conductive layer 112b and the conductive layer 202 in different processes, different materials can be used for the conductive layer 112b and the conductive layer 202, and thus the range of material selection can be expanded.

[0083] In Figure 1A etc., an example in which the capacitor element 150 is composed of the conductive layer 112b, the conductive layer 202, and the insulating layer 120 is used for explanation, but the structure of the capacitor element 150 is not particularly limited. Further, the semiconductor device 10 may not include the capacitor element 150. Note that when the capacitor element 150 composed of the conductive layer 112b, the conductive layer 202, and the insulating layer 120 is not provided, the conductive layer 112b and the conductive layer 202 may be formed in the same process.

[0084] In Figure 1A etc., the other of the source electrode and the drain electrode of the transistor 100 is electrically connected to one of the pair of electrodes of the capacitor element 150, and one of the source electrode and the drain electrode of the transistor 200 is electrically connected to the other of the pair of electrodes of the capacitor element 150, but the electrical connection relationship among the transistor 100, the transistor 200, and the capacitor element 150 is not particularly limited.

[0085] An insulating layer 195 is provided so as to cover the transistor 100, the transistor 200, and the capacitor element 150. The insulating layer 195 serves as a protective layer for the transistor 100, the transistor 200, and the capacitor element 150. Further, in Figure 2A and Figure 2B the perspective view shown, the insulating layer 195 is omitted.

[0086] Describe the detailed structures of transistor 100 and transistor 200.

[0087] There is no particular limitation on the semiconductor material used for semiconductor layer 108 and semiconductor layer 208. For example, a semiconductor composed of a single element or a compound semiconductor can be used. As a semiconductor composed of a single element, silicon and germanium can be cited, for example. As a compound semiconductor, gallium arsenide and silicon germanium can be cited, for example. In addition, as a compound semiconductor, an organic semiconductor, a nitride semiconductor, and an oxide semiconductor (OS: Oxide Semiconductor) can be cited, for example. Note that these semiconductor materials can also contain impurities as dopants.

[0088] There is no particular limitation on the crystallinity of the semiconductor material used for semiconductor layer 108 and semiconductor layer 208, and an amorphous semiconductor, a single crystal semiconductor, or a semiconductor having crystallinity other than a single crystal (microcrystalline semiconductor, polycrystalline semiconductor, or a semiconductor having a crystalline region in a part thereof) can be used. When a single crystal semiconductor or a semiconductor having crystallinity is used, deterioration of the transistor characteristics can be suppressed, which is preferable.

[0089] Silicon can be used for both semiconductor layer 108 and semiconductor layer 208. As silicon, single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon can be cited. As polycrystalline silicon, low temperature polycrystalline silicon (LTPS: Low Temperature PolySilicon) can be cited, for example. A transistor using amorphous silicon for the channel formation region can be formed on a large glass substrate and can be manufactured at low cost. A transistor using polycrystalline silicon in the channel formation region has a high field effect mobility and can operate at high speed. In addition, compared with a transistor using amorphous silicon, a transistor using microcrystalline silicon in the channel formation region has a high field effect mobility and can operate at high speed.

[0090] Both semiconductor layer 108 and semiconductor layer 208 preferably contain a metal oxide (also referred to as an oxide semiconductor) that exhibits semiconductor characteristics.

[0091] The band gap of the metal oxide used for semiconductor layer 108 and semiconductor layer 208 is preferably 2.0 eV or more, and more preferably 2.5 eV or more.

[0092] Compared with a transistor using amorphous silicon, the field effect mobility of a transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) is very high. In addition, the off-state current of the OS transistor is extremely small, and the charge stored in a capacitor connected in series with the transistor can be maintained for a long period. In addition, by using an OS transistor, the power consumption of the semiconductor device can be reduced.

[0093] The insulating layer 110 preferably has more than one layer of inorganic insulating film. As materials that can be used for the inorganic insulating film, for example, oxides, nitrides, oxynitrides, and oxynitridos can be cited. As oxides, for example, silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, gallium zinc oxide, and hafnium aluminate can be cited. As nitrides, for example, silicon nitride and aluminum nitride can be cited. As oxynitrides, for example, silicon oxynitride, aluminum oxynitride, gallium oxynitride, yttrium oxynitride, and hafnium oxynitride can be cited. As oxynitridos, for example, silicon oxynitride and aluminum oxynitride can be cited.

[0094] Note that in this specification and the like, oxynitride refers to a material in which the oxygen content is more than the nitrogen content in its composition. Oxynitridos refers to a material in which the nitrogen content is more than the oxygen content in its composition.

[0095] The insulating layer 110 has a region in contact with the semiconductor layer 108. When a metal oxide is used as the semiconductor layer 108, in order to improve the interface characteristics between the semiconductor layer 108 and the insulating layer 110, at least a part of the region of the insulating layer 110 in contact with the semiconductor layer 108 preferably contains oxygen. Specifically, the part of the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108 preferably contains oxygen. One or more of oxides and oxynitrides can be appropriately used for the part of the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108.

[0096] The insulating layer 110 preferably has a stacked structure. Figure 1B Examples such as the insulating layer 110 including an insulating layer 110a, an insulating layer 110b on the insulating layer 110a, and an insulating layer 110c on the insulating layer 110b are shown.

[0097] Figure 3 is Figure 1B An enlarged view of the transistor 100 shown. The region of the semiconductor layer 108 in contact with the insulating layer 110b is used as a channel formation region. The insulating layer 110b preferably contains oxygen, and any one or more of the above-mentioned oxides and oxynitrides are preferably used. Specifically, one or both of silicon oxide and silicon oxynitride can be appropriately used for the insulating layer 110b.

[0098] The insulating layer 110b is more preferably a film that releases oxygen by heating. Since the insulating layer 110b releases oxygen due to the heat applied in the manufacturing process of the transistor 100, oxygen can be supplied to the semiconductor layer 108. By supplying oxygen from the insulating layer 110b to the semiconductor layer 108, especially to the channel formation region, oxygen vacancies (V O ) can be repaired, and oxygen vacancies (V O ) can be reduced. Thereby, a transistor with good electrical characteristics and high reliability can be realized.

[0099] For example, oxygen can be supplied to the insulating layer 110b by performing a heat treatment in an oxygen-containing atmosphere or a plasma treatment in an oxygen-containing atmosphere. Additionally, an oxide film can be formed on the top surface of the insulating layer 110b by sputtering in an oxygen-containing atmosphere to supply oxygen. Then, the oxide film can also be removed. Additionally, the method for supplying oxygen to the insulating layer 110b will be described in Embodiment 2.

[0100] The insulating layer 110b is preferably formed by a deposition method such as sputtering or plasma enhanced chemical vapor deposition (PECVD: Plasma Enhanced Chemical Vapor Deposition, also denoted as plasma CVD). In particular, by forming using the sputtering method and not using a hydrogen-containing gas as the deposition gas, a film with an extremely low hydrogen content can be achieved. Therefore, it is possible to suppress the supply of hydrogen to the channel formation region and stabilize the electrical characteristics of the transistor 100.

[0101] Preferably, substances (e.g., atoms, molecules, and ions) are easily diffusible in the insulating layer 110b. It can also be said that the diffusion coefficient of substances in the insulating layer 110b is preferably large. Particularly preferably, oxygen is easily diffusible in the insulating layer 110b. That is, the oxygen diffusion coefficient in the insulating layer 110b is preferably large. The oxygen diffusion in the insulating layer 110b is supplied to the semiconductor layer 108 through the interface between the insulating layer 110b and the semiconductor layer 108. Figure 3 The diffusion of oxygen in the insulating layer 110b to the interface between the insulating layer 110b and the semiconductor layer 108 is schematically shown by an arrow. By using the insulating layer 110b in which oxygen is easily diffusible, oxygen in the insulating layer 110b can be efficiently supplied to the semiconductor layer 108 (especially, the channel formation region).

[0102] The oxygen diffusion coefficient of the insulating layer 110b at 350 °C is preferably 5×10 -12 cm 2 / sec or more, more preferably 1×10 -11 cm 2 / sec or more, further preferably 5×10 -11 cm 2 / sec or more, still further preferably 1×10 -10 cm 2 / sec or more. Thus, oxygen in the insulating layer 110b can be efficiently supplied to the semiconductor layer 108. The larger the diffusion coefficient, the better, so no particular upper limit is set. In the calculation of the diffusion coefficient, for example, thermal desorption spectrometry (TDS) can be used. Alternatively, secondary ion mass spectrometry (SIMS) can also be used.

[0103] A specific description of the formation of the insulating layer 110b will be given. Here, an example of forming silicon oxynitride by the PECVD method will be described.

[0104] As the source gas for the insulating layer 110b, a gas containing a silicon-containing deposition gas and an oxidizing gas can be used. As the silicon-containing deposition gas, for example, one or more of silane (SiH4), disilane (Si2H6), trisilane (Si3H8), silane fluoride (SiF4), TEOS (Tetraethoxysilane: tetraethoxysilane, Si(OC2H5)4) can be used. As the oxidizing gas, an oxygen-containing gas can be appropriately used. As the oxidizing gas, for example, one or more of oxygen (O2), ozone (O3), nitrous oxide (N2O), nitric oxide (NO), and nitrogen dioxide (NO2) can be used. When silane (SiH4) is used as the silicon-containing deposition gas and nitrous oxide (N2O) is used as the oxidizing gas, the generation of fine particles can be reduced compared with the case of using oxygen (O2), so it is preferable. Alternatively, when forming silicon oxide for the insulating layer 110b and TEOS is used as the silicon-containing deposition gas, oxygen (O2) can be appropriately used as the oxidizing gas.

[0105] In the formation of the insulating layer 110b using the PECVD method, by reducing the plasma density with respect to the flow rate of the deposition gas, that is, reducing the ratio of the plasma density to the flow rate of the deposition gas, an insulating layer with a large diffusion coefficient can be formed. Here, in the case of plasmaizing the source gas using an RF power supply, by reducing the power of the RF power supply (hereinafter also referred to as the RF power), the plasma density can be reduced. By reducing the RF power with respect to the flow rate of the deposition gas (reducing the ratio of the RF power to the flow rate of the deposition gas), an insulating layer with a large diffusion coefficient can be formed. By reducing the ratio of the RF power to the flow rate of the deposition gas (hereinafter, also referred to as the F ratio), the oxygen diffusion coefficient in the insulating layer 110b becomes larger, and the oxygen contained in the insulating layer 110b can be efficiently supplied to the semiconductor layer 108 (especially the channel formation region). However, in the case of using a hydrogen-containing gas (e.g., SiH4) as the source gas, when the F ratio is too small, sometimes the amount of hydrogen contained in the insulating layer 110b becomes large. When a large amount of hydrogen is contained in the insulating layer 110b, the amount of impurities (e.g., water, hydrogen, and ammonia) including hydrogen released from the insulating layer 110b may become large.

[0106] When the flow rate unit of the gas is expressed in sccm (Standard Cubic Centimeters Per Minute) and the RF power is expressed in W (Watt), the F ratio is preferably 12 or less, 10 or less, 9 or less, 8 or less, 7 or less, 6 or less, or 5 or less, and is 2 or more or 3 or more. For example, when the flow rate of silane (SiH4) is 290 sccm and the RF power is 1160 W, the F ratio is 4. By setting the F ratio within the above range, the oxygen contained in the insulating layer 110b can be efficiently supplied to the semiconductor layer 108 (especially the channel formation region), and the amount of impurities released from the insulating layer 110b can be reduced.

[0107] In this specification, etc., sccm represents the flow rate at 1 atmosphere and 0 °C (273.15 K). In addition, although the F ratio is shown when the unit of the gas flow rate is sccm and the RF power is W, when using different units from these, convert the unit to calculate the F ratio. For example, when the flow rate is 0.3 SLM (Standard Liter Per Minute), the flow rate can be converted to 300 sccm to calculate the F ratio.

[0108] Compared with a transistor having a long channel length, in the transistor 100 having a short channel length, the oxygen vacancies (V O ) and V OThe influence of H on the electrical characteristics is significant. Therefore, it is very important to efficiently supply oxygen from the insulating layer 110b to the semiconductor layer 108 (especially the channel formation region) and reduce the amount of impurities released from the insulating layer 110b. By setting the F ratio in the formation of the insulating layer 110b within the above range, a transistor with good electrical characteristics and high reliability can be achieved.

[0109] When gas is released from the film due to heating of the film, as the rate-limiting process of gas release, diffusion rate-limiting in the film and reaction rate-limiting on the film surface can be cited. A film in which substances diffuse easily is not likely to become diffusion rate-limiting, so the temperature at which gas starts to be released during heating (hereinafter also referred to as the release temperature) is low. On the other hand, a film in which substances do not diffuse easily becomes diffusion rate-limiting, so the gas release temperature is high. As described above, it is preferable to use a film in which substances diffuse easily for the insulating layer 110b. Therefore, the gas release temperature when heating the insulating layer 110b is preferably low. For example, in the TDS of the insulating layer 110b, the gas release temperature is preferably low. In particular, in the TDS of the insulating layer 110b, the release temperature of oxygen ( 16 O2, m / z = 32) is preferably low.

[0110] In the manufacturing process of the semiconductor device 10, sometimes oxygen is supplied from the insulating layer 110b to the semiconductor layer 108, and the amount of oxygen that may be released from the insulating layer 110b in the semiconductor device 10 after the manufacturing process may be small. Therefore, when performing the TDS of the semiconductor device 10, sometimes the amount of oxygen released is small. However, since a film in which oxygen diffuses easily also easily diffuses substances other than oxygen, when the release temperature of gases other than oxygen is low, this film can be considered a film in which oxygen diffuses easily. For example, in the TDS of the semiconductor device 10, when the release temperature of nitrogen ( 14 N2, m / z = 28) is low, it can be considered that the release temperature of oxygen is also low, and from this, it can be speculated that this film is a film in which oxygen diffuses easily. In the TDS of the semiconductor device 10, the release temperature of nitrogen ( 14 N2, m / z = 28) is preferably 250 °C or lower, 200 °C or lower, 180 °C or lower, 170 °C or lower, or 160 °C or lower and 140 °C or higher. Thereby, oxygen contained in the insulating layer 110b can be efficiently supplied to the semiconductor layer 108 (especially the channel formation region), and the amount of impurities released from the insulating layer 110b can be reduced. In addition, when performing the TDS of the semiconductor device 10, it is preferable to remove the layer on the upper side of the insulating layer 110b to expose the insulating layer 110b. Furthermore, in this embodiment, the heating rate of the sample surface temperature in the TDS is approximately 14 °C / min. In addition, the heating rate of the stage on which the sample is placed can be, for example, about 32 °C / min.

[0111] An example of a method for calculating the release temperature in TDS will be described. In a graph with the X-axis representing the sample surface temperature and the Y-axis representing the detection intensity of the mass spectrometer (e.g., current value), a tangent can be drawn at the point with the maximum slope on the low-temperature side of the peak, and the intersection of this tangent with the X-axis (Y = 0) can be set as the release temperature. It is preferable to perform background processing on the detection intensity of the mass spectrometer. As background processing, for example, a method of subtracting the minimum value of the detection intensity in the entire measured temperature range from the measured value as the background value can be cited.

[0112] Note that if the F ratio during film formation is high, the etching rate with respect to the etchant becomes slow, and if the F ratio during film formation is low, the etching rate with respect to the etchant becomes fast. Therefore, the etching rate can be used as an index of diffusion ease. As this etchant, for example, an etchant containing hydrofluoric acid can be used. Specifically, hydrofluoric acid and BHF (Buffered Hydrofluoric acid) can be cited. BHF is an etchant containing hydrofluoric acid and a buffer (e.g., ammonium fluoride (NH4F)). In addition, an etchant to which a surfactant is added can also be used. For example, when the insulating layer 110b uses silicon oxide or silicon oxynitride, the etching rate of the insulating layer 110b with respect to 0.5 wt% hydrofluoric acid at 25°C is preferably 8 nm / min or more, 9 nm / min or more, 10 nm / min or more, 11 nm / min or more, or 12 nm / min or more and 15 nm / min or less. In addition, the etching rate can be calculated by dividing the difference between the thickness of the target film before etching and the thickness of the target film after etching by the etching time.

[0113] Here, by using a material with high conductivity for the semiconductor layer 108, a transistor with a large on-state current can be realized. However, when using a material with high conductivity, oxygen vacancies (V O ) are easily formed. When the number of oxygen vacancies (V O ) in the channel formation region increases, sometimes the threshold voltage of the transistor drifts, and the drain current flowing when the gate voltage is 0V (hereinafter, also referred to as the cut-off current) increases. For example, in an n-channel transistor, when the threshold voltage drifts negatively, sometimes the cut-off current increases. By providing the insulating layer 110b, oxygen is supplied at least to the region of the semiconductor layer 108 in contact with the insulating layer 110b, that is, the channel formation region. Therefore, the oxygen vacancies (V O ) in the channel formation region can be reduced. Thereby, threshold voltage drift can be suppressed, so a transistor with a small cut-off current and a large on-state current can be realized. Thereby, a low-power and high-performance semiconductor device can be realized.

[0114] In the semiconductor layer 108, the region in contact with the conductive layer 112a is used as one of the source region and the drain region of the transistor 100, and the region in contact with the conductive layer 112b is used as the other of the source region and the drain region. The source region and the drain region are regions where the resistance is lower than that of the channel formation region. The source region and the drain region can also be said to be regions where the carrier concentration is higher and the oxygen vacancy density is higher than that of the channel formation region.

[0115] The insulating layer 110a is provided between the insulating layer 110b and the conductive layer 112a. The insulating layer 110c is provided between the insulating layer 110b and the conductive layer 112b. The insulating layer 110a and the insulating layer 110c preferably have a small amount of impurities (such as hydrogen and water) released from themselves and are not easily permeated by impurities. Thereby, the impurities contained in the insulating layer 110a and the insulating layer 110c can be suppressed from diffusing into the channel formation region. Therefore, a transistor having good electrical characteristics and high reliability can be realized.

[0116] The insulating layer 110a and the insulating layer 110c preferably use a film that is not easily permeated by oxygen. Thereby, the oxygen contained in the insulating layer 110b can be suppressed from diffusing through the insulating layer 110a into the conductive layer 112a. Similarly, the oxygen contained in the insulating layer 110b can be suppressed from diffusing through the insulating layer 110c into the conductive layer 112b. Thereby, the oxidation of the conductive layer 112a and the conductive layer 112b can be suppressed and the resistance can be prevented from increasing. At the same time, the diffusion of the oxygen contained in the insulating layer 110b to the insulating layer 110a side and the insulating layer 110c side is suppressed, whereby the amount of oxygen supplied from the insulating layer 110b to the channel formation region increases, and the oxygen vacancies (V O ) and V O H in the channel formation region can be reduced.

[0117] By using a film that does not easily diffuse oxygen for both the insulating layer 110a and the insulating layer 110c, oxygen can be effectively supplied from the insulating layer 110b to the channel formation region. In addition, one or both of the insulating layer 110a and the insulating layer 110c may not be provided.

[0118] The insulating layer 110a and the insulating layer 110c preferably both contain nitrogen, and preferably use any one or more of the above nitrides and oxynitrides. For example, the insulating layer 110a and the insulating layer 110c can both be appropriately made of silicon nitride or silicon oxynitride. Alternatively, any one or more of oxides and oxynitrides can be used for one or both of the insulating layer 110a and the insulating layer 110c. For example, the insulating layer 110a and the insulating layer 110c can both be appropriately made of aluminum oxide. Note that the insulating layer 110a can use the same material or a different material from the insulating layer 110c.

[0119] Note that in this specification and the like, different materials refer to materials in which part or all of the constituent elements are different, or materials in which the constituent elements are the same but the composition is different.

[0120] The thickness T110a of the insulating layer 110a can be, for example, 3 nm or more, 5 nm or more, 10 nm or more, 20 nm or more, 50 nm or more, or 70 nm or more and less than 1 μm, 500 nm or less, 400 nm or less, 300 nm or less, 200 nm or less, 150 nm or less, or 120 nm or less. As Figure 3 shown, the thickness T110a can be the shortest distance between the formed surface of the insulating layer 110a (here, the top surface of the conductive layer 112a) and the bottom surface of the insulating layer 110b when viewed from the cross section.

[0121] When the thickness T110a of the insulating layer 110a is relatively thick, sometimes the amount of impurities released from the insulating layer 110a becomes larger, and the amount of impurities diffused into the channel formation region becomes larger. On the other hand, when the thickness T110a is relatively thin, sometimes the oxygen contained in the insulating layer 110b diffuses through the insulating layer 110a to the conductive layer 112a side, and the amount of oxygen supplied to the channel formation region decreases. By setting the thickness T110a within the above range, oxygen vacancies (V O ) and V O H in the channel formation region can be reduced. In addition, it is possible to suppress the increase in the resistance of the conductive layer 112a due to the oxidation of the conductive layer 112a caused by the oxygen contained in the insulating layer 110b.

[0122] The thickness T110c of the insulating layer 110c can be, for example, 3 nm or more, 5 nm or more, 10 nm or more, 15 nm or more, or 20 nm or more and 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 150 nm or less, 120 nm or less, or 100 nm or less. As Figure 3 shown, the thickness T110c can be the shortest distance between the formed surface of the insulating layer 110c (here, the top surface of the insulating layer 110b) and the bottom surface of the conductive layer 112b when viewed from the cross section.

[0123] When the thickness T110c of the insulating layer 110c is relatively thick, sometimes the amount of impurities released from the insulating layer 110c becomes larger, and the amount of impurities diffused into the channel formation region becomes larger. On the other hand, when the thickness T110c is relatively thin, sometimes the oxygen contained in the insulating layer 110b diffuses through the insulating layer 110c to the conductive layer 112b side, and the amount of oxygen supplied to the channel formation region decreases. By setting the thickness T110c within the above range, oxygen vacancies (V O ) and V O H in the channel formation region can be reduced. In addition, it is possible to suppress the increase in the resistance of the conductive layer 112b due to the oxidation of the conductive layer 112b caused by the oxygen contained in the insulating layer 110b.

[0124] At least one of the regions of the semiconductor layer 108 that are in contact with the insulating layer 110a and the regions that are in contact with the insulating layer 110c may also be a region with a lower resistance than the channel formation region (hereinafter, also referred to as a low-resistance region). This region can also be said to be a region with a higher carrier concentration and a higher oxygen vacancy density than the channel formation region. By using a material that releases impurities (e.g., water and hydrogen) for the insulating layer 110a, the region of the semiconductor layer 108 that is in contact with the insulating layer 110a can be used as a low-resistance region. The semiconductor layer 108 may have a structure including a low-resistance region between the region in contact with the conductive layer 112a (one of the source region and the drain region) and the channel formation region. Similarly, by using a material that releases impurities as the insulating layer 110c, the region of the semiconductor layer 108 that is in contact with the insulating layer 110c can be made into a low-resistance region. The semiconductor layer 108 may have a structure including a low-resistance region between the region in contact with the conductive layer 112b (the other of the source region and the drain region) and the channel formation region. The low-resistance region can be used as a buffer region for mitigating the drain electric field. These low-resistance regions can also be used as the source region or the drain region.

[0125] By providing a low-resistance region between the drain region and the channel formation region, a high electric field is not easily generated near the drain region, the generation of hot carriers can be suppressed, and the degradation of the transistor can be suppressed. For example, when the conductive layer 112a is used as the drain electrode and the conductive layer 112b is used as the source electrode, by setting the region of the semiconductor layer 108 that is in contact with the insulating layer 110a as a low-resistance region, a high electric field is not easily generated near the drain region, the generation of hot carriers can be suppressed, and the degradation of the transistor can be suppressed. When the conductive layer 112a is used as the source electrode and the conductive layer 112b is used as the drain electrode, by setting the region of the semiconductor layer 108 that is in contact with the insulating layer 110c as a low-resistance region, a high electric field is not easily generated near the drain region, the generation of hot carriers can be suppressed, and the degradation of the transistor can be suppressed.

[0126] As described above, when the amount of impurities released from the insulating layer 110a and the insulating layer 110c is excessive, there is a concern that the impurities may diffuse into the channel formation region. Even when using a material that releases impurities as the insulating layer 110a and the insulating layer 110c, the amount of impurities released is preferably small.

[0127] The insulating layer 110 preferably includes at least the insulating layer 110b. For example, it may not include one or both of the insulating layer 110a and the insulating layer 110c. In addition, the insulating layer 110 may have a stacked structure of two or four or more layers or a single-layer structure.

[0128] There is no limitation on the top surface shape of the openings 141 and 143. For example, it can be circular, oval, triangular, quadrangular (including rectangle, rhombus, square), pentagonal or other polygonal shapes or the rounded shapes of these polygonal shapes. The polygonal shape can also be a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees). As Figure 1A etc. show, the top surface shapes of the openings 141 and 143 are preferably both circular. By making the top surface shape of the opening circular, the processing accuracy when forming the opening can be improved, and a fine opening can be formed. Note that in this specification, etc., the circle is not limited to a perfect circle.

[0129] In this specification, etc., the top surface shape of the opening 141 refers to the shape of the top surface end on the opening 141 side of the insulating layer 110. In addition, the top surface shape of the opening 143 refers to the shape of the bottom surface end on the opening 143 side of the conductive layer 112b.

[0130] As Figure 1A etc. show, the top surface shape of the opening 141 and the top surface shape of the opening 143 can be the same or substantially the same. At this time, as Figure 1B and Figure 1C etc. show, the bottom surface end on the opening 143 side of the conductive layer 112b and the top surface end on the opening 141 side of the insulating layer 110 are preferably the same or substantially the same. The bottom surface of the conductive layer 112b refers to the surface on the insulating layer 110 side. The top surface of the insulating layer 110 refers to the surface on the conductive layer 112b side.

[0131] In addition, the top surface shape of the opening 141 and the top surface shape of the opening 143 can also be different. In addition, when the top surface shapes of the openings 141 and 143 are circular, the openings 141 and 143 can be concentric or non - concentric.

[0132] Refer to Figure 4A and Figure 4B to illustrate the channel length and channel width of the transistor 100. Figure 4A and Figure 4B are Figure 1A and Figure 1B the enlarged views of the transistor 100 shown.

[0133] Figure 4BIn the figure, a double arrow in dashed line indicates the channel length L100 of the transistor 100. The channel length L100 of the transistor 100 corresponds to the length of the side on the opening 141 side of the insulating layer 110b when viewed in cross section. That is to say, the channel length L100 is determined according to the thickness T110b of the insulating layer 110b and the angle θ110 formed by the side on the opening 141 side of the insulating layer 110b and the formed surface of the insulating layer 110b (here, the top surface of the insulating layer 110a). Therefore, for example, the channel length L100 can be set to a value smaller than the limit resolution of the exposure apparatus, and a fine transistor can be realized. Specifically, a transistor with an extremely short channel length that cannot be realized in an exposure apparatus (for example, with a minimum line width of about 2 μm or 1.5 μm) used in the mass production of conventional flat panel displays can be realized. In addition, a transistor with a channel length less than 10 nm can be realized even in a state where a very expensive exposure apparatus used in the most advanced LSI technology is not used.

[0134] The channel length L100 can be, for example, 5 nm or more, 7 nm or more, or 10 nm or more and less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less. For example, the channel length L100 can be set to be 100 nm or more and 1 μm or less.

[0135] By shortening the channel length L100, the on-state current of the transistor 100 can be increased. By using the transistor 100, a circuit capable of operating at high speed can be manufactured. Moreover, the occupied area of the circuit can be reduced. Therefore, a small semiconductor device can be realized. For example, when the semiconductor device according to one embodiment of the present invention is used in a large display device or a high-definition display device, the signal delay of each wiring can be reduced even when the number of wirings increases, thereby suppressing display unevenness. In addition, since the occupied area of the circuit can be reduced, the frame of the display device can be reduced.

[0136] By adjusting the thickness T110b and the angle θ110 of the insulating layer 110b, the channel length L100 can be controlled. In Figure 4B the figure, a double arrow in dotted line indicates the thickness T110b of the insulating layer 110b.

[0137] The thickness T110b of the insulating layer 110b can be, for example, 5 nm or more, 7 nm or more, or 10 nm or more and less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less.

[0138] The side surface on one side of the opening 141 of the insulating layer 110 preferably has a tapered shape. The angle θ110 is preferably less than 90 degrees. By reducing the angle θ110, the coverage of the layer formed on the insulating layer 110 (for example, the semiconductor layer 108) can be improved. In addition, the smaller the angle θ110, the longer the channel length L100 can be, and the larger the angle θ110, the shorter the channel length L100 can be.

[0139] The angle θ110 can be, for example, 30 degrees or more, 35 degrees or more, 40 degrees or more, 45 degrees or more, 50 degrees or more, 55 degrees or more, 60 degrees or more, 65 degrees or more, or 70 degrees or more and less than 90 degrees, 85 degrees or less, or 80 degrees or less. The angle θ110 can also be 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less.

[0140] Note that Figure 4B structures in which the shape of the side surface on one side of the opening 141 of the insulating layer 110 is shown as a straight line when viewed in cross section are shown in etc., but one aspect of the present invention is not limited thereto. When viewed in cross section, the shape of the side surface on one side of the opening 141 of the insulating layer 110 can also be a curve, or can have both a region where the shape of the side surface is a straight line and a region where the shape is a curve.

[0141] Here, the conductive layer 112b is preferably not provided inside the opening 141. Specifically, the conductive layer 112b preferably does not have a region in contact with the side surface on one side of the opening 141 of the insulating layer 110. When the conductive layer 112b is also provided inside the opening 141, the channel length L100 of the transistor 100 is shorter than the length of the side surface of the insulating layer 110b, so that the control of the channel length L100 sometimes becomes difficult. Therefore, it is preferable that the top surface shape of the opening 143 is the same as the top surface shape of the opening 141 or the opening 143 includes the opening 141 when viewed from above (also referred to as when viewed from the plane).

[0142] In Figure 4A and Figure 4B the width D141 of the opening 141 is indicated by a double-headed arrow with a double-dashed line. Figure 4A An example in which the top surface shape of the opening 141 is circular is shown. At this time, the width D141 corresponds to the diameter of the circle, and the channel width W100 of the transistor 100 corresponds to the length of the circumference of the circle. That is, the channel width W100 is π×D141. Thus, when the top surface shape of the opening 141 is circular, a transistor with a smaller channel width W100 can be realized compared to other shapes.

[0143] The width D141 of the opening 141 sometimes varies in the depth direction. As the width D141 of the opening 141, for example, the average value of the three diameters of the highest position, the lowest position, and the position of the midpoint of the insulating layer 110b (or insulating layer 110) when viewed in cross-section can be used. Alternatively, as the diameter of the opening 141, for example, any of the diameters of the highest position, the lowest position, and the position of the midpoint of the insulating layer 110b (or insulating layer 110) when viewed in cross-section can also be used.

[0144] When forming the opening 141 by photolithography, the width D141 of the opening 141 is above the limit resolution of the exposure apparatus. The width D141 can be, for example, 200 nm or more, 300 nm or more, 400 nm or more, or 500 nm or more and less than 5 μm, 4.5 μm or less, 4 μm or less, 3.5 μm or less, 3 μm or less, 2.5 μm or less, 2 μm or less, 1.5 μm or less, or 1 μm or less.

[0145] Note that when shortening the channel length L100 of the transistor 100, the insulating layer 110a and the insulating layer 110c are preferably made of a material that releases less hydrogen from itself. When the insulating layer 110a and the insulating layer 110c use a material that also releases a small amount of hydrogen, their thicknesses are preferably small. For example, when the channel length L100 is 100 nm or less, the thickness T110a of the insulating layer 110a and the thickness T110c of the insulating layer 110c are preferably 1 nm or more, 3 nm or more, or 5 nm or more, and 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, 15 nm or less, or 10 nm or less. Thereby, the amount of impurities diffused into the channel formation region can be reduced, and thus a transistor with good electrical characteristics and high reliability can be realized even when the channel length L100 is short.

[0146] Note that here, a structure in which the region of the semiconductor layer 108 in contact with the insulating layer 110b is used as the channel formation region is described as an example, but one aspect of the present invention is not limited thereto. The region of the semiconductor layer 108 in contact with the insulating layer 110a can also be used as the channel formation region. Similarly, the region in contact with the insulating layer 110c can also be used as the channel formation region.

[0147] Figure 1B Examples such as those showing the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 covering the opening 141 and the opening 143 in the transistor 100 are shown, but one aspect of the present invention is not limited thereto, and a structure in which the insulating layer 110 and the conductive layer 112a form a step and the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 are provided along the step can also be adopted.

[0148] Next, use Figures 5A to 5CDescribe the detailed structure of the transistor 200. Figures 5A to 5C is Figures 1A to 1C an enlarged view of the transistor 200 shown.

[0149] The channel length of the transistor 200 is the length of the region where the semiconductor layer 208 and the conductive layer 204 overlap between a pair of regions 208D. In Figure 5A and Figure 5B the channel length L200 of the transistor 200 is indicated by a dashed double arrow. The channel length L200 of the transistor 200 is determined according to the length of the conductive layer 204 and is a value above the limit resolution of the exposure apparatus used in the manufacture of the transistor. For example, the channel length L200 can be 1.5 μm or more. By increasing the channel length, a transistor with high saturation can be achieved.

[0150] The conductive layer 202 serving as the back gate electrode of the transistor 200 preferably extends beyond the end of the region where the conductive layer 204 and the semiconductor layer 208 overlap in the channel length direction. That is, the size of the conductive layer 202 is preferably larger than the size of the region where the conductive layer 204 and the semiconductor layer 208 overlap in the channel length direction. Specifically, the conductive layer 202 preferably has a portion protruding beyond the end of the conductive layer 204 in the channel length direction.

[0151] In this specification and the like, for the sake of convenience in explanation, the portion of the semiconductor layer 208 that overlaps with the conductive layer 204 is sometimes referred to as the channel formation region, but in fact, the channel may sometimes be formed in the portion that does not overlap with the conductive layer 204 but overlaps with the conductive layer 202.

[0152] The channel width of the transistor 200 is the width of the region where the semiconductor layer 208 and the conductive layer 204 overlap in the direction orthogonal to the channel length direction. In Figure 5A and Figure 5C the channel width W200 of the transistor 200 is indicated by a dotted double arrow.

[0153] As described above, the channel length L100 of the transistor 100 can be set to a value smaller than the limit resolution of the exposure apparatus, and the channel length L200 of the transistor 200 can be set to a value equal to or greater than the limit resolution of the exposure apparatus. For example, by using the transistor 100 as a transistor that needs to have a large on-state current and using the transistor 200 as a transistor that needs to have high saturation, a high-performance semiconductor device 10 that utilizes the advantages of each transistor can be realized. Also, some processes can be made common to form the transistor 100 and the transistor 200. Specifically, the semiconductor layer 108 and the semiconductor layer 208 can be formed by the same process. A part of the insulating layer 106 is used as the gate insulating layer of the transistor 100, and another part of the insulating layer 106 is used as the gate insulating layer of the transistor 200. The conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b can be formed by the same process. Therefore, the productivity of the semiconductor device 10 can be improved and the manufacturing cost can be reduced.

[0154] As Figure 5A and Figure 5C shown, it is preferable that the conductive layer 204 and the conductive layer 202 protrude to the outside of the end of the semiconductor layer 208 in the channel width direction of the transistor 200. At this time, as Figure 5C shown, the entirety in the channel width direction of the semiconductor layer 208 is covered by the conductive layer 204 and the conductive layer 202 with the insulating layer 106 and the insulating layer 120 therebetween. By adopting such a structure, the electric field generated by a pair of gate electrodes can surround the semiconductor layer 208.

[0155] In Figure 5A and Figure 5C , the conductive layer 204 and the conductive layer 202 are not electrically connected. In addition, a constant potential can be supplied to one of the pair of gate electrodes and a signal for driving the transistor 200 can be supplied to the other. At this time, the threshold voltage when the transistor 200 is driven by the other gate electrode can be controlled by the potential supplied to one gate electrode.

[0156] The conductive layer 204 and the conductive layer 202 can also be electrically connected to each other. By supplying the same potential to the conductive layer 204 and the conductive layer 202, an electric field for causing a channel can be effectively applied to the semiconductor layer 208, and the on-state current of the transistor 200 can be increased. Therefore, a miniaturized transistor 200 can be realized. For example, an opening reaching the conductive layer 202 can be formed in the insulating layer 106 and the insulating layer 120, and the conductive layer 204 can be formed so as to cover the opening.

[0157] The conductive layer 202 can also be electrically connected to the conductive layer 212a or the conductive layer 212b. For example, an opening reaching the conductive layer 202 can be provided in the insulating layer 120, and the conductive layer 212a or the conductive layer 212b can be formed so as to cover the opening.

[0158] The insulating layer 120 provided in contact with the top surface and the side surface of the conductive layer 202 may use the material that can be used for the insulating layer 110.

[0159] The insulating layer 120 preferably has a laminated structure. Figure 5B Structures such as those showing that the insulating layer 120 has a laminated structure of an insulating layer 120a and an insulating layer 120b on the insulating layer 120a are shown. Both the insulating layer 120a and the insulating layer 120b may use the material that can be used for the insulating layer 110.

[0160] More preferably, a film that releases oxygen by heating is used for the insulating layer 120b in contact with the channel formation region of the semiconductor layer 208. Since the insulating layer 120b releases oxygen due to the heat applied in the manufacturing process of the transistor 200, oxygen can be supplied to the semiconductor layer 208, particularly to the channel formation region of the semiconductor layer 208. The oxygen diffusion in the insulating layer 120b diffuses in the insulating layer 120b and is supplied to the semiconductor layer 208 through the interface between the insulating layer 120b and the semiconductor layer 208. By supplying oxygen from the insulating layer 120b to the semiconductor layer 208, particularly to the channel formation region, oxygen vacancies (V O ) can be repaired, and oxygen vacancies (V O ) can be reduced. Thereby, a transistor with good electrical characteristics and high reliability can be realized.

[0161] The oxygen diffusion coefficient of the insulating layer 120b at 350 °C is preferably 1×10 -12 cm 2 / sec or more, and more preferably 5×10 -12 cm 2 / sec or more.

[0162] The insulating layer 120b may use the material that can be used for the insulating layer 110b. The insulating layer 120b preferably contains oxygen, and one or more of oxides and oxynitrides may be appropriately used. Specifically, the insulating layer 120b may appropriately use, for example, silicon oxide or silicon oxynitride.

[0163] A specific description of the formation of the insulating layer 120b will be given. Here, an example of forming silicon oxynitride by the PECVD method will be described.

[0164] As the source gas for the insulating layer 120b, a gas containing a silicon-containing deposition gas and an oxidation gas may be used. The silicon-containing deposition gas and the oxidation gas may be referred to the above description.

[0165] When forming the insulating layer 120b using the PECVD method, the F ratio is preferably 20 or less, 18 or less, 16 or less, 14 or less, 13 or less, 12 or less, or 11 or less and 4 or more, 6 or more, 7 or more, 8 or more, or 9 or more. As described above, it is also possible to make the oxygen diffusion coefficient in the insulating layer 120b smaller than the oxygen diffusion coefficient in the insulating layer 110b. Therefore, compared with the F ratio in the formation of the insulating layer 110b, the F ratio in the formation of the insulating layer 120b can be increased. By increasing the F ratio, the deposition rate of the insulating layer 120b becomes faster, and thus the productivity can be improved. For example, when the insulating layer 120b is made of silicon oxide or silicon oxynitride, at 25 °C, the etching rate of the insulating layer 120b with respect to 0.5 wt% hydrofluoric acid is preferably 5 nm / min or more, 6 nm / min or more, or 7 nm / min or more and 15 nm / min or less.

[0166] Here, compared with the transistor 100 with a small channel length, in the transistor 200 with a large channel length, the influence of oxygen vacancies (V O ) and V O H on the power supply characteristics is very small. Therefore, the amount of oxygen supplied from the insulating layer 120b to the semiconductor layer 208 can also be less than the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer 108. The amount of oxygen released from the insulating layer 120b can also be less than the amount of oxygen released from the insulating layer 110b.

[0167] The diffusion coefficient of the substance in the insulating layer 110b is preferably larger than the diffusion coefficient of the substance in the insulating layer 120b. In particular, the oxygen diffusion coefficient in the insulating layer 110b is preferably larger than the oxygen diffusion coefficient in the insulating layer 120b. Thus, the transistor 100 with a small channel length can also be a transistor that exhibits good electrical characteristics and high reliability. Preferably, the F ratio in the formation of the insulating layer 110b is lower than the F ratio in the formation of the insulating layer 120b. Preferably, the etching rate of the insulating layer 110b is faster than the etching rate of the insulating layer 120b with respect to one etchant.

[0168] The insulating layer 120a in contact with the conductive layer 202 is preferably made of a material in which the metal elements contained in the conductive layer 202 do not easily diffuse. Thus, it is possible to suppress the metal elements contained in the conductive layer 202 from diffusing through the insulating layer 120 into the channel formation region of the semiconductor layer 208.

[0169] The insulating layer 120a preferably uses a material that can be used for the insulating layer 110a and the insulating layer 110c. The insulating layer 120a preferably contains nitrogen, and one or more of nitrides and nitrogen oxides can be appropriately used. Specifically, for example, silicon nitride can be appropriately used for the insulating layer 120a. Alternatively, any one or more of oxides and oxynitrides can also be used for the insulating layer 120a. For example, aluminum oxide can be appropriately used for the insulating layer 120a. Note that the insulating layer 120a, the insulating layer 110a, and the insulating layer 110c can use the same material or different materials.

[0170] Preferably, the amount of impurities (e.g., water and hydrogen) released from the insulating layer 120a itself is small. Thereby, it is possible to suppress the impurities contained in the insulating layer 120a from diffusing into the channel formation region of the semiconductor layer 208 through the insulating layer 120b, and a transistor having good electrical characteristics and high reliability can be realized.

[0171] Note that, in this example, the insulating layer 120 has a stacked structure of two layers, but one embodiment of the present invention is not limited thereto. The insulating layer 120 can have a stacked structure of three or more layers or a single-layer structure.

[0172] The insulating layer 120 is preferably provided in at least a portion in contact with the channel formation region of the semiconductor layer 208 and is provided so as to cover the top surface and the side surfaces of the conductive layer 202. In Figure 5B etc., the semiconductor layer 208 has a portion protruding beyond the end of the insulating layer 120. The semiconductor layer 208 has a region in contact with the side surface of the insulating layer 120. A part of the end of the semiconductor layer 208 is in contact with the top surface of the insulating layer 120, and the other part is in contact with the top surface of the insulating layer 110. It can also be said that a part of the bottom surface of the semiconductor layer 208 is in contact with the top surface of the insulating layer 120, and the other part is in contact with the top surface of the insulating layer 110. Alternatively, the insulating layer 120 can be provided in the region where the semiconductor layer 208 is provided so that the entire bottom surface of the semiconductor layer 208 is in contact with the top surface of the insulating layer 120.

[0173] Note, Figure 5BThe example shown in FIG. shows that the thickness of the semiconductor layer 208 is uniform at any position, but one embodiment of the present invention is not limited thereto. The thickness may also be different between the region of the semiconductor layer 208 overlapping with the insulating layer 106 and the region not overlapping with the insulating layer 106. For example, when forming the openings 147a and 147b, sometimes a part of the semiconductor layer 208 is removed, and the thickness of the region of the semiconductor layer 208 not overlapping with the insulating layer 106 is smaller than the thickness of the region overlapping with the insulating layer 106. Alternatively, the thickness may also be different between the region of the semiconductor layer 208 overlapping with any one of the insulating layer 106, the conductive layer 212a, and the conductive layer 212b and the region not overlapping with any one of them. For example, when forming the conductive layer 212a and the conductive layer 212b, sometimes a part of the semiconductor layer 208 is removed, and the thickness of the region of the semiconductor layer 208 not overlapping with any one of the insulating layer 106, the conductive layer 212a, and the conductive layer 212b is smaller than the thickness of the region overlapping with any one of them. Alternatively, the thickness may also be different between the region of the semiconductor layer 208 overlapping with the insulating layer 106, the region overlapping with any one of the insulating layer 106, the conductive layer 212a, and the conductive layer 212b, and the region not overlapping with any one of them.

[0174] In the semiconductor layer 208, the region 208D is a region where the resistance is lower than that of the channel formation region. The region 208D can be said to be a region with a higher carrier concentration, a higher oxygen vacancy density, or a higher impurity concentration compared to the channel formation region.

[0175] The region 208L is a region where the resistance is equal to or lower than that of the channel formation region. The region 208L can also be said to be a region with an equal or higher carrier concentration, an equal or higher oxygen vacancy density, or an equal or higher impurity concentration compared to the channel formation region. And, the region 208L is a region where the resistance is equal to or higher than that of the region 208D. The region 208L can also be said to be a region with an equal or lower carrier concentration, an equal or lower oxygen vacancy density, or an equal or lower impurity concentration compared to the region 208D.

[0176] The region 208L is used as a buffer region for alleviating the drain electric field. Since the region 208L does not overlap with the conductive layer 204, almost no channel is formed when a gate voltage is supplied to the conductive layer 204. The carrier concentration in the region 208L is preferably higher than that in the channel formation region. Thus, the region 208L can be used as an LDD (Lightly Doped Drain) region. By providing the region 208L serving as an LDD region between the channel formation region and the region 208D, a transistor 200 with high drain breakdown voltage can be realized.

[0177] In addition, the carrier concentration of the semiconductor layer 208 preferably has the following distribution: the lowest in the channel formation region, and increasing in order of the region 208L and the region 208D. By providing the region 208L between the channel formation region and the region 208D, for example, even if impurities such as hydrogen diffuse from the region 208D in the manufacturing process, the carrier concentration in the channel formation region can be maintained extremely low.

[0178] Note that the carrier concentration in the region 208L may also be non-uniform, and sometimes has a gradient that is lower on the side closer to the channel formation region from the side of the region 208D. For example, it may also have a gradient in which one or both of the hydrogen concentration and the oxygen vacancy concentration in the region 208L are lower on the side closer to the channel formation region from the side of the region 208D.

[0179] As Figure 5A and Figure 5B shown, the ends of a part of the conductive layer 212a and the conductive layer 212b are preferably located inside the openings 147a and 147b. In other words, in the openings 147a and 147b, the ends of a part of the conductive layer 212a and the conductive layer 212b are preferably in contact with the semiconductor layer 208. Thereby, the region in contact with the conductive layer 212a can be adjacent to one of the pair of regions 208D, and similarly, the region in contact with the conductive layer 212b can be adjacent to the other of the pair of regions 208D.

[0180] Note that there is no particular limitation on the top surface shape of the openings 147a and 147b. The top surface shape of the openings 147a and 147b can be the shape that can be used for the openings 141 and 143. Figure 5A etc. show that the top surface shape of the openings 147a and 147b is different from the top surface shape of the openings 141 and 143, that is, a quadrangular shape with rounded corners, but one embodiment of the present invention is not limited thereto. The top surface shape of the openings 147a and 147b can also be the same as the top surface shape of the openings 141 and 143.

[0181] When adding impurity elements to the semiconductor layer 208 to form the region 208L and the region 208D, the conductive layer 104 can also be used as a mask and the impurity elements can be supplied to the semiconductor layer 108 through the insulating layer 106. Thus, the region 108L is formed in the region of the semiconductor layer 108 that does not overlap with the conductive layer 104. Note that in the transistor 100, the region of the semiconductor layer 108 that contacts the conductive layer 112b is used as a source region or a drain region. The region 108L is formed in a part of the source region or the drain region. Note that the impurity element concentration of the region 108L can also be different from that of the region 208L. Additionally, the region 108L may not be formed. For example, when the conductive layer 104 extends and covers the end of the semiconductor layer 108, the entire semiconductor layer 108 is covered by the conductive layer 104, so the semiconductor layer 108 is not supplied with impurity elements and the region 108L is not formed.

[0182] Additionally, a structure is shown here in which the conductive layer 212a and the conductive layer 212b are formed by the same process as the conductive layer 204, but one aspect of the present invention is not limited thereto. The conductive layer 212a and the conductive layer 212b can also be formed by a process different from that of the conductive layer 204. For example, the conductive layer 104 and the conductive layer 204 are formed on the insulating layer 106, and the conductive layer 204 is used as a mask to supply impurity elements to the semiconductor layer 208, thereby forming a source region and a drain region. An insulating layer 195 can be formed on the conductive layer 104 and the conductive layer 204, and openings reaching the source region and openings reaching the drain region are formed in the insulating layer 106 and the insulating layer 195, and the conductive layer 212a and the conductive layer 212b are formed so as to cover these openings.

[0183] [Semiconductor layer 108 and semiconductor layer 208] The metal oxides that can be used for the semiconductor layer 108 and the semiconductor layer 208 will be specifically described. As the metal oxides, for example, indium oxide, gallium oxide, and zinc oxide can be cited. The metal oxide preferably contains at least indium or zinc. In addition, the metal oxide preferably contains two or three selected from indium, element M, and zinc. Element M is a metal element or a semi-metal element with a high bond energy with oxygen, for example, a metal element or a semi-metal element with a higher bond energy with oxygen than indium. As element M, specifically, aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony, etc. can be cited. The element M contained in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and further preferably one or more of gallium and tin. Note that in this specification, etc., metal elements and semi-metal elements are sometimes collectively referred to as "metal elements", and the "metal elements" described in this specification, etc., sometimes include semi-metal elements.

[0184] The semiconductor layer 108 and the semiconductor layer 208 can be made of, for example, indium zinc oxide (also referred to as In-Zn oxide or IZO (registered trademark)), indium tin oxide (also referred to as In-Sn oxide or ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium tungsten oxide (also referred to as In-W oxide or IWO), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (also referred to as In-Ga-Sn oxide or IGTO), gallium zinc oxide (also referred to as Ga-Zn oxide or GZO), aluminum zinc oxide (also referred to as Al-Zn oxide or AZO), indium aluminum zinc oxide (also referred to as In-Al-Zn oxide or IAZO), indium tin zinc oxide (also referred to as In-Sn-Zn oxide or ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (also referred to as In-Ga-Zn oxide or IGZO), indium gallium tin zinc oxide (also referred to as In-Ga-Sn-Zn oxide or IGZTO), indium gallium aluminum zinc oxide (also referred to as In-Ga-Al-Zn oxide, IGAZO, IGZAO or IAGZO), etc. Alternatively, indium tin oxide containing silicon (also referred to as ITSO), gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. can be used.

[0185] When the proportion of the number of indium atoms to the sum of the number of atoms of all metal elements in the metal oxide is increased, the field-effect mobility of the transistor can be increased. In addition, a transistor with a large on-state current can be realized.

[0186] Note that the metal oxide can also replace indium or contain one or more metal elements in a large period number of the periodic table in addition to indium. There is a tendency that the larger the orbital overlap of the metal elements, the greater the carrier conduction in the metal oxide. Therefore, by including metal elements in a large period number, the field-effect mobility of the transistor can sometimes be increased. Examples of metal elements in a large period number include metal elements belonging to the 5th period and metal elements belonging to the 6th period. Specifically, as the metal element, yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium can be cited. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0187] The metal oxide can also contain one or more non-metal elements. When the metal oxide contains non-metal elements, sometimes the carrier concentration increases or the band gap becomes narrow, etc., and the field-effect mobility of the transistor can be increased. Examples of non-metal elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0188] When the ratio of the number of zinc atoms to the sum of the number of atoms of all metal elements in the metal oxide is increased, the metal oxide has high crystallinity, and diffusion of impurities in the metal oxide can be suppressed. Therefore, variations in the electrical characteristics of the transistor are suppressed, and reliability can be improved.

[0189] When the ratio of the number of atoms of element M to the sum of the number of atoms of all metal elements in the metal oxide is increased, formation of oxygen vacancies (V O ) in the metal oxide can be suppressed. Therefore, generation of carriers due to the oxygen vacancies (V O ) is suppressed, and a transistor with a small off-state current can be formed. In addition, variations in the electrical characteristics of the transistor are suppressed, and reliability can be improved.

[0190] The electrical characteristics and reliability of the transistor differ depending on the composition of the metal oxide used for the semiconductor layer 108 and the semiconductor layer 208. Therefore, by varying the composition of the metal oxide according to the required electrical characteristics and reliability of the transistor, a semiconductor device having both excellent electrical characteristics and high reliability can be realized.

[0191] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of element M. Examples of the atomic ratios of the metal elements in such an In-M-Zn oxide include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 6:1:6, In:M:Zn = 10:1:1, In:M:Zn = 10:1:3, In:M:Zn = 10:1:4, In:M:Zn = 10:1:6, In:M:Zn = 10:1:7, In:M:Zn = 10:1:8, In:M:Zn = 5:2:5, In:M:Zn = 10:1:10, In:M:Zn = 20:1:10, In:M:Zn = 40:1:10, and compositions in the vicinity thereof. In addition, the vicinity of the composition includes a range of ±30% of the desired atomic ratio. By increasing the atomic ratio of indium in the metal oxide, the on-state current or field-effect mobility of the transistor can be increased.

[0192] The atomic ratio of In in the In-M-Zn oxide may also be less than the atomic ratio of element M. As the atomic ratio of the metal elements in such an In-M-Zn oxide, for example, In:M:Zn = 1:3:2, In:M:Zn = 1:3:3, In:M:Zn = 1:3:4, and compositions in the vicinity thereof can be cited. By increasing the proportion of the atomic number of M in the metal oxide, the generation of oxygen vacancies (V O ) can be suppressed.

[0193] Note that when multiple metal elements are included as element M, the total of the atomic ratios of these metal elements can be the atomic ratio of element M.

[0194] In this specification and the like, the atomic ratio of indium to the sum of the atomic numbers of all the contained metal elements is sometimes referred to as the indium content rate. The same applies to other metal elements.

[0195] By using a material with a high indium content rate for the semiconductor layer 108 and the semiconductor layer 208, the on-state current or field-effect mobility of the transistor can be improved. Also, by including element M, the generation of oxygen vacancies (V O ) can be suppressed. The content rate of element M (the ratio of the atomic number of element M to the sum of the atomic numbers of all the contained metal elements) is preferably 0.1% or more and 3% or less, more preferably 0.1% or more and 2% or less. Thereby, a transistor with good electrical characteristics can be achieved. For example, it is preferable to use a metal oxide such as In:M:Zn = 40:1:10 and its vicinity. Element M is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium. Specifically, a metal oxide such as In:Sn:Zn = 40:1:10 and its vicinity can be appropriately used. Alternatively, a metal oxide such as In:Al:Zn = 40:1:10 and its vicinity can be appropriately used.

[0196] Here, when a polycrystalline metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208, grain boundaries become recombination centers and capture carriers, so that the on-state current of the transistor sometimes becomes small. When using a metal oxide having a composition that easily becomes a polycrystalline structure, it is preferable to include an element that inhibits crystallization. For example, indium tin oxide containing silicon (ITSO) is less likely to become a polycrystalline structure than indium tin oxide (ITO), so it can be suitably used for the semiconductor layer 108 and the semiconductor layer 208. When using ITSO, the content rate of silicon (the ratio of the number of silicon atoms to the sum of the number of atoms of all metal elements contained) is preferably 1% or more and 20% or less, more preferably 3% or more and 20% or less, more preferably 3% or more and 15% or less, and more preferably 5% or more and 15% or less. Specifically, metal oxides such as In:Sn:Si = 45:5:4, In:Sn:Si = 95:5:8 and those near them can be suitably used.

[0197] In the compositional analysis of the semiconductor layer 108 and the semiconductor layer 208, for example, energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectrometry (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES) can be used. Alternatively, multiple of the above methods can be combined for analysis. Note that elements with a low content rate are sometimes affected by the analysis accuracy, and the actual content rate is different from the content rate obtained by analysis. For example, when the content rate of element M is low, the content rate of element M obtained by analysis is sometimes lower than the actual content rate, is difficult to quantify, or is below the detection limit.

[0198] The metal oxide can be suitably formed by a sputtering method or an atomic layer deposition (ALD) method. Note that when the metal oxide is formed by the sputtering method, the composition of the formed metal oxide is sometimes different from the composition of the sputtering target. In particular, the content rate of zinc in the formed metal oxide sometimes decreases to about 50% of the sputtering target.

[0199] The semiconductor layer 108 and the semiconductor layer 208 may also have a stacked structure including two or more metal oxide layers. The compositions of the two or more metal oxide layers included in the semiconductor layer 108 and the semiconductor layer 208 may be the same or substantially the same as each other. By adopting a stacked structure of metal oxide layers having the same composition, for example, it can be formed using the same sputtering target, so that the manufacturing cost can be reduced.

[0200] The compositions of the two or more metal oxide layers included in the semiconductor layer 108 and the semiconductor layer 208 may also be different from each other. For example, a stacked structure of a first metal oxide layer having a composition of In:M:Zn = 1:3:4 [atomic ratio] or near it and a second metal oxide layer having a composition of In:M:Zn = 1:1:1 [atomic ratio] or near it provided on the first metal oxide layer may be appropriately used. In addition, gallium, aluminum, or tin is particularly preferably used as the element M. The element M in the first metal oxide layer and the second metal oxide layer may be the same or different from each other. For example, the first metal oxide layer and the second metal oxide layer may also be IGZO layers having different compositions from each other.

[0201] For example, a stacked structure of a first metal oxide layer having a composition of In:Zn = 4:1 [atomic ratio] or near it and a second metal oxide layer having a composition of In:M:Zn = 1:1:1 [atomic ratio] or near it provided on the first metal oxide layer may be appropriately used.

[0202] For example, a stacked structure selected from any one of indium oxide, indium gallium oxide, and IGZO and any one of IAZO, IAGZO, and ITZO (registered trademark) may be used.

[0203] In addition, in the case of adopting a stacked structure of a first metal oxide layer containing a first metal oxide and a second metal oxide layer containing a second metal oxide and the composition of the first metal oxide is the same or substantially the same as the composition of the second metal oxide, sometimes the boundary (interface) between the first metal oxide layer and the second metal oxide layer cannot be clearly confirmed.

[0204] The semiconductor layer 108 and the semiconductor layer 208 preferably use a crystalline metal oxide. As the structure of the crystalline metal oxide, for example, a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, and a microcrystalline (nc: nano-crystal) structure can be cited. By using a crystalline metal oxide for the semiconductor layer 108 and the semiconductor layer 208, the density of defect states in the semiconductor layer 108 and the semiconductor layer 208 can be reduced, and thus a highly reliable semiconductor device can be realized.

[0205] The semiconductor layer 108 and the semiconductor layer 208 preferably use CAAC-OS or nc-OS.

[0206] CAAC-OS has a plurality of layered crystals. The c-axis of the crystal is oriented in the normal direction of the formation surface. The semiconductor layer 108 and the semiconductor layer 208 preferably each have layered crystals parallel to or substantially parallel to the formation surface. For example, the semiconductor layer 108 preferably has layered crystals parallel to or substantially parallel to the top surface in the region in contact with the top surface of the conductive layer 112b, and has layered crystals parallel to or substantially parallel to the side surface in the region in contact with the side surface of the conductive layer 112b. In particular, the semiconductor layer 108 preferably has layered crystals parallel to or substantially parallel to the side surface of the insulating layer 110 as the formation surface in the opening 141. By adopting such a structure, the layered crystals of the semiconductor layer 108 are substantially parallel to the channel length direction of the transistor 100, so that the on-state current of the transistor can be increased. Similarly, the semiconductor layer 208 preferably has layered crystals parallel to or substantially parallel to the formation surface (here, the top surface and the side surface of the insulating layer 120 and the top surface of the insulating layer 110). In particular, the semiconductor layer 208 preferably has layered crystals parallel to or substantially parallel to the top surface of the insulating layer 120 as the formation surface in the region overlapping with the conductive layer 204.

[0207] By using a metal oxide with high crystallinity for the channel formation region, the density of defect states in the channel formation region can be reduced. On the other hand, by using a metal oxide with low crystallinity, a transistor capable of flowing a large current can be realized.

[0208] The higher the substrate temperature during the formation of the metal oxide, the higher the crystallinity of the metal oxide that can be formed. The substrate temperature during formation can be adjusted, for example, according to the temperature of the stage on which the substrate is placed during formation. In addition, the higher the flow ratio of oxygen gas to the total deposition gas used during formation (hereinafter, also referred to as the oxygen flow ratio) or the oxygen partial pressure in the processing chamber, the higher the crystallinity of the metal oxide that can be formed.

[0209] The crystallinity of the semiconductor layer 108 and the semiconductor layer 208 can be analyzed, for example, by X-ray diffraction (XRD: X-Ray Diffraction), transmission electron microscope (TEM: Transmission Electron Microscope), or electron diffraction (ED: Electron Diffraction). Alternatively, multiple of the above methods can also be combined for analysis.

[0210] When using a metal oxide for the semiconductor layer 108 and the semiconductor layer 208, it is preferable to minimize V O H to make it highly pure intrinsic or substantially highly pure intrinsic. Thus, in order to obtain VO Metal oxides with sufficiently reduced H. Importantly, impurities such as water and hydrogen in the metal oxides are removed (sometimes referred to as dehydration and dehydrogenation treatment); and oxygen is supplied to the metal oxides to repair oxygen vacancies (V O ). By using metal oxides with sufficiently reduced impurities such as V O H in the channel formation region of a transistor, stable electrical characteristics can be imparted. Note that the treatment of supplying oxygen to the metal oxides to repair oxygen vacancies (V O ) is sometimes referred to as oxidation treatment.

[0211] When using a metal oxide for the semiconductor layer 108 and the semiconductor layer 208, it is preferable that the carrier concentration in the channel formation region is 1×10 18 cm -3 or less, more preferably less than 1×10 17 cm -3 , further preferably less than 1×10 16 cm -3 , even more preferably less than 1×10 13 cm -3 , further preferably less than 1×10 12 cm -3 . There is no limitation on the lower limit value of the carrier concentration in the channel formation region. For example, it can be set to 1×10 -9 cm -3 .

[0212] The OS transistor has small electrical characteristic variations caused by being irradiated with radiation, that is, it has high tolerance to radiation. Therefore, it can be appropriately used in an environment where radiation may be incident. The OS transistor can also be said to have high reliability for radiation. For example, the OS transistor can be appropriately used for the pixel circuit of an X-ray flat panel detector. In addition, the OS transistor can be appropriately used for semiconductor devices used in outer space. As radiation, electromagnetic radiation (e.g., X-rays and γ-rays) and particle radiation (e.g., α-rays, β-rays, proton radiation, and neutron radiation) can be cited.

[0213] The semiconductor layer 108 and the semiconductor layer 208 may also contain a layered material used as a semiconductor. The layered material is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked by bonds weaker than covalent bonds and ionic bonds such as van der Waals bonds. The layered material has high conductivity in the unit layer, that is, it has high two-dimensional conductivity. By using a material used as a semiconductor and having high two-dimensional conductivity for the channel formation region, a transistor with a large on-state current can be provided.

[0214] As the above-mentioned layered materials, for example, graphene, silicene, chalcogenides, etc. can be cited. Chalcogenides are compounds containing chalcogen elements (belonging to Group 16 elements). In addition, as chalcogenides, transition metal chalcogenides, Group 13 chalcogenides, etc. can be cited. As transition metal chalcogenides that can be used as the channel formation region of a transistor, specifically, molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), zirconium selenide (typically ZrSe2), etc. can be cited.

[0215] [Conductive layer 112a, conductive layer 112b, conductive layer 104, conductive layer 204, conductive layer 212a, conductive layer 212b, conductive layer 202] The conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a, the conductive layer 212b, and the conductive layer 202 can each have a single-layer structure or a stacked structure of two or more layers. As materials that can be used for the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a, the conductive layer 212b, and the conductive layer 202, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, and alloys containing one or more of the above metals as components can be cited. A low-resistance conductive material containing one or more of copper, silver, gold, and aluminum can be appropriately used for the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a, the conductive layer 212b, and the conductive layer 202. In particular, copper or aluminum has an advantage in mass productivity and is therefore preferred.

[0216] The conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a, the conductive layer 212b, and the conductive layer 202 can use a conductive metal oxide (oxide conductor). As the oxide conductor (OC: Oxide Conductor), for example, indium oxide, zinc oxide, In-Sn oxide (ITO), In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide (also called ITO containing silicon or ITSO), zinc oxide added with gallium, and In-Ga-Zn oxide can be cited. In particular, a metal oxide containing indium is preferably used because of its high conductivity.

[0217] For example, oxygen vacancies are formed in a metal oxide having semiconductor characteristics, and hydrogen is added to the oxygen vacancies to form donor energy levels near the conduction band. As a result, the conductivity of the metal oxide increases, and it becomes a conductor. The metal oxide that has become a conductor may be referred to as an oxide conductor.

[0218] As the conductive layers 112a, 112b, 104, 204, 212a, 212b, and 202, a stacked structure of a conductive film containing the above-described oxide conductor (metal oxide) and a conductive film containing a metal or an alloy may also be employed. By using a conductive film containing a metal or an alloy, the wiring resistance can be reduced.

[0219] As the conductive layers 112a, 112b, 104, 204, 212a, 212b, and 202, a Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may also be applied. By using a Cu-X alloy film, processing can be performed by a wet etching method, and thus the manufacturing cost can be reduced.

[0220] Note that the materials for the conductive layers 112a, 112b, 104, 204, 212a, 212b, and 202 may be the same or different.

[0221] The conductive layers 112a and 112b have regions in contact with the semiconductor layer 108. When a metal oxide is used as the semiconductor layer 108, there is a concern that when a metal that is easily oxidized (for example, aluminum) is used as the conductive layers 112a and 112b, an insulating oxide (for example, aluminum oxide) is formed between the conductive layer 112a and the semiconductor layer 108 and between the conductive layer 112b and the semiconductor layer 108, hindering their conduction. Therefore, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains a low resistance even when oxidized, or an oxide conductor for the conductive layers 112a and 112b.

[0222] As the conductive layers 112a and 112b, for example, titanium, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel are preferably used. Since these materials are conductive materials that are not easily oxidized or materials that maintain a low resistance even when oxidized, they are preferable. Note that when the conductive layer 112a has a stacked structure, at least the layer in contact with the semiconductor layer 108 is preferably made of a conductive material that is not easily oxidized. The same applies to the conductive layer 112b.

[0223] The conductive layer 112a and the conductive layer 112b can use the above-mentioned oxide conductors. Specifically, metal oxides such as indium oxide, zinc oxide, ITO, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn oxide containing silicon, or zinc oxide added with gallium can be used.

[0224] The conductive layer 112a and the conductive layer 112b can also use nitride conductors. Examples of nitride conductors include tantalum nitride and titanium nitride.

[0225] Here, in the capacitor element 150, the conductive layer 112b is provided on the insulating layer 120b. As described above, the conductive layer 112b preferably uses a conductive material that is not easily oxidized, a conductive material that maintains a low resistance even when oxidized, or an oxide conductor. And the amount of oxygen released from the insulating layer 120b is less than the amount of oxygen released from the insulating layer 110b. Therefore, the possibility that the conductive layer 112b in the region in contact with the insulating layer 120b is oxidized and the resistance of the conductive layer 112b becomes high is very low.

[0226] The conductive layer 112a, the conductive layer 112b, and the conductive layer 104 can also have a stacked structure. In Figure 6A and Figure 6B the conductive layer 112a has a stacked structure of a conductive layer 112a_1 and a conductive layer 112a_2 on the conductive layer 112a_1.

[0227] The conductive layer 112a_2 in the region in contact with the semiconductor layer 108 preferably uses a conductive material that is not easily oxidized, a conductive material that maintains a low resistance even when oxidized, or an oxide conductor. The materials that can be used for the conductive layer 112a_2 can refer to the description of the conductive layer 112a.

[0228] The conductive layer 112a_1 does not have a region in contact with the semiconductor layer 108, so there is no particular limitation on the material used. For example, the conductive layer 112a_1 preferably uses a material with a lower resistivity than the conductive layer 112a_2. Thereby, the resistance of the conductive layer 112a can be reduced. For example, the conductive layer 112a_2 can appropriately use In-Sn-Si oxide (ITSO), and the conductive layer 112a_1 can appropriately use copper or tungsten.

[0229] In addition, Figure 6A and Figure 6BA structure is shown in which the thickness of the conductive layer 112a_1 is the same as or substantially the same as the thickness of the conductive layer 112a_2. However, one aspect of the present invention is not limited to this. The thickness of the conductive layer 112a_1 and the thickness of the conductive layer 112a_2 may also be different. For example, a material having a resistivity lower than that of the conductive layer 112a_2 may be used for the conductive layer 112a_1 and the thickness of the conductive layer 112a_1 may be made larger than the thickness of the conductive layer 112a_2. Thereby, the resistance of the conductive layer 112a can be reduced.

[0230] As Figure 6A shown, the end of the conductive layer 112a_2 may also be aligned or substantially aligned with the end of the conductive layer 112a_1. For example, by forming a first film that will become the conductive layer 112a_1 and a second film that will become the conductive layer 112a_2 and processing the first film and the second film, the conductive layer 112a can be formed.

[0231] The end of the conductive layer 112a_2 may also not be aligned with the end of the conductive layer 112a_1. As Figure 6B shown, the conductive layer 112a_2 may be provided so as to cover the conductive layer 112a_1. The conductive layer 112a_2 is in contact with the top surface and the side surface of the conductive layer 112a_1. It can also be said that the conductive layer 112a_2 has a portion that protrudes beyond the end of the conductive layer 112a_1. For example, the conductive layer 112a_1 can be formed, a film that will become the conductive layer 112a_2 can be formed on the conductive layer 112a_1, and the film can be processed to form the conductive layer 112a_2.

[0232] Note that the structure of the conductive layer 112a shown in Figure 6A and Figure 6B can be used in other structural examples.

[0233] [Insulating layer 106] The insulating layer 106 may have a single-layer structure or a laminated structure of two or more layers. The insulating layer 106 preferably includes one or more inorganic insulating films. As materials that can be used for the inorganic insulating film, for example, oxides, nitrides, oxynitrides, and nitrogen oxides can be cited. The insulating layer 106 can use the materials that can be used for the insulating layer 110.

[0234] The insulating layer 106 has regions in contact with the semiconductor layer 108 and the semiconductor layer 208. When the semiconductor layer 108 and the semiconductor layer 208 use metal oxides, at least the film in the film constituting the insulating layer 106 that is in contact with the semiconductor layer 108 and the semiconductor layer 208 preferably uses any one of the above-mentioned oxides and oxynitrides. In addition, the insulating layer 106 more preferably uses a film that releases oxygen by heating.

[0235] Specifically, when the insulating layer 106 has a single-layer structure, the insulating layer 106 preferably uses an oxide or an oxynitride. Specifically, the insulating layer 106 may appropriately use silicon oxide or silicon oxynitride.

[0236] When the insulating layer 106 has a stacked structure, preferably, the insulating film on the side in contact with the semiconductor layer 108 and the semiconductor layer 208 contains an oxide or an oxynitride, and the insulating film on the side in contact with the conductive layer 104 and the conductive layer 204 contains a nitride or a nitrogen oxide. As such an oxide or oxynitride, for example, silicon oxide or silicon oxynitride can be appropriately used. As such a nitride or nitrogen oxide, silicon nitride or silicon oxynitride can be appropriately used.

[0237] Silicon nitride and silicon oxynitride have the characteristics of releasing very little amount of impurities (such as water and hydrogen) by themselves and being not easily permeable to oxygen and hydrogen. Therefore, they can be appropriately used as the insulating layer 106. Since the diffusion of impurities from the insulating layer 106 to the semiconductor layer 108 and the semiconductor layer 208 is suppressed, good electrical characteristics of the transistor can be achieved and the reliability can be improved.

[0238] Note that in a micro transistor, when the thickness of the gate insulating layer is small, the leakage current sometimes increases. By using a material with a relatively high relative dielectric constant (also called a high-k material) for the gate insulating layer, it is possible to achieve low voltage operation of the transistor while maintaining the physical thickness. As high-k materials that can be used for the insulating layer 106, for example, gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium can be cited.

[0239] [Insulating layer 195] The insulating layer 195 used as a protective layer for the transistor 100, the transistor 200, and the capacitor element 150 preferably uses a material in which impurities are not easily diffused. By providing the insulating layer 195, it is possible to effectively suppress the diffusion of impurities from the outside into the transistor, thereby improving the reliability of the semiconductor device. Examples of impurities include water and hydrogen.

[0240] The insulating layer 195 may be an insulating layer containing an inorganic material or an insulating layer containing an organic material. The insulating layer 195 can, for example, appropriately use an inorganic material such as an oxide, an oxynitride, a nitrogen oxide, or a nitride. More specifically, one or more of silicon nitride, silicon oxynitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used. As organic materials, for example, one or more of acrylic resin and polyimide resin can be used. A photosensitive material can also be used as an organic material. In addition, two or more of the above insulating films can be laminated. The insulating layer 195 may also have a stacked structure including an insulating layer containing an inorganic material and an insulating layer containing an organic material.

[0241] [Substrate 102] Although there is no particular limitation on the material of the substrate 102, it is at least required to have heat resistance capable of withstanding subsequent heat treatment. For example, a single-crystalline semiconductor substrate or a polycrystalline semiconductor substrate made of silicon or silicon carbide, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or an organic resin substrate can be used as the substrate 102. In addition, semiconductor elements may be provided on the substrate 102. Note that the shapes of the semiconductor substrate and the insulating substrate may be circular or angular.

[0242] As the substrate 102, a flexible substrate can also be used, and transistors 100, etc. can be directly formed on the flexible substrate. Alternatively, a release layer may be provided between the substrate 102 and the transistors 100, etc. By providing the release layer, after manufacturing a part or all of the semiconductor device on the release layer, it can be separated from the substrate 102 and transferred to another substrate. At this time, the transistors 100, etc. can also be transferred to a substrate with low heat resistance or a flexible substrate.

[0243] Next, a structural example in which a part of the structure is different from the above structural example 1 will be described. Hereinafter, the description of the parts overlapping with the above structural example 1 may be omitted. In addition, in the following drawings, the same hatching is used for the parts having the same functions as those in the above structural example 1, and sometimes no reference numerals are attached.

[0244] <Structural Example 2> Figure 7A is a top view of a semiconductor device 10A according to an aspect of the present invention. Figure 7B is along Figure 7A the cross-sectional view of the cross-section along the dotted line A1 - A2 shown. The cross-sectional view along the dotted line B1 - B2 can be referred to Figure 1C .

[0245] The semiconductor device 10A includes a transistor 100, a transistor 200A, a capacitor element 150, and an insulating layer 110. The main difference between the transistor 200A and the transistor 100 shown, etc. is that the side surface of the insulating layer 120 does not contact the semiconductor layer 208. Figure 1C The insulating layer 120 is provided over the entire region where the semiconductor layer 208 is provided, and the bottom surface of the semiconductor layer 208 is in contact with the top surface of the insulating layer 120 as a whole. Thereby, the step of the formed surface of the semiconductor layer 208 becomes smaller, and the coverage of the semiconductor layer 208 can be improved.

[0246] Note that the structure of the insulating layer 120 shown in Structural Example 2 can be used for other structural examples.

[0247] Note that the structure of the insulating layer 120 shown in Structural Example 2 can be used for other structural examples.

[0248] <Structural Example 3> Figure 8A It is a top view of the semiconductor device 10B according to one embodiment of the present invention. Figure 8B It is along Figure 8A The cross-sectional view of the cross-section along the dotted line A1 - A2 shown, Figure 8C It is the cross-sectional view of the cross-section along the dotted line B1 - B2.

[0249] The semiconductor device 10B includes a transistor 100, a transistor 200B, a capacitor element 150A, and an insulating layer 110. The main difference between the transistor 200B and Figure 1C the transistor 200 shown, etc. is that the conductive layer 202 is provided between the insulating layer 110 and the substrate 102. The main difference between the capacitor element 150A and the capacitor element 150 is that the insulating layer 110 is included instead of the insulating layer 120.

[0250] The conductive layer 202 is provided on the substrate 102. The conductive layer 202 can be formed by the same process as the conductive layer 112a. For example, by forming a film that will become the conductive layer 202 and the conductive layer 112a and processing this film, the conductive layer 202 and the conductive layer 112a can be formed. By forming the conductive layer 202 and the conductive layer 112a by the same process, the productivity of the semiconductor device 10B can be improved and the manufacturing cost can be reduced.

[0251] In the transistor 200B, a part of the insulating layer 110 and the insulating layer 120 is used as a back gate insulating layer (second gate insulating layer).

[0252] The capacitor element 150A includes a conductive layer 112b and a conductive layer 202 serving as a pair of electrodes and the insulating layer 110 sandwiched therebetween. Note that although Figure 8C the structure in which the insulating layer 120 is not provided between the conductive layer 112a and the insulating layer 110 is shown, etc., one embodiment of the present invention is not limited thereto, and the insulating layer 120 may be provided between the conductive layer 112a and the insulating layer 110, and the insulating layer 110 and the insulating layer 120 may also be used as the dielectric of the capacitor element 150A.

[0253] Note that the structure of the conductive layer 202 shown in Structural Example 3 can be used for other structural examples.

[0254] <Structural Example 4> Figure 9A It is a top view of the semiconductor device 10C according to one embodiment of the present invention. Figure 9B It is along Figure 9A The cross-sectional view of the cross-section along the dotted line A1 - A2 shown, Figure 9C It is the cross-sectional view of the cross-section along the dotted line B1 - B2.

[0255] The semiconductor device 10C includes a transistor 100, a transistor 200, a capacitor element 150B, and an insulating layer 110. The capacitor element 150B is mainly different from the capacitor element 150 shown in Figure 1C etc. in that it includes a conductive layer 112a instead of the conductive layer 112b and includes an insulating layer 110 instead of the insulating layer 120.

[0256] The capacitor element 150B includes a conductive layer 112a and a conductive layer 202 serving as a pair of electrodes, and an insulating layer 110 sandwiched therebetween. The conductive layer 112a is used as one of the source electrode and the drain electrode of the transistor 100, and is also used as one of the pair of electrodes of the capacitor element 150.

[0257] The conductive layer 202 can also be formed using the same material and process as the conductive layer 112b. In Figure 10A and Figure 10B the same hatching is attached to the conductive layer 202 and the conductive layer 112b. For example, by forming a film that will become the conductive layer 202 and the conductive layer 112b on the insulating layer 110 and processing the film, the conductive layer 202 and the conductive layer 112b can be formed. By forming the conductive layer 202 and the conductive layer 112b in the same process, the productivity of the semiconductor device 10C can be improved and the manufacturing cost can be reduced.

[0258] Note that the structure of the capacitor element 150B shown in Structural Example 4 can be used for other structural examples.

[0259] <Structural Example 5> Figure 11A and Figure 11B are cross-sectional views of a semiconductor device 10D according to an aspect of the present invention. A top view of the semiconductor device 10D can be referred to Figure 1A . Figure 11A is a cross-sectional view of a cross-section along the dotted line A1 - A2 shown in Figure 1A , Figure 11B is a cross-sectional view of a cross-section along the dotted line B1 - B2 shown in Figure 1A .

[0260] The semiconductor device 10D is mainly different from the semiconductor device 10 shown in Figure 1B etc. in that it includes an insulating layer 110d and an insulating layer 110e.

[0261] Figure 11C shows Figure 11AAn enlarged view of the transistor 100 and its vicinity. The insulating layer 110 includes an insulating layer 110d between the conductive layer 112a and the insulating layer 110a, and includes an insulating layer 110e between the conductive layer 112b and the insulating layer 110c. The insulating layer 110d and the insulating layer 110e can use the materials that can be used for the insulating layer 110a and the insulating layer 110c. For example, the insulating layer 110d and the insulating layer 110e can appropriately use silicon nitride or silicon oxynitride.

[0262] When a material that releases impurities (such as water and hydrogen) is used for the insulating layer 110d, the region of the semiconductor layer 108 in contact with the insulating layer 110d can be a low-resistance region. The semiconductor layer 108 can have a low-resistance region between the region in contact with the conductive layer 112a (one of the source region and the drain region) and the channel formation region. Similarly, when a material that releases impurities is used for the insulating layer 110e, the region of the semiconductor layer 108 in contact with the insulating layer 110e can be a low-resistance region. The semiconductor layer 108 can have a low-resistance region between the region in contact with the conductive layer 112b (the other of the source region and the drain region) and the channel formation region. The low-resistance region can be used as a buffer region to mitigate the drain electric field. Note that these low-resistance regions can also be used as the source region or the drain region.

[0263] By providing a low-resistance region between the drain region and the channel formation region, a high electric field is not easily generated near the drain region, thereby suppressing the generation of hot carriers, and thus the deterioration of the transistor can be suppressed. For example, when the conductive layer 112a is used as the drain electrode and the conductive layer 112b is used as the source electrode, by using the region of the semiconductor layer 108 in contact with the insulating layer 110d as the low-resistance region, a high electric field is not easily generated near the drain region, thereby suppressing the generation of hot carriers, and thus the deterioration of the transistor can be suppressed. When the conductive layer 112a is used as the source electrode and the conductive layer 112b is used as the drain electrode, by using the region of the semiconductor layer 108 in contact with the insulating layer 110e as the low-resistance region, a high electric field is not easily generated near the drain region, thereby suppressing the generation of hot carriers, and thus the deterioration of the transistor can be suppressed.

[0264] When the region of the semiconductor layer 108 in contact with the insulating layer 110d is used as the source region or the drain region, the distance from the source region of the semiconductor layer 108 to the gate electrode and the distance from the drain region to the gate electrode can be further made uniform. Thereby, the electric field applied to the gate electrode of the channel formation region can be further made uniform.

[0265] The insulating layer 110a located between the insulating layer 110d and the insulating layer 110b preferably releases less impurities from itself and is not easily permeated by impurities. Thereby, the diffusion of impurities through the insulating layer 110a and the insulating layer 110b to the channel formation region of the semiconductor layer 108 and its vicinity can be suppressed, and a transistor with good electrical characteristics and high reliability can be realized.

[0266] The insulating layer 110d preferably includes a region having a higher hydrogen content than the insulating layer 110a. In the analysis of the hydrogen content of the insulating layer 110, for example, secondary ion mass spectrometry (SIMS) can be used.

[0267] By making the deposition conditions of the insulating layer 110d different from those of the insulating layer 110a, the amount of hydrogen released can be adjusted. Specifically, any one or more of the deposition power (deposition power density), deposition pressure, deposition gas type, deposition gas flow ratio, deposition temperature, and distance between the substrate and the electrode during formation may be made different between the insulating layer 110d and the insulating layer 110a. For example, by making the deposition power density of the insulating layer 110d smaller than that of the insulating layer 110a, the hydrogen content in the insulating layer 110d can be made higher than that in the insulating layer 110a. Thereby, the amount of hydrogen released from itself due to the heat applied to the insulating layer 110d can be increased.

[0268] The hydrogen content in the deposition gas used to form the insulating layer 110d is preferably higher than that in the deposition gas used to form the insulating layer 110a. Specifically, when forming a silicon nitride film or a silicon oxynitride film by the PECVD method in each of the insulating layer 110d and the insulating layer 110a, the ratio of the flow rate of ammonia gas to the total deposition gas used to form the insulating layer 110d (hereinafter, also referred to as the ammonia flow ratio) is preferably higher than the ammonia flow ratio of the deposition gas used to form the insulating layer 110a. By forming the insulating layer 110d under the condition of a high ammonia flow ratio, the hydrogen content in the insulating layer 110d can be increased. In addition, the amount of hydrogen released from itself due to the heat applied to the insulating layer 110d can be increased. In addition, ammonia gas can also be used when forming the insulating layer 110d and not used when forming the insulating layer 110a. In particular, when shortening the channel length L100 (for example, 100 nm or less) or when using a material with high conductivity for the semiconductor layer 108, ammonia gas can also be not used when forming the insulating layer 110a. In these cases, when the amount of hydrogen released from the insulating layer 110a increases, the influence on the electrical characteristics is sometimes greater. By not using ammonia gas when forming the insulating layer 110a, the hydrogen amount in the insulating layer 110a can be further reduced, thereby enabling a transistor with good electrical characteristics.

[0269] The film density of the insulating layer 110a is preferably higher than that of the insulating layer 110d. Thereby, it is possible to suppress hydrogen contained in the insulating layer 110d from diffusing through the insulating layer 110a and the insulating layer 110b to the channel formation region of the semiconductor layer 108 and its vicinity. The evaluation of the film density can be performed, for example, by Rutherford Backscattering Spectrometry (RBS) or X-Ray Reflection (XRR). The difference in film density can sometimes be evaluated from the cross-sectional Transmission Electron Microscopy (TEM) image. In TEM observation, when the film density is high, the Transmission Electron (TE) image is dark, and when the film density is low, the TE image is light. Therefore, in the TE image, the insulating layer 110a sometimes appears darker than the insulating layer 110d. Note that even if the insulating layers 110d and 110a are made of the same material, the film densities are different, and thus these boundaries can sometimes be observed with different contrasts in the cross-sectional TEM image.

[0270] The insulating layer 110c located between the insulating layer 110e and the insulating layer 110b preferably releases less impurity from itself and is less likely to allow impurity penetration. Thereby, it is possible to suppress the diffusion of impurities through the insulating layer 110c and the insulating layer 110b to the channel formation region of the semiconductor layer 108 and its vicinity, and a transistor with good electrical characteristics and high reliability can be realized. The film density of the insulating layer 110c is preferably higher than that of the insulating layer 110e. Regarding the insulating layer 110c, reference can be made to the description of the insulating layer 110a, and regarding the insulating layer 110e, reference can be made to the description of the insulating layer 110d.

[0271] In addition, one of the insulating layers 110d and 110e may not be included.

[0272] Note that the structure of the insulating layer 110 shown in Structural Example 5 can be used for other structural examples.

[0273] <Structural Example 6> Figure 12A is a cross-sectional view of a transistor 100A of a semiconductor device that can be used in one embodiment of the present invention. The top view of the transistor 100A can be referred to Figure 1A the transistor 100 shown. Figure 12A is a cross-sectional view of a cross-section along the Figure 1A dash-dotted line A1 - A2 shown.

[0274] The transistor 100A and Figure 1BThe main difference of the transistor 100 as shown is that the thickness of the region of the conductive layer 112a in contact with the bottom surface of the semiconductor layer 108 is different from the thickness of the region not in contact with the semiconductor layer 108.

[0275] As Figure 12A shown, the thickness of the region of the conductive layer 112a in contact with the bottom surface of the semiconductor layer 108 is preferably thinner than the thickness of the region not in contact with the semiconductor layer 108. Figure 12A Shows the height H104 from the formed surface of the conductive layer 112a (here, the top surface of the substrate 102) to the lowest position of the bottom surface of the conductive layer 104. In addition, shows the height H112 from the formed surface of the conductive layer 112a (here, the top surface of the substrate 102) to the highest position in the region where the conductive layer 112a is in contact with the semiconductor layer 108. As Figure 12B shown, the height H104 is preferably the same as or substantially the same as the height H112. Or, as Figure 12B shown, the height H104 is preferably lower than the height H112.

[0276] By making the height H104 from the formed surface of the conductive layer 112a to the lowest position of the bottom surface of the conductive layer 104 equal to or lower than the height H112 from the formed surface of the conductive layer 112a to the highest position in the region where the conductive layer 112a is in contact with the layer 108, the electric field applied to the gate electrode in the channel formation region near the conductive layer 112a can be enhanced, and thus the on-state current of the transistor 100A can be increased. In addition, the electric field applied to the gate electrode in the channel formation region can be made more uniform.

[0277] Here, when the electric field applied to the gate electrode in the channel formation region is not uniform, sometimes the electrical characteristics in the case where the conductive layer 112a is used as the source electrode and the conductive layer 112b is used as the drain electrode are different from the electrical characteristics in the case where the conductive layer 112a is used as the drain electrode and the conductive layer 112b is used as the source electrode. By making the electric field applied to the gate electrode in the channel formation region of the transistor 100A more uniform, the electrical characteristics can be made equal. Therefore, the transistor 100A can be appropriately used in a circuit structure where the source and drain are replaced.

[0278] Note that it is sufficient to appropriately adjust the thickness of the conductive layer 112a so that the height H104 is equal to or lower than the height H112.

[0279] Note that the structure of the conductive layer 112a shown in Structural Example 6 can be used for other structural examples.

[0280] <Structural Example 7> Figure 13A Is a top view of the semiconductor device 10E according to one embodiment of the present invention. Figure 13B Is a cross-sectional view of a cross-section along the Figure 13A indicated dotted line A1 - A2, Figure 13CIt is a sectional view of a cross-section along the dotted line B1 - B2.

[0281] The semiconductor device 10E includes a transistor 100B, a transistor 200, a capacitor element 150, and an insulating layer 110. The main difference between the transistor 100B and Figure 1B the transistor 100 shown, etc. is that it includes a conductive layer 103 and an insulating layer 107 between the conductive layer 112a and the insulating layer 110.

[0282] The insulating layer 107 is located on the conductive layer 112a. The insulating layer 107 is provided so as to cover the top surface and the side surfaces of the conductive layer 112a.

[0283] The conductive layer 103 is located on the insulating layer 107. The conductive layer 112a and the conductive layer 103 are electrically insulated from each other by the insulating layer 107. An opening 148 reaching the insulating layer 107 is provided in the region of the conductive layer 103 overlapping with the conductive layer 112a.

[0284] The insulating layer 110 is provided on the insulating layer 107 and the conductive layer 103. The insulating layer 110 is provided so as to cover the top surface and the side surfaces of the conductive layer 103 and the top surface of the insulating layer 107. An opening 141 reaching the conductive layer 112a is provided in the insulating layer 110 and the insulating layer 107.

[0285] The insulating layer 110a is located on the insulating layer 107 and the conductive layer 103. The insulating layer 110a is provided so as to cover the top surface and the side surfaces of the conductive layer 103. The insulating layer 110a is provided so as to cover a part of the opening 148. The insulating layer 110a is in contact with the insulating layer 107 through the opening 148.

[0286] There is no particular limitation on the top surface shape of the opening 148. The top surface shape of the opening 148 can be a shape usable for the opening 141. As Figure 13A shown, it is preferable that the top surface shapes of both the opening 141 and the opening 148 are circular. By making the top surface shape of the opening circular, the processing accuracy when forming the opening can be improved, and thus a fine opening can be formed.

[0287] In this specification, etc., the top surface shape of the opening 148 refers to the shape of the top surface end or the bottom surface end of the opening 148 side of the conductive layer 103.

[0288] When the top surface shapes of the opening 141 and the opening 148 are circular, the opening 141 and the opening 148 are preferably concentric. Thereby, when viewed from the cross-section, the shortest distances between the semiconductor layer 108 and the conductive layer 103 on both sides of the opening 141 can be made equal. In addition, the opening 141 and the opening 148 are sometimes not concentric.

[0289] In transistor 100B, the semiconductor layer 108 has a region that overlaps with the conductive layer 104 with the insulating layer 106 therebetween and overlaps with the conductive layer 103 with a part of the insulating layer 110 (in particular, the insulating layer 110a and the insulating layer 110b) therebetween. In other words, there is a region in the semiconductor layer 108 that is sandwiched between the conductive layer 104 and the conductive layer 103, where the insulating layer 106 is sandwiched between the semiconductor layer 108 and the conductive layer 104 and a part of the insulating layer 110 (in particular, the insulating layer 110a and the insulating layer 110b) is sandwiched between the semiconductor layer 108 and the conductive layer 103.

[0290] The conductive layer 103 is used as the back gate electrode (or the second gate electrode) of the transistor 100B. In addition, a part of the insulating layer 110 is used as the back gate insulating layer (or the second gate insulating layer) of the transistor 100B. The conductive layer 103 can use the materials that can be used for the conductive layer 112a and the conductive layer 104. Note that the conductive layer 103 may not be provided.

[0291] By providing the back gate electrode in the transistor 100B, the potential of the back gate electrode side (also referred to as the back channel side) of the semiconductor layer 108 can be fixed, and the saturation of the Id-Vd characteristics can be improved.

[0292] Since the transistor 100B includes the back gate electrode, the potential of the back gate electrode side of the semiconductor layer 108 can be fixed, and the drift of the threshold voltage can be suppressed. Here, when the threshold voltage of the transistor drifts, the drain current flowing when the gate voltage is 0V (hereinafter, also referred to as the cut-off current) sometimes becomes large. By suppressing the drift of the threshold voltage, a transistor with a small cut-off current can be realized. Thereby, a semiconductor device with low power consumption can be realized.

[0293] The insulating layer 107 can use the materials that can be used for the insulating layer 110. The insulating layer 107 in contact with the conductive layer 112a and the conductive layer 103 preferably uses a nitrogen-containing insulating layer. The insulating layer 107 can appropriately use the materials that can be used for the insulating layer 110a and the insulating layer 110c. The insulating layer 107 can appropriately use, for example, silicon nitride. Note that in the present embodiment, the insulating layer 107 having a single-layer structure is shown, but one aspect of the present invention is not limited thereto. The insulating layer 107 may also have a laminated structure of two or more layers.

[0294] The conductive layer 103 can also be electrically connected to the conductive layer 112a. For example, by providing an opening in the region of the insulating layer 107 that overlaps with the conductive layer 112a and providing the conductive layer 103 in a manner that covers the opening, a structure in which the conductive layer 103 is in contact with the conductive layer 112a can be obtained. By electrically connecting the conductive layer 112a serving as a source electrode or a drain electrode to the conductive layer 103 serving as a back gate electrode, the source electrode or the drain electrode and the back gate electrode can have the same potential. For example, when the conductive layer 112a is used as a source electrode, the threshold voltage drift of the transistor 100B can be suppressed. In addition, the reliability of the transistor 100B can be improved. Note that the conductive layer 103 that contacts the top surface of the conductive layer 112a can also be formed without providing the insulating layer 107.

[0295] The conductive layer 103 can also be electrically connected to the conductive layer 104. For example, by providing an opening in the regions of the insulating layer 106 and the insulating layer 110 that overlap with the conductive layer 103 and providing the conductive layer 104 in a manner that covers the opening, a structure in which the conductive layer 103 is in contact with the conductive layer 104 can be obtained. By electrically connecting the conductive layer 104 serving as a gate electrode to the conductive layer 103 serving as a back gate electrode, the back gate electrode and the gate electrode can have the same potential, and thus the on-state current of the transistor 100B can be increased.

[0296] The thickness of the conductive layer 103 can also be greater than the thickness T110b of the insulating layer 110. Thereby, the potential on the back gate electrode side of the semiconductor layer 108 can be fixed over a wide range between the source region and the drain region in the semiconductor layer 108.

[0297] The transistor 100B has a region in which the conductive layer 103, the insulating layer 110, the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 are sequentially overlapped in one direction, and no other layers are included therebetween. As this direction, a direction perpendicular to the channel length direction can be cited. By expanding this region, the potential on the back gate electrode side of the semiconductor layer 108 can be more reliably controlled.

[0298] The thickness of the conductive layer 103 can be greater than the sum of the thickness of the portion of the inner side of the opening 141 in the semiconductor layer 108 that contacts the conductive layer 112a and the thickness of the insulating layer 106 that contacts this portion.

[0299] Note that the structure of the conductive layer 103 and the insulating layer 107 shown in Structural Example 7 can be used for other structural examples.

[0300] <Structural Example 8> Figure 14AThe equivalent circuit diagram of the transistor 100C of the semiconductor device that can be used in one embodiment of the present invention is shown. The transistor 100C is a transistor group including transistors 100_1 to 100_p (p is an integer of 2 or more). The transistors 100_1 to 100_p are connected in parallel, and the transistor 100C can be regarded as one transistor.

[0301] The gate electrodes of the transistors 100_1 to 100_p are electrically connected to each other. The source electrodes of the transistors 100_1 to 100_p are electrically connected to each other. The drain electrodes of the transistors 100_1 to 100_p are electrically connected to each other.

[0302] Note that in Figure 14A the transistors 100_1 to 100_p are n-channel transistors, but one embodiment of the present invention is not limited thereto. The transistors 100_1 to 100_p may also be p-channel transistors.

[0303] Taking the case where p is 4 as an example for specific description. Figure 14B The equivalent circuit diagram of the transistor 100C of one embodiment of the present invention is shown. Figure 14C The top view of the transistor 100C is shown. Figure 15 Shown along Figure 14C the cross-sectional view of the cross-section along the dash-dotted line A3 - A4 in Figure 16 The perspective view of the transistor 100C is shown.

[0304] The transistor 100C includes transistors 100_1 to 100_4. Each of the transistors 100_1 to 100_4 can adopt the structure of the above-mentioned transistor 100. Note that the transistor 100 is taken as an example for description here, but one embodiment of the present invention is not limited thereto. Any one of the transistors 100A to 100D may also be adopted as the transistors 100_1 to 100_4.

[0305] Figure 14C etc. show the structure in which the transistors 100_1 to 100_4 are arranged in 2 rows and 2 columns, but there is no particular limitation on the arrangement of the transistors. For example, the transistors 100_1 to 100_4 may also be arranged in 1 row and 4 columns. The arrangement manner of the transistors may be matrix-like or not matrix-like.

[0306] Transistors 100_1 to 100_4 each include a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b. The conductive layer 104 is used as the gate electrode of transistors 100_1 to 100_4. A part of the insulating layer 106 is used as the gate insulating layer of transistors 100_1 to 100_4. The conductive layer 112a is used as the other of the source electrode and the drain electrode of transistors 100_1 to 100_4, and the conductive layer 112b is used as one of the source electrode and the drain electrode.

[0307] Figure 17A It is a perspective view showing the conductive layer 112a in the abstract.

[0308] Figure 17B It is a perspective view showing the conductive layer 112a, the conductive layer 112b, the openings 141_1 to 141_4, and the openings 143_1 to 143_4 in the abstract. Note that the openings 141_1 to 141_4 provided in the insulating layer 110 are shown by dashed lines. Regarding the openings 141_1 to 141_4 and the openings 143_1 to 143_4, reference can be made to the description of the openings 141 and 143, so detailed description is omitted.

[0309] When the transistor 100C is regarded as one transistor, the channel width of this transistor is the sum of the channel widths of transistors 100_1 to 100_4. For example, when the top surface shapes of the openings 141_1 to 141_4 are circular and the width of each of the openings 141_1 to 141_4 is described as the width D141, the transistor 100C can be regarded as a transistor with a channel width of "D141×π×4" (refer to Figure 4A and Figure 4B ). The transistor 100C composed of p transistors can be regarded as a transistor with a channel width of "D141×π×p". In addition, the transistor 100C can be regarded as a transistor having a channel length L100 (refer to Figure 4B ). By connecting multiple transistors in parallel, the channel width becomes larger, and the on-state current can be increased. In addition, the channel width can be made different by adjusting the number (p) of transistors connected in parallel. It is only necessary to determine the number (p) of transistors connected in parallel in such a way as to achieve the desired on-state current.

[0310] Figure 17C It is a perspective view showing the conductive layer 112a and the semiconductor layer 108 in the abstract. The semiconductor layer 108 is provided so as to cover the openings 141_1 to 141_4 and the openings 143_1 to 143_4. Note that Figure 17CThe structure in which transistors 100_1 to 100_4 share the semiconductor layer 108 is shown, but one embodiment of the present invention is not limited thereto. The semiconductor layer 108 may also be separated for transistors 100_1 to 100_4.

[0311] Figure 17D FIG. shows a perspective view of the conductive layer 112a and the conductive layer 104. The conductive layer 104 is disposed so as to cover the openings 141_1 to 141_4 and the openings 143_1 to 143_4.

[0312] Note that the structure of the transistor 100C shown in Structural Example 8 can be used for other structural examples. For example, the transistor 100C can be used as one or more of the transistors included in the semiconductor device shown in FIGS. 1 to 13.

[0313] <Structural Example 9> Figure 18A FIG. shows an equivalent circuit diagram of a transistor 100D of a semiconductor device that can be used in one embodiment of the present invention. The transistor 100D is a transistor group including transistors 100_1 to 100_q (q is an integer of 2 or more). The transistors 100_1 to 100_q are connected in series, and the transistor 100D can be regarded as one transistor.

[0314] Note that in Figure 18A , the transistors 100_1 to 100_q are n-channel transistors, but one embodiment of the present invention is not limited thereto. The transistors 100_1 to 100_q may also be p-channel transistors.

[0315] Taking the case where q = 4 as an example for specific description. Figure 18B FIG. shows an equivalent circuit diagram of a transistor 100D according to one embodiment of the present invention. Figure 18C FIG. shows a top view of the transistor 100D. Figure 19 FIG. shows along Figure 18C A cross-sectional view of the cross-section along the dotted line A5 - A6 in. Figure 20 FIG. shows a perspective view of the transistor 100D.

[0316] The transistor 100D includes transistors 100_1 to 100_4. Each of the transistors 100_1 to 100_4 can adopt the structure of the above-mentioned transistor 100. Note that the transistor 100 is taken as an example for description herein, but one embodiment of the present invention is not limited thereto. Any one of the transistors 100A to 100D can also be used as the transistors 100_1 to 100_4.

[0317] Figure 18CFIG. shows a structure in which transistors 100_1 to 100_4 are arranged in 2 rows and 2 columns, but there is no particular limitation on the arrangement of the transistors. For example, transistors 100_1 to 100_4 may also be arranged in 1 row and 4 columns. The arrangement of the transistors may be in a matrix form or not in a matrix form.

[0318] Transistor 100_1 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108_1, a conductive layer 112a, and a conductive layer 112b. The conductive layer 112a is used as one of the source electrode and the drain electrode of the transistor 100_1, and the conductive layer 112b is used as the other of the source electrode and the drain electrode.

[0319] Transistor 100_2 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108_2, a conductive layer 112a, and a conductive layer 112c. The conductive layer 112a is used as one of the source electrode and the drain electrode of the transistor 100_2, and the conductive layer 112c is used as the other of the source electrode and the drain electrode. The conductive layer 112a is shared by the transistor 100_1 and the transistor 100_2.

[0320] Transistor 100_3 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108_3, a conductive layer 112c, and a conductive layer 112d. The conductive layer 112c is used as one of the source electrode and the drain electrode of the transistor 100_3, and the conductive layer 112d is used as the other of the source electrode and the drain electrode. The conductive layer 112c is shared by the transistor 100_2 and the transistor 100_3.

[0321] Transistor 100_4 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108_4, a conductive layer 112d, and a conductive layer 112e. The conductive layer 112d is used as one of the source electrode and the drain electrode of the transistor 100_4, and the conductive layer 112e is used as the other of the source electrode and the drain electrode. The conductive layer 112d is shared by the transistor 100_3 and the transistor 100_4.

[0322] Figure 21A FIG. is a perspective view showing the conductive layer 112a and the conductive layer 112d. The conductive layer 112a and the conductive layer 112d can be formed by the same process.

[0323] Figure 21BThe abstract shows a perspective view of conductive layers 112a, 112b, 112c, 112d, 112e, openings 141_1 to 141_4, and openings 143_1 to 143_4. The conductive layers 112a to 112e can be formed by the same process. Opening 143_1 is provided in conductive layer 112b, openings 143_2 and 143_3 are provided in conductive layer 112c, and opening 143_4 is provided in conductive layer 112e.

[0324] Figure 21C The abstract shows a perspective view of conductive layers 112a, 112d, and semiconductor layers 108_1 to 108_4. The semiconductor layers 108_1 to 108_4 can be formed by the same process.

[0325] Figure 21D The abstract shows a perspective view of conductive layers 112a, 112d, and conductive layer 104. Conductive layer 104 is used as the gate electrode of transistors 100_1 to 100_4.

[0326] One of the source and drain electrodes of transistor 100_1 is electrically connected to one of the source and drain electrodes of transistor 100_2. The other of the source and drain electrodes of transistor 100_2 is electrically connected to one of the source and drain electrodes of transistor 100_3. The other of the source and drain electrodes of transistor 100_3 is electrically connected to one of the source and drain electrodes of transistor 100_4.

[0327] When transistor 100D is regarded as a single transistor, the channel length of this transistor is the sum of the channel lengths of transistors 100_1 to 100_4. For example, when the channel length of each of transistors 100_1 to 100_4 is described as channel length L100, transistor 100D can be regarded as a transistor with a channel length of "L100 × 4" (see Figure 4B ). Transistor 100D composed of q transistors can be regarded as a transistor with a channel length of "L100 × q". In addition, transistor 100D can be regarded as a transistor with a channel width W100 (see Figure 4A and Figure 4B ). By connecting multiple transistors in series, the channel length becomes larger, and the saturation can be improved. In addition, by adjusting the number (q) of transistors connected in series, the channel length can be made different. It is only necessary to determine the number (q) of transistors connected in series in such a way as to achieve the desired saturation.

[0328] Note that the structure of the transistor 100D shown in Structural Example 9 can be used for other structural examples. For example, the transistor 100D can be used as one or more of the transistors included in the semiconductor devices shown in FIGS. 1 to 13.

[0329] The transistor 100D can also be used as each of the transistors in the transistor 100C. That is, the transistor groups connected in parallel can also be connected in series (hereinafter, also referred to as series-parallel connection).

[0330] This embodiment can be appropriately combined with other embodiments. In addition, in this specification, when multiple structural examples are shown in one embodiment, the structural examples can be appropriately combined.

[0331] (Embodiment 2) In this embodiment, a method for manufacturing a display device according to one aspect of the present invention will be described with reference to Figures 22A to 26B Note that, regarding the materials and formation methods of the respective components, parts that are the same as those described in the above Embodiment 1 may sometimes be omitted.

[0332] Figures 22A to 26B Cross-sectional views along the Figure 1A indicated dotted line A1 - A2 and cross-sectional views along the dotted line B1 - B2 are shown side by side.

[0333] The thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by sputtering, chemical vapor deposition (CVD: Chemical Vapor Deposition), vacuum evaporation, pulsed laser deposition (PLD: Pulsed Laser Deposition), ALD, etc. As the CVD method, there are PECVD and thermal CVD methods. In addition, as one of the thermal CVD methods, there is metal organic chemical vapor deposition (MOCVD: Metal Organic CVD) method.

[0334] The thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by wet deposition methods such as spin coating, dipping, spraying, inkjet, dispenser, screen printing, offset printing, doctor knife method, slot die coating, roll coating, curtain coating, or blade coating.

[0335] When processing the thin films constituting the semiconductor device, photolithography or the like can be used. Alternatively, nanoimprinting, sandblasting, lift-off, etc. can be used to process the thin films. In addition, island-shaped thin films can be directly formed by a deposition method using a masking mask such as a metal mask.

[0336] Lithography typically has the following two methods. One is a method of forming a resist mask on a film to be processed, processing the film by etching or the like, and removing the resist mask. The other is a method of depositing a photosensitive film and then performing exposure and development to process the film into a desired shape.

[0337] In lithography, as the light used for exposure, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or light obtained by mixing these lights can be used. In addition, ultraviolet light, KrF laser, ArF laser, etc. can also be used. Furthermore, immersion exposure technology can also be utilized for exposure. In addition, as the light used for exposure, extreme ultraviolet (EUV) light or X-rays can also be used. In addition, instead of the light used for exposure, an electron beam can also be used. When using extreme ultraviolet light, X-rays, or an electron beam, extremely fine processing can be performed, so it is preferred. Note that when performing exposure by scanning with a light beam such as an electron beam, a photomask is not required.

[0338] As an etching method for the film, one or more of a dry etching method, a wet etching method, and a sandblasting method can be utilized.

[0339] First, a film that will become the conductive layer 112a is formed on the substrate 102, and this film is processed to form the conductive layer 112a. The formation of this film can appropriately utilize the sputtering method.

[0340] Next, an insulating film 110af that will become the insulating layer 110a and an insulating film 110bf that will become the insulating layer 110b are formed on the conductive layer 112a ( Figure 22A ).

[0341] When forming the insulating film 110af and the insulating film 110bf, the sputtering method or the PECVD method can be appropriately utilized. It is preferred to continuously form the insulating film 110bf in a vacuum in such a manner that the surface of the insulating film 110af is not exposed to the atmosphere after forming the insulating film 110af. By continuously forming the insulating film 110af and the insulating film 110bf, attachment of impurities derived from the atmosphere to the surface of the insulating film 110af can be suppressed. Examples of such impurities include water and organic substances.

[0342] As described above, the amount of oxygen released from the insulating layer 110b is preferably large. Furthermore, the diffusion coefficient of substances (especially oxygen) in the insulating layer 110b is preferably large. When forming the insulating film 110bf that will become the insulating layer 110b using the PECVD method, the F ratio is preferably within the above range. As a result, oxygen easily diffuses in the insulating layer 110b, and the oxygen contained in the insulating layer 110b can be efficiently supplied to the semiconductor layer 108 (especially the channel formation region), and the amount of impurities released from the insulating layer 110b can be reduced.

[0343] The substrate temperature when forming the insulating film 110af and the insulating film 110bf is preferably 180 °C or higher and 450 °C or lower, more preferably 200 °C or higher and 450 °C or lower, more preferably 250 °C or higher and 450 °C or lower, more preferably 300 °C or higher and 450 °C or lower, more preferably 300 °C or higher and 400 °C or lower, more preferably 350 °C or higher and 400 °C or lower. By setting the substrate temperature when forming the insulating film 110af and the insulating film 110bf within the above range, the release of impurities (such as water and hydrogen) from the insulating film 110af and the insulating film 110bf themselves can be reduced, and thus the diffusion of impurities into the semiconductor layer 108 can be suppressed. Therefore, a transistor with good electrical characteristics and high reliability can be achieved.

[0344] Note that since the insulating film 110af and the insulating film 110bf are formed first and then the semiconductor layer 108 and the semiconductor layer 208 are formed, there is no concern about the oxygen detachment from the semiconductor layer 108 and the semiconductor layer 208 due to the heat applied when forming the insulating film 110af and the insulating film 110bf.

[0345] After forming the insulating film 110bf, oxygen can also be supplied to the insulating film 110bf. As a method for supplying oxygen, for example, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or a plasma treatment can be used. As the plasma treatment, a device that plasmaizes oxygen gas with high-frequency power can be appropriately used. As a device that plasmaizes a gas with high-frequency power, for example, a PECVD device, a plasma etching device, and a plasma ashing device can be cited. The plasma treatment is preferably performed in an oxygen-containing atmosphere. For example, it is preferably performed in an atmosphere containing one or more of oxygen, nitrous oxide (N2O), nitrogen dioxide (NO2), carbon monoxide, and carbon dioxide.

[0346] Note that this plasma treatment can also be continuously performed in a vacuum in such a manner that the surface of the insulating film 110bf is not exposed to the atmosphere. For example, when a PECVD apparatus is used to form the insulating film 110bf, it is preferable to perform this plasma treatment using the PECVD apparatus. Thereby, the productivity can be improved. Specifically, after the insulating film 110bf is formed using the PECVD apparatus, N2O plasma treatment can be continuously performed in a vacuum.

[0347] A metal oxide layer 137 is preferably formed on the insulating film 110bf ( Figure 22B ). By forming the metal oxide layer 137, oxygen can be supplied to the insulating film 110bf.

[0348] There is no limitation on the conductivity of the metal oxide layer 137. The metal oxide layer 137 can use at least one of an insulating film, a semiconductor film, and a conductive film. For example, the metal oxide layer 137 can use alumina, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or indium tin oxide containing silicon (ITSO).

[0349] As the metal oxide layer 137, an oxide material containing one or more elements the same as those of the semiconductor layer 108 and the semiconductor layer 208 is preferably used. In particular, a metal oxide material applicable to the semiconductor layer 108 and the semiconductor layer 208 is preferably used.

[0350] When forming the metal oxide layer 137, the higher the oxygen flow ratio of the deposition gas introduced into the processing chamber of the deposition apparatus or the oxygen partial pressure in the processing chamber, the more oxygen can be supplied to the insulating film 110bf. The oxygen flow ratio or the oxygen partial pressure is, for example, 50% or more and 100% or less, preferably 65% or more and 100% or less, more preferably 80% or more and 100% or less, and further preferably 90% or more and 100% or less. In particular, it is preferable to set the oxygen flow ratio to 100% to make the oxygen partial pressure as close to 100% as possible.

[0351] Thus, by forming the metal oxide layer 137 by sputtering in an oxygen-containing atmosphere, oxygen can be supplied to the insulating film 110bf while preventing oxygen from escaping from the insulating film 110bf when forming the metal oxide layer 137. As a result, more oxygen can be enclosed in the insulating film 110bf. And, more oxygen can be supplied to the semiconductor layer 108 by a subsequent heat treatment. As a result, oxygen vacancies and V O H in the semiconductor layer 108 can be reduced, and a transistor having good electrical characteristics and high reliability can be realized.

[0352] The heat treatment is preferably performed after the formation of the metal oxide layer 137. By performing the heat treatment after the formation of the metal oxide layer 137, oxygen can be effectively supplied from the metal oxide layer 137 to the insulating film 110bf.

[0353] The temperature of the heat treatment is preferably 150 °C or higher, 200 °C or higher, 230 °C or higher, or 250 °C or higher, and lower than the strain point of the substrate, 450 °C or lower, 400 °C or lower, 350 °C or lower, or 300 °C or lower. The heat treatment can be performed in an atmosphere containing one or more of noble gases, nitrogen, and oxygen. As the nitrogen-containing atmosphere or oxygen-containing atmosphere, dry air (CDA: Clean Dry Air) can also be used. Note that the content of hydrogen, oxygen, etc. in this atmosphere is preferably as small as possible. As this atmosphere, a high-purity gas with a dew point of -60 °C or lower, preferably -100 °C or lower, is preferably used. By using an atmosphere with as little content of hydrogen, water, etc. as possible, absorption of hydrogen, water, etc. by the insulating film 110af, the insulating film 110bf, etc. can be prevented as much as possible. This heat treatment can use an oven, a rapid thermal annealing (RTA) apparatus, etc. By using an RTA apparatus, the heat treatment time can be shortened.

[0354] After the formation of the metal oxide layer 137 or after the above heat treatment, oxygen can also be supplied to the insulating film 110bf through the metal oxide layer 137. As a method for supplying oxygen, for example, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or a plasma treatment can be used. Regarding the plasma treatment, reference can be made to the above description, so its detailed description is omitted.

[0355] Next, the metal oxide layer 137 is removed. Although there is no particular limitation on the method for removing the metal oxide layer 137, a wet etching method can be appropriately adopted. By using the wet etching method, etching of the insulating film 110bf when removing the metal oxide layer 137 can be suppressed. Therefore, a decrease in the thickness of the insulating film 110bf can be suppressed, and the thickness of the insulating layer 110b can be made uniform.

[0356] After removing the metal oxide layer 137, oxygen can also be supplied to the insulating film 110bf. Regarding the method for supplying oxygen, reference can be made to the above description. For example, as Figure 22C shown, a film 139 can also be formed on the insulating film 110bf and oxygen can be supplied to the insulating film 110bf through the film 139. As this treatment, a plasma treatment in an oxygen-containing atmosphere can be used. Figure 22C The case of supplying oxygen to the insulating film 110bf is schematically indicated by an arrow in

[0357] The film 139 is preferably a conductive film or a semiconductor film. The film 139 can be a metal oxide film, a metal film, or an alloy film. When a metal oxide is used as the film 139 and formed by sputtering or the like in an oxygen-containing atmosphere, oxygen can also be supplied to the insulating film 110bf during the formation of the film 139, so it is preferred.

[0358] The thickness of the film 139 is preferably thin. Specifically, the thickness of the film 139 is preferably 1 nm or more, 2 nm or more, or 3 nm or more, and 20 nm or less, 15 nm or less, or 10 nm or less. Typically, it can be about 5 nm.

[0359] The substrate temperature during the formation of the film 139 is preferably 350 °C or lower, more preferably 340 °C or lower, still more preferably 330 °C or lower, and further preferably 300 °C or lower. Thereby, the amount of oxygen supplied to the insulating film 110bf can be increased.

[0360] By providing the film 139, when a bias voltage is applied between a pair of electrodes in the presence of supplied oxygen, ionized oxygen is easily attracted. Therefore, the amount of oxygen supplied to the insulating film 110bf can be increased.

[0361] As a processing apparatus for supplying oxygen, a dry etching apparatus, an ashing apparatus, a PECVD apparatus, etc. can be appropriately used. In particular, an ashing apparatus is preferably used. When a bias voltage is applied between a pair of electrodes included in the processing apparatus, for example, the bias voltage can be set to 10 V or more and 1 kV or less. Or, for example, the power density of the bias voltage can be set to 1 W / cm 2 or more and 5 W / cm 2 or less.

[0362] Next, the film 139 is removed. The removal of the film 139 can be appropriately carried out by a wet etching method.

[0363] The oxygen supply treatment for the insulating film 110bf is not limited to the above method. For example, oxygen radicals, oxygen atoms, oxygen atomic ions, or oxygen molecular ions are supplied to the insulating film 110bf by ion doping, ion implantation, or plasma treatment. In addition, after forming a film that inhibits oxygen desorption on the insulating film 110bf, oxygen can be supplied to the insulating film 110bf through this film. It is preferred to remove this film after supplying oxygen. As the above film that inhibits oxygen desorption, a conductive film or a semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, or tungsten can be used.

[0364] Preferably, the amount of oxygen released from the insulating layer 110b in contact with the channel formation region of the transistor 100 having a short channel length is larger than the amount of oxygen released from the insulating layer 120b in contact with the channel formation region of the transistor 200 having a long channel length. By supplying oxygen to the insulating film 110bf that becomes the insulating layer 110b, the amount of oxygen contained in the insulating layer 110b increases, and the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer 108 can increase, and good electrical characteristics can also be exhibited in the transistor 100 having a short channel length.

[0365] Next, an insulating film 110cf that will become the insulating layer 110c is formed on the insulating film 110bf ( Figure 22D ). Since the formation of the insulating film 110cf can refer to the description of the formation of the insulating film 110af and the insulating film 110bf, the detailed description is omitted.

[0366] Next, a film that will become the conductive layer 202 is formed on the insulating film 110cf, and the film is processed to form the conductive layer 202 ( Figure 23A ). The formation of this film can appropriately use a sputtering method.

[0367] Next, an insulating film 120af that will become the insulating layer 120a and an insulating film 120bf that will become the insulating layer 120b are formed so as to cover the conductive layer 202 ( Figure 23B ).

[0368] When forming the insulating film 120af and the insulating film 120bf, a sputtering method or a PECVD method can be appropriately used. It is preferable to continuously form the insulating film 120bf in a vacuum without exposing the surface of the insulating film 120af to the atmosphere after forming the insulating film 120af. By continuously forming the insulating film 120af and the insulating film 120bf, attachment of impurities derived from the atmosphere to the surface of the insulating film 120af can be suppressed. Examples of such impurities include water and organic substances.

[0369] As described above, the amount of oxygen released from the insulating layer 120b can also be smaller than the amount of oxygen released from the insulating layer 110b. In addition, the diffusion coefficient of oxygen in the insulating layer 120b can be made smaller than the diffusion coefficient of oxygen in the insulating layer 110b. When forming the insulating film 120bf that will become the insulating layer 120b by the PECVD method, the F ratio is preferably within the above range.

[0370] When forming the insulating film 120af and the insulating film 120bf, the substrate temperature is preferably 180 °C or higher and 450 °C or lower, more preferably 200 °C or higher and 450 °C or lower, more preferably 250 °C or higher and 450 °C or lower, more preferably 300 °C or higher and 450 °C or lower, more preferably 300 °C or higher and 400 °C or lower, and more preferably 350 °C or higher and 400 °C or lower. By setting the substrate temperature when forming the insulating film 120af and the insulating film 120bf within the above range, the release of impurities (such as water and hydrogen) from the insulating film 120af and the insulating film 120bf themselves can be reduced, and thus the diffusion of impurities into the semiconductor layer 108 can be suppressed. Therefore, a transistor with good electrical characteristics and high reliability can be achieved.

[0371] Note that since the insulating film 120af and the insulating film 120bf are formed first and then the semiconductor layer 108 and the semiconductor layer 208 are formed, there is no concern about the oxygen being detached from the semiconductor layer 108 and the semiconductor layer 208 due to the heat applied when forming the insulating film 120af and the insulating film 120bf.

[0372] Oxygen can also be supplied to the insulating film 120bf after the insulating film 120bf is formed. Regarding the method of supplying oxygen, reference can be made to the above description.

[0373] Next, the insulating film 120af and the insulating film 120bf are processed to form the insulating layer 120 including the insulating layer 120a and the insulating layer 120b. The processing of the insulating film 120af and the insulating film 120bf can be appropriately performed using, for example, a dry etching method.

[0374] Next, a conductive film 112bf that will become the conductive layer 112b is formed on the insulating film 110cf and the insulating layer 120 ( Figure 23C ). The formation of the conductive film 112bf can be appropriately performed using, for example, a sputtering method.

[0375] Next, the conductive film 112bf is processed to form the conductive layer 112B ( Figure 24A ). The conductive layer 112B will become the conductive layer 112b later. The formation of the conductive layer 112B can be appropriately performed using, for example, a wet etching method.

[0376] Next, a part of the conductive layer 112B is removed to form the conductive layer 112b having an opening 143. The formation of the conductive layer 112b can be appropriately performed using, for example, a wet etching method.

[0377] Next, a part of the insulating film 110af, the insulating film 110bf, and the insulating film 110cf is removed to form the insulating layer 110 having an opening 141 ( Figure 24B)。The opening 141 is provided in the region overlapping with the opening 143. The conductive layer 112a is exposed by forming the opening 141. When forming the insulating layer 110, for example, a dry etching method can be appropriately used.

[0378] The opening 141 can be formed, for example, using the resist mask used for forming the opening 143. Specifically, a resist mask can be formed on the conductive layer 112B, a part of the conductive layer 112B can be removed using the resist mask to form the opening 143, and a part of the insulating films 110af, 110bf, and 110cf can be removed using the resist mask to form the opening 141. The opening 141 can also be formed using a resist mask different from the resist mask used for forming the opening 143.

[0379] In addition, a part of the conductive layer 112a in the region overlapping with the opening 141 can be removed when forming the opening 141 or after forming the opening 141. By making the thickness of the region of the conductive layer 112a in contact with the bottom surface of the semiconductor layer 108 thinner than the region not in contact with the semiconductor layer 108, the electric field applied to the gate electrode in the channel formation region near the conductive layer 112a can be enhanced, thereby increasing the on-state current of the transistor.

[0380] Next, a metal oxide film 108f that will become the semiconductor layer 108 and the semiconductor layer 208 is formed so as to cover the opening 141 and the opening 143 ( Figure 24C )。The metal oxide film 108f is provided in contact with the top surface and side surfaces of the insulating layer 110, the top surface of the conductive layer 112a, the top surface and side surfaces of the conductive layer 112b, and the top surface and side surfaces of the insulating layer 120.

[0381] The metal oxide film 108f is preferably formed by a sputtering method using a metal oxide target. Alternatively, the metal oxide film 108f is preferably formed by an ALD method. Because of the high coverage, the ALD method can also be appropriately used when forming the metal oxide film 108f provided so as to cover the opening 141 and the opening 143. By using the ALD method, the metal oxide film can also be formed with high coverage on the side surfaces of the insulating layer 110. In addition, the ALD method is easy to control the deposition rate, so a thin film with high yield can be formed.

[0382] The metal oxide film 108f is preferably a dense film with as few defects as possible. In addition, the metal oxide film 108f is preferably a high-purity film in which impurities containing hydrogen elements are reduced as much as possible. In particular, a metal oxide film with crystallinity is preferably used as the metal oxide film 108f.

[0383] When forming the metal oxide film 108f, oxygen gas is preferably used. By using oxygen gas, oxygen can be appropriately supplied to the insulating layer 110 and the insulating layer 120. For example, when an oxide or oxynitride is used for the insulating layer 110b, oxygen can be appropriately supplied to the insulating layer 110b. Similarly, when an oxide or oxynitride is used for the insulating layer 120b, oxygen can be appropriately supplied to the insulating layer 120b.

[0384] By supplying oxygen to the insulating layer 110b and supplying oxygen to the channel formation region of the semiconductor layer 108 in a subsequent process, oxygen vacancies and V in the channel formation region can be reduced. O H. In addition, by supplying oxygen to the insulating layer 120b and supplying oxygen to the channel formation region of the semiconductor layer 208 in a subsequent process, oxygen vacancies and V in the channel formation region can be reduced. O H.

[0385] When forming the metal oxide film 108f, oxygen gas and an inert gas (for example, helium gas, argon gas, xenon gas, etc.) can also be mixed. Note that the higher the oxygen flow ratio of the deposition gas or the oxygen partial pressure in the processing chamber when forming the metal oxide film, the higher the crystallinity of the metal oxide film can be, and a transistor with high reliability can be achieved. On the other hand, the lower the oxygen flow ratio or the oxygen partial pressure, a metal oxide film with lower crystallinity and higher conductivity can be achieved, so a transistor with a large on-state current can be achieved.

[0386] Here, when the oxygen flow ratio or the oxygen partial pressure is high, the metal oxide film sometimes has a polycrystalline structure. In the case of a metal oxide film having a polycrystalline structure, grain boundaries become recombination centers and capture carriers, so the on-state current of the transistor sometimes becomes small. Therefore, it is preferable to adjust the oxygen flow ratio or the oxygen partial pressure so that the metal oxide film 108f does not have a polycrystalline structure. Since it is likely to have a polycrystalline structure depending on the composition of the metal oxide film, it is only necessary to adjust the oxygen flow ratio or the oxygen partial pressure according to the composition of the metal oxide film 108f.

[0386] When the substrate temperature is higher when forming the metal oxide film, a metal oxide film with higher crystallinity and higher density can be formed. On the other hand, as the substrate temperature becomes lower, a metal oxide film with lower crystallinity and higher conductivity can be formed.

[0388] The substrate temperature when forming the metal oxide film 108f is preferably above room temperature and below 250 °C, more preferably above room temperature and below 200 °C, and further preferably above room temperature and below 140 °C. For example, the substrate temperature is preferably above room temperature and below 140 °C, whereby the productivity can be improved. In addition, by forming the metal oxide film 108f at room temperature or in a state where the substrate is not heated, the crystallinity can be reduced.

[0389] When the substrate temperature is high, the metal oxide film sometimes has a polycrystalline structure. Therefore, it is preferable to adjust the substrate temperature so that the metal oxide film 108f does not have a polycrystalline structure. The substrate temperature can be adjusted according to the composition applied to the metal oxide film 108f.

[0390] When using the ALD method, it is preferable to use deposition methods such as thermal ALD method or PEALD (Plasma Enhanced ALD). The thermal ALD method is preferable because it has extremely high coverage. In addition, the PEALD method is preferable because it not only has high coverage but also enables low-temperature deposition.

[0391] The metal oxide film can be formed, for example, by using a precursor containing a constituent metal element and an oxidizing agent and using the ALD method.

[0392] For example, when forming an In-Ga-Zn oxide, three precursors including a precursor containing indium, a precursor containing gallium, and a precursor containing zinc can be used. Alternatively, two precursors including a precursor containing indium and a precursor containing gallium and zinc can also be used.

[0393] Examples of the precursor containing indium include triethylindium, indium tris(2,2,6,6-tetramethyl-3,5-heptanedionate), cyclopentadienylindium, indium(III) chloride, and (3-(dimethylamino)propyl)dimethylindium.

[0394] Examples of the precursor containing gallium include trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamide)gallium(III), gallium(III) acetylacetonate, gallium tris(2,2,6,6-tetramethyl-3,5-heptanedionate), dimethylchlorogallium, and diethylchlorogallium.

[0395] Examples of the precursor containing zinc include dimethylzinc, diethylzinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), and zinc chloride.

[0396] Examples of the oxidizing agent include ozone, oxygen, and water.

[0397] As a method for controlling the composition of the obtained film, adjustment of one or more of the type of source gas, the flow rate ratio of the source gas, the time for flowing the source gas, and the order of flowing the source gas can be cited. By adjusting them, the composition of the metal oxide film 108f can be controlled. In addition, by adjusting them, a film with a continuously changing composition can be formed. The composition of the metal oxide film 108f can also change continuously.

[0398] Before depositing the metal oxide film 108f, it is preferable to perform at least one of a treatment for removing water, hydrogen, organic substances, etc. adsorbed on the surfaces of the insulating layer 110 and the insulating layer 120 and a treatment for supplying oxygen to the insulating layer 110. For example, a heat treatment can be performed at a temperature of 70°C or higher and 200°C or lower in a reduced-pressure atmosphere. Alternatively, a plasma treatment in an oxygen-containing atmosphere can also be performed. Or, by performing a plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide (N2O), oxygen can also be supplied to the insulating layer 110. When performing a plasma treatment containing nitrous oxide gas, the organic substances on the surface of the insulating layer 110 can be appropriately removed and oxygen can be supplied to the insulating layer 110. Preferably, after such a treatment, the metal oxide film 108f is continuously deposited in such a manner that the surface of the insulating layer 110 is not exposed to the atmosphere.

[0399] Note that in the case where the semiconductor layer 108 and the semiconductor layer 208 have a stacked structure, it is preferable that after depositing the lower metal oxide film, the upper metal oxide film is continuously deposited in such a manner that its surface is not exposed to the atmosphere.

[0400] In the case where the semiconductor layer 108 and the semiconductor layer 208 have a stacked structure, all the layers constituting the semiconductor layer 108 and the semiconductor layer 208 can be formed using the same deposition method (e.g., sputtering method or ALD method), or different deposition methods can be used for each layer. For example, the first metal oxide layer can be deposited using the sputtering method and the second metal oxide layer can be deposited using the ALD method.

[0401] Next, the metal oxide film 108f is processed into an island shape to form the semiconductor layer 108 and the semiconductor layer 208( Figure 25A ).

[0402] When forming the semiconductor layer 108 and the semiconductor layer 208, a wet etching method can be appropriately used. At this time, a part of the insulating layer 110 in a region that does not overlap with the semiconductor layer 108 and the semiconductor layer 208 may be etched and its thickness may become thinner. Note that in the etching of the metal oxide film 108f, it is preferable to use a material with a high selectivity as the insulating layer 110c to suppress the thinning of the thickness of the insulating layer 110c. The same applies to the insulating layer 120.

[0403] Preferably, the heat treatment is performed after depositing the metal oxide film 108f or after processing the metal oxide film 108f into the semiconductor layer 108 and the semiconductor layer 208. By the heat treatment, hydrogen and water contained in the metal oxide film 108f or the semiconductor layer 108 and the semiconductor layer 208 or adsorbed on the surfaces of the metal oxide film 108f or the semiconductor layer 108 and the semiconductor layer 208 can be removed. In addition, by the heat treatment, the film quality of the metal oxide film 108f or the semiconductor layer 108 and the semiconductor layer 208 is sometimes improved (for example, reduction of defects or improvement of crystallinity).

[0404] By the heat treatment, oxygen can also be supplied from the insulating layer 110b to the metal oxide film 108f or the semiconductor layer 108. Thereby, oxygen vacancies (V O ) in the channel formation region can be reduced. At this time, more preferably, the heat treatment is performed before processing the metal oxide film 108f into the semiconductor layer 108 and the semiconductor layer 208. Since the heat treatment can be referred to the above description, the detailed description is omitted. In addition, not limited to this heat treatment, in the heating process (for example, the process of forming the insulating layer 106) after forming the metal oxide film 108f, oxygen can also be supplied to the channel formation region.

[0405] Note that it is not necessarily required to perform this heat treatment. In addition, the heat treatment performed in a later process can be used as the heat treatment in this process without performing the heat treatment in this process. Sometimes, the heat treatment (for example, the deposition process) in a later process can be used as the heat treatment in this process.

[0406] Next, an insulating film 106f that will become the insulating layer 106 is formed so as to cover the semiconductor layer 108, the semiconductor layer 208, and the insulating layer 110( Figure 25B ). When forming the insulating film 106f, for example, the PECVD method or the ALD method can be appropriately used.

[0407] When using a metal oxide for the semiconductor layer 108 and the semiconductor layer 208, it is preferable to use the insulating layer 106 as a barrier film for suppressing oxygen diffusion. By the insulating layer 106 having the function of suppressing oxygen diffusion, oxygen contained in the semiconductor layer 108 and the semiconductor layer 208 can be suppressed from diffusing to the upper side of the insulating layer 106, thereby suppressing the increase of oxygen vacancies (V O ) in the semiconductor layer 108 and the semiconductor layer 208. As a result, a transistor having good electrical characteristics and high reliability can be realized.

[0408] Note that in this specification and the like, a barrier film refers to a film having barrier properties. For example, an insulating layer having barrier properties may be referred to as a barrier insulating layer. In this specification and the like, barrier properties refer to one or both of the functions of suppressing the diffusion of a target substance (which can also be said to have low permeability) and capturing or fixing (also referred to as gettering) the substance.

[0409] By increasing the temperature at the time of forming the insulating film 106f, an insulating layer with fewer defects can be formed. However, when the temperature at the time of forming the insulating film 106f is high, oxygen detaches from the semiconductor layer 108 and the semiconductor layer 208, and sometimes oxygen vacancies (V O ) and V O H in the semiconductor layer 108 and the semiconductor layer 208 increase. The substrate temperature at the time of forming the insulating film 106f is preferably 180 °C or higher and 450 °C or lower, more preferably 200 °C or higher and 450 °C or lower, more preferably 250 °C or higher and 450 °C or lower, more preferably 300 °C or higher and 450 °C or lower, and more preferably 300 °C or higher and 400 °C or lower. By setting the substrate temperature at the time of forming the insulating film 106f within the above range, it is possible to reduce the defects of the insulating layer 106 while suppressing the detachment of oxygen from the semiconductor layer 108 and the semiconductor layer 208. Therefore, a transistor with good electrical characteristics and high reliability can be realized.

[0410] Before forming the insulating film 106f, the surfaces of the semiconductor layer 108 and the semiconductor layer 208 can also be subjected to plasma treatment. By this plasma treatment, impurities such as water adsorbed on the surfaces of the semiconductor layer 108 and the semiconductor layer 208 can be reduced. Therefore, the impurities at the interface between the semiconductor layer 108 and the insulating layer 106 and at the interface between the semiconductor layer 208 and the insulating layer 106 can be reduced, so a transistor with high reliability can be realized. In particular, when the surfaces of the semiconductor layer 108 and the semiconductor layer 208 are exposed to the atmosphere between the formation of the semiconductor layer 108 and the semiconductor layer 208 and the formation of the insulating film 106f, plasma treatment is preferred. The plasma treatment can be performed, for example, in an atmosphere of oxygen, ozone, nitrogen, nitrous oxide, argon, etc. The plasma treatment and the deposition of the insulating layer 106 are preferably carried out continuously without exposure to the atmosphere.

[0411] Next, the insulating film 106f is processed to form the insulating layer 106( Figure 25C ). Openings 147a and 147b reaching the semiconductor layer 208 are provided in the insulating layer 106. When forming the insulating layer 106, a dry etching method can be appropriately used.

[0412] Next, a film that will become the conductive layer 104, conductive layer 204, conductive layer 212a, and conductive layer 212b is formed on the insulating layer 106, and this film is processed to form the conductive layer 104, conductive layer 204, conductive layer 212a, and conductive layer 212b( Figure 26A ). This film can be formed, for example, by appropriately using a sputtering method, a thermal CVD method (including MOCVD method), or an ALD method.

[0413] Next, the conductive layer 204, conductive layer 212a, and conductive layer 212b are used as masks to supply (also referred to as adding or implanting) impurities to the semiconductor layer 208. As a result, in the semiconductor layer 208, a region 208D is formed in a region that does not overlap with any of the conductive layer 204, conductive layer 212a, conductive layer 212b, and insulating layer 106, and a region 208L is formed in a region that does not overlap with any of the conductive layer 204, conductive layer 212a, and conductive layer 212b and overlaps with the insulating layer 106( Figure 26B ). At this time, it is preferable to determine the impurity supply conditions according to the material and thickness of the conductive layer 204 as a mask so that impurities are not supplied as much as possible in the region of the semiconductor layer 208 that overlaps with the conductive layer 204. As a result, a channel formation region with a sufficiently reduced impurity concentration can be formed in the region of the semiconductor layer 208 that overlaps with the conductive layer 204. Similarly, the semiconductor layer 108 can also supply impurities using the conductive layer 104 as a mask. A region 108L is formed in a region of the semiconductor layer 108 that does not overlap with the conductive layer 104 and overlaps with the insulating layer 106.

[0414] For the supply of impurities, a plasma ion doping method or an ion implantation method can be appropriately used. In these methods, the concentration distribution in the depth direction can be controlled with high precision according to the ion acceleration voltage and dose, etc. By using the plasma ion doping method, the productivity can be improved. In addition, by using an ion implantation method that utilizes mass separation, the purity of the supplied impurities can be improved.

[0415] In the supply of impurities, it is preferable to adjust the supply conditions so that the impurity concentration at the surface of the semiconductor layer 208 or in a portion closer to the surface is the highest.

[0416] As a raw material for the supply of impurities, for example, a gas containing the above impurity element can be used. When supplying boron, typically one or more of B2H6 gas and BF3 gas can be used. In addition, when supplying phosphorus, typically PH3 gas can be used. In addition, a gas obtained by diluting these source gases with a noble gas can also be used.

[0417] As a raw material for the supply of impurities, for example, CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF, H2, (C5H5)2Mg, and noble gases can be used. Note that the raw materials are not limited to gases, and solids or liquids can also be heated to vaporize them.

[0418] By setting conditions such as the acceleration voltage and dose according to the composition, density, and thickness of the insulating layer 106 and the semiconductor layer 208, etc., the addition of impurities can be controlled.

[0419] When adding boron using the ion implantation method or the plasma ion doping method, the acceleration voltage can be, for example, 5 kV or more and 100 kV or less, preferably 7 kV or more and 70 kV or less, more preferably 10 kV or more and 50 kV or less. In addition, the dose can be, for example, 1×10 13 ions / cm 2 or more and 1×10 17 ions / cm 2 or less, preferably 1×10 14 ions / cm 2 or more and 5×10 16 ions / cm 2 or less, more preferably 1×10 15 ions / cm 2 or more and 3×10 16 ions / cm 2 or less.

[0420] When adding phosphorus using the ion implantation method or the plasma ion doping method, the acceleration voltage can be, for example, 10 kV or more and 100 kV or less, preferably 30 kV or more and 90 kV or less, more preferably 40 kV or more and 80 kV or less. In addition, the dose can be, for example, 1×10 13 ions / cm 2 or more and 1×10 17 ions / cm 2 or less, preferably 1×10 14 ions / cm 2 or more and 5×10 16 ions / cm 2 or less, more preferably 1×10 15 ions / cm 2 or more and 3×10 16 ions / cm 2 or less.

[0421] Note that the method of supplying impurities is not limited to this. For example, plasma treatment or treatment using thermal diffusion caused by heating can also be performed. In the case of using the plasma treatment method, impurities can be added by first generating plasma in a gas atmosphere containing the added impurities and then performing plasma treatment. As a device for generating the above plasma, a dry etching device, an ashing device, a plasma CVD device, a high-density plasma CVD device, etc. can be used.

[0422] For example, by performing plasma treatment using a plasma CVD device in an atmosphere containing hydrogen, hydrogen can be supplied as an impurity to the semiconductor layer 208 in a region that does not overlap with the conductive layer 204. In addition, by using a plasma CVD device during the supply of impurities and the formation of the insulating layer 195, the supply of impurities and the formation of the insulating layer 195 can be continuously performed in the device, so the productivity can be improved.

[0423] A capacitor element 150 is formed in a region where the conductive layer 202, the insulating layer 120, and the conductive layer 112b overlap each other.

[0424] Next, an insulating layer 195 is formed so as to cover the conductive layer 104, the conductive layer 204, the conductive layer 212a, the conductive layer 212b, the insulating layer 106, and the semiconductor layer 208 ( Figure 1B and Figure 1C ). The insulating layer 195 can be appropriately formed by the PECVD method.

[0425] When the deposition temperature of the insulating layer 195 is too high, the impurities contained in the regions 108L, 208L, and 208D may diffuse to the periphery of the semiconductor layer 108 and the semiconductor layer 208 including the channel formation region. In addition, the resistance of the regions 108L, 208L, and 208D may increase. Therefore, it is only necessary to determine the deposition temperature of the insulating layer 195 in consideration of the diffusion of impurities.

[0426] The deposition temperature of the insulating layer 195 is preferably, for example, 150 °C or higher and 400 °C or lower, more preferably 180 °C or higher and 360 °C or lower, and further preferably 200 °C or higher and 250 °C or lower. By depositing the insulating layer 195 at a low temperature, even a transistor with a short channel length can have excellent electrical characteristics.

[0427] Alternatively, a heat treatment may be performed after the formation of the insulating layer 195. By this heat treatment, the resistance of regions 108L, 208L, and 208D may sometimes be further reduced. For example, by performing the heat treatment, it may be possible to appropriately diffuse impurities to form regions 208L and 208D having an ideal impurity concentration gradient. Since the heat treatment can be referred to the above description, detailed description is omitted. Note that when the temperature of the heat treatment is too high (e.g., 500 °C or higher), the impurities diffuse into the channel formation region, which may cause deterioration of the electrical characteristics and reliability of the transistor.

[0428] Note that it is not always necessary to perform this heat treatment. In addition, the heat treatment to be performed in a later process may be used as the heat treatment in this process without performing the heat treatment in this process. Sometimes, the heat treatment in a later process (e.g., a deposition process, etc.) may be used as the heat treatment in this process.

[0429] A semiconductor device according to one embodiment of the present invention can be manufactured by the above process.

[0430] This embodiment can be appropriately combined with other embodiments.

[0431] (Embodiment 3) In this embodiment, a display device according to one embodiment of the present invention will be described with reference to FIGS. 27 to 51.

[0432] The display device of this embodiment can be a high-resolution display device or a large display device. Therefore, for example, the display device of this embodiment can be used as a display unit of a device such as an electronic device having a large screen such as a television device, a desktop or notebook computer, a monitor for a computer, etc., a digital signage, a pachinko machine, etc.; a digital camera; a digital video camera; a digital photo frame; a mobile phone; a portable game machine; a portable information terminal; a sound reproduction device.

[0433] The display device of this embodiment can be a high-definition display device. Therefore, for example, the display device of this embodiment can be used as a display unit of an information terminal device (wearable device) such as a watch type and a bracelet type, etc., and a wearable device worn on the head such as a VR device such as a head-mounted display (HMD) and a glasses type AR device.

[0434] A semiconductor device according to one embodiment of the present invention can be used in a display device or a module including the display device. As a module including the display device, examples include a module in which a flexible printed circuit (hereinafter referred to as FPC) or a connector such as a TCP (Tape Carrier Package) is mounted on the display device, and a module in which an integrated circuit (IC) is mounted by a method such as COG (Chip On Glass) or COF (Chip On Film).

[0435] The display device according to the present embodiment may also have a function of a touch panel. For example, various detection elements (which may also be referred to as sensor elements) capable of detecting the approach or contact of a detection object such as a finger can also be used as the display device.

[0436] As a sensor type, for example, a capacitive type, a resistive film type, a surface acoustic wave type, an infrared type, an optical type, and a piezoresistive type can be cited.

[0437] As the capacitive type, for example, there are a surface capacitive type and a projected capacitive type. In addition, as the projected capacitive type, for example, there are a self-capacitive type and a mutual-capacitive type. The mutual-capacitive type is preferably used because multi-point sensing can be performed simultaneously.

[0438] As a touch panel, for example, an Out-Cell type, an On-Cell type, and an In-Cell type can be cited. Note that the In-Cell type touch panel refers to a structure in which electrodes constituting a detection element are provided on one or both of a substrate supporting a display element (also referred to as a display device) and a counter substrate.

[0439] Figure 27A It is a perspective view of the display device 50A.

[0440] The display device 50A has a structure in which a substrate 152 is bonded to a substrate 151. In Figure 27A it, the substrate 152 is shown by a dashed line.

[0441] The display device 50A includes a display unit 162, a connection unit 140, a circuit unit 164, a conductive layer 165, and the like. Figure 27A An example in which the display device 50A is mounted with an IC 173 and an FPC 172 is shown. Therefore, the Figure 27A structure shown can also be referred to as a display module including the display device 50A, an IC, and an FPC.

[0442] The connection unit 140 is provided outside the display unit 162. The connection unit 140 can be provided along one or more sides of the display unit 162. The connection unit 140 can also be one or more. Figure 27AAn example is shown in which the connection portion 140 is provided in a manner surrounding the four sides of the display portion. In the connection portion 140, the common electrode of the display element is electrically connected to the conductive layer, and a potential can be supplied to the common electrode.

[0443] The circuit portion 164 includes, for example, a scan line driving circuit (also referred to as a gate driver). Additionally, the circuit portion 164 may also include both a scan line driving circuit and a signal line driving circuit (also referred to as a source driver).

[0444] The conductive layer 165 has a function of supplying signals and power to the display portion 162 and the circuit portion 164. The signals and power are input to the conductive layer 165 from the outside via the FPC 172 or input to the conductive layer 165 from the IC 173.

[0445] Figure 27A An example is shown in which the IC 173 is provided on the substrate 151 by a method such as the COG method or the COF method. As the IC 173, for example, an IC including one or both of a scan line driving circuit and a signal line driving circuit can be used. Note that the display device 50A and the display module do not necessarily have to be provided with an IC. Additionally, the IC can be mounted on the FPC by a method such as the COF method.

[0446] A semiconductor device according to one aspect of the present invention can be used, for example, for one or both of the display portion 162 and the circuit portion 164 of the display device 50A.

[0447] For example, when a semiconductor device according to one aspect of the present invention is used for a pixel circuit of a display device, the occupied area of the pixel circuit can be reduced, and a high-definition display device can be realized. In addition, for example, when a semiconductor device according to one aspect of the present invention is used for a driving circuit of a display device (for example, one or both of a gate line driving circuit and a source line driving circuit), the occupied area of the driving circuit can be reduced, and a narrow-bezel display device can be realized. Additionally, a semiconductor device according to one aspect of the present invention has good electrical characteristics, and by using this semiconductor device for a display device, the reliability of the display device can be improved.

[0448] The display portion 162 is an image display area in the display device 50A and includes a plurality of pixels 210 arranged periodically. Figure 27A An enlarged view of one pixel 210 is shown.

[0449] There is no particular limitation on the arrangement of the pixels in the display device of the present embodiment, and various methods can be adopted. As the arrangement of the pixels, for example, stripe arrangement, S-stripe arrangement, matrix arrangement, Delta arrangement, Bayer arrangement, and Pentile arrangement can be cited.

[0450] Figure 27AThe pixel 210 shown includes a sub-pixel 230R that presents red light, a sub-pixel 230G that presents green light, and a sub-pixel 230B that presents blue light. By using the sub-pixels 230R, 230G, and 230B to form a pixel 210, full-color display can be achieved. The sub-pixels 230R, 230G, and 230B are all used as sub-pixels. Additionally, in Figure 27A the display device 50A shown, an example of arranging pixels 230 used as sub-pixels in a stripe configuration is shown. The number of sub-pixels that make up a pixel 210 is not limited to three and can also be four or more. For example, it can also include four sub-pixels that present light of R, G, B, and white (W). Or, it can also include four sub-pixels that present four kinds of light of R, G, B, and Y.

[0451] The sub-pixels 230R, 230G, and 230B all include a display element and a circuit that controls the driving of the display element.

[0452] Various elements can be used as the display element. For example, a liquid crystal element and a light-emitting element can be cited. In addition to this, MEMS (Micro Electro Mechanical Systems) elements of a shutter method or a light interference method, display elements using a microcapsule method, an electrophoresis method, an electrowetting method, or an electronic ink (registered trademark) method, etc. can also be used. Additionally, a QLED (Quantum-dot LED) that utilizes a light source and a color conversion technology using a quantum dot material can also be used.

[0453] As a display device using a liquid crystal element, for example, a transmissive liquid crystal display device, a reflective liquid crystal display device, and a transflective liquid crystal display device can be cited.

[0454] As a mode applicable to a display device using a liquid crystal element, for example, a vertical alignment (VA) mode, a fringe field switching (FFS) mode, an in-plane switching (IPS) mode, a twisted nematic (TN) mode, an axially symmetric aligned micro-cell (ASM) mode, an optically compensated birefringence (OCB) mode, a ferroelectric liquid crystal (FLC) mode, an antiferroelectric liquid crystal (AFLC) mode, an electrically controlled birefringence (ECB) mode, and a guest-host mode can be cited. As the VA mode, for example, a multi-domain vertical alignment (MVA) mode, a patterned vertical alignment (PVA) mode, and an advanced super view (ASV) mode can be cited.

[0455] As a liquid crystal material applicable to a liquid crystal element, for example, a thermotropic liquid crystal, a low-molecular liquid crystal, a high-molecular liquid crystal, a polymer dispersed liquid crystal (PDLC), a polymer network liquid crystal (PNLC), a ferroelectric liquid crystal, and an antiferroelectric liquid crystal can be cited. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, a blue phase, etc. depending on conditions. In addition, as the liquid crystal material, either a positive-type liquid crystal or a negative-type liquid crystal can be used, and it can be selected according to the mode or design to be used.

[0456] As a light-emitting element, for example, a self-luminous light-emitting element such as a light emitting diode (LED), an organic LED (OLED), and a semiconductor laser can be cited. As the LED, for example, a small-sized LED, a micro-LED, etc. can be used.

[0457] Examples of the luminescent substance contained in the light-emitting element include a substance that emits fluorescence (fluorescent material), a substance that emits phosphorescence (phosphorescent material), a substance that exhibits thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) material), and an inorganic compound (quantum dot material, etc.).

[0458] The emission color of the light-emitting element may be infrared, red, green, blue, cyan, magenta, yellow, white, or the like. In addition, when the light-emitting element has a microcavity structure, the color purity can be further improved.

[0459] In a pair of electrodes included in the light-emitting element, one electrode is used as the anode and the other electrode is used as the cathode.

[0460] The display device according to one embodiment of the present invention may also adopt any one of the following structures: a top emission type that emits light in a direction opposite to the substrate on which the light-emitting element is formed, a bottom emission type that emits light to the side of the substrate on which the light-emitting element is formed, and a dual emission type that emits light from both sides.

[0461] In the present embodiment, the case where the light-emitting element is used as the display element is mainly described as an example.

[0462] Figure 27B It is a block diagram for explaining the display device 50A. The display device 50A includes a display unit 162 and a circuit unit 164. The display unit 162 includes a plurality of pixels 230 arranged periodically (pixels 230[1, 1] to pixels 230[m, n], where m and n are each independently an integer of 2 or more). The circuit unit 164 includes a first drive circuit unit 231 and a second drive circuit unit 232.

[0463] The circuits included in the first drive circuit unit 231 are used as, for example, a scan line drive circuit. The circuits included in the second drive circuit unit 232 are used as, for example, a signal line drive circuit. Note that a certain circuit may also be provided at a position opposite to the first drive circuit unit 231 with the display unit 162 interposed therebetween. A certain circuit may also be provided at a position opposite to the second drive circuit unit 232 with the display unit 162 interposed therebetween.

[0464] As the circuit unit 164, various circuits such as a shift register circuit, a level converter circuit, an inverter circuit, a latch circuit, an analog switch circuit, a demultiplexer circuit, and a logic circuit can be used. Transistors and capacitor elements can be used in the circuit unit 164. In addition, the transistors included in the circuit unit 164 can be formed by the same process as the transistors included in the pixels 230.

[0465] The display device 50A includes wirings 236 and 238 arranged substantially in parallel. The potential of the wiring 236 is controlled by a circuit included in the first drive circuit section 231, and the potential of the wiring 238 is controlled by a circuit included in the second drive circuit section 232. In Figure 27B , an example in which the wirings 236 and 238 are connected to the pixel 230 is shown. However, the wirings 236 and 238 are merely an example, and the wirings connected to the pixel 230 are not limited to the wirings 236 and 238.

[0466] A semiconductor device according to one embodiment of the present invention can form a vertical transistor (VFET) having a submicron channel length and a large on-state current and a TGSA-type transistor having a long channel length and high saturation using some processes in common. An oxide semiconductor (OS) can be appropriately used in the channel formation regions of these transistors, and transistors with a small off-state current can be realized. A semiconductor device according to one embodiment of the present invention can be appropriately used for one or both of the display section 162 and the circuit section 164. In addition, a semiconductor device according to one embodiment of the present invention can be used for both the display section 162 and the circuit section 164, that is, all the transistors included in the display device are OS transistors. Thus, by using OS transistors as all the transistors included in the display device, the effect of reducing the manufacturing cost can be achieved.

[0467] <Structural example of a drive circuit> As a circuit that can be used for the drive circuit, a structural example is described taking a latch circuit as an example.

[0468] Figure 28A It is a circuit diagram showing a structural example of the latch circuit LAT. Figure 28A The shown latch circuit LAT includes a transistor Tr31, a transistor Tr33, a transistor Tr35, a transistor Tr36, a capacitive element C31, and an inverter circuit INV. In Figure 28A , a node that electrically connects one of the source and drain of the transistor Tr33, the gate of the transistor Tr35, and one electrode of the capacitive element C31 is referred to as a node N.

[0469] In Figure 28AIn the latch circuit LAT shown, when a high-potential signal is input to the terminal SMP, the transistor Tr33 is turned on. Therefore, the potential of the node N becomes a potential corresponding to the potential of the terminal ROUT, and data corresponding to the signal input to the latch circuit LAT from the terminal ROUT is written to the latch circuit LAT. After writing data to the latch circuit LAT, by making the potential of the terminal SMP low, the transistor Tr33 is turned off. Therefore, the potential of the node N is held, and the data written to the latch circuit LAT is held. Specifically, for example, when the potential of the node N is low, the latch circuit LAT can hold data of "0", and when the potential of the node N is high, the latch circuit LAT can hold data of "1".

[0470] The transistor Tr33 preferably uses a transistor with a small off-state current. The transistor Tr33 can appropriately use an OS transistor. Therefore, the latch circuit LAT can hold data for a long time. Therefore, the frequency of writing data to the latch circuit LAT again can be reduced.

[0471] In this specification and the like, sometimes "writing data that outputs the signal input from the terminal SP2 to the terminal LIN to the latch circuit LAT" is simply referred to as "writing data to the latch circuit LAT". That is to say, for example, sometimes "writing data of '1' to the latch circuit LAT" is simply referred to as "writing data to the latch circuit LAT".

[0472] In the latch circuit LAT, a semiconductor device according to one aspect of the present invention can be appropriately used. For example, as one or more of the transistors Tr31, Tr33, Tr35, and Tr36, Figure 1B transistors 100 or transistors 200 shown etc. can be used.

[0473] Figure 28B The structural example of the inverter circuit INV is shown. The inverter circuit INV includes transistors Tr41, Tr43, Tr45, Tr47, and a capacitor element C41.

[0474] When the latch circuit LAT has Figure 28A the structure shown and the inverter circuit INV has Figure 28B the structure shown, all the transistors in the latch circuit LAT use transistors of the same polarity, for example, n-channel transistors. Thus, for example, in addition to the transistor Tr33, the transistors Tr31, Tr35, Tr36, Tr41, Tr43, Tr45, and Tr47 can also be OS transistors. Therefore, all the transistors in the latch circuit LAT can be manufactured by the same process.

[0475] In the inverter circuit INV, a semiconductor device according to one aspect of the present invention can be suitably used. For example, as one or more of the transistors Tr41, Tr43, Tr45, and Tr47, a transistor 100 or a transistor 200 as shown in Figure 1B etc. can be used.

[0476] By using one or more of the transistors 100 to 100D, the occupied area can be reduced, and thus a display device with a narrow border can be realized. In addition, as a transistor that is required to have a large on-state current, one or more of the transistors 100 to 100D can be suitably used. Furthermore, as a transistor that is required to have a high saturation, one or more of the transistors 200 to 200B can be suitably used. Thereby, a high-performance display device can be realized.

[0477] <Structural example 1 of pixel circuit> Figure 29A Shows a structural example of the pixel 230. The pixel 230 includes a pixel circuit 51 and a light-emitting device 61.

[0478] Figure 29A The pixel circuit 51 shown includes a transistor 52A, a transistor 52B, and a capacitor element 53. The pixel circuit 51 is a 2Tr1C type pixel circuit including two transistors and one capacitor element. Note that there is no particular limitation on the pixel circuit that can be used in one aspect of the present invention.

[0479] The anode of the light-emitting device 61 is electrically connected to one of the source and drain of the transistor 52B and one electrode of the capacitor element 53. The other of the source and drain of the transistor 52B is electrically connected to the wiring ANO. The gate of the transistor 52B is electrically connected to one of the source and drain of the transistor 52A and the other electrode of the capacitor element 53. The other of the source and drain of the transistor 52A is electrically connected to the wiring GL. The gate of the transistor 52A is electrically connected to the wiring GL. The cathode of the light-emitting device 61 is electrically connected to the wiring VCOM.

[0480] The wiring GL corresponds to the wiring 236, and the wiring SL corresponds to the wiring 238. The wiring VCOM is a wiring for supplying a potential for supplying current to the light-emitting device 61. The transistor 52A has a function of controlling the on-state or off-state between the wiring SL and the gate of the transistor 52B according to the potential of the wiring GL. For example, VDD is supplied to the wiring ANO, and VSS is supplied to the wiring VCOM.

[0481] The transistor 52B has a function of controlling the amount of electric current flowing through the light-emitting device 61. The capacitive element 53 has a function of holding the gate potential of the transistor 52B. The intensity of the light emitted by the light-emitting device 61 is controlled according to the image signal supplied to the gate of the transistor 52B.

[0482] A part or all of the transistors included in the pixel circuit 51 may also be provided with a back gate. Figure 29A The illustrated pixel circuit 51 shows a structure in which the transistor 52B includes a back gate and the back gate is electrically connected to one of the source and drain of the transistor 52B. In addition, the back gate of the transistor 52B may also be electrically connected to the gate of the transistor 52B.

[0483] The above semiconductor device can be applied to the pixel circuit 51. Preferably, the saturation of the transistor 52B, which serves as a driving transistor for controlling the current flowing through the light-emitting device 61, is higher than that of the transistor 52A, which serves as a selection transistor for controlling the selection state of the pixel 230. By using one of the transistors 200 to 200B with a long channel length as the transistor 52B, a display device with high reliability can be provided. In addition, by using one of the transistors 100 to 100D as the transistor 52A, the occupied area of the pixel circuit 51A can be reduced, and thus a high-definition display device can be realized.

[0484] Note that one of the transistors 100 to 100D may also be used as the transistor 52B. By using a transistor with a short channel length as the transistor 52B, a display device with high brightness can be realized. In addition, the occupied area of the pixel circuit 51 can be reduced, and thus a high-definition display device can be realized.

[0485] Figure 29B Shows a structure example different from Figure 29A the illustrated pixel 230. The pixel 230 includes a pixel circuit 51A and a light-emitting device 61.

[0486] Figure 29B The illustrated pixel circuit 51A is mainly different from Figure 29A the illustrated pixel circuit 51 in that it includes a transistor 52C. The pixel circuit 51A includes a transistor 52A, a transistor 52B, a transistor 52C, and a capacitive element 53. The pixel circuit 51A is a 3Tr1C type pixel circuit including three transistors and one capacitive element.

[0487] One of the source and drain of the transistor 52C is electrically connected to the other of the source and drain of the transistor 52B. The other of the source and drain of the transistor 52C is electrically connected to the wiring V0. For example, the wiring V0 is supplied with a reference potential. The gate of the transistor 52C is electrically connected to the wiring GL.

[0488] The transistor 52C has a function of controlling the conduction state or non-conduction state between one of the source and drain of the transistor 52B and the wiring V0 according to the potential of the wiring GL. The unevenness of the gate-source potential of the transistor 52B can be suppressed according to the reference potential of the wiring V0 supplied through the transistor 52C.

[0489] In addition, a current value that can be used for setting pixel parameters can be obtained using the wiring V0. Specifically, the wiring V0 can be used as a monitoring line for outputting the current flowing through the transistor 52B or the current flowing through the light-emitting device 61 to the outside. The current output to the wiring V0 can be converted into a voltage by a source follower circuit or the like and output to the outside. Alternatively, it can be converted into a digital signal by an AD converter or the like and output to the outside.

[0490] The above semiconductor device can be applied to the pixel circuit 51A. By using one of the transistors 200 to 200B having a long channel length as the transistor 52B, a display device with high reliability can be provided. In addition, by using one or more of the transistors 100 to 100D as the transistors 52A and 52C, the occupied area of the pixel circuit 51A can be reduced, and thus a high-definition display device can be realized. Note that one of the transistors 100 to 100D can also be used as the transistor 52B.

[0491] Figure 29C An example of the structure of the pixel circuit 51 is shown. Figure 29C It is a cross-sectional view of the pixel circuit 51. Figure 29C The abstract shows the pixel electrodes included in the transistor 52A, the transistor 52B, the capacitive element 53, and the light-emitting device 61. Note that the electrical connection between the transistor 52A and the transistor 52B is omitted.

[0492] The transistor 52A includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b. The transistor 52B includes a conductive layer 202, an insulating layer 106, a semiconductor layer 208, an insulating layer 120, a conductive layer 204, a conductive layer 212a, and a conductive layer 212b. Since the transistors 52A and 52B can be referred to the above description, the detailed description is omitted.

[0493] The capacitive element 53 includes a conductive layer 212a, a conductive layer 112p, and an insulating layer 106 sandwiched therebetween. The conductive layer 112p is provided on the insulating layer 120. The conductive layer 112p can be formed, for example, by the same process as the conductive layer 112b. An insulating layer 106 is provided on the conductive layer 112p, and a conductive layer 212a is provided on the insulating layer 106. The conductive layer 212a is used as one of the source electrode and the drain electrode of the transistor 52B and is also used as one electrode of the capacitive element 53. In addition, there is no particular limitation on the structure of the capacitive element 53.

[0494] An insulating layer 195 is provided so as to cover the transistor 52A, the transistor 52B, and the capacitive element 53. An insulating layer 233 is provided so as to cover the insulating layer 195, and an insulating layer 235 is provided so as to cover the insulating layer 233. A light-emitting device 61 can be provided on the insulating layer 235. Figure 29C The pixel electrode 111 used as one electrode of the light-emitting device 61 is shown. The insulating layer 195 and the insulating layer 233 have a first opening reaching the conductive layer 212a, and a conductive layer 234 is provided so as to cover the first opening. The conductive layer 234 is electrically connected to the conductive layer 212a through the first opening. The insulating layer 235 has a second opening reaching the conductive layer 234, and the pixel electrode 111 is provided so as to cover the second opening. The pixel electrode 111 is electrically connected to the conductive layer 234 through the second opening. The insulating layer 195 can be referred to the above description, so the detailed description is omitted. The insulating layer 233 and the insulating layer 235 have a function of reducing the unevenness due to the transistor 52A, the transistor 52B, and the transistor 52C to make the formation surface of the light-emitting device 61 flatter. In addition, in this specification, etc., the insulating layer 233 and the insulating layer 235 are sometimes referred to as a planarization layer.

[0495] The insulating layer 233 and the insulating layer 235 preferably use an organic insulating film. As materials that can be used for the organic insulating film, acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimide amide resin, silicone resin, benzocyclobutene resin, phenolic resin, and precursors of these resins can be used. The insulating layer 235 can also adopt a laminated structure of an organic insulating film and an inorganic insulating film. The insulating layer 235 preferably has a laminated structure of an organic insulating film and an inorganic insulating film on the organic insulating film. Thus, the inorganic insulating film can be used as an etching protection layer when forming the light-emitting device 61. Specifically, it is possible to suppress a part of the insulating layer 235 from being etched when forming the pixel electrode 111 and forming a recess in the insulating layer 235. Alternatively, a recess can be provided in the insulating layer 235 when forming the pixel electrode 111. Similarly, the insulating layer 233 can also adopt a laminated structure of an organic insulating film and an inorganic insulating film.

[0496] <Example 2 of the structure of the pixel circuit> Figure 30 An example of a structure different from the above-described pixel 230 is shown. The pixel 230 includes a pixel circuit 51B and a light-emitting device 61.

[0497] The pixel circuit 51B includes transistors M11, M12, M13, M14, M15, M16, a capacitor element C11, and a capacitor element C12. The pixel circuit 51B is a 6Tr2C type pixel circuit including six transistors and two capacitor elements.

[0498] The anode of the light-emitting device 61 is electrically connected to one of the source and drain of the transistor M15. The cathode of the light-emitting device 61 is electrically connected to the wiring VCOM. The other of the source and drain of the transistor M15 is electrically connected to one of the source and drain of the transistor M12, one of the source and drain of the transistor M13, one of the source and drain of the transistor M16, one electrode of the capacitor element C11, and one electrode of the capacitor element C12. The gate of the transistor M12 is electrically connected to one of the source and drain of the transistor M11, the other of the source and drain of the transistor M13, and the other electrode of the capacitor element C11. The back gate of the transistor M12 is electrically connected to one of the source and drain of the transistor M14 and the other electrode of the capacitor element C12.

[0499] The other of the source and drain of the transistor M11 is electrically connected to the wiring SL. The other of the source and drain of the transistor M12 is electrically connected to the wiring ANO. The other of the source and drain of the transistor M14 is electrically connected to the wiring V0. The other of the source and drain of the transistor M16 is electrically connected to the wiring V1. For example, a constant potential is supplied to the wiring V1. The gates of the transistor M11 and the transistor M16 are electrically connected to the wiring GL1. The gates of the transistor M13 and the transistor M14 are electrically connected to the wiring GL2. The gate of the transistor M15 is electrically connected to the wiring GL3.

[0500] The transistor M11 is used as a selection transistor that controls the conduction state or non-conduction state between the gate of the transistor M12 and the wiring SL. The transistor M12 is used as a driving transistor that controls the current flowing through the light-emitting device 61. The transistor M14 has a function of supplying the potential of the wiring V0 to the back gate of the transistor M12. By supplying a constant potential to the back gate of the transistor M12, the threshold voltage can be controlled. The capacitive element C11 has a function of holding the gate potential of the transistor M12. The capacitive element C12 has a function of holding the back gate potential of the transistor M12. The pixel circuit 51B has a so-called internal correction function of the threshold voltage that corrects the threshold voltage of the transistor M12 by the back gate. Specifically, the back gate potential that makes the threshold voltage of the transistor M12 0V is held in the capacitive element C12. Thus, regardless of the non-uniformity of the threshold voltage of the transistor and the deterioration over time, the threshold voltage of the transistor M12 can be constantly corrected to 0V or near it.

[0501] The above semiconductor device can be suitably used for the pixel circuit 51B. For example, as the transistors M11, M13, M14, M15, and M16, one or more of the transistors 100 to 100D shown below can be used, and as the transistor M12, one of the transistors 200 to 200B can be used. Figure 1B etc., and as the transistor M12, one of the transistors 200 to 200B can be used.

[0502] The transistor M12 used as the driving transistor preferably has high saturation. By using one of the transistors 200 to 200B with a long channel length as the transistor M12, a display device with high reliability can be realized. In addition, by using one or more of the transistors 100 to 100D as the transistors M11, M13, M14, M15, and M16, the occupied area of the pixel circuit 51B can be reduced, and thus a high-definition display device can be realized.

[0503] Note that one of the transistors 100 to 100D can also be used as the transistor M12. By using a transistor with a short channel length as the transistor M12, a display device with high brightness can be realized. In addition, the occupied area of the pixel circuit 51B can be reduced, and thus a high-definition display device can be realized.

[0504] By using a plurality of transistors and capacitive elements for the pixel circuit, a high-performance display device can be realized. By using the semiconductor device according to one aspect of the present invention, even if the number of transistors and capacitive elements increases, the occupied area can be reduced, and thus a high-performance and high-definition display device can be realized. For example, a display device with a definition of 300 ppi or more, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, or 3000 ppi or more can be realized.

[0505] A semiconductor device according to one embodiment of the present invention can reduce the occupied area, so that the aperture ratio of pixels can be increased in a bottom emission structure display device. For example, a display device with an aperture ratio of 50% or more, 55% or more, or 60% or more can be realized.

[0506] Note that in this specification and the like, the aperture ratio refers to the ratio of the area of the region where light is emitted to the pixel area.

[0507] Figures 31 to 33 A structural example showing the layout of pixel 230 is shown. Figure 31 corresponds to Figure 30 A top view of the circuit diagram shown. Figure 31 A pixel electrode 111 included in transistor M11, transistor M12, transistor M13, transistor M14, transistor M15, transistor M16, capacitor element C11, capacitor element C12, wiring GL1, wiring GL2, wiring GL3, wiring SL, wiring V1, wiring ANO, and light-emitting device 61 is shown. Note that in Figure 31 , in order to easily understand the structure below the pixel electrode 111, the pixel electrode 111 is shown with a transparent shadow. In addition, the wiring ANO includes wiring ANO_1 and wiring ANO_2. Wiring ANO_1 and wiring ANO_2 are electrically connected to each other and used as the wiring ANO. In Figure 31 , the wiring V0 is omitted.

[0508] Figure 32 is from Figure 31 A top view with the pixel electrode 111 removed. Figure 33 is from Figure 32 A top view with the wiring V1, wiring SL, and wiring ANO_2 removed. Note that in Figures 31 to 33 , the range of one pixel 230 is shown with a double-dot chain line.

[0509] Figure 34 , Figure 35A and Figure 35B respectively show Figure 31 A cross-sectional view of the cross-section along the dotted line G1-G2 in, a cross-sectional view of the cross-section along the dotted line B3-G4, and a cross-sectional view of the cross-section along the dotted line G5-G6 in.

[0510] Figures 31 to 3 5 shows an example in which the transistor 100 shown in Figure 1B and the like is used as transistor M11, transistor M13, transistor M14, transistor M15, and transistor M16, and the transistor 200 is used as transistor M12.

[0511] The transistor M11 includes a conductive layer 112a, a conductive layer 112b, a semiconductor layer 108, an insulating layer 106, and a conductive layer 104. In the transistor M11, the conductive layer 112b is used as one of the source electrode and the drain electrode, and the conductive layer 112a is used as the other of the source electrode and the drain electrode. A part of the insulating layer 106 is used as the gate insulating layer, and the conductive layer 104 is used as the gate electrode. In addition, the conductive layer 104 is used as the wiring GL1.

[0512] The conductive layer 112b and the insulating layer 110 have an opening 143 and an opening 141 in the region overlapping with the conductive layer 112a. The semiconductor layer 108 is disposed so as to cover the opening 143 and the opening 141. The insulating layer 106 is disposed on the semiconductor layer 108, and the conductive layer 104 is disposed on the insulating layer 106.

[0513] The transistor M12 includes a conductive layer 202, an insulating layer 120, a semiconductor layer 208, an insulating layer 106, a conductive layer 204, a conductive layer 212a, and a conductive layer 212b. In the transistor M12, the conductive layer 204 is used as the gate electrode (which can also be said to be the first gate electrode), and a part of the insulating layer 106 is used as the gate insulating layer (which can also be said to be the first gate insulating layer). The conductive layer 202 is used as the back gate electrode (which can also be said to be the second gate electrode), and a part of the insulating layer 120 is used as the back gate insulating layer (which can also be said to be the second gate insulating layer). The conductive layer 212a is used as one of the source electrode and the drain electrode, and the conductive layer 212b is used as the other of the source electrode and the drain electrode.

[0514] The conductive layer 202 is disposed on the insulating layer 110, and the insulating layer 120 is disposed so as to cover the conductive layer 202. The semiconductor layer 208 is disposed on the insulating layer 120, and the insulating layer 106 is disposed so as to cover the semiconductor layer 208. The conductive layer 204, the conductive layer 212a, and the conductive layer 212b are disposed on the insulating layer 106. The insulating layer 106 has an opening 147a and an opening 147b reaching the semiconductor layer 208, and the conductive layer 212a and the conductive layer 212b are in contact with the semiconductor layer 208 through the opening 147a and the opening 147b.

[0515] The insulating layer 106 has an opening 188 reaching the conductive layer 112b, and the conductive layer 204 is disposed so as to cover the opening 188. The conductive layer 204 is electrically connected to the conductive layer 112b through the opening 188.

[0516] Figure 36A A top view showing the conductive layer 112a is shown. In Figure 36A In addition to the conductive layer 112a, the conductive layer 112aA and the conductive layer 112aB are also shown, and they can be formed by the same process. The conductive layer 112aB is used as the wiring V0. The conductive layer 112aB (wiring V0) extends in the column direction.

[0517] Note that the horizontal and vertical directions of the drawings are regarded as the row direction and the column direction respectively, but not limited thereto, and the row direction and the column direction can also be swapped.

[0518] Figure 36B A top view showing the conductive layer 202 and the insulating layer 120. In Figure 36B the insulating layer 120 is shown by a dashed line.

[0519] Figure 36C A top view showing the conductive layer 112b. In Figure 36C in addition to the conductive layer 112b, the conductive layers 112bA, 112bB, 112bC, 112p, and 112q are also shown, and they can be formed by the same process. In the conductive layer 112b, in addition to the opening 143 in the transistor M11, the opening 143A in the transistor M13 is also provided. The opening 143B in the transistor M14 is provided in the conductive layer 112bA. The opening 143C in the transistor M15 is provided in the conductive layer 112bB. The opening 143D in the transistor M16 is provided in the conductive layer 112bC. The opening 143p is provided in the conductive layer 112p, and the opening 143q is provided in the conductive layer 112q. The openings 143 to 143D, the opening 143p, and the opening 143q can be formed by the same process. Note that in Figure 36C the top surface shapes of the opening 143p and the opening 143q are different from those of the openings 143 to 143D, but there is no particular limitation on the top surface shapes of the opening 143p and the opening 143q. For example, the top surface shapes of the openings 143 to 143D, the opening 143p, and the opening 143q can be circular. In addition, the openings 141 to 141D, the opening 141p, and the opening 141q are provided in the region of the insulating layer 110 that overlaps with the openings 143 to 143D, the opening 143p, and the opening 143q.

[0520] Figure 37A A top view showing the semiconductor layer 108 and the semiconductor layer 208. In Figure 37A in addition to the semiconductor layer 108 and the semiconductor layer 208, the semiconductor layers 108A, 108B, 108C, and 108D are also shown, and they can be formed by the same process.

[0521] Figure 37B A top view showing the conductive layers 104, 204, 212a, and 212b. In Figure 37BIn addition to the conductive layers 104, 204, 212a, and 212b, conductive layers 104A, 104B, 104p, 104q, 104r, 104s, and the wiring ANO_1 are also shown, and they can be formed by the same process. The conductive layer 104 is used as the wiring GL1, the conductive layer 104A is used as the wiring GL2, and the conductive layer 104B is used as the wiring GL3. The conductive layer 104 (wiring GL1), the conductive layer 104A (wiring GL2), the conductive layer 104B (wiring GL3), and the wiring ANO_1 extend in the row direction.

[0522] Figure 37C A top view showing the wiring V1, the wiring SL, and the wiring ANO_2. In Figure 37C In addition to the wiring V1, the wiring SL, and the wiring ANO_2, the conductive layer 234 is also shown, and they can be formed by the same process. The wiring V1, the wiring SL, and the wiring ANO_2 extend in the column direction.

[0523] As Figure 34 shown, an insulating layer 195 and an insulating layer 233 are provided on the wiring ANO_1. The insulating layer 195 and the insulating layer 233 have an opening 183 reaching the wiring ANO_1, and the wiring ANO_2 is provided so as to cover the opening 183. The wiring ANO_1 and the wiring ANO_2 are electrically connected to each other through the opening 183 and are used as the wiring ANO.

[0524] The conductive layer 112a in the transistor M11 is electrically connected to the wiring SL through the conductive layer 104s. The conductive layer 104s is electrically connected to the conductive layer 112a through the opening 190, the opening 143p, and the opening 141p. An opening 141p reaching the conductive layer 112a is provided in the insulating layer 110, and a conductive layer 112p having an opening 143p is provided on the insulating layer 110. An insulating layer 106 is provided on the conductive layer 112p, and an opening 190 is provided in a region of the insulating layer 106 overlapping the opening 143p. The conductive layer 104s is provided so as to cover the opening 190, the opening 143p, and the opening 141p. An insulating layer 195 and an insulating layer 233 are provided on the conductive layer 104s, an opening 191 is provided in a region of the insulating layer 195 and the insulating layer 233 overlapping the conductive layer 104s, and the wiring SL is provided so as to cover the opening 191.

[0525] The conductive layer 212a in the transistor M12 is electrically connected to the conductive layer 112aA through the opening 189, the opening 143q, and the opening 141q. The opening 141q reaching the conductive layer 212a is provided in the insulating layer 110, and the conductive layer 112q having the opening 143q is provided on the insulating layer 110. The insulating layer 106 is provided on the conductive layer 112q, and the opening 189 is provided in the region of the insulating layer 106 overlapping with the opening 143q. The conductive layer 212a is provided in a manner covering the opening 189, the opening 143q, and the opening 141q.

[0526] The transistor M13 includes a conductive layer 112aA, a conductive layer 112b, a semiconductor layer 108A, an insulating layer 106, and a conductive layer 104A. In the transistor M13, the conductive layer 112aA is used as one of the source electrode and the drain electrode, and the conductive layer 112b is used as the other of the source electrode and the drain electrode. A part of the insulating layer 106 is used as a gate insulating layer, and the conductive layer 104A is used as a gate electrode. The conductive layer 112b is used as one of the source electrode and the drain electrode of the transistor M11, and is also used as the other of the source electrode and the drain electrode of the transistor M13.

[0527] The conductive layer 112b and the insulating layer 110 have an opening 143A and an opening 141A in the region overlapping with the conductive layer 112aA. The semiconductor layer 108A is provided in a manner covering the opening 143A and the opening 141A. The insulating layer 106 is provided on the semiconductor layer 108A, and the conductive layer 104A is provided on the insulating layer 106.

[0528] The transistor M14 includes a conductive layer 112aB, a conductive layer 112bA, a semiconductor layer 108B, an insulating layer 106, and a conductive layer 104A. In the transistor M14, the conductive layer 112bA is used as one of the source electrode and the drain electrode, and the conductive layer 112aB is used as the other of the source electrode and the drain electrode. A part of the insulating layer 106 is used as a gate insulating layer, and the conductive layer 104A is used as a gate electrode. The conductive layer 104A is used as the gate electrode of the transistor M13 and is also used as the gate electrode of the transistor M14.

[0529] The conductive layer 112bA and the insulating layer 110 have an opening 143B and an opening 141B in the region overlapping with the conductive layer 112aB. The semiconductor layer 108B is provided in a manner covering the opening 143B and the opening 141B. The insulating layer 106 is provided on the semiconductor layer 108B, and the conductive layer 104A is provided on the insulating layer 106.

[0530] The transistor M15 includes a conductive layer 112aA, a conductive layer 112bB, a semiconductor layer 108C, an insulating layer 106, and a conductive layer 104B. In the transistor M15, the conductive layer 112bB is used as one of the source electrode and the drain electrode, and the conductive layer 112aA is used as the other of the source electrode and the drain electrode. A part of the insulating layer 106 is used as the gate insulating layer, and the conductive layer 104B is used as the gate electrode. The conductive layer 112aA is used as one of the source electrode and the drain electrode of the transistor M13, and is also used as the other of the source electrode and the drain electrode of the transistor M15.

[0531] The conductive layer 112bB and the insulating layer 110 have openings 143C and 141C in the region overlapping with the conductive layer 112aA. The semiconductor layer 108C is disposed so as to cover the openings 143C and 141C. The insulating layer 106 is provided on the semiconductor layer 108C, and the conductive layer 104B is provided on the insulating layer 106.

[0532] As Figure 34 shown, the conductive layer 112bB in the transistor M15 is electrically connected to the pixel electrode 111 through the conductive layer 104p and the conductive layer 234. The insulating layer 106 has an opening 181 reaching the conductive layer 112bB, and the conductive layer 104p is disposed so as to cover the opening 181. The insulating layer 195 and the insulating layer 233 are provided on the conductive layer 104p. The insulating layer 195 and the insulating layer 233 have an opening 182 reaching the conductive layer 104p, and the conductive layer 234 is disposed so as to cover the opening 182. The insulating layer 235 is provided on the conductive layer 234. The insulating layer 235 has an opening 184 reaching the conductive layer 234, and the pixel electrode 111 is disposed so as to cover the opening 184.

[0533] The transistor M16 includes a conductive layer 112aA, a conductive layer 112bC, a semiconductor layer 108D, an insulating layer 106, and a conductive layer 104. In the transistor M16, the conductive layer 112aA is used as one of the source electrode and the drain electrode, and the conductive layer 112bC is used as the other of the source electrode and the drain electrode. A part of the insulating layer 106 is used as the gate insulating layer, and the conductive layer 104 is used as the gate electrode. The conductive layer 112aA is used as one of the source electrode and the drain electrode of the transistor M13, the other of the source electrode and the drain electrode of the transistor M15, and is also used as one of the source electrode and the drain electrode of the transistor M16. The conductive layer 104 is used as the gate electrode of the transistor M11 and is also used as the gate electrode of the transistor M16.

[0534] The conductive layer 112bC and the insulating layer 110 have openings 143D and 141D in the region overlapping with the conductive layer 112aA. The semiconductor layer 108D is disposed so as to cover the openings 143D and 141D. An insulating layer 106 is provided on the semiconductor layer 108D, and a conductive layer 104 is provided on the insulating layer 106.

[0535] As Figure 35A shown, the capacitor element C12 is provided with a conductive layer 112aA, a conductive layer 202, an insulating layer 110 sandwiched between the conductive layer 112aA and the conductive layer 202, and an insulating layer 120 on the conductive layer 202. An insulating layer 120 is provided on the conductive layer 202. The insulating layer 120 has an opening 185 reaching the conductive layer 202, and a conductive layer 112bA is disposed so as to cover the opening 185. Note that there is no particular limitation on the top surface shape of the opening 185. An insulating layer 106 is provided on the conductive layer 112bA, and a conductive layer 104q is provided on the insulating layer 106. The conductive layer 104q is electrically connected to the conductive layer 112bA through openings 186 and 187 provided in the insulating layer 106. The conductive layer 104q can be formed by the same process as the conductive layers 104 and 204. For example, a material having a resistivity lower than that of the conductive layer 112bA is preferably used as the conductive layer 104q. Thereby, the wiring resistance between the capacitor element C12 and the transistor M14 can be reduced. Note that the conductive layer 104q may not be provided. Although a structure in which the conductive layer 112bA and the conductive layer 202 are electrically connected because the conductive layer 112bA has a region in contact with the conductive layer 202 is shown, one embodiment of the present invention is not limited thereto, and a structure in which the conductive layer 112bA does not have a region in contact with the conductive layer 202 and the conductive layer 112bA and the conductive layer 202 are electrically connected through the conductive layer 104q may also be employed. Specifically, the conductive layer 112bA may not be provided in the opening 185, and the conductive layer 104q may be disposed so as to cover the openings 185 and 187.

[0536] As Figure 35B shown, the capacitor element C11 includes a conductive layer 112b, a conductive layer 212a, and an insulating layer 106 sandwiched between the conductive layer 112b and the conductive layer 212a.

[0537] The conductive layer 112a serving as the other of the source electrode and the drain electrode of the transistor M11 is electrically connected to the wiring SL through the conductive layer 104s. Openings 190 reaching the conductive layer 112a are provided in the insulating layer 110 and the insulating layer 106, and the conductive layer 104s is disposed so as to cover the openings 190. An insulating layer 195 and an insulating layer 233 are provided on the conductive layer 104s. Openings 191 reaching the conductive layer 104s are provided in the insulating layer 195 and the insulating layer 233, and the wiring SL is disposed so as to cover the openings 191.

[0538] The conductive layer 212b, which serves as the other of the source electrode and the drain electrode of the transistor M12, is electrically connected to the wiring ANO_2 through the opening 193. Openings 193 reaching the conductive layer 212b are provided in the insulating layer 195 and the insulating layer 233, and the wiring ANO_2 is provided so as to cover the openings 193.

[0539] The conductive layer 112bC, which serves as the other of the source electrode and the drain electrode of the transistor M16, is electrically connected to the wiring V1 through the conductive layer 104r. An opening 194 reaching the conductive layer 112bC is provided in the insulating layer 106, and the conductive layer 104r is provided so as to cover the opening 194. The insulating layer 195 and the insulating layer 233 are provided on the conductive layer 104r. Openings 196 reaching the conductive layer 104r are provided in the insulating layer 195 and the insulating layer 233, and the wiring V1 is provided so as to cover the openings 196.

[0540] Figure 38 The layout in which the sub-pixels are arranged in 3 rows and 6 columns is shown. Figure 38 Six pixels 230R (pixels 230R[p, q] to pixels 230R[p + 2, q + 1], where p and q are each independently an integer of 2 or more), six pixels 230G (pixels 230G[p, q] to pixels 230G[p + 2, q + 1]), and six pixels 230B (pixels 230B[p, q] to pixels 230B[p + 2, q + 1]), which serve as sub-pixels, are shown. These sub-pixels are arranged in a stripe pattern. One pixel 230R, one pixel 230G, and one pixel 230B are used as one pixel 210. Figure 38 The pixels 210 (pixels 210[p, q] to pixels 210[p + 2, q + 1]) arranged in 3 rows and 2 columns are shown. Figure 39 It shows the correspondence to Figure 38 the configurations of the respective pixels 230R, pixels 230G, and pixels 230B. Each of the pixels 230R, pixels 230G, and pixels 230B can adopt the layout of the above-mentioned pixel 230.

[0541] Figure 38 The layout in which the adjacent pixels 230 are axisymmetric with respect to their boundaries is shown. Specifically, the layouts of the pixels 230R[p, q], pixels 230R[p + 1, q], and pixels 230R[p + 2, q] provided in the same column and the layouts of the pixels 230G[p, q], pixels 230G[p + 1, q], and pixels 230G[p + 2, q] provided in the adjacent column are axisymmetric with respect to the boundaries of these columns (refer to Figure 38arrow A). In addition, the layout of pixel 230G[p, q], pixel 230G[p + 1, q], and pixel 230G[p + 2, q] is axisymmetric with respect to the boundary of these columns with the layout of pixel 230B[p, q], pixel 230B[p + 1, q], and pixel 230B[p + 2, q] set on adjacent columns (refer to Figure 38 arrow B). Since the subsequent layout is the same, detailed description is omitted.

[0542] The layout of pixel 230R[p, q], pixel 230G[p, q], pixel 230B[p, q], pixel 230R[p, q + 1], pixel 230G[p, q + 1], and pixel 230B[p, q + 1] set on the same row is axisymmetric with respect to the boundary of these rows with the layout of pixel 230R[p + 1, q], pixel 230G[p + 1, q], pixel 230B[p + 1, q], pixel 230R[p + 1, q + 1], pixel 230G[p + 1, q + 1], and pixel 230B[p + 1, q + 1] set on adjacent rows (refer to Figure 38 arrow C). In addition, the layout of pixel 230R[p + 1, q], pixel 230G[p + 1, q], pixel 230B[p + 1, q], pixel 230R[p + 1, q + 1], pixel 230G[p + 1, q + 1], and pixel 230B[p + 1, q + 1] is axisymmetric with respect to the boundary of these rows with the layout of pixel 230R[p + 2, q], pixel 230G[p + 2, q], pixel 230B[p + 2, q], pixel 230R[p + 2, q + 1], pixel 230G[p + 2, q + 1], and pixel 230B[p + 2, q + 1] set on adjacent rows (refer to Figure 38 arrow D). Since the subsequent layout is the same, detailed description is omitted.

[0543] Pixel 230 shares wirings, etc. with adjacent pixels 230. Figures 40A to 42B An enlarged view showing pixel 230R[p + 1, q], pixel 230G[p + 1, q], pixel 230B[p + 1, q], and its vicinity is shown.

[0544] Pixels 230 set on the same column share wiring ANO_2 and wiring V0 with pixels 230 set on adjacent columns. In addition, pixels 230 share opening 183 and opening 193 with pixels 230 set on adjacent columns. Specifically, pixel 230R[p + 1, q] and pixel 230R[p + 2, q] set on the same column share wiring ANO_2 and wiring V0 with pixel 230G[p + 1, q] and pixel 230G[p + 2, q] set on adjacent columns (refer to Figure 40A andFigure 42B arrow A). In addition, pixel 230R[p+1, q] and pixel 230G[p+1, q] arranged on an adjacent column share opening 183 and opening 193 (see Figure 40A and Figure 42B arrow A).

[0545] Pixels 230 arranged on the same column and pixels 230 arranged on an adjacent column share wiring V1. Specifically, pixel 230G[p+1, q] and pixel 230G[p+2, q] arranged on the same column and pixel 230B[p+1, q] and pixel 230B[p+2, q] arranged on an adjacent column share wiring V1 (see Figure 42B arrow B). In addition, wiring ANO_2 and wiring V0 shared among pixels 230 and wiring V1 shared among pixels 230 are alternately arranged (see Figure 38 and Figure 42B arrow A and arrow B).

[0546] Wiring V0 corresponds to Figure 36A the conductive layer 112aB shown in etc. It can also be said that pixels 230 arranged on the same column and pixels 230 arranged on an adjacent column share the conductive layer 112aB (wiring V0) included in transistor M14 (see Figure 40A arrow A). In addition, pixels 230 and pixels 230 arranged on an adjacent column share the semiconductor layer 208, conductive layer 212b, and opening 147b included in transistor M12 (see Figure 41B and Figure 42A arrow A). Furthermore, pixels 230 can also share insulating layer 120 with pixels 230 arranged on an adjacent column. Figure 40B An example in which pixel 230R[p+1, q] and pixel 230G[p+1, q] arranged on an adjacent column share insulating layer 120 is shown (see Figure 40B arrow A). Insulating layer 120 surrounds the conductive layer 204 in pixel 230R[p+1, q] and the conductive layer 204 in pixel 230G[p+1, q]. Insulating layer 120 is in contact with the top surface and side surfaces of the conductive layer 204 in pixel 230R[p+1, q] and the top surface and side surfaces of the conductive layer 204 in pixel 230G[p+1, q]. In addition, adjacent pixels 230 may not share insulating layer 120.

[0547] Pixels 230 arranged on the same row share the wiring ANO_1 with pixels 230 arranged on an adjacent row. Specifically, pixels 230R[p, q], pixels 230G[p, q], pixels 230B[p, q], pixels 230R[p, q + 1], pixels 230G[p, q + 1], and pixels 230B[p, q + 1] arranged on the same row share the wiring ANO_1 with pixels 230R[p + 1, q], pixels 230G[p + 1, q], pixels 230B[p + 1, q], pixels 230R[p + 1, q + 1], pixels 230G[p + 1, q + 1], and pixels 230B[p + 1, q + 1] arranged on an adjacent row (see Figure 42A for arrow C).

[0548] Pixels 230 share the conductive layer 112a, conductive layer 104s, opening 190, opening 194, and opening 191 included in the transistor M11 with pixels 230 arranged on an adjacent row (see Figure 40A , Figure 42A and Figure 42B for arrow D).

[0549] Two adjacent rows and two columns of pixels 230 share the conductive layer 104r, opening 196, and the conductive layer 112bC included in the transistor M16. Specifically, pixels 230G[p + 1, q], pixels 230G[p + 2, q], pixels 230B[p + 1, q], and pixels 230B[p + 2, q] share the conductive layer 104r and the conductive layer 112bC (see Figure 41A , Figure 42A and Figure 42B for arrow B and arrow D).

[0550] By sharing components among adjacent pixels, the occupied area of the pixel circuit can be reduced, thereby enabling a high-definition display device. Note that although a structure in which components are shared among adjacent pixels is shown here, one aspect of the present invention is not limited to this, and components may not be shared among adjacent pixels either.

[0551] An example of a structure different from the above-described display device will be described.

[0552] <Structural Example 1 of Display Device> Figure 43A An example of a cross-section showing a part of the region including the FPC 172, a part of the circuit section 164, a part of the display section 162, a part of the connection section 140, and a part of the region including the end portion of the display device 50A is shown.

[0553] Figure 43AThe display device 50A shown includes a transistor 205D, a transistor 205R, a transistor 205G, a transistor 207G, a transistor 207B, a light-emitting element 130R, a light-emitting element 130G, a light-emitting element 130B, etc. between a substrate 151 and a substrate 152. The light-emitting element 130R is a display element included in a pixel 230R that presents red light, the light-emitting element 130G is a display element included in a pixel 230G that presents green light, and the light-emitting element 130B is a display element included in a pixel 230B that presents blue light.

[0554] The display device 50A adopts an SBS structure. In the SBS structure, the materials and structures of the respective light-emitting elements can be optimized separately, the degree of freedom in the selection of materials and structures increases, and it becomes easy to improve the brightness and reliability.

[0555] The display device 50A adopts a top emission type. In the top emission type, transistors and the like can be arranged in a manner over...

Claims

1. A semiconductor device, comprising: a transistor; and a first insulating layer, wherein the transistor includes a first conductive layer, a second conductive layer having a region overlapping with the first conductive layer across the first insulating layer, and a semiconductor layer, the second conductive layer has a first opening in a region overlapping with the first conductive layer, the first insulating layer has a second opening reaching the first conductive layer in a region overlapping with the first opening, the semiconductor layer contacts the top surface of the first conductive layer, the side surface of the first insulating layer, and the side surface of the second conductive layer in the first opening and the second opening, Moreover, the oxygen diffusion coefficient of the first insulating layer at 350 °C is 5×10 -12 cm 2 / sec or more.

2. The semiconductor device according to claim 1, wherein the diffusion coefficient of oxygen is calculated by thermal desorption spectroscopy or secondary ion mass spectrometry.

3. The semiconductor device according to claim 1, wherein the semiconductor layer contains a metal oxide.

4. The semiconductor device according to any one of claims 1 to 3, further comprising a second insulating layer and a third insulating layer, wherein the second insulating layer is located between the first insulating layer and the first conductive layer, the third insulating layer is located between the first insulating layer and the second conductive layer, the first insulating layer contains an oxide or an oxynitride, and each of the second insulating layer and the third insulating layer contains a nitride or a nitrogen oxide.

5. The semiconductor device according to claim 4, further comprising a fourth insulating layer, wherein the fourth insulating layer is located between the second insulating layer and the first conductive layer, and the fourth insulating layer has a region with a higher hydrogen content than the second insulating layer.

6. The semiconductor device according to claim 4, further comprising a fifth insulating layer, wherein the fifth insulating layer is located between the third insulating layer and the second conductive layer, and the fifth insulating layer has a region with a higher hydrogen content than the third insulating layer.

7. A semiconductor device, comprising: a first transistor; a second transistor; and a first insulating layer, wherein the first transistor includes a first conductive layer, a second conductive layer having a region overlapping with the first conductive layer across the first insulating layer, and a first semiconductor layer, the second conductive layer has a first opening in a region overlapping with the first conductive layer, the first insulating layer has a second opening reaching the first conductive layer in a region overlapping with the first opening, the first semiconductor layer contacts the top surface of the first conductive layer, the side surface of the first insulating layer, and the side surface of the second conductive layer in the first opening and the second opening, the second transistor includes a third conductive layer on the first insulating layer, a second semiconductor layer, and a second insulating layer located between the third conductive layer and the second semiconductor layer, the second insulating layer contacts the top surface and the side surface of the third conductive layer, and the diffusion coefficient of oxygen in the first insulating layer is larger than the diffusion coefficient of oxygen in the second insulating layer.

8. The semiconductor device according to claim 7, wherein the diffusion coefficient of oxygen is calculated by thermal desorption spectroscopy or secondary ion mass spectrometry.

9. The semiconductor device according to claim 7, wherein each of the first semiconductor layer and the second semiconductor layer contains a metal oxide.

10. The semiconductor device according to claim 7, wherein the second conductive layer and the third conductive layer are made of different materials.

11. The semiconductor device according to claim 7, wherein the second conductive layer and the third conductive layer are made of the same material.

12. A semiconductor device, comprising: a first transistor; a second transistor; and a first insulating layer, wherein the first transistor includes a first conductive layer, a second conductive layer having a region overlapping with the first conductive layer across the first insulating layer, and a first semiconductor layer, the second conductive layer has a first opening in a region overlapping with the first conductive layer, the first insulating layer has a second opening reaching the first conductive layer in a region overlapping with the first opening, the first semiconductor layer contacts the top surface of the first conductive layer, the side surface of the first insulating layer, and the side surface of the second conductive layer in the first opening and the second opening, the second transistor includes a third conductive layer on the first insulating layer, a second semiconductor layer, and a second insulating layer located between the third conductive layer and the second semiconductor layer, the second insulating layer contacts the top surface and the side surface of the third conductive layer, and an etching rate of an etchant for the first insulating layer is faster than an etching rate of the second insulating layer.

13. The semiconductor device according to claim 12, wherein the etchant contains hydrofluoric acid.

14. The semiconductor device according to claim 12, wherein each of the first semiconductor layer and the second semiconductor layer contains a metal oxide.

15. The semiconductor device according to claim 12, wherein the second conductive layer and the third conductive layer are made of different materials.

16. The semiconductor device according to claim 12, wherein the second conductive layer and the third conductive layer are made of the same material.

17. The semiconductor device according to any one of claims 7 to 16, further comprising a third insulating layer and a fourth insulating layer, wherein the third insulating layer is located between the first insulating layer and the first conductive layer, the fourth insulating layer is located between the first insulating layer and the second conductive layer, the fourth insulating layer is located between the first insulating layer and the third conductive layer, the first insulating layer contains an oxide or an oxynitride, and each of the third insulating layer and the fourth insulating layer contains a nitride or a nitroxide.

18. The semiconductor device according to claim 17, further comprising a fifth insulating layer, wherein the fifth insulating layer is located between the third insulating layer and the first conductive layer, and the fifth insulating layer has a region with a higher hydrogen content than the third insulating layer.

19. The semiconductor device according to claim 17, further comprising a sixth insulating layer, wherein the sixth insulating layer is located between the fourth insulating layer and the second conductive layer, the sixth insulating layer is located between the fourth insulating layer and the third conductive layer, And the sixth insulating layer has a region where the amount of hydrogen thereof is greater than that of the fourth insulating layer.

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