Silicon-based gallium nitride epitaxial structure with low radio frequency loss and preparation method

Abstract

The invention discloses a silicon-based gallium nitride epitaxial structure with low radio frequency loss and a preparation method, and relates to the technical field of semiconductors, and the silicon-based gallium nitride epitaxial structure comprises a substrate which comprises a pretreatment layer which is located at one side of the substrate and comprises a plurality of silicon dioxide units which are arranged at intervals; wherein the substrate is a monocrystalline silicon substrate; the nucleating layer and the substrate are stacked, and the nucleating layer is located on the surface, where the pretreatment layer is arranged, of the substrate; the gradient superlattice buffer layer is stacked with the nucleation layer and is located on the surface, away from the substrate, of the nucleation layer; and the gallium nitride layer is laminated with the gradual change superlattice buffer layer and is positioned on the surface, deviating from the substrate, of the gradual change superlattice buffer layer. According to the invention, the radio frequency loss of the silicon-based gallium nitride device can be reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductors, and particularly relates to a silicon-based gallium nitride epitaxial structure with low radio frequency loss and a preparation method thereof. Background Art

[0002] The radio frequency field is an important application scenario of gallium nitride (GaN) technology. Due to its excellent electron mobility, high saturation velocity, high breakdown voltage, and strong radiation resistance, GaN materials have become the core technology for the construction of 5G base stations. Gallium nitride power amplifiers can significantly improve the performance of base stations while reducing the volume and power consumption of equipment. With the rapid deployment of 5G networks, the application proportion of gallium nitride power amplifiers in base station equipment continues to climb, and it will also contribute to the development of 6G networks in the future.

[0003] Among them, epitaxially growing gallium nitride materials on a silicon substrate has great advantages in terms of process adaptability and cost control, and can be integrated with CMOS processes to achieve higher integration chips. In addition, the performance of silicon-based gallium nitride is slightly inferior to that of silicon carbide-based gallium nitride, but it can already reach 5-8 times the power density of LDMOS. When the frequency is higher than 2 GHz, the cost is similar to that of LDMOS with the same performance.

[0004] However, in the process of directly epitaxially growing gallium nitride materials on a silicon substrate, due to the large lattice mismatch and thermal mismatch between the silicon substrate and the gallium nitride materials, directly epitaxially growing gallium nitride materials on the silicon substrate will result in poor crystal quality of gallium nitride, or the gallium nitride epitaxial layer will directly break during the cooling process. To solve this problem, a relatively thick nucleation layer or a graded buffer layer is usually introduced between the silicon substrate and the gallium nitride epitaxial layer. However, when epitaxially growing an AlN nucleation layer and an AlGaN graded buffer layer, due to the diffusion of Al and Ga atoms on the surface and inside of the silicon substrate, a P-type conductive channel is formed at the interface between the Si substrate and the AlN nucleation layer. The existence of the P-type conductive channel will cause a large radio frequency loss problem in Si-based GaN materials, resulting in signal transmission loss, affecting the accuracy of signals and the working efficiency of devices, and seriously affecting device performance, including output power, power added efficiency, gain, etc.

[0005] To solve this problem, it is necessary to reduce the concentration of the P-type conductive channel at the AlN / Si interface. Currently, the main solutions are: one is to reduce the growth temperature and thickness of AlN; the other is to neutralize the diffusion of Al and Ga by ion implanting P ions at the AlN / Si interface. However, the crystal quality of Si-based GaN obtained by these methods is still poor compared with other substrates and needs to be further improved. Summary of the Invention

[0006] To solve the above problems existing in the prior art, the present invention provides a silicon-based gallium nitride epitaxial structure with low radio frequency loss and a preparation method thereof. The technical problems to be solved by the present invention are realized through the following technical solutions:

[0007] In a first aspect, the present invention provides a silicon-based gallium nitride epitaxial structure with low radio frequency loss, including:

[0008] A substrate, including a pretreatment layer, located on one side of the substrate. The pretreatment layer includes a plurality of spaced-apart silicon dioxide units; wherein, the substrate is a single crystal silicon substrate;

[0009] A nucleation layer, stacked with the substrate layer, located on the surface of the substrate where the pretreatment layer is provided;

[0010] A graded superlattice buffer layer, stacked with the nucleation layer, located on the surface of the nucleation layer facing away from the substrate;

[0011] A gallium nitride layer, stacked with the graded superlattice buffer layer, located on the surface of the graded superlattice buffer layer facing away from the substrate.

[0012] In a second aspect, the present invention further provides a preparation method of a silicon-based gallium nitride epitaxial structure with low radio frequency loss, used to prepare the above-mentioned silicon-based gallium nitride epitaxial structure with low radio frequency loss, including:

[0013] Providing a substrate; wherein, the substrate is a single crystal silicon substrate;

[0014] Fabricating a photoresist mask pattern on the substrate;

[0015] Performing oxygen ion implantation on one side of the substrate where the photoresist mask pattern is provided, and then removing the photoresist mask pattern;

[0016] Performing thermal annealing on the substrate to form a plurality of spaced-apart silicon dioxide units, constituting the pretreatment layer;

[0017] Growing a nucleation layer on the surface of the substrate where the pretreatment layer is provided;

[0018] Growing a graded superlattice buffer layer on the surface of the nucleation layer facing away from the substrate;

[0019] Growing a gallium nitride layer on the surface of the graded superlattice buffer layer facing away from the substrate.

[0020] Advantages of the present invention:

[0021] A silicon-based gallium nitride epitaxial structure with low radio frequency loss and a preparation method thereof provided by the present invention include a Si substrate, an AlN nucleation layer, an AlGaN graded buffer layer, and a GaN layer stacked in sequence. Silica units are arranged at intervals in the Si substrate. Since the diffusion rate of Al atoms in the Si substrate is much smaller than that of SiO2 in the Si substrate, compared with the Si substrate region without silica units, the P-type conductive channels caused by Al diffusion in the silica units are almost non-existent. Moreover, O is N-type conductive in the Si substrate, and the excess O diffusing into the Si substrate will further neutralize the P-type conductive channels caused by Al diffusion in the Si substrate, reducing the concentration of P-type conductive channels in the substrate, thereby reducing radio frequency loss.

[0022] In addition, due to the large lattice mismatch (16.9%) and thermal expansion coefficient mismatch (56%) between GaN and Si crystals, setting a GaN epitaxial layer on the Si substrate not only has a high dislocation density, but also the tensile stress caused by thermal mismatch will make it have a large residual strain. In this embodiment, SiO2 regions are formed on the high-resistance silicon substrate. Since the thermal expansion coefficients of Si and SiO2 are different, the introduction of SiO2 units will generate compressive strain due to the difference in thermal expansion coefficients, which can further compensate for the tensile stress caused by thermal mismatch, thereby improving the crystal quality of GaN and reducing the dislocation density and warping of GaN.

[0023] The present invention will be further described in detail below with reference to the drawings and embodiments. Description of the Drawings

[0024] Figure 1 is a schematic diagram of a silicon-based gallium nitride epitaxial structure with low radio frequency loss provided by an embodiment of the present invention;

[0025] Figure 2 is a flowchart of a preparation method of a silicon-based gallium nitride epitaxial structure with low radio frequency loss provided by an embodiment of the present invention;

[0026] Figure 3 is a schematic diagram of a preparation method of a silicon-based gallium nitride epitaxial structure with low radio frequency loss provided by an embodiment of the present invention. Detailed Embodiments

[0027] The present invention will be further described in detail below with specific embodiments, but the embodiments of the present invention are not limited thereto.

[0028] Please refer to Figure 1 , Figure 1 is a schematic diagram of a silicon-based gallium nitride epitaxial structure with low radio frequency loss provided by an embodiment of the present invention. A silicon-based gallium nitride epitaxial structure with low radio frequency loss provided by the present invention includes:

[0029] The substrate 10 includes a pretreatment layer 20 located on one side of the substrate 10. The pretreatment layer 20 includes a plurality of spaced-apart silicon dioxide units 21. Optionally, the substrate 10 is a high-resistivity silicon substrate;

[0030] The nucleation layer 30 is stacked with the substrate 10 and is located on the surface of the substrate 10 where the pretreatment layer 20 is provided. Optionally, the nucleation layer 30 is an AlN nucleation layer;

[0031] The graded superlattice buffer layer 40 is stacked with the nucleation layer 30 and is located on the surface of the nucleation layer 30 facing away from the substrate 10. Optionally, the graded superlattice buffer layer 40 is an AlGaN graded buffer layer;

[0032] The gallium nitride layer 50 is stacked with the graded superlattice buffer layer 40 and is located on the surface of the graded superlattice buffer layer 40 facing away from the substrate 10.

[0033] Specifically, please continue to refer to Figure 1 , the silicon-based gallium nitride epitaxial structure with low radio frequency loss provided in this embodiment includes an Si substrate 10, an AlN nucleation layer, an AlGaN graded buffer layer, and a GaN layer stacked in sequence. The Si substrate 10 is provided with spaced-apart silicon dioxide units 21. Since the diffusion rate of Al atoms in the Si substrate is much smaller than that of SiO2 in the Si substrate, the diffusion efficiency of Al atoms in SiO2 is small, resulting in very little Al atoms diffusing in SiO2. And the bond energy of the Si-Si bond is about 178 kJ / mol, and the bond energy of the Si-O bond is about 460 kJ / mol. Under the same conditions, more energy is required for Al atoms to undergo substitutional diffusion with SiO2. Compared with the Si substrate region without the silicon dioxide units 21, the P-type conductive channels caused by Al diffusion in the silicon dioxide units 21 are almost non-existent. And, O is N-type conductive in the Si substrate, and the excess O diffusing into the Si substrate will further neutralize the P-type conductive channels caused by Al diffusion in the Si substrate, reducing the concentration of P-type conductive channels in the substrate 10, thereby reducing the radio frequency loss.

[0034] In addition, due to the large lattice mismatch (16.9%) and thermal expansion coefficient mismatch (56%) between GaN and Si crystals, setting a GaN epitaxial layer on the Si substrate not only has a high dislocation density, but also the tensile stress caused by the thermal mismatch will make it have a large residual strain. In this embodiment, SiO2 regions are formed on the high-resistivity silicon substrate. Since the thermal expansion coefficients of Si and SiO2 are different, the introduction of the SiO2 units will generate compressive strain due to the difference in thermal expansion coefficients, which can further compensate for the tensile stress caused by the thermal mismatch, thereby improving the crystal quality of GaN and reducing the dislocation density and warpage of GaN.

[0035] In an alternative embodiment of the present invention, the resistivity of the substrate 10 is greater than or equal to 5000 Ω·cm.

[0036] Specifically, in this embodiment, the substrate 10 is a high-resistivity silicon substrate with a resistivity greater than or equal to 5000 Ω·cm. Optionally, the resistivity of the substrate 10 is 5500 Ω·cm.

[0037] It should be noted that there are relatively high electron or hole concentrations in a low-resistivity silicon substrate. During the transmission of microwave signals, these electrons or holes will scatter, resulting in relatively large signal losses. Compared with a high-resistivity silicon substrate, it can better reduce signal losses.

[0038] In an alternative embodiment of the present invention, the thickness of the substrate 10 is 0.6 - 1 mm, the thickness of the pretreatment layer 20 is 20 - 100 nm, the thickness of the nucleation layer 30 is 100 - 300 nm, the thickness of the graded superlattice buffer layer 40 is 2 - 3 μm, and the thickness of the gallium nitride layer 50 is 1.5 - 3 μm.

[0039] Specifically, in this embodiment, the thickness of the substrate 10 can be 0.8 mm or 0.9 mm. The thickness of the silicon dioxide unit 21 in the pretreatment layer 20 can be 40 nm, 60 nm, or 80 nm. The thickness of the nucleation layer 30 can be 150 nm, 200 nm, or 250 nm. The thickness of the graded superlattice buffer layer 40 can be 2.4 μm or 2.6 μm. The thickness of the gallium nitride layer 50 can be 1.8 μm, 2.4 μm, or 2.8 μm.

[0040] Based on the same inventive concept, please refer to Figure 2 and Figure 3 , Figure 2 is a flowchart of a method for fabricating a low-radio-frequency-loss silicon-based gallium nitride epitaxial structure provided by an embodiment of the present invention. Figure 3 is a schematic diagram of a method for fabricating a low-radio-frequency-loss silicon-based gallium nitride epitaxial structure provided by an embodiment of the present invention. The present invention also provides a method for fabricating a low-radio-frequency-loss silicon-based gallium nitride epitaxial structure for fabricating the low-radio-frequency-loss silicon-based gallium nitride epitaxial structure provided by the above embodiments of the present invention. For the embodiments of the method, please refer to the above, and details will not be repeated here. The fabrication method includes:

[0041] S101: Provide a substrate 10; wherein, the substrate 10 is a single-crystalline silicon substrate;

[0042] S102: Fabricate a photoresist mask pattern on the substrate 10;

[0043] S103: Perform oxygen ion implantation on one side of the substrate 10 where the photoresist mask pattern is set, and then remove the photoresist mask pattern;

[0044] S104. Perform a thermal annealing treatment on the substrate 10 to form a plurality of spaced-apart silicon dioxide units 21, constituting a pretreatment layer 20;

[0045] S105. Grow a nucleation layer 30 on the surface of the substrate 10 where the pretreatment layer 20 is provided;

[0046] S106. Grow a graded superlattice buffer layer 40 on the surface of the nucleation layer 30 facing away from the substrate 10;

[0047] S107. Grow a gallium nitride layer 50 on the surface of the graded superlattice buffer layer 40 facing away from the substrate 10.

[0048] Specifically, please continue to refer to Figure 3 , in this embodiment, a photoresist mask pattern is first set on the provided substrate 10, oxygen ion implantation is carried out, and then high-temperature thermal annealing is continued. A plurality of spaced-apart silicon dioxide units 21 are formed on one side of the substrate 10. It can also be understood that oxygen ion implantation is carried out in the area of the substrate 10 not covered by the photoresist mask pattern, and silicon dioxide units 21 are formed in this area; since the diffusion rate of Al atoms in the Si substrate is much smaller than the diffusion rate of SiO2 in the Si substrate, the diffusion efficiency of Al atoms in SiO2 is small, resulting in very few Al atoms diffusing in SiO2. And the bond energy of the Si-Si bond is about 178 kJ / mol, and the bond energy of the Si-O bond is about 460 kJ / mol. Under the same conditions, more energy is required for Al atoms to undergo substitutional diffusion with SiO2. Compared with the Si substrate area without silicon dioxide units 21, the P-type conductive channels caused by Al diffusion in the silicon dioxide units 21 are almost non-existent; moreover, O is N-type conductive in the Si substrate 10, and the excess O diffusing into the Si substrate will further neutralize the P-type conductive channels caused by Al diffusion in the Si substrate, reducing the concentration of P-type conductive channels in the substrate, thereby reducing radio frequency loss.

[0049] In addition, due to the large lattice mismatch (16.9%) and thermal expansion coefficient mismatch (56%) between GaN and the Si crystal, setting a GaN epitaxial layer on the Si substrate not only has a high dislocation density, but also the tensile stress caused by the thermal mismatch will make it have a large residual strain. In this embodiment, SiO2 regions are formed on the high-resistance silicon substrate. Since the thermal expansion coefficients of Si and SiO2 are different, the introduction of SiO2 units will generate compressive strain due to the difference in thermal expansion coefficients, which can further compensate for the tensile stress caused by the thermal mismatch, thereby improving the crystal quality of GaN and reducing the dislocation density and warping of GaN.

[0050] In an alternative embodiment of the present invention, please continue to refer to Figure 3 , manufacturing a photoresist mask pattern on the substrate 10 includes:

[0051] The substrate 10 is exposed and developed using a photoresist mask, and a photoresist mask pattern is formed on the substrate 10. The photoresist mask patterns are arranged at intervals on the surface of the substrate 10, and the interval distance is 0.1 - 10 μm; the shape of the orthographic projection of the photoresist mask pattern on the substrate 10 includes a square, a rectangle, a circle, an ellipse, a triangle or a polygon, and the width dimension of the photoresist mask pattern can be 2 - 10 μm, and can be 4 μm, 6 μm, 8 μm.

[0052] In an alternative embodiment of the present invention, oxygen ion implantation is performed on one side of the substrate 10 where the photoresist mask pattern is provided, and then the photoresist mask pattern is removed, including:

[0053] Using an ion implanter to perform oxygen ion implantation on one side of the substrate 10 where the photoresist mask pattern is provided, wherein the oxygen ion implantation depth is 20 - 100 nm;

[0054] After the oxygen ion implantation is completed, ultrasonic cleaning is performed with acetone, absolute ethanol and deionized water for 5 - 30 min to remove the photoresist mask pattern. After being placed in a spin dryer for 15 - 20 min, it is then dried in an oven at 130 - 150 °C for 25 - 35 min.

[0055] In an alternative embodiment of the present invention, high-temperature thermal annealing is performed on the substrate 10, including:

[0056] The temperature of the high-temperature thermal annealing is 1100 - 1350 °C, and the annealing time is 3 - 8 h.

[0057] In an alternative embodiment of the present invention, a nucleation layer 30 is grown on the surface of the pretreatment layer 20 provided on the substrate 10, including:

[0058] In the first stage, the first nucleation layer 30 is grown at 800 - 900 °C under high-V and high-III conditions, and the growth thickness is 20 - 100 nm; wherein the high-V and high-III conditions refer to that the molar ratio of group-V element NH3 and group-III element TMAl is greater than 15, the source flow rate of TMAl is 200 - 300 sccm, and the source flow rate of NH3 is 4000 - 5000 sccm;

[0059] In the second stage, the second nucleation layer 30 is grown at 1000 - 1200 °C under low-V and low-III conditions, and the growth thickness is 100 - 200 nm; wherein the low-V and low-III conditions refer to that the molar ratio of group-V element NH3 and group-III element TMAl is less than 10, the source flow rate of TMAl is 150 - 200 sccm, and the source flow rate of NH3 is 1000 - 2000 sccm.

[0060] In an alternative embodiment of the present invention, a graded superlattice buffer layer 40 is grown on the surface of the nucleation layer 30 facing away from the substrate 10, including:

[0061] The graded superlattice buffer layer 40 is grown under the condition that the temperature is 1000 - 1050 °C.

[0062] In an alternative embodiment of the present invention, a gallium nitride layer 50 is grown on the surface of the graded superlattice buffer layer 40 facing away from the substrate 10, including:

[0063] The gallium nitride layer is grown under the condition that the temperature is 1000 - 1050 °C.

[0064] In an alternative embodiment of the present invention, the preparation of a gallium nitride on silicon epitaxial structure with low radio frequency loss is achieved through the following process, including:

[0065] S1. A photoresist mask pattern is fabricated on the high-resistivity silicon substrate 10, as shown in Figure 3 (a).

[0066] Specifically, a single-crystalline silicon with a crystal orientation of 111 is selected as the substrate. The resistivity of the silicon substrate is 5000 - 10000 Ω·cm, and the thickness of the silicon substrate 10 is 500 - 1000 μm, and 800 μm can be selected. Before fabricating the photoresist mask pattern, the high-resistivity silicon substrate 10 needs to be organically cleaned. It is ultrasonically cleaned with acetone, absolute ethanol, and deionized water for 5 - 30 min, and placed in a spin dryer for 15 - 20 min, and then put into an oven at 130 °C to be dried for 30 min. Then, a photoresist with a thickness of 2 - 10 μm is spin-coated on the surface of the substrate 10, and a pattern is left through photolithography and development. The pattern includes, but is not limited to, a square (length and width 2 - 10 μm), a circle (diameter 2 - 10 μm), a triangle (side length 2 - 10 μm), etc. The interval between the patterns is about 0.1 - 10 μm.

[0067] S2. Oxygen ion implantation is performed on the surface of the silicon substrate 10 with the photoresist mask pattern, and then the photoresist is removed, as shown in Figure 3 (b).

[0068] Specifically, oxygen ion implantation is performed on the surface of the silicon substrate 10 with the photoresist mask pattern through an ion implanter. The energy of the ion implantation is 150 - 300 keV, and the implantation dose is 1×10 17 cm -2 ~5×10 18 cm -2, the temperature during ion implantation is maintained at 500 - 700 °C, and the implantation depth extends from the surface of the substrate 10 to 20 - 100 nm below. After ion implantation is completed, it is ultrasonically cleaned with acetone, absolute ethanol, and deionized water for 5 - 30 min respectively to remove the photoresist mask pattern. After being placed in a spin dryer for 15 - 20 min, it is then put into an oven at 130 °C and dried for 30 min.

[0069] S3. A pretreatment layer 20 is formed by high-temperature thermal annealing, as Figure 3 (c) shows.

[0070] Specifically, the ion-implanted substrate 10 with the photoresist mask removed is placed in a high-temperature furnace tube annealing equipment for high-temperature thermal annealing to reduce the defects generated during the implantation process and promote the reaction between oxygen ions and silicon to form a uniform silicon dioxide pretreatment layer 20. Among them, the annealing temperature is 1100 - 1350 °C, the annealing time is 3 - 8 hours, and the annealing atmosphere is oxygen and argon, where the content of oxygen is 2% - 5% to prevent surface oxygen deficiency during long-term annealing, and the rest of the gas is argon.

[0071] S4. An AlN nucleation layer 30, a graded superlattice buffer layer 40, and a GaN layer are epitaxially grown on the substrate 10 pretreatment layer 20, as Figure 3 (c) - 3(f) show.

[0072] Specifically, the AlN nucleation layer 30 is epitaxially grown on the AlN combined layer through a metalorganic chemical vapor deposition (MOCVD) process. The growth of the AlN nucleation layer 30 is divided into two stages. First, the AlN nucleation layer 30 is grown under the conditions of low temperature and high V / III. Among them, the flow rate of the TMAl source is 200 - 300 sccm, the flow rate of NH3 is 4000 - 5000 sccm, the growth thickness is 20 - 80 nm, and the temperature is 800 - 900 °C. Then, the AlN nucleation layer 30 is grown under the conditions of high temperature and low V / III. The flow rates of the TMAl source and NH3 are 150 - 200 sccm and 1000 - 2000 sccm respectively, the growth thickness is 100 - 150 nm, and the temperature is 1000 - 1200 °C.

[0073] Continue to epitaxially grow the graded superlattice buffer layer 40 on the AlN nucleation layer 30 through the MOCVD process. Among them, the thickness of the graded superlattice buffer layer 40 is 1 - 5 μm, and the growth temperature is 1015 °C.

[0074] Finally, a GaN layer is epitaxially grown on the graded superlattice buffer layer 40 by using the MOCVD process. Specifically, the temperature of the reaction chamber can be raised to 1100 - 1200 °C, then the TMAl source is turned off, and the flow rates of TMGa and NH3 are adjusted to 200 - 300 sccm and 8000 - 10000 sccm respectively to form a GaN layer with a thickness of 1.5 - 3 μm by epitaxy on the graded superlattice buffer layer 40.

[0075] It should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variant are intended to cover non-exclusive inclusion, so that an article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed. Without more limitations, an element defined by the statement "including one..." does not exclude the existence of another identical element in the article or device including the said element. Words such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The orientation or positional relationship indicated by "above", "below", "left", "right", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation of the present invention.

[0076] In the description of this specification, the description referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not have to be directed to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.

[0077] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can still be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A silicon-based gallium nitride epitaxial structure with low radio frequency loss, characterized in that: include: A substrate, comprising a pre-processed layer, located on one side of the substrate, wherein the pre-processed layer comprises a plurality of silicon dioxide units arranged at intervals; wherein the substrate is a single crystal silicon substrate; A nucleation layer, stacked with the substrate and located on a surface of the substrate where the pretreatment layer is disposed; A gradient superlattice buffer layer is stacked with the nucleation layer and is located on a surface of the nucleation layer away from the substrate; The gallium nitride layer is stacked with the gradient superlattice buffer layer and is located on a surface of the gradient superlattice buffer layer away from the substrate.

2. The silicon-based gallium nitride epitaxial structure with low radio frequency loss according to claim 1, characterized in that: The resistivity of the substrate is greater than or equal to 5000Ω·cm.

3. The silicon-based gallium nitride epitaxial structure with low radio frequency loss according to claim 1, characterized in that: The thickness of the substrate is 0.6-1 mm, the thickness of the pretreatment layer is 20-100 nm, the thickness of the nucleation layer is 100-300 nm, the thickness of the gradient superlattice buffer layer is 2-3 μm, and the thickness of the gallium nitride layer is 1.5-3 μm.

4. A method for preparing a silicon-based gallium nitride epitaxial structure with low radio frequency loss, for preparing a silicon-based gallium nitride epitaxial structure with low radio frequency loss as claimed in any one of claims 1 to 3, characterized in that: include: A substrate is provided; wherein the substrate is a single crystal silicon substrate; Fabricating a photoresist mask pattern on the substrate; Performing oxygen ion implantation on a side of the substrate where the photoresist mask pattern is disposed, and then removing the photoresist mask pattern; Performing thermal annealing on the substrate to form a plurality of silicon dioxide units arranged at intervals to constitute a pretreatment layer; Growing a nucleation layer on the surface of the substrate where the pretreatment layer is disposed; Growing a graded superlattice buffer layer on a surface of the nucleation layer facing away from the substrate; A gallium nitride layer is grown on a surface of the graded superlattice buffer layer facing away from the substrate.

5. The method for preparing a silicon-based gallium nitride epitaxial structure with low radio frequency loss according to claim 4, characterized in that: Producing a photoresist mask pattern on the substrate, comprising: The substrate is exposed and developed using a photoresist mask to form a photoresist mask pattern on the substrate. The photoresist mask pattern is arranged at intervals on the surface of the substrate with an interval distance of 0.1 to 10 μm. The shape of the orthographic projection of the photoresist mask pattern on the substrate includes a square, a rectangle, a circle, an ellipse, a triangle or a polygon.

6. The method for preparing a silicon-based gallium nitride epitaxial structure with low radio frequency loss according to claim 4, characterized in that: Performing oxygen ion implantation on a side of the substrate where the photoresist mask pattern is disposed, and then removing the photoresist mask pattern, comprising: Using an ion implanter to implant oxygen ions on a side of the substrate where the photoresist mask pattern is disposed, wherein the oxygen ion implantation depth is 20 to 100 nm; After the oxygen ion implantation is completed, acetone, anhydrous ethanol and deionized water are used for ultrasonic cleaning for 5 to 30 minutes to remove the photoresist mask pattern, and the film is placed in a spin dryer for 15 to 20 minutes and then dried in a drying oven at 130 to 150° C. for 25 to 35 minutes.

7. The method for preparing a silicon-based gallium nitride epitaxial structure with low radio frequency loss according to claim 4, characterized in that: The substrate is subjected to thermal annealing, comprising: The thermal annealing temperature is 1100-1350°C, and the annealing time is 3-8h.

8. The method for preparing a silicon-based gallium nitride epitaxial structure with low radio frequency loss according to claim 4, characterized in that: Growing a nucleation layer on the surface of the substrate where the pretreatment layer is provided, comprising: In the first stage, a first nucleation layer is grown at 800-900° C. under a first preset condition, with a growth thickness of 20-100 nm; wherein the first preset condition includes a molar ratio of the V group element NH3 to the III group element TMAl greater than 15, a source flow rate of TMAl of 200-300 sccm, and a source flow rate of NH3 of 4000-5000 sccm; In the second stage, a second nucleation layer is grown at 1000-1200°C under second preset conditions with a growth thickness of 100-200nm; wherein the second preset conditions include a molar ratio of group V element NH3 to group III element TMAl being less than 10, a source flow rate of TMAl being 150-200sccm, and a source flow rate of NH3 being 1000-2000sccm.

9. The method for preparing a silicon-based gallium nitride epitaxial structure with low radio frequency loss according to claim 4, characterized in that: Growing a graded superlattice buffer layer on a surface of the nucleation layer away from the substrate comprises: The graded superlattice buffer layer is grown at a temperature of 1000-1050°C.

10. The method for preparing a silicon-based gallium nitride epitaxial structure with low radio frequency loss according to claim 4, characterized in that: Growing a gallium nitride layer on a surface of the graded superlattice buffer layer away from the substrate comprises: The gallium nitride layer is grown at a temperature of 1000-1050°C.

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