System and method for improving FPGA dynamic aging test coverage rate

Abstract

The invention provides a system and a method for improving the dynamic burn-in test coverage rate of an FPGA (Field Programmable Gate Array). The system comprises a PC (Personal Computer) upper computer, an equipment main control FPGA (Field Programmable Gate Array) chip, namely an FPGA 0, n tested FPGA chips, n Flash memories and a microcontroller MCU (Microprogrammed Control Unit), n is an integer greater than 1, the PC upper computer is connected with the FPGA 0 for communication, and configuration programs of different function aging tests in the tested FPGA chips are loaded on line; the FPGA 0 is connected with the n FPGA chips to be tested, the content of the loading configuration file issued by the PC upper computer is written into the FPGA chips to be tested, and online loading configuration of the FPGA chips to be tested is completed. According to the method, the burn-in test program can be updated in real time in the burn-in process, configuration of multiple FPGAs can be completed at the same time, the dynamic burn-in test coverage rate and loading efficiency are improved, the flexibility is high, and the method can be widely applied to different FPGA dynamic burn-in test scenes.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and particularly relates to a system and method for improving the dynamic burn-in test coverage rate of an FPGA. Background Art

[0002] With the rapid development of the aerospace industry, as the "heart-level" chip of a single model aircraft, FPGAs have been widely used in important aerospace models such as Tianwen-1, Chang'e-6, and the space station. As a core component, the quality assurance problem has gradually become a bottleneck in the development of aerospace equipment, directly affecting China's national defense construction and aerospace infrastructure construction.

[0003] Dynamic burn-in testing is one of the important methods to eliminate early-failure circuits. Before FPGA dynamic burn-in testing, the test program is generally burned into the FPGA to be tested in two ways. One is to directly burn it into the FPGA through JTAG, and the other is to solidify it into the configuration Flash chip. After the FPGA is powered on, the test program is automatically loaded from the Flash into the FPGA chip. However, both methods can only make the FPGA load one program during the dynamic burn-in process. If the test program needs to be replaced, it takes a long time, resulting in relatively low test coverage rate and loading efficiency. In addition, since the dynamic burn-in test program establishes self-tests inside the FPGA, generating input excitation modules and true value comparison modules, it needs to use the resources inside the FPGA itself and cannot achieve full coverage testing of the resources of each functional module, and there are certain potential hazards in its quality and reliability.

[0004] Patent document CN108037445A discloses an FPGA burn-in test system and its circuit configuration method, which uses a PROM to configure multiple FPGA chips simultaneously in the passive serial mode. However, the test program in the PROM cannot be modified, that is, the test resources covered by the test program loaded into the FPGA are fixed, and during the burn-in process, only one test program can be configured, and the configuration file cannot be updated in real time, resulting in a low burn-in test coverage rate.

[0005] Patent document CN113985257A discloses an FPGA burn-in junction temperature dynamic adjustment system to ensure that the junction temperature of the device reaches the specified value during the burn-in process and does not undergo over-burn-in. By using the system controller to read the FPGA configuration file stored in the Flash and output it to the FPGA to complete the configuration process. However, during the burn-in process, the FPGA to be tested can only load the program solidified in the Flash, and this program is fixed, so the test coverage rate is limited, and one Flash can only configure one FPGA, with low loading efficiency. If the test program needs to be updated, each Flash needs to be re-solidified, which takes a long time.

[0006] In summary, the above two patent documents cannot meet the purpose of both improving the FPGA burn-in test coverage and configuring multiple FPGAs at the same time to improve loading efficiency. Summary of the invention

[0007] The purpose of the present invention is to provide a system and method for improving the coverage of FPGA dynamic burn-in test, so as to solve the problem that only one test program can be run during the FPGA dynamic burn-in process, resulting in failure to implement full coverage test of resources and low loading efficiency during the loading process.

[0008] In order to solve the technical problem, the present invention adopts the following technical solution:

[0009] A system for improving the coverage of FPGA dynamic burn-in test, characterized by comprising a PC host computer, a device main control FPGA chip, namely FPGA0, n FPGA chips to be tested, n Flash memories, and a microcontroller MCU, wherein n is an integer greater than 1,

[0010] The PC host computer is connected to FPGA0 for communication, transmits the status information of n FPGA chips under test, sends an online loading configuration enable signal and the file content of the online loading configuration to FPGA0, and loads the configuration program of different function burn-in tests in the FPGA chip under test online;

[0011] The FPGA0 is connected to n FPGA chips under test, and the contents of the loading configuration file sent by the PC host computer are written into the FPGA chip under test, so as to complete the online loading configuration of the FPGA chip under test;

[0012] The FPGA chip under test is a chip under test for dynamic burn-in test and is placed on a board;

[0013] The n Flash memories are respectively connected to the n FPGA chips under test, and are used to store the burn-in test program loaded by default after the FPGA chips under test are powered on;

[0014] The microcontroller MCU is connected to FPGA0 and is used to control the temperature.

[0015] Furthermore, the main interface of the PC host computer includes a board control and detection interface, a temperature and time control interface, a loading interface, and a log interface.

[0016] The board control and detection interface is used to display the status of the FPGA chip under test;

[0017] The temperature and time control interface is used to set the temperature and time of the FPGA chip burn-in test under test;

[0018] The loading interface is used to select the configuration program to be loaded and the FPGA chip under test. After the selection is completed, click the start loading button and wait for the burn-in test result.

[0019] The log interface is used to print the burn-in test result.

[0020] Furthermore, the board control and detection interface includes multiple burn-in boards. Each burn-in board consists of n test stations, which are respectively used to display the status of n FPGA chips under test. The board of the burn-in board is a printed circuit board for placing the FPGA chip under test. The test station is used to monitor the temperature and voltage data information of the FPGA chip under test, and the data information is displayed on the PC host computer.

[0021] The present invention also provides a method for improving the dynamic burn-in test coverage rate of an FPGA, which is characterized in that it uses the above system for improving the dynamic burn-in test coverage rate of an FPGA, and includes the following steps:

[0022] S1. Power on the system;

[0023] S2. Start the PC host computer software;

[0024] S3. Turn on the power of the FPGA chip under test;

[0025] S4. The FPGA chip under test loads the default configuration program stored in the Flash memory;

[0026] S5. After the default configuration program is loaded, the PC host computer is in an idle state at this time, waiting for other operation requests;

[0027] S6. Set the burn-in temperature and time;

[0028] S7. After the FPGA chip under test reaches the set temperature, the PC host computer performs an online loading operation of the configuration program for the burn-in test;

[0029] S8. The FPGA chip under test performs the burn-in test and prints the test result;

[0030] S9. After all burn-in tests are completed and the test results are successfully printed, the PC host computer switches the SlaveSerial mode of the FPGA chip under test back to the Master-SPI mode;

[0031] S10. After the FPGA chip under test is switched back to the Master-SPI mode, the PC host computer controls the power-off of the FPGA chip under test on the board to end this burn-in test.

[0032] Furthermore, in step S4, the default aging temperature and aging time are set in the default configuration program; in step S6, if the PC host computer does not set the temperature and time, the PC host computer heats up the FPGA chip under test according to the default aging temperature and aging time; if the PC host computer sets the temperature and time, the PC host computer heats up the FPGA chip under test according to the set temperature and time.

[0033] Furthermore, in step S7, click the online loading button in the PC host computer interface, the PC host computer pops up an online loading interface, selects the configuration program for the aging test to be added, and selects the FPGA chip under test for the aging test; after completing step S7, the FPGA chip under test starts the aging test and feeds back the test results to the device master FPGA chip; the device master FPGA chip then feeds back the test results to the PC host computer; the PC host computer prints the test results in the log and performs the online loading of the next aging test configuration program.

[0034] Furthermore, in step S7, the configuration programs for different functional aging tests in the FPGA chip under test are loaded online through the PC host computer to improve the test coverage rate. The FPGA chip under test performs the aging test simultaneously. The configuration program includes each functional module inside the FPGA chip under test, and different configuration programs are separately developed and compiled for each functional module to achieve full functional coverage of the aging test of the FPGA chip under test.

[0035] Furthermore, the PC host computer communicates with the device master FPGA chip through the network cable using the UDP protocol; the PC host computer sends an online loading configuration enable signal and the file content of the online loading configuration to the device master FPGA chip; the device master FPGA chip transmits the status information of the FPGA chip under test to the PC host computer.

[0036] Furthermore, the device master FPGA chip stores the received loading configuration program content in the static random access memory SRAM resource, and then writes the loading configuration program content into the FPGA chip under test through the Slave Serial mode to complete the online loading configuration of the FPGA chip under test;

[0037] After the program test in the FPGA chip under test is completed, the test results are transmitted to the device master FPGA chip through the low-amplitude differential signal LVDS connection line, and the device master FPGA chip then transmits the test results to the PC host computer.

[0038] Furthermore, the configuration program includes the functional modules BRAM, XADC, CMT, GTH, DSP, IOB, and CLB of the internal resources of the FPGA chip under test.

[0039] Compared with the prior art, the present invention has the following beneficial effects:

[0040] Compared with the above-mentioned patent document CN108037445A, which uses PROM to realize the simultaneous configuration of multiple FPGAs, the test program in the PROM cannot be modified, that is, the test resources covered by the test program loaded into the FPGA are fixed. In the present invention, the burn-in program can be changed at any time through the PC host computer, and the coverage can be improved by adding multiple burn-in test programs. It can also realize the simultaneous configuration of multiple FPGAs, which has higher coverage and better flexibility than the method proposed in the document.

[0041] Compared with the above-mentioned patent document CN113985257A, which uses Flash to configure FPGA, during the burn-in process, the FPGA under test can only load the program solidified in Flash, which is fixed, so the test coverage is limited, and one Flash can only configure one FPGA, and the loading efficiency is slow. If the test program needs to be updated, each Flash needs to be re-solidified, which takes a long time. The method provided by the present invention can add multiple burn-in programs in real time through a PC host computer during burn-in and configure multiple FPGAs under test at the same time, solving the problem of low Flash configuration test coverage and loading efficiency, and realizing a more flexible, high-coverage, and high-efficiency FPGA burn-in dynamic test solution.

[0042] The present invention provides a system and method for improving FPGA dynamic burn-in test, which solves the problem that only one test program can be run during FPGA dynamic burn-in process, resulting in failure to implement full coverage test of resources and low loading efficiency during loading process.

[0043] The present invention can update the burn-in test program in real time during the burn-in process and complete the configuration of multiple FPGAs at the same time according to the screening requirements of different aerospace models, thereby improving the dynamic burn-in test coverage and loading efficiency. The circuit structure is simple, the system complexity is low, and it has strong flexibility. It can be widely used in FPGA dynamic burn-in test scenarios of different aerospace models and different needs, further ensuring the quality reliability of FPGA and guaranteeing the success of model missions. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] To more clearly illustrate the technical solutions disclosed in the present invention, the following will briefly introduce the drawings required for some of the embodiments disclosed in the present invention. Obviously, the drawings in the following description are only the drawings of some embodiments disclosed in the present invention. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limitations on the actual dimensions of the products involved in the embodiments disclosed in the present invention, the actual processes of the methods, etc.

[0045] Figure 1 It is the architecture diagram of the system and method for improving the dynamic burn-in test coverage rate of FPGA in the present invention.

[0046] Figure 2 It is the flowchart of the method for improving the dynamic burn-in test coverage rate of FPGA in the present invention. Detailed implementation manners

[0047] The following further describes the detailed implementation manners of the present invention in conjunction with the drawings.

[0048] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention. Therefore, the present invention is not limited by the specific implementation manners disclosed below.

[0049] Figure 1 It is the architecture diagram of the system and method for improving the dynamic burn-in test coverage rate of FPGA in the present invention. As Figure 1 shown, the system for improving the dynamic burn-in test coverage rate of FPGA in the present invention includes a PC host computer, a device master FPGA chip (FPGA0), multiple FPGA chips to be tested (FPGA1,..., FPGAn), multiple Flash memories (Flash_1,..., Flash_n), and a microcontroller MCU, where n is an integer greater than 1.

[0050] The method of the present invention can add multiple burn-in programs through the PC host computer and adopt a cyclic loading method to improve the burn-in test coverage rate of the FPGA to be tested. Moreover, the device master FPGA chip (FPGA0) can realize the simultaneous online loading of multiple FPGA chips to be tested (FPGA1,..., FPGAn), greatly improving the online loading efficiency.

[0051] The PC host computer is connected to the device master FPGA chip. The device master FPGA chip is connected to multiple FPGA chips under test. Multiple FPGA chips under test are respectively connected to multiple Flash memories. The microcontroller MCU is connected to the device master FPGA chip.

[0052] In the present invention, multiple burn-in programs are added through the PC host computer, and the loop loading method is adopted to improve the burn-in test coverage rate of the FPGA chips under test. Moreover, FPGA0 can realize the simultaneous online loading of the FPGA chips under test, greatly improving the online loading efficiency.

[0053] The PC host computer is used to control the entire dynamic burn-in test process and simultaneously monitor the real-time status information of all FPGA chips under test. In one embodiment, the PC host computer communicates with the device master FPGA chip (FPGA0) using the UDP protocol through a gigabit Ethernet cable, transmits the status information of multiple FPGA chips under test (FPGA1, ……, FPGAn), sends an online loading configuration enable signal and the file content of the online loading configuration to FPGA0. FPGA0 stores the received file content of the loading configuration sent by the PC host computer into the static random access memory (SRAM), and then writes the file content of the loading configuration sent by the PC host computer into the FPGA chips under test through the SlaveSerial mode, completing the online loading configuration of the FPGA chips under test.

[0054] In order to further improve the test coverage rate and reduce potential quality and reliability hidden dangers, in the burn-in test of the present invention, the configuration programs for different functional tests are loaded online through the PC host computer. In theory, it can achieve full coverage of the internal resources of the FPGA chips under test. The test results after running are first input into the device master FPGA chip, i.e., FPGA0, through the serial port, and then FPGA0 outputs them to the PC host computer through the Ethernet. The PC host computer displays the results on the PC host computer interface and prints out the test results. The configuration programs include each functional module inside the FPGA chips under test. In one embodiment, the configuration programs for different functional tests respectively include the functional modules BRAM, XADC, CMT, GTH, DSP, IOB, CLB, etc. of the internal resources of the FPGA chips under test. Each functional module is separately developed and compiled into different configuration files to achieve full functional coverage of the functional module.

[0055] The device master FPGA chip is the control chip for the dynamic aging test, which is used to realize the information transmission, information processing and module control of the entire dynamic aging test, including a module for data transmission with the PC host computer and a module for receiving and processing the information processing of the configuration file sent by the PC host computer. The device master FPGA chip transmits the status information of the FPGA chip under test to the PC host computer. In one embodiment, during the loading process, the PC host computer sends a loading enable instruction, and the device master FPGA chip enters the online loading data processing by judging whether the instruction is an online loading instruction, and sends the processed configuration file information to the FPGA chip under test through Slave Serial, waiting for the program test of the FPGA chip under test to be completed, and the test results are transmitted to the device master FPGA chip FPGA0 through the LVDS connection line, and the device master FPGA chip FPGA0 then transmits the test results to the PC host computer. Preferably, the device master FPGA chip adopts the model XCK7325T-2FFG900I.

[0056] The FPGA chip under test is a chip under dynamic burn-in test and is placed on a board. During the burn-in test, the solidified test program is loaded by default through the Flash memory after the first power-on. In one embodiment, the FPGA chip under test of the present invention is a chip of model XC7VX690T-2FFG1927I. Multiple FPGA chips under test are subjected to burn-in test at the same time, and the specific number is determined by the resources of the device master FPGA0. After the program test in the FPGA chip under test is completed, the test results are transmitted to the device master FPGA chip through a low amplitude differential signal (LVDS) connection line, and the device master FPGA chip then transmits the test results to the PC host computer.

[0057] The Flash memory is used to store the burn-in test program loaded by default after the FPGA chip under test is powered on. When the FPGA chip under test is powered on, the burn-in test program loaded by default in the Flash memory corresponding to the FPGA chip under test is obtained to complete the program loading of the FPGA chip under test. In one embodiment, the Flash memory can be model MT25QU256ABA1EW9-0SIT, which is used to store the firmware program of the FPGA chip under test. When the FPGA chip under test is powered on, the firmware information in the Flash memory corresponding to the FPGA chip under test is obtained to complete the program loading of the FPGA chip under test.

[0058] The microcontroller MCU is used to control the temperature.

[0059] The main interface of the PC host computer includes the board control and detection interface, temperature and time control interface, loading interface, and log interface.

[0060] The board control and detection interface includes N aging boards, and each aging board consists of n test stations, which are respectively used to display the status of n FPGA chips under test. The board of the aging board is a printed circuit board for placing the FPGA chips under test. The test stations are used to monitor the temperature and voltage data information of the FPGA chips under test. Displaying the temperature and voltage information of each test station facilitates monitoring the real-time status information of the FPGA chips under test, and the data information is displayed on the PC host computer.

[0061] The temperature and time control interface is used to set the temperature and time for the aging test of the FPGA chips under test. After the temperature setting is completed, after waiting for the time of heating up or cooling down, the temperature of the FPGA chips under test stabilizes at the set target temperature.

[0062] The loading interface is used to select the loading configuration program and the FPGA chips under test to be loaded. After the selection is completed, click the start loading button and wait for the aging test result. In the loading interface on the host computer, the loading configuration program and the FPGA chips under test to be loaded can be selected. After the selection is completed, click start loading and wait for the loading result. The test result after loading the configuration file is printed in the log interface.

[0063] The log interface is used to print the aging test results.

[0064] Online loading performs the online loading operation of the configuration file for the FPGA chips under test on each board in the cabinet through the PC host computer software. The PC host computer issues a loading instruction through the network. After the aging board receives it, the main control FPGA chip of the aging board device switches the loading mode of the test station to Slave Serial. Then the PC host computer sends the configuration file to the main control FPGA chip of the aging board device, that is, FPGA0, and then performs online configuration on the FPGA chips under test through FPGA0; after the loading test is completed, the result is transmitted to the PC host computer through FPGA0. After the result detection is completed, the PC host computer automatically switches the program of the FPGA chips under test back to the test program solidified in the Flash.

[0065] In one embodiment, in the functional module of the present invention, the PC host computer is connected to the FPGA through a gigabit Ethernet cable using the UDP protocol to control the entire dynamic burn-in process, including temperature control, online loading control, etc., and can monitor the voltage information, operating status, etc. of all the FPGA chips under test in real time, facilitating quick understanding of the real-time status of all the FPGA chips under test. In the functional module, FPGA0 implements functions such as information transmission, information processing, and module control for the entire dynamic burn-in test. In the functional module, the Flash memory is used to store the burn-in test program that is default loaded after the FPGA chip under test is powered on. It has a certain coverage rate and can implement burn-in tests on resources such as BLOCK, BRAM, RAM, CLB, IOB, DSP, and CMT inside the FPGA n.

[0066] To meet the quality assurance requirements of certain models and further improve the coverage rate of the dynamic burn-in test, it is necessary to enable the online loading function. The TS3A27518ERTWR chip is used to switch between two loading methods. This chip selects the program data transmission of the FPGA chip under test through MODE_SEL connected to the FPGA0 chip. When the FPGA chip under test uses online loading, FPGA0 needs to set FPGA_M2, FPGA_M1, and FPGA_M0 to 1-1-1, and the loading method of the FPGA chip under test is switched from the default Master-SPI mode configured by Flash to the Slave Serial mode configured by FPGA0. To facilitate the simultaneous operation of the online loading of multiple FPGA n under test and considering the layout aesthetics, as shown in Figure 1 As shown, connecting FPGA0 to four FPGA chips under test can enable the host computer to perform online loading on the four FPGA chips under test simultaneously through FPGA0.

[0067] Figure 2 This is the flowchart of the method for improving the coverage rate of the FPGA dynamic burn-in test of the present invention. As Figure 2 shown, the method for improving the coverage rate of the FPGA dynamic burn-in test of the present invention uses the above-mentioned system for improving the coverage rate of the FPGA dynamic burn-in test, including the following steps:

[0068] S1. Power on the system

[0069] S2. Start the PC host computer software

[0070] S3. Turn on the power of the FPGA chip under test

[0071] S3-1. Click the start test button in the PC host computer software with the mouse;

[0072] S3-2. The PC host computer uses the UDP protocol to search for the board through the network cable;

[0073] When the PC host computer detects the presence of the board and the FPGA chip under test, the power supply of the FPGA chip under test is turned on.

[0074] S4. The FPGA chip under test loads the default configuration program stored in the Flash memory.

[0075] After the power supply of the FPGA chip under test is turned on, the FPGA chip under test loads the default configuration program stored in the Flash memory. The default aging temperature and aging time are set in the default configuration program.

[0076] S5. After the default configuration program is loaded, the PC host computer is in an idle state, waiting for other operation requests.

[0077] S6. Set the aging temperature and time.

[0078] If the PC host computer does not set the temperature and time, the PC host computer heats up the FPGA chip under test according to the default aging temperature and aging time.

[0079] If the PC host computer sets the temperature and time, the PC host computer heats up the FPGA chip under test according to the set temperature and time.

[0080] S7. After the FPGA chip under test reaches the set temperature, the PC host computer performs an online loading operation of the configuration program for aging test on it.

[0081] Click the online loading button in the PC host computer interface. The PC host computer pops up an online loading interface, selects the configuration program for aging test to be added, and selects the FPGA chip under test to be subjected to aging test.

[0082] The PC host computer sends a Slave Serial mode instruction to the FPGA0 chip and sends the data information of the aging test configuration program to the device master control FPGA chip in data packets of 8KB each time.

[0083] The device master control FPGA chip receives through a static random access memory (SRAM) with a depth of 8KB, and loads the data to the FPGA chip under test according to the Slave Serial mode instruction for the configuration program of the aging test.

[0084] S8. The FPGA chip under test performs an aging test and prints the test results.

[0085] After step S7 is completed, the FPGA chip under test starts to perform an aging test and feeds back the test results to the device master control FPGA chip.

[0086] The device master control FPGA chip then feeds back the test results to the PC host computer.

[0087] The PC host computer prints the test results in the log and loads the next burn-in test configuration program online.

[0088] S9. After all the aging tests are completed and the test results are successfully printed, the PC host computer switches the SlaveSerial mode of the tested FPGA chip back to the Master-SPI mode.

[0089] S10: After the FPGA chip under test switches back to Master-SPI mode, the FPGA chip under test on the PC host control board is powered off, ending this burn-in test.

[0090] In one embodiment, the method of the present invention is as follows:

[0091] Step 1: Power on the system;

[0092] Step 2, start the host computer software;

[0093] Step 3. Click the mouse to start the test and turn on the power of FPGAn station. The host computer will check whether the board exists according to the status of the LAN IP connection. If the board exists and FPGAn exists on the station, the power of FPGAn will be turned on.

[0094] Step 4: After the FPGA is powered on, the FPGAn program is started by default using the fixed configuration program in the Flash.

[0095] Step 5: After completing the default configuration of FPGA, the host computer will control the temperature of FPGAn to 125°C by default (the temperature can be modified according to specific needs). At this time, the host computer is in an idle state, waiting for other operation requests.

[0096] Step 6: The aging time can be set according to actual needs. If the aging time is not set for the host computer, the host computer will heat up the FPGAn according to the set temperature until the temperature reaches the set temperature and is maintained continuously.

[0097] Step 7, after reaching the target temperature, the host computer can perform an online loading program operation on it. Click the online loading button in the host computer interface, and the host computer will pop up the online loading interface. Select the configuration file of the burn-in function test to be added, and select the FPGAn chip to be loaded;

[0098] Step 8. After the above selection is completed, click "Start Loading". The host computer will send a Slave Serial mode instruction to FPGA0 and send the data information of the burn-in function test configuration file to FPGA0 in data packets of 8 KB each time. FPGA0 receives it through an SRAM with a depth of 8 KB and loads the data to FPGAn according to the Slave Serial timing. After the loading is completed, the burn-in function test is performed in FPGAn, and the test result is fed back to FPGA0, and then FPGA0 feeds it back to the host computer. The host computer prints the test result in the log and proceeds to the online loading of the next function test file.

[0099] Step 9. After waiting for the online loading of all the configuration files for the burn-in function tests and printing the test result of the last online loading program, the host computer will let the program of FPGAn switch back to the Master-SPI mode to load from the Flash.

[0100] Step 10. If the burn-in time is set in Step 6, enter the test with the specified burn-in time. During the burn-in test, the online loading of FPGAn can be performed, and the steps are the same as Steps 7 to 9.

[0101] Step 11. After the set burn-in time is completed, the host computer controls the power-off of FPGAn on the burn-in time board to end this burn-in test, and the state of this burn-in board returns to the state in Step 3.

[0102] The present invention provides a system and method for improving the dynamic burn-in test coverage rate of FPGA. Based on the requirements of various major aerospace models, it can meet the requirements of each model task, can flexibly customize the FPGA dynamic burn-in test scheme, enable the FPGA under test to update multiple burn-in test programs simultaneously in the dynamic burn-in test, and achieve high-efficiency and high-coverage FPGA dynamic burn-in test. The present invention can perform burn-in tests on different functions within the FPGA chip under test, achieve full coverage testing inside the FPGA chip, and multiple FPGA chips under test can perform burn-in tests simultaneously, ensuring the on-orbit reliability of the FPGA used in aerospace models.

[0103] Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention without departing from the spirit and scope of the present invention. Therefore, any simple modification, equivalent change, and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention all belong to the protection scope of the technical solution of the present invention.

Claims

1. A system for improving FPGA dynamic burn-in test coverage, characterized in that: It includes a PC host computer, a device main control FPGA chip, namely FPGA0, n FPGA chips to be tested, n Flash memories, and a microcontroller MCU, where n is an integer greater than 1. The PC host computer is connected to FPGA0 for communication, transmits the status information of n FPGA chips under test, sends an online loading configuration enable signal and the file content of the online loading configuration to FPGA0, and loads the configuration program of different function burn-in tests in the FPGA chip under test online; The FPGA0 is connected to n FPGA chips under test, and the contents of the loading configuration file sent by the PC host computer are written into the FPGA chip under test, so as to complete the online loading configuration of the FPGA chip under test; The FPGA chip under test is a chip under test for dynamic burn-in test and is placed on a board; The n Flash memories are respectively connected to the n FPGA chips under test, and are used to store the burn-in test program loaded by default after the FPGA chips under test are powered on; The microcontroller MCU is connected to FPGA0 and is used to control the temperature.

2. The system for improving FPGA dynamic burn-in test coverage according to claim 1, characterized in that: The main interface of the PC host computer includes a board control and detection interface, a temperature and time control interface, a loading interface, and a log interface. The board control and detection interface is used to display the status of the FPGA chip under test; The temperature and time control interface is used to set the temperature and time of the FPGA chip burn-in test under test; The loading interface is used to select the configuration program to be loaded and the FPGA chip to be tested. After the selection is completed, click the Start Loading button to wait for the burn-in test result; The log interface is used to print the aging test results.

3. The system for improving FPGA dynamic burn-in test coverage according to claim 2, characterized in that: The board control and detection interface includes multiple aging boards, each of which is composed of n test stations, which are used to display the status of n FPGA chips under test. The board of the aging board is a printed circuit board for placing the FPGA chip under test. The test station is used to monitor the temperature and voltage data information of the FPGA chip under test, and the data information is displayed on the PC host computer.

4. A method for improving FPGA dynamic burn-in test coverage, characterized in that: The system for improving the coverage of FPGA dynamic burn-in test according to any one of claims 1 to 3 comprises the following steps: S1, system power on; S2, start the PC host software; S3, turn on the power supply of the FPGA chip under test; S4, the FPGA chip under test loads the default configuration program stored in the Flash memory; S5. The default configuration program is loaded. At this time, the PC host computer is in an idle state, waiting for other operation requests; S6. Set the aging temperature and time; S7, after the FPGA chip under test reaches the set temperature, the PC host computer performs the online loading operation of the configuration program for the burn-in test; S8, the FPGA chip under test is subjected to a burn-in test and the test results are printed; S9. After all the burn-in tests are completed and the test results are successfully printed, the PC host computer switches the SlaveSerial mode of the tested FPGA chip back to the Master-SPI mode; S10, after the FPGA chip under test switches back to the Master-SPI mode, the PC host computer controls the FPGA chip under test on the board to power off, thus ending this burn-in test.

5. The system for improving FPGA dynamic burn-in test coverage according to claim 4, characterized in that: In step S4, the default configuration program is set with a default aging temperature and aging time; in step S6, if the PC host computer does not set the temperature and time, the PC host computer heats up the FPGA chip under test according to the default aging temperature and aging time; if the PC host computer sets the temperature and time, the PC host computer heats up the FPGA chip under test according to the set temperature and time.

6. The system for improving FPGA dynamic burn-in test coverage according to claim 5, characterized in that: In step S7, click the online loading button in the PC host computer interface, the PC host computer pops up the online loading interface, select the configuration program of the burn-in test to be added, and select the FPGA chip under test that needs to be tested for burn-in test; after completing step S7, the FPGA chip under test starts the burn-in test and feeds back the test results to the device main control FPGA chip; the device main control FPGA chip then feeds back the test results to the PC host computer; The PC host computer prints the test results in the log and loads the next burn-in test configuration program online.

7. The system for improving FPGA dynamic burn-in test coverage according to claim 4, characterized in that: In step S7, the configuration program for different functional burn-in tests in the FPGA chip under test is loaded online through the PC host computer to improve the test coverage, and the FPGA chip under test is burn-in tested at the same time. The configuration program includes various functional modules inside the FPGA chip under test. Each functional module is independently developed and compiled into a different configuration program to achieve full functional coverage of the burn-in test of the FPGA chip under test.

8. The system for improving FPGA dynamic burn-in test coverage according to claim 1, characterized in that: The PC host computer uses the UDP protocol to communicate with the device master FPGA chip through a network cable; the PC host computer sends an online loading configuration enable signal and the file content of the online loading configuration to the device master FPGA chip; the device master FPGA chip transmits the status information of the FPGA chip under test to the PC host computer.

9. The system for improving FPGA dynamic burn-in test coverage according to claim 4, characterized in that: The device master FPGA chip stores the received loading configuration program content into the static random access memory SRAM resource, and then writes the loading configuration program content into the FPGA chip under test through the Slave Serial mode to complete the online loading configuration of the FPGA chip under test; The program test in the FPGA chip under test is completed, and the test results are transmitted to the device main control FPGA chip through the low amplitude differential signal LVDS connection line, and the device main control FPGA chip then transmits the test results to the PC host computer.

10. The system for improving FPGA dynamic burn-in test coverage according to claim 7, characterized in that: The configuration program includes the functional modules BRAM, XADC, CMT, GTH, DSP, IOB, and CLB of the internal resources of the FPGA chip under test.

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