Laser radar two-dimensional scanning driving system, method and circuit
By using multiplexers and driving signal shaping circuits to replace FPGA chips in the lidar two-dimensional scanning driving system, the problems of high cost and large space occupancy of FPGA chips are solved, and a low-cost and miniaturized lidar driving system design is realized, enhancing the resolution and flexibility of the system.
Patent Information
- Application Number
- CN202411997834.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2025-06-27
AI Technical Summary
In the existing lidar two-dimensional scanning drive system, the FPGA chip is costly and takes up a large space, and the hardware resources of the SPAD SoC are not fully utilized, resulting in high overall solution cost and complex product design.
Using multiplexer and drive signal shaping circuit instead of FPGA chips, making full use of the hardware resources of SPAD SoC, achieving accurate and independent control of multiple cathodes, and saving PCB space and heat dissipation structure through small-sized device design.
A low-cost lidar two-dimensional scanning drive system is realized, reducing the use of FPGA chips, saving PCB space and thermal structure design, miniaturizing product design, and improving the resolution and flexibility of the system.
Smart Images
Figure CN120214752A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of lidar, and particularly to a two-dimensional scanning drive system, method, and circuit for lidar. Background Art
[0002] A pure solid-state lidar using a two-dimensional scanning method uses vertical-cavity surface-emitting lasers (VCSELs), and controls different illuminated blocks through multiple anodes and cathodes. Each block can be independently illuminated, and the control method is to drive the corresponding anode and cathode. The lidar with VCSELs needs to reach a light power of hundreds of watts within nanoseconds to achieve long-distance measurement and high precision. For this purpose, the anode is usually kept on for a long time (in the microsecond range), while the cathode needs to be switched on and off within an ultra-short time (1 - 6 nanoseconds). The cathode is controlled by a low-side drive signal, so there are high requirements for the frequency and width of the low-side drive signal.
[0003] SPAD SoC usually outputs one or two low-side drive signals, while a two-dimensional VCSEL has eight or more cathodes. The current solution is to receive the low-side drive signals through an FPGA, distribute the drive signals according to the exposure blocks of the SPAD SoC, and adjust the signal width to improve the light power and ranging accuracy. The FPGA also drives the anode by controlling a high-side switch chip. Figure 2 The block diagram is shown, where the anode drive integrated chip of the VCSEL is a high-side switch, and the control is achieved through buses such as SPI and IIC or hardware decoding.
[0004] During the laser emission process, the trig out signal output by the SPAD SoC drives the corresponding cathode of the VCSEL, and the signal is distributed and shaped through the FPGA to meet the drive width requirements. Information is exchanged between the SPAD SoC and the FPGA through a communication bus, including the exposure duration and the current exposure block. The exposure duration determines the on time of the anode switch, and the exposure block indicates the anodes and cathodes that need to be driven. However, the cost of the FPGA chip is relatively high, and at the same time, it also involves a complex power supply system and requires a specific heat dissipation structure design. The overall cost of the solution is high, and it also occupies a relatively large amount of PCB and product space. Moreover, the SPAD SoC integrates a microcontroller internally, which is not used in this solution, resulting in a waste of hardware resources. Summary of the Invention
[0005] To solve the above technical problems, this application provides a two-dimensional scanning drive system, method, and circuit for lidar.
[0006] In a first aspect, this application provides a two-dimensional scanning drive system for lidar, where the two-dimensional scanning drive system for lidar includes: a control chip, an anode control terminal, a cathode control terminal, and a matrix laser.
[0007] The control chip transmits an anode control signal to the anode control terminal;
[0008] The control chip transmits a cathode control signal to the cathode control terminal;
[0009] The anode control terminal and the cathode control terminal are connected to the area array laser;
[0010] The cathode control terminal includes a multiplexer and a drive signal shaping circuit. The multiplexer receives the cathode control signal and outputs a drive signal to the drive signal shaping circuit. The drive signal shaping circuit shapes the drive signal and then outputs a cathode drive signal to the cathode control terminal.
[0011] Among them, the area array laser includes: N cathode drive ports and M anode drive ports, where N is an even number and M is a natural number greater than 1.
[0012] This application uses a multiplexer and a drive signal shaping circuit instead of an FPGA chip, making full use of the hardware resources of the SPAD SoC and reducing the use of high-cost devices such as FPGAs, thus achieving an overall low-cost solution;
[0013] The devices used in this solution are small in size, which can save the PCB space and the design of the heat dissipation structure, making the design of the pure solid-state lidar product miniaturized.
[0014] Further, the cathode control terminal includes N cathode output ports, and the N cathode output ports are respectively connected to the N cathode drive ports; the cathode control terminal also includes an enable port, and the enable port is connected to the enable terminal of the control chip.
[0015] Further, the cathode controller also includes P control signal receiving terminals, and the P control signal receiving terminals are respectively connected to trigger port 1 to trigger port P of the control chip; the cathode control terminal also includes cathode signal receiving terminals, and the cathode signal receiving terminals are connected to the I / O pins of the control chip; among them, N and P satisfy the condition: is a positive integer.
[0016] This solution realizes the precise independent control of multiple cathodes by setting multiple cathode output ports, enhancing the resolution and flexibility of the system. The enable port can effectively manage the start and stop of the system and optimize the energy efficiency. Through multiple control signal receiving terminals and cathode signal receiving terminals, the system receives trigger signals and control signals simultaneously, and the system can further output various drive signals, meeting the requirements of multiple cathode drive ports of the system, improving the control accuracy and signal stability, and at the same time having strong scalability to adapt to different application requirements and improve the overall performance.
[0017] Further, the multiplexer includes: a logic 1 output terminal and a logic 0 output terminal, and a logic 1 output terminal and a corresponding logic 0 output terminal form a binary digit output terminal; the multiplexer further includes N / P NAND gates and an enable terminal.
[0018] Further, the multiplexer further includes: the N / P NAND gates include multiple input terminals, one of the input terminals is connected to the enable terminal, and the remaining input terminals are respectively connected to the binary digit output terminals in the order of binary numerical values; the N / P NAND gates and P control signal receiving terminals form N drive signal output terminals.
[0019] The design of this multiplexer provides binary digit output through the combination of multiple logic output terminals and NAND gates, and is flexibly controlled through the enable terminal. The configuration of multiple input terminals and control signal receiving terminals enables the system to generate multiple precise drive signal outputs, enhancing the multi-signal processing ability of the multiplexer. This design improves the flexibility, precision, and control ability of the system, and has strong scalability to adapt to more complex application scenarios.
[0020] Further, the drive signal shaping circuit includes: N shaping sub-circuits, and the input terminals of the N shaping sub-circuits are respectively and correspondingly connected to the N drive signal output terminals; the output terminals of the N shaping sub-circuits are respectively and correspondingly connected to N cathode output ports.
[0021] Since the signals of the control chip have limited driving ability and cannot directly provide high-quality drive signals that meet various application requirements. It cannot provide sufficient current or sufficient driving force to drive multiple loads or achieve high-precision signal transmission. In addition, when the signal passes through the multiplexer, the quality of the signal will further deteriorate, especially the edges of the signal (i.e., the rising edge and falling edge of the signal) will become blurred or unstable, which will affect the accuracy and response time of the device. In order to ensure that the drive signal can be accurately transmitted and meet the application requirements of high precision and high stability, a signal shaping circuit needs to be added to the signal path.
[0022] Further, the anode control terminal includes M anode output ports;
[0023] The M anode output ports output anode drive signals to the M anode drive ports; the anode control terminal further includes an anode signal input terminal, and the anode signal input terminal is connected to the I / O pin of the control chip.
[0024] Further, the control chip controls the anode control terminal through a control bus or hardwiring.
[0025] This solution enables the control chip to control the high-side integrated chip to open the corresponding channels through the control bus or hardwiring, thereby realizing the control of the anode control terminal.
[0026] In a second aspect, the present application proposes a method based on the lidar two-dimensional scanning drive system described in the first aspect. The method includes:
[0027] S1: Drive the x-th anode drive port;
[0028] S2: Drive the y-th cathode drive port;
[0029] S3: The laser unit with the coordinates (x, y) of the area array laser is lit;
[0030] where x is any integer less than or equal to M, and y is any integer less than or equal to N;
[0031] The specific step S1 is: The control chip sends an anode control signal to the anode control terminal, and the anode control terminal outputs an anode drive signal to the area array laser;
[0032] The specific step S2 is:
[0033] S21: The control chip sends a cathode control signal to the multiplexer;
[0034] S22: The multiplexer outputs a drive signal to the drive signal shaping circuit based on the internal logic gate according to the cathode control signal;
[0035] S23: The drive signal shaping circuit shapes the drive signal and outputs a cathode drive signal to the area array laser.
[0036] The present application uses a multiplexer and a drive signal shaping circuit to replace the FPGA chip, making full use of the hardware resources of the SPAD SoC and reducing the use of high-cost devices such as FPGAs, thereby realizing an overall low-cost solution;
[0037] The devices used in this solution are of small size, which can save the PCB space and the design of the heat dissipation structure, making the design of the pure solid-state lidar product miniaturized.
[0038] In a third aspect, the present application proposes a lidar two-dimensional scanning drive circuit. The circuit includes: the lidar two-dimensional scanning drive system described in the first aspect and a circuit protection board; the lidar two-dimensional scanning drive system is integrated on the circuit protection board.
[0039] In summary, the present application proposes a two-dimensional scanning drive system, method, and circuit for a lidar. The two-dimensional scanning drive system of the lidar includes: a control chip: responsible for coordinating and transmitting signals; an anode control terminal and a cathode control terminal: the control chip transmits signals to the anode control terminal and the cathode control terminal respectively to control the operation of the area array laser; an area array laser: the area array laser consists of multiple ports, including N cathode drive ports and M anode ports, where N is an even number and M is a natural number greater than 1. The cathode control terminal includes two parts: a multiplexer: used to receive the cathode control signal from the control chip and, after being processed by the internal logic circuit, transmit the drive signal to the drive signal shaping circuit; the drive signal shaping circuit is used to receive and process the drive signal transmitted by the multiplexer, ensure that the output signal is suitable for driving, and finally transmit the processed cathode drive signal to the cathode drive port.
[0040] Compared with the prior art, the present application has at least the following beneficial effects:
[0041] The present application uses a multiplexer and a drive signal shaping circuit instead of an FPGA chip, making full use of the hardware resources of the SPAD SoC and reducing the use of high-cost devices such as FPGAs to achieve an overall low-cost solution;
[0042] The devices used in this solution are of small size, which can save the PCB space and the design of the heat dissipation structure, making the design of the pure solid-state lidar product miniaturized. BRIEF DESCRIPTION OF THE DRAWINGS
[0043] Attached Figure 1 is a schematic diagram of the two-dimensional scanning drive system of the lidar shown in the embodiments of the present invention.
[0044] Attached Figure 2 is a circuit principle block diagram of the low-side routing scheme shown in the embodiments of the present invention.
[0045] Attached Figure 3 is a 4-to-1 multiplexer shown in the embodiments of the present invention.
[0046] Attached Figure 4 is the drive signal routing shown in the embodiments of the present invention (realizing that one block in each of the left and right regions of the VCSEL is lit at the same time).
[0047] Attached Figure 5 is the drive signal routing shown in the embodiments of the present invention (only the block on the left side of the VCSEL is lit at the same time).
[0048] Attached Figure 6 is the drive signal routing shown in the embodiments of the present invention (only the block on the right side of the VCSEL is lit at the same time).
[0049] Attached Figure 7The driving signal routing shown in the embodiments of the present invention (different positions on both sides of the VCSEL can be lit according to the configuration at the same time).
[0050] Appendix Figure 8 The principle block diagram of the driving shaping circuit shown in the embodiments of the present invention.
[0051] Appendix Figure 9 The signal diagram of each node of the driving shaping circuit shown in the embodiments of the present invention.
[0052] Appendix Figure 10 The flowchart of the lidar two-dimensional scanning driving method shown in the embodiments of the present invention.
[0053] Appendix Figure 11 The flowchart of the driving method for the cathode port shown in the embodiments of the present invention. Detailed implementation manners
[0054] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.
[0055] Embodiment 1:
[0056] As shown in the appendix Figure 1 The present application provides a lidar two-dimensional scanning driving system, and the lidar two-dimensional scanning driving system includes: a control chip, an anode control terminal, a cathode control terminal, and a planar array laser;
[0057] The control chip transmits an anode control signal to the anode control terminal;
[0058] The control chip transmits a cathode control signal to the cathode control terminal;
[0059] The anode control terminal and the cathode control terminal are connected to the planar array laser;
[0060] The cathode control terminal includes a multiplexer and a driving signal shaping circuit. The multiplexer receives the cathode control signal and outputs a driving signal to the driving signal shaping circuit. The driving signal shaping circuit shapes the driving signal and then outputs a cathode driving signal to the cathode control terminal.
[0061] Among them, the planar array laser includes: N cathode driving ports and M anode ports, where N is an even number and M is a natural number greater than 1.
[0062] This application uses a multiplexer and a drive signal shaping circuit to replace the FPGA chip, making full use of the hardware resources of the SPAD SoC and reducing the use of high-cost devices such as FPGAs to achieve an overall low-cost solution;
[0063] The devices used in this solution are of small size, which can save the PCB space and the design of the heat dissipation structure, making the design of the pure solid-state lidar product miniaturized.
[0064] As shown in the appendix Figure 1 In this embodiment, the control chip used is the SPAD SoC. Twelve anode drive ports AA - AF and BA - BF are set on the area array laser, and eight cathode drive ports 1 - 8 are also set. The anode drive ports form the x-axis of the area array laser, and the cathode drive ports form the y-axis of the area array laser. Based on this positioning, the drive coordinates of AC6, AF3, and BE1 are given in sequence in the figure.
[0065] To make more full use of the hardware resources of the SPAD SoC and reduce the use of high-cost devices such as FPGAs, the solution shown in the appendix is proposed. The high-side drive is driven by the built-in microcontroller of the SPAD SoC, and the low-side routing scheme is used to replace the FPGA. The low-side routing scheme consists of a multiplexer and a drive signal shaping circuit. As shown in the appendix Figure 1 In this solution, the SPAD SoC controls the high-side integrated chip to open the corresponding channels through the control bus or hard wire to achieve the control of the VCSEL anode. The low-side drive of the cathode is realized by the SPAD SoC outputting drive signals to drive the gallium nitride switching tubes through the low-side routing circuit. Figure 2 In the embodiment of the present invention, optionally, the cathode control end includes N cathode output ports, and the N cathode output ports are respectively connected to the N cathode drive ports; the cathode control end further includes an enable port, and the enable port is connected to the enable end of the control chip.
[0066] In the embodiment of the present invention, optionally, the cathode controller further includes P control signal receiving ends, and the P control signal receiving ends are respectively connected to trigger port 1 to trigger port P of the control chip; the cathode control end further includes
[0067] a cathode signal receiving end, and the a cathode signal receiving end is connected to the I / O pin of the control chip; where N and P satisfy the condition: N and P are positive integers. N and P are positive integers.
[0068] This solution realizes the precise and independent control of multiple cathodes by setting multiple cathode output ports, enhancing the resolution and flexibility of the system. The enable port can effectively manage the startup and shutdown of the system and optimize the energy efficiency. Through multiple control signal receivers and cathode signal receivers, the system receives trigger signals and control signals simultaneously, and the system can further output multiple drive signals, meeting the requirements of multiple cathode drive ports of the system, improving the control accuracy and signal stability, and at the same time having strong scalability to adapt to different application requirements and improve the overall performance.
[0069] As shown in the Figure 1 appendix, correspondingly, the cathode control terminal is also provided with eight cathode output ports, and the cathode surface array laser is also provided with two trigger ports. According to the digital circuit logic inside the cathode control terminal, it can be obtained that the cathode control terminal is also provided with two cathode signal receivers.
[0070] In an embodiment of the present invention, optionally, the multiplexer includes: a logic 1 output terminal and a logic 0 output terminal, and a logic 1 output terminal and a corresponding logic 0 output terminal form a binary digit output terminal; the multiplexer further includes N / P NAND gates and an enable terminal.
[0071] In an embodiment of the present invention, optionally, the multiplexer further includes: the N / P NAND gates include multiple input terminals, one of which is connected to the enable terminal, and the remaining input terminals are respectively connected to the binary digit output terminals in the order of binary values; the N / P NAND gates and P control signal receivers form N drive signal output terminals.
[0072] This multiplexer design provides binary digit output through the combination of multiple logic output terminals and NAND gates, and is flexibly controlled through the enable terminal. The configuration of multiple input terminals and control signal receivers enables the system to generate multiple precise drive signal outputs, enhancing the multi-signal processing ability of the multiplexer. This design improves the flexibility, accuracy and control ability of the system, and has strong scalability to adapt to more complex application scenarios.
[0073] A multiplexer (MUX for short) is an important digital circuit component, widely used in fields such as communication, data transmission, computer systems, and signal processing. Its main function is to combine multiple input signals into one signal and select the signal to be transmitted currently through a control signal. The basic operation of the multiplexer is similar to a "selector switch". It enables multiple signals to share the same transmission channel or resource by selecting different input signals, thereby improving the efficiency of the system.
[0074] The multiplexer has multiple input terminals (usually (2^n) input terminals), one output terminal, and a control terminal. The function of the control terminal is to determine which input signal is transmitted to the output terminal according to a preset selection signal. The number of control signals is usually (n), so that one of the (2^n) inputs can be selected.
[0075] Input terminals: The multiplexer usually has multiple input ports. Commonly, there are multiple input terminals such as 2, 4, 8, etc.
[0076] Control lines: The number of control ports determines the number of input signals that the multiplexer can select. For example, if there are two signals (00, 01, 10, 11) at the control terminal, one of the four inputs can be selected.
[0077] Output terminal: The multiplexer has only one output terminal, and the selected input signal is transmitted to this output terminal through the control signal of the multiplexer.
[0078] Taking a 4:1 multiplexer as an example, it has 4 input terminals (I0, I1, I2, I3) and 1 output terminal (Y). Its control terminal has two signals (S0, S1), which are used to select which input signal is transmitted to the output terminal.
[0079] Assuming that the selection signal combined by S0 and S1 is "10", the signal of input terminal I2 will be transmitted to the output terminal Y of the multiplexer.
[0080] 2:1 multiplexer: It has only two inputs (I0, I1), one output (Y), and one control signal (S).
[0081] If S = 0, the output is I0; if S = 1, the output is I1.
[0082] 4:1 multiplexer: It has 4 inputs (I0, I1, I2, I3), one output (Y), and two control signals (S0, S1).
[0083] The control signals can represent 4 combinations (00, 01, 10, 11) to select the corresponding input.
[0084] 8:1 multiplexer: It has 8 input terminals and three control signals, and can select one of the 8 inputs.
[0085] If required by the system, 16:1, 32:1, etc. can also be selected, which are applicable to more complex systems.
[0086] In this embodiment, the multiplexer can refer to Figure 34-to-1 multiplexer. The A and B pins of the multiplexer are connected to the IO interface of the SPAD SoC microcontroller to control the selection of the output channel. The INH pin is the enable signal of the multiplexer and is connected to the SPAD SoC to turn the multiplexer on and off. 1-COM and 2-COM are respectively connected to trig out1 and trig out2 of the SPAD SoC, and these two are the outputs of the drive signals. The 1Y0 to 1Y3 and 2Y0 to 2Y3 pins are respectively corresponding to the cathode drive switches of 1 to 8 of the VCSEL. The SPAD SoC can control the levels of the A and B pins to route trig out1 to 1Y0, 1Y1, 1Y2 or 1Y3, and route tirg out2 to 2Y0, 2Y1, 2Y2 or 2Y3.
[0087] Each NAND gate corresponds to a binary number. When AB is any value, a NAND gate will be selected for output. Figure 3 The NAND gates in [reference] are numbered from top to bottom, and the following table can be obtained:
[0088]
[0089] The trig out1 / 2 signal can expand the selection range of the 4-to-1 multiplexer. In this embodiment, the 4-to-1 multiplexer is expanded to an 8-to-1 multiplexer.
[0090] The specific routing channels are as shown in [reference] Figure 4 When the A and B pins are both at low level, the drive signals of trig out1 / 2 are routed to 1 / 2Y0; when A is at low level and B is at high level, the drive signals of trig out1 / 2 are routed to 1 / 2Y1; when A is at high level and B is at low level, the drive signals of trig out1 / 2 are routed to 1 / 2Y2; when A and B are both at high level, the drive signals of trig out1 / 2 are routed to 1 / 2Y3; this method can achieve that in the left and right regions of the VCSEL, one block is lit in each region at the same time.
[0091] It should be noted that Trig out1 and Trig out2 can also output drive signals staggeredly, which can achieve more lighting modes of different blocks of the VCSEL, as shown in [reference] Figure 5 -[reference] Figure 7 shown, which is the drive signal routing of different block lighting modes.
[0092] In an embodiment of the present invention, optionally, the drive signal shaping circuit includes: N shaping sub-circuits, the input ends of the N shaping sub-circuits are respectively connected to the output ends of N drive signals; the output ends of the N shaping sub-circuits are respectively corresponding to N cathode output ports.
[0093] Due to the limited driving ability of the signal of the control chip, it cannot directly provide high-quality driving signals that meet various application requirements. It cannot provide sufficient current or sufficient driving force to drive multiple loads or achieve high-precision signal transmission. In addition, when the signal passes through the multiplexer, the quality of the signal will further deteriorate, especially the edges of the signal (i.e., the rising edge and falling edge of the signal) will become blurred or unstable, which will affect the accuracy and response time of the device. In order to ensure that the driving signal can be accurately transmitted and meet the application requirements of high precision and high stability, a signal shaping circuit needs to be added to the signal path.
[0094] Due to the limited driving ability of the SPAD SoC trig out signal, it cannot output driving signals that fully meet various application requirements, and the edges of the driving signal will also deteriorate after this signal passes through the multiplexer. A signal shaping circuit is needed to adjust the driving signal. As shown in the appendix Figure 8 As shown, the driving shaping circuit includes an RC circuit, a dual-channel buffer U1, and a high-speed comparator U2. The RC circuit is used to adjust the width of the driving signal. The U1 buffer adjusts the signal edge to make the rising and falling edges of the signal stable and maintain a high slope. The U2 high-speed comparator can compare the time difference between the two signals output by the previous stage and finally output a driving signal that meets the width requirements.
[0095] Different RC values form different RC time constants τ, which play a decisive role in the width of the finally output driving signal. The selection value of RC can be adjusted according to the width of the driving signal required by the actual application. As shown in the appendix Figure 9 are the signals of each node of the driving shaping circuit.
[0096] In an embodiment of the present invention, optionally, the anode control end includes M anode output ports;
[0097] The M anode output ports output anode driving signals to the M anode ports; the anode control end further includes an anode signal input end, and the anode signal input end is connected to the I / O pin of the control chip.
[0098] In an embodiment of the present invention, optionally, the control chip controls the anode control end through a control bus or a hard wire.
[0099] In this solution, the control chip controls the high-side integrated chip to open the corresponding channel through the control bus or the hard wire to realize the control of the anode control end.
[0100] Embodiment 2:
[0101] As shown in the appendix Figure 10 As shown, the present application proposes a method based on the lidar two-dimensional scanning driving system described in the first aspect. The method includes:
[0102] S1: Drive the x-th anode drive port;
[0103] S2: Drive the y-th cathode drive port;
[0104] S3: Turn on the laser unit at the coordinates (x, y) of the area array laser;
[0105] Wherein, x is any integer less than or equal to M, and y is any integer less than or equal to N;
[0106] The specific step S1 is: The control chip sends an anode control signal to the anode control terminal, and the anode control terminal outputs an anode drive signal to the area array laser;
[0107] As shown in the appendix Figure 11 As shown, the specific step S2 is:
[0108] S21: The control chip sends a cathode control signal to the multiplexer;
[0109] S22: The multiplexer outputs a drive signal to the drive signal shaping circuit based on the internal logic gate according to the cathode control signal;
[0110] S23: The drive signal shaping circuit shapes the drive signal and outputs a cathode drive signal to the area array laser.
[0111] This application uses a multiplexer and a drive signal shaping circuit to replace the FPGA chip, making full use of the hardware resources of the SPAD SoC and reducing the use of high-cost devices such as FPGAs to achieve an overall low-cost solution;
[0112] The devices used in this solution are small in size, which can save the PCB space and the design of the heat dissipation structure, making the design of the pure solid-state lidar product miniaturized.
[0113] The high-side drive is driven by the built-in microcontroller of the SPAD SoC, and the low-side routing scheme is used to replace the FPGA. The low-side routing scheme consists of a multiplexer and a drive signal shaping circuit. This scheme enables the SPAD SoC to control the high-side integrated chip to open the corresponding channels through the control bus or hard wire to achieve the control of the VCSEL anode. The low-side drive of the cathode is realized by the SPAD SoC outputting a drive signal to drive the gallium nitride switch tube through the low-side routing circuit.
[0114] Embodiment 3:
[0115] This application proposes a lidar two-dimensional scanning drive circuit, and the circuit includes: the lidar two-dimensional scanning drive system described in Embodiment 1 and a circuit protection board; the lidar two-dimensional scanning drive system is integrated on the circuit protection board.
[0116] In summary, the present application proposes a two-dimensional scanning drive system, method and circuit for a lidar. The two-dimensional scanning drive system of the lidar includes: a control chip: responsible for coordinating and transmitting signals. Anode control terminal and cathode control terminal: The control chip transmits signals to the anode control terminal and the cathode control terminal respectively to control the operation of the area array laser. Area array laser: The area array laser consists of multiple ports, including N cathode drive ports and M anode ports, where N is an even number and M is a natural number greater than 1. The cathode control terminal includes two parts: a multiplexer: used to receive the cathode control signal from the control chip, and after being processed by the internal logic circuit, transmit the drive signal to the drive signal shaping circuit. The drive signal shaping circuit is used to receive and process the drive signal transmitted by the multiplexer, ensure that the output signal is suitable for driving the area array laser, and finally transmit the processed cathode drive signal to the cathode drive port.
[0117] The present application uses a multiplexer and a drive signal shaping circuit to replace the FPGA chip, making full use of the hardware resources of the SPAD SoC and reducing the use of high-cost devices such as FPGAs, thus realizing an overall low-cost solution;
[0118] The devices used in this solution are of small size, which can save the PCB space and the design of the heat dissipation structure, making the design of the all-solid-state lidar product miniaturized.
[0119] In several embodiments provided by the present application, it can be understood that each block in the flowchart or block diagram may represent a module, a program segment, or a part of code, and the module, program segment, or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved.
[0120] When the above-mentioned functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art or part of this technical solution can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing an electronic device to execute all or part of the steps of the methods described in various embodiments of this application. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs that can store program codes.
[0121] The specific embodiments described above further elaborate on the purpose, technical solution, and beneficial effects of this application. It should be understood that the above description is only the specific embodiments of this application and is not used to limit the protection scope of this application. It is particularly pointed out that for those skilled in the art, any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of this application shall be included in the protection scope of this application.
Claims
1. A laser radar two-dimensional scanning drive system, the laser radar two-dimensional scanning drive system comprising: Control chip, anode control terminal, cathode control terminal and area array laser; The control chip transmits an anode control signal to the anode control terminal; The control chip transmits the cathode control signal to the cathode control terminal; The anode control end and the cathode control end are connected to the area array laser; It is characterized in that the cathode control end includes a multiplexer and a drive signal shaping circuit, the multiplexer receives the cathode control signal and outputs the drive signal to the drive signal shaping circuit, and the drive signal shaping circuit shapes the drive signal and then outputs the cathode drive signal to the cathode control end. The planar array laser comprises: N cathode drive ports and M anode drive ports, wherein N is an even number and M is a natural number greater than 1.
2. The laser radar two-dimensional scanning drive system according to claim 1, characterized in that: The cathode control end includes N cathode output ports, and the N cathode output ports are respectively connected to the N cathode driving ports; the cathode control end also includes an enable port, and the enable port is connected to the enable end of the control chip.
3. The laser radar two-dimensional scanning drive system according to claim 2, characterized in that: The cathode controller also includes P control signal receiving terminals, and the P control signal receiving terminals are connected to the trigger port 1 of the control chip to the trigger port P respectively; the cathode control terminal also includes a cathode signal receiving terminal, the A cathode signal receiving end is connected to the I / O pin of the control chip; wherein N and P meet the conditions: Is a positive integer.
4. The laser radar two-dimensional scanning drive system according to claim 3, characterized in that: The multiplexer comprises: logic 1 output and A logic 0 output terminal, and a logic 1 output terminal and a corresponding logic 0 output terminal form a binary digital output terminal; the multiplexer also includes N / P NAND gates and an enable terminal.
5. The laser radar two-dimensional scanning drive system according to claim 4, characterized in that: The multiplexer also includes: the N / P NAND gates include multiple input terminals, one of which is connected to the enable terminal, and the remaining input terminals are respectively connected to the binary digital output terminals in binary numerical order; the N / P NAND gates and P control signal receiving terminals constitute N drive signal output terminals.
6. The laser radar two-dimensional scanning drive system according to claim 4, characterized in that: The driving signal shaping circuit comprises: N shaping sub-circuits, wherein the input ends of the N shaping sub-circuits are respectively connected to N driving signal output ends; and the output ends of the N shaping sub-circuits are respectively corresponding to N cathode output ports.
7. The laser radar two-dimensional scanning drive system according to claim 1, characterized in that: The anode control terminal includes M anode output ports; The M anode output ports output anode drive signals to the M anode drive ports; the anode control end further includes an anode signal input end, and the anode signal input end is connected to the I / O pin of the control chip.
8. The laser radar two-dimensional scanning drive system according to claim 6, characterized in that: The control chip controls the anode control terminal via a control bus or a hard line.
9. A method based on the laser radar two-dimensional scanning driving system according to any one of claims 1 to 8, characterized in that: The method comprises: S1: drives the xth anode drive port; S2: drives the yth cathode drive port; S3: The laser unit with coordinates (x, y) of the area array laser is lit; Wherein, x is any integer less than or equal to M, and y is any integer less than or equal to N; The step S1 specifically includes: the control chip sends an anode control signal to the anode control terminal, and the anode control terminal outputs an anode drive signal to the area array laser; The step S2 is specifically as follows: S21: The control chip sends a cathode control signal to the multiplexer; S22: the multiplexer outputs a driving signal to a driving signal shaping circuit based on an internal logic gate according to the cathode control signal; S23: The drive signal shaping circuit shapes the drive signal and outputs a cathode drive signal to the area array laser.
10. A laser radar two-dimensional scanning driving circuit, the circuit comprising: The laser radar two-dimensional scanning drive system and circuit protection board as described in any one of claims 1 to 8; The laser radar two-dimensional scanning drive system is integrated on the circuit protection board.