Laser radar echo signal acquisition system and method

Abstract

The embodiment of the invention provides a laser radar echo signal acquisition system and method, and the system comprises a soft core processor which is used for driving a signal acquisition module to acquire a radar echo optical signal through a JESD module according to preset first configuration information, and the first configuration information is the configuration information of a register in the signal acquisition module; the signal acquisition module is used for determining a radar echo digital signal according to the acquired radar echo optical signal; the JESD module is used for acquiring a radar echo digital signal and converting the radar echo digital signal into a parallel echo digital signal; and the data splicing module is used for splicing the received parallel echo digital signals and converting the spliced radar echo digital signals into radar echo digital signals in a low clock domain through an asynchronous first-in first-out buffer. The signal acquisition module with the JESD interface is used for acquiring echo signals, so that the signal acquisition rate is increased; and the signal acquisition module is driven and controlled through the soft core processor, so that the subsequent debugging efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of radar transceiver, and particularly to a lidar echo signal acquisition system and method. Background Art

[0002] Lidar is a technology that measures the position and distance of targets by emitting laser beams and receiving echo signals, and is widely used in many industries, including autonomous driving, robot navigation, environmental perception, and map making. With the continuous development of technology, the performance of lidar has been continuously improved, and the improvement of the echo signal sampling rate is a key indicator among them.

[0003] For the sampling of echo signals, usually an analog-to-digital converter (ADC) chip with a low voltage differential signaling (LVDS) interface is used, and the sampling rate can reach 1 Gbps. The ADC chip is driven and configured by writing registers through a field programmable gate array (FPGA), and the corresponding ADC signals are read back for subsequent processing.

[0004] However, the sampling rate of the existing solution is limited by the LVDS interface and can only reach 1 Gbps. For the existing application requirements, the data volume can reach a throughput of several G or even dozens of G, and the acquisition method using the LVDS interface cannot be achieved. At the same time, the ADC chip with the LVDS interface consumes more pins. When using a high-resolution ADC chip, a large number of pins will be consumed for data transmission. And the method of directly writing registers by the FPGA to drive and control the ADC chip or other slave devices is single, and the debugging efficiency is slow. Summary of the Invention

[0005] An embodiment of the present invention provides a lidar echo signal acquisition system and method. By using a signal acquisition module with a JESD interface to acquire echo signals, the signal acquisition rate is improved; and the subsequent debugging efficiency is improved by driving and controlling the signal acquisition module through a soft-core processor.

[0006] In a first aspect, this embodiment provides a lidar echo signal acquisition system, including: a radar main control module and a signal acquisition module with a high-speed serial protocol JESD interface. The radar main control module is based on a field programmable gate array architecture and includes a soft-core processor, a JESD module, and a data splicing module; wherein,

[0007] The soft-core processor is used to drive the signal acquisition module to acquire the radar echo optical signal through the JESD module according to the preset first configuration information, where the first configuration information is the configuration information of the registers in the signal acquisition module;

[0008] The signal acquisition module is used to determine the radar echo digital signal according to the acquired radar echo optical signal;

[0009] The JESD module is used to obtain the radar echo digital signal and convert the radar echo digital signal into a parallel echo digital signal;

[0010] The data splicing module is used to splice the received parallel echo digital signal, and convert the spliced radar echo digital signal into a radar echo digital signal in a low clock domain through an asynchronous first-in first-out buffer.

[0011] In a second aspect, this embodiment provides a method for acquiring a lidar echo signal, which is executed by the lidar echo signal acquisition system described in the first aspect embodiment. The method includes:

[0012] Through the soft-core processor, according to the preset first configuration information, drive the signal acquisition module to acquire the radar echo optical signal through the JESD module, where the first configuration information is the configuration information of the registers in the signal acquisition module;

[0013] Through the signal acquisition module, determine the radar echo digital signal according to the acquired radar echo optical signal;

[0014] Through the JESD module, obtain the radar echo digital signal and convert the radar echo digital signal into a parallel echo digital signal;

[0015] Through the data splicing module, splice the received parallel echo digital signal, and convert the spliced radar echo digital signal into a radar echo digital signal in a low clock domain through an asynchronous first-in first-out buffer.

[0016] An embodiment of the present invention provides a lidar echo signal acquisition system and method. The system includes a radar main control module and a signal acquisition module with a high-speed serial protocol JESD interface. The radar main control module is based on a field-programmable gate array architecture and includes a soft-core processor, a JESD module, and a data splicing module. Among them, the soft-core processor is used to drive the signal acquisition module to collect lidar echo optical signals through the JESD module according to pre-set first configuration information, and the first configuration information is the configuration information of registers in the signal acquisition module. The signal acquisition module is used to determine lidar echo digital signals according to the collected lidar echo optical signals. The JESD module is used to obtain the lidar echo digital signals and convert the lidar echo digital signals into parallel echo digital signals. The data splicing module is used to splice the received parallel echo digital signals and convert the spliced lidar echo digital signals into the lidar echo digital signals in a low clock domain through an asynchronous first-in-first-out buffer. This system uses a signal acquisition module with a JESD interface to collect lidar echo signals, improving the signal acquisition rate. In addition, by implementing a soft-core processor inside the field-programmable gate array architecture to drive and control the signal acquisition module, the convenience and efficiency of subsequent debugging are improved. Description of the Drawings

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0018] Figure 1 It is a schematic structural diagram of a lidar echo signal acquisition system provided in Embodiment 1 of the present invention;

[0019] Figure 2 It is a schematic structural diagram of another lidar echo signal acquisition system provided in Embodiment 1 of the present invention;

[0020] Figure 3 It is a schematic structural diagram of another lidar echo signal acquisition system provided in Embodiment 1 of the present invention;

[0021] Figure 4 It is a schematic structural diagram of another lidar echo signal acquisition system provided in Embodiment 1 of the present invention;

[0022] Figure 5 It is a schematic structural diagram of another lidar echo signal acquisition system provided in Embodiment 1 of the present invention;

[0023] Figure 6 This is a schematic flowchart of a method for collecting lidar echo signals provided in the second embodiment of the present invention. Detailed implementation manners

[0024] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0025] It should be noted that the terms "original", "target", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0026] Embodiment 1

[0027] Figure 1 This is a schematic structural diagram of a lidar echo signal acquisition system provided in the first embodiment of the present invention. This embodiment is applicable to the situation of collecting lidar echo signals. The system can be implemented by hardware and / or software and is generally integrated in a computer device. As Figure 1As shown in the figure, the system includes a radar main control module 10 and a signal acquisition module 20 with a high-speed serial protocol JESD interface. The radar main control module 10 is based on a field programmable gate array architecture and includes a soft-core processor 11, a JESD module 12, and a data splicing module 13. Among them, the soft-core processor 11 is used to drive the signal acquisition module 20 to collect radar echo optical signals through the JESD module according to pre-set first configuration information, and the first configuration information is the configuration information of the registers in the signal acquisition module 20. The signal acquisition module 20 is used to determine radar echo digital signals according to the collected radar echo optical signals. The JESD module 12 is used to obtain radar echo digital signals and convert the radar echo digital signals into parallel echo digital signals. The data splicing module 13 is used to splice and process the received parallel echo digital signals, and convert the spliced and processed radar echo digital signals into radar echo digital signals in a low clock domain through an asynchronous first-in first-out buffer.

[0028] In this embodiment, the lidar echo signal acquisition system includes a radar main control module 10 and a signal acquisition module 20. When the lidar detects a target object, the target object will reflect the radar echo, denoted as the radar echo optical signal, and the signal acquisition module 20 is used to collect the radar echo optical signal reflected by the target object. Different from the limited sampling rate of the ADC chip with an LVDS interface in the prior art, in this embodiment, the signal acquisition module 20 with a JESD interface is used to collect the radar echo optical signal. Using the signal acquisition module 20 with a JESD interface to collect the radar echo optical signal can improve the signal acquisition rate, and the single-channel (Lane) transmission rate of the JESD interface can reach up to 12.5 Gbps.

[0029] According to the above description, in this embodiment, the signal acquisition module 20 can use an ADC chip with a JESD interface to collect the radar echo optical signal. Preferably, the ADC chip used is a 12-bit dual-channel ADC chip. The dual-channel ADC chip has a total of 8 Lanes, and the transmission rate of each Lane reaches 10 Gbps. The sampling rate of a single ADC chip can reach 2 Gsps, and on the basis of realizing dual-channel 12-bit sampling, only 8 pairs of pins are occupied. Compared with the existing LVDS interface acquisition method, it not only improves the signal transmission rate, but also can ensure high resolution without consuming too many FPGA pins. For application scenarios that require the use of an ADC chip with high resolution, compared with the LVDS interface, the ADC acquisition solution with a JESD interface requires fewer input / output (I / O) pins, which is convenient for integrating other modules.

[0030] In this embodiment, the radar main control module 10 is based on a field-programmable gate array (FPGA) architecture. The radar main control module 10 includes a soft-core processor 11, a JESD module 12, and a data splicing module 13.

[0031] Considering the method of writing registers in the signal acquisition module using FPGA in the prior art, that is, configuring registers through Register Transfer Level (RTL) design code and logic. When the register configuration needs to be modified, the RTL design needs to be re-modified to configure the registers, resulting in low debugging efficiency and high costs. To address this issue, a soft-core processor 11 is implemented inside the radar main control module 10 in this embodiment. The soft-core processor 11 can be understood as a Central Processing Unit (CPU). The soft-core processor 11 can be implemented by a MicroBlaze IP core, which has the advantages of fast running speed, less resource occupation, and strong configurability. The corresponding functions can be simply implemented without using an independent CPU solution. The MicroBlaze embedded soft-core is an optimized microprocessor soft-core that can be embedded in an FPGA. Based on the soft-core processor, developers can directly configure the registers in the signal acquisition module and slave devices in the Software Development Kit (SDK) to drive the signal acquisition module and various slave devices, improving development efficiency.

[0032] The soft-core processor 11 is used to drive the signal acquisition module 20 to collect radar echo optical signals according to the pre-set first configuration information through the JESD module 12. The first configuration information is the configuration information of the registers in the signal acquisition module 20. Developers can configure the registers in the signal acquisition module 20 through the SDK, and record this configuration information as the first configuration information. The first configuration information may include calibration information, reset information, etc. Specifically, the soft-core processor 11 is used to drive the signal acquisition module 20 to collect the radar echo optical signals returned by the target object according to the first configuration information through the JESD module 12. Exemplarily, the soft-core processor 11 transmits the first configuration information to the JESD module 12 through the AXI bus, and the JESD module 12 transmits the first configuration information to the signal acquisition module 20 to drive the signal acquisition module 20 to collect radar echo optical signals.

[0033] Among them, the signal acquisition module 20 is used to determine the radar echo digital signal according to the acquired radar echo optical signal. In this embodiment, the soft-core processor 11 drives the signal acquisition module 20 to collect radar echoes. After the signal acquisition module 20 collects the radar echo optical signal returned by the target object, it needs to first convert the radar echo optical signal into a radar echo electrical signal, and then convert the radar echo electrical signal into a radar echo digital signal, and transmit the radar echo digital signal to the radar main control module 10, so that the radar main control module 10 processes the acquired radar echo digital signal and sends the processed point cloud data to the host computer.

[0034] Among them, the JESD module 12 is used to obtain the radar echo digital signal and convert the radar echo digital signal into a parallel echo digital signal. Specifically, the JESD module 12 picks up the radar echo digital signal on each Lane and outputs it in the low clock domain; at the same time, it outputs a configuration signal to ensure data synchronization during high-speed transmission without problems such as disorder and data loss. It can be understood that the JESD module 12 gives a synchronization signal to the signal acquisition module 20, and the data needs to be aligned when transmitting data. After alignment, the data can be sent and received, that is, to achieve data synchronization from the signal acquisition module 20 to the radar main control module 10 and align the clocks. After synchronization, the serial radar digital signal is converted into a parallel signal, denoted as the parallel echo digital signal.

[0035] Among them, the data splicing module 13 is used to splice the received parallel echo digital signal and convert the spliced serial echo digital signal into a radar echo digital signal through an asynchronous first-in first-out buffer.

[0036] In this embodiment, considering the wiring problem of the interface of the signal acquisition module 20, there may be a situation where data arrives out of order. It is necessary to splice the echo data output by the JESD module 12. Exemplarily, there may be a high-low bit misalignment in the received echo digital signal. For example, a signal that should originally be in the high eight bits is received in the low eight bits. At this time, splicing is required. Move the low eight bits to the high eight bits and move the high eight bits to other places to sort them in the correct order. Specifically, splice the data output by the JESD module 12 to obtain the radar echo digital signal. While ensuring the correct data sorting, convert the radar echo digital signal into the required 12-bit data through an asynchronous first-in-first-out buffer (First In First Out, FIFO) for the data transmitted by the JESD module 12, that is, the radar echo digital signal, and send the radar echo digital signal to the subsequent processing module. The role of the FIFO is to perform cross-clock domain processing on the radar echo digital signal. Since the data acquisition module 20 is acquired in a high-speed clock domain, and the subsequent processing of the acquired data cannot reach such a high rate, therefore, cross-clock domain processing needs to be performed through the FIFO to obtain the radar echo digital signal in the low clock domain. Since the sampling rate of the radar echo optical signal collected by the JESD interface is relatively high, and various subsequent processing modules cannot process at such a high clock, therefore, convert the radar echo digital signal into the radar echo digital signal in the low clock domain in the low clock domain.

[0037] It should be noted that by using an ADC chip with an FPGA+JESD interface to collect lidar echo signals, the efficiency of echo data collection can be improved, the pins of the FPGA can be saved, the wiring complexity can be reduced, and the flexibility and scalability of the system can be improved. Based on the soft-core processor, developers can directly debug the registers through the SDK software and modify the configuration information without configuring the registers by modifying the RTL design, which improves the debugging efficiency of developers. Moreover, the operation of modifying the registers in the SDK is simple, and even personnel without FPGA development experience can configure the registers, which is convenient for joint debugging with other software developers. By using the method of implementing the CPU inside the FPGA to drive the registers of the ADC chip and various slave devices, the module debugging difficulty is reduced, the debugging efficiency is improved, and it is convenient for joint debugging with other software developers.

[0038] The embodiment of the present invention provides a laser radar echo signal acquisition system, which includes: a radar main control module and a signal acquisition module carrying a high-speed serial protocol JESD interface, the radar main control module is based on a field programmable gate array architecture, and includes a soft-core processor, a JESD module and a data splicing module; wherein the soft-core processor is used to drive the signal acquisition module to acquire radar echo optical signals through the JESD module according to a pre-set first configuration information, and the first configuration information is the configuration information of the register in the signal acquisition module; the signal acquisition module is used to determine the radar echo digital signal according to the acquired radar echo optical signal; the JESD module is used to obtain the radar echo digital signal and convert the radar echo digital signal into a parallel echo digital signal; the data splicing module is used to splice the received parallel echo digital signals, and convert the spliced ​​radar echo digital signals into radar echo digital signals in a low clock domain through an asynchronous first-in-first-out buffer. The system uses a signal acquisition module with a JESD interface to acquire radar echo signals, thereby improving the signal acquisition rate. In addition, by implementing a soft-core processor inside the field programmable gate array structure to drive and control the signal acquisition module, the convenience and efficiency of subsequent debugging are improved.

[0039] As an optional embodiment of this embodiment, based on the above embodiment, this optional embodiment further refines the functions of the soft core processor 11 and the JESD module 12. The soft core processor 11 is used to transmit the first configuration information to the JESD module 12; the JESD module 12 is used to transmit the first configuration information to the signal acquisition module 20 to drive the signal acquisition module 20 to collect the radar echo light signal.

[0040] In this embodiment, a soft-core processor 12 is implemented internally through the MicroBlaze IP core to drive and control the JESD module 12 and the signal acquisition module 20. Specifically, the soft-core processor 11 transmits the first configuration information to the JESD module 12, and the JESD module 12 transmits the first configuration information to the signal acquisition module 20. When the first configuration information is transmitted to the signal acquisition module 20, it is equivalent to realizing the configuration of the registers in the signal acquisition module 20, thereby driving the signal acquisition module 20 to collect the radar echo optical signal. The soft-core processor 12 and each module exchange data through the bus protocol (Advanced eXtensibleInterface, AXI). Since the interactive data in this embodiment is configuration information, the throughput requirement for data transmission is not high. For example, it can be implemented in the form of the AXI4-Lite bus protocol.

[0041] The above technical solution specifies the step in which the soft-core processor drives the signal acquisition module to collect the radar echo optical signal based on the first configuration information, and realizes the function of driving and controlling the signal acquisition module based on the soft-core processor.

[0042] Figure 2 FIG. 4 is a schematic structural diagram of another lidar echo signal acquisition system provided in the first embodiment of the present invention. As another alternative embodiment of the first embodiment of the present invention, on the basis of the above embodiment, in this alternative embodiment, the signal acquisition module 20 is further refined, as Figure 2 shown, the signal acquisition module 20 includes a front-end processing unit 21 and a 12-bit dual-channel analog-to-digital conversion chip 22. The 12-bit dual-channel analog-to-digital conversion chip 22 has a total of 8 channels; wherein, the front-end processing unit 21 is used to convert the radar echo optical signal reflected by the target object into a radar echo electrical signal and transmit it to the 12-bit dual-channel analog-to-digital conversion chip; the analog-to-digital conversion chip 22 is used to convert the radar echo electrical signal into a radar echo digital signal.

[0043] In this embodiment, the signal acquisition module 20 includes a front-end processing unit 21 and a 12-bit dual-channel analog-to-digital conversion chip 22. The front-end processing unit 21 converts the radar echo optical signal reflected by the target object into a radar echo electrical signal and sends it into the 12-bit dual-channel analog-to-digital conversion (ADC) chip. The radar echo electrical signal is converted into a radar echo digital signal by the ADC chip and sent into the radar main control module 10 for subsequent processing, and the radar main control module 10 is used to interact with the ADC chip for configuration information.

[0044] Preferably, the ADC chip uses a 12-bit dual-channel ADC chip, which has a total of 8 channels (Lanes). The transmission rate of each Lane reaches 10 Gbps, and the sampling rate of a single ADC chip can reach 2 Gsps. Moreover, on the basis of realizing dual-channel 12-bit sampling, only 8 pairs of pins are occupied. Compared with the existing LVDS interface acquisition method, it not only improves the signal transmission rate, but also can ensure high resolution without consuming too many FPGA pins.

[0045] The above technical solution specifies that the signal acquisition module includes a front-end processing unit and a dual-channel analog-to-digital conversion chip, realizes the conversion of the collected radar echo optical signal into a radar echo electrical signal, and then converts the radar echo electrical signal into a radar echo digital signal for transmitting the radar echo digital signal to the radar main control module for subsequent processing.

[0046] As another alternative embodiment of the first embodiment of the present invention, on the basis of the above embodiment, in this alternative embodiment, the function of the JESD module 12 is further refined. The JESD module 12 is specifically used for:

[0047] a) Send data synchronization configuration information to the signal acquisition module 20.

[0048] Among them, the data synchronization configuration information can be understood as the synchronization signal sent by the host to the slave, which is used to ensure data synchronization during data transmission. Specifically, the JESD module 12 sends data synchronization configuration information to the signal acquisition module 20 to ensure data synchronization during the high-speed transmission from the signal acquisition module 20 to the radar main control module 10, and to avoid problems such as data disorder and data loss.

[0049] b) Pick up the radar echo digital signals on each channel of the 12-bit dual-channel analog-to-digital conversion chip respectively.

[0050] Specifically, the JESD module 12 is used to pick up the data on 8 lanes, that is, pick up the radar echo digital signals on each channel of the 12-bit dual-channel analog-to-digital conversion chip.

[0051] c) Convert the radar echo digital signals into multi-channel parallel echo digital signals and output each channel of parallel echo digital signals to the data splicing module 13.

[0052] In this embodiment, the radar echo digital signals are converted into multi-channel parallel echo digital signals and output to the data splicing module 13.

[0053] The above technical solution refines the function of the JESD module, and realizes the conversion of the serial radar echo digital signals into parallel echo digital signals and output to the data splicing module 13.

[0054] Figure 3 FIG. 22 is a schematic structural diagram of another lidar echo signal acquisition system provided in the first embodiment of the present invention. As an optional embodiment of the present invention, on the basis of the above embodiment, the radar main control module 10 can be optimized, and further includes a slave device driver module 14; the soft-core processor 11 is further configured to drive and control at least one slave device 30 through the slave device driver module 14 according to the pre-set second configuration information.

[0055] Similar to the case of driving and controlling the signal acquisition module by the soft-core processor, considering that in the prior art, the method of writing registers in the slave device by FPGA, that is, configuring the registers through RTL design code and logic, when the configuration of the registers needs to be modified, it is necessary to re-modify the RTL design to configure the registers, resulting in low debugging efficiency and high cost. To solve this problem, in this embodiment, the soft-core processor 11 implemented inside the radar main control module 10 is also used to drive and control the slave device 30.

[0056] Among them, the second configuration information is the configuration information of the registers in the slave device 30. The slave device 30 can be a temperature sensor, a voltage sensor, etc. The temperature sensor is used to pick up temperature information, and the voltage sensor is used to pick up voltage information. There is no specific limitation on what the slave device specifically includes here. During the process of the signal acquisition module 20 high-speed acquiring radar echoes, the radar main control module 10 can also perform data interaction with various slave devices 30.

[0057] In this embodiment, developers can configure the registers in the signal acquisition module 20 through the SDK, and record this configuration information as the second configuration information. Among them, the second configuration information may include calibration information, reset information, etc. Specifically, the soft-core processor 11 is used to drive and control at least one slave device 30 through the slave device driver module 14 according to the second configuration information, so that the slave device 30 acquires corresponding data. Exemplarily, the soft-core processor 11 transmits the second configuration information to the slave device driver module 14 through the AXI bus, and the slave device driver module 14 transmits the second configuration information to the slave device 30 to drive the slave device 30 to acquire corresponding data.

[0058] Different from the prior art where the register is controlled by writing to the register, in this embodiment, the soft-core processor 12 is used to drive and control the slave device.

[0059] The above technical solution adds the function of driving and controlling the slave device through the soft-core processor.

[0060] Furthermore, the soft-core processor 11 can be optimized to transmit the second configuration information to the slave device driver module 14; the slave device driver module 14 is used to transmit the second configuration information to the slave device to drive the slave device to acquire sensor signals.

[0061] In this embodiment, a soft-core processor 11 is implemented internally through the MicroBlaze IP core. In addition to driving and controlling the JESD module 12 and the signal acquisition module 20, it can also drive and control the slave device 30. Specifically, the soft-core processor 11 transmits the second configuration information to the slave device driver module 14, and the slave device driver module 14 transmits the second configuration information to the slave device 30. When the second configuration information is transmitted to the slave device 30, it is equivalent to configuring the registers in the slave device 30, thereby driving the slave device 30 to collect the radar echo optical signal. The soft-core processor 12 and each module perform data interaction through the AXI bus protocol of the bus. Since the interaction data in this embodiment is configuration information and the throughput requirement for data transmission is not high, exemplarily, it can be implemented in the manner of the AXI4-Lite bus protocol. By interacting with the soft-core processor 11 for configuration information, the register operations of various slave devices 30 are performed to realize the function of driving and controlling various slave devices 30.

[0062] The above technical solution specifies the steps of the soft-core processor driving and controlling the slave device based on the second configuration information, and realizes the function of driving and controlling the slave device based on the soft-core processor.

[0063] As an alternative embodiment of the embodiment of the present invention, on the basis of the above embodiment, the soft-core processor 11 is further configured to: read the first current configuration information of the registers in the signal acquisition module 20 through the JESD module 12; read the second current configuration information of the registers in the slave device 30 through the slave device driver module 14.

[0064] In this embodiment, the configuration information of the registers in the signal acquisition module 20 at the current moment is recorded as the first current configuration information, and the configuration information of the registers in the slave device 30 at the current moment is recorded as the second current configuration information. Specifically, the soft-core processor 11 reads the first current configuration information of the registers in the signal acquisition module 20 through the JESD module 12; reads the second current configuration information of the registers in the slave device 30 through the slave device driver module 14. It can be understood that the soft-core processor 11 can read back the configuration information of the registers in the signal acquisition module 20 and the registers in the slave device 30.

[0065] The above technical solution adds the function of the soft-core processor to read the current configuration information of the registers in the signal acquisition module and the slave device, and realizes the data interaction between the soft-core processor and the signal acquisition module and the data interaction between the soft-core processor and the slave device.

[0066] Figure 4This is a schematic structural diagram of another lidar echo signal acquisition system provided by Embodiment 1 of the present invention. As an alternative embodiment of the present invention, on the basis of the above embodiment, the radar main control module 10 can be further optimized to include: a signal processing module 15 and a data transmission module 16; wherein, the signal processing module 15 is used to convert the radar echo digital signal into point cloud data and transmit it to the data transmission module 16; the data transmission module 16 is used to transmit the point cloud data to the host computer 40.

[0067] In this embodiment, the radar main control module 10 further includes a signal processing module 15 and a data transmission module 16. The signal processing module 15 processes the collected radar echo digital signal and converts it into point cloud data for output. The data transmission module 16 transmits the point cloud data and other configuration information to the host computer 50 through Ethernet or serial port.

[0068] The above technical solution adds that the radar main control module further includes a signal processing module and a data transmission module, which are used to convert the collected radar echo digital signal into point cloud data and transmit it to the host computer, realizing the acquisition and upload of radar echoes.

[0069] Figure 5 This is a schematic structural diagram of another lidar echo signal acquisition system provided by Embodiment 1 of the present invention. As an alternative embodiment of the present invention, the radar main control module 10 further includes a debugging module 17, which is specifically used for: receiving the first modified configuration information of the registers in the signal acquisition module 20 from the user to debug the registers in the signal acquisition module 20; receiving the second modified configuration information of the registers in the slave device 30 from the user to debug the registers in the slave device 30.

[0070] Among them, the user can be understood as a developer. In this embodiment, the modified configuration information of the registers in the signal acquisition module 20 is recorded as the first modified configuration information, and the modified configuration information of the registers in the slave device 30 is recorded as the second modified configuration information.

[0071] Considering that the method of directly writing registers by FPGA to drive and control ADC chips or other slave devices in the prior art is relatively single and the debugging efficiency is slow. Exemplarily, in the prior art, when adding certain functions or wanting to rewrite registers, it is necessary to rewrite RTL and compile, and each modification requires recompilation, resulting in a long development cycle. In this embodiment, a soft-core processor is implemented inside the radar main control module 10 through the IP core of MicroBlaze to drive and control the signal acquisition module 20 and other slave devices 30. During the debugging process, the registers can be directly controlled, improving the debugging efficiency of developers and facilitating joint debugging with other software developers.

[0072] Continuing with the above description, the debugging module 17 can provide a human-machine interaction interface for developers to perform debugging operations on the signal acquisition module and the registers in the slave device. The debugging module can be presented in the form of an SDK software. Developers can directly debug the registers through the SDK software, modify the configuration information, without having to configure the registers by modifying the RTL design, which improves the debugging efficiency of developers. Moreover, the operation of modifying registers in the SDK is simple, and even those without FPGA development experience can configure the registers, facilitating joint debugging with other software developers.

[0073] Embodiment 2

[0074] Figure 6 FIG. is a schematic flowchart of a method for collecting lidar echo signals provided by Embodiment 2 of the present invention. This embodiment is applicable to the situation of collecting lidar echo signals. This method can be executed by a lidar echo signal acquisition system, which can be implemented by software and / or hardware and is generally integrated in a computer device. As Figure 2 shown, the method specifically includes the following operations:

[0075] S210. Through the soft-core processor, according to the pre-set first configuration information, drive the signal acquisition module through the JESD module to collect the radar echo optical signal.

[0076] In this embodiment, the lidar echo signal acquisition system includes a radar main control module and a signal acquisition module. When the lidar detects a target object, the target object will reflect the radar echo, denoted as the radar echo optical signal. The signal acquisition module is used to collect the radar echo optical signal reflected by the target object. Different from the limited sampling rate of the ADC chip using the LVDS interface in the prior art, in this embodiment, the signal acquisition module with the JESD interface is used to collect the radar echo optical signal. Using the signal acquisition module with the JESD interface to collect the radar echo optical signal can improve the signal acquisition rate, and the Lane transmission rate of the JESD interface can reach up to 12.5 Gbps at most.

[0077] Continuing with the above description, in this embodiment, the signal acquisition module uses an ADC chip with a JESD interface to collect the radar echo optical signal. Preferably, the ADC chip used is a 12-bit dual-channel ADC chip. The dual-channel ADC chip has a total of 8 Lanes, with a transmission rate of 10 Gbps for each Lane. The sampling rate of a single ADC chip can reach 2 Gsps. Moreover, on the basis of achieving dual-channel 12-bit sampling, only 8 pairs of pins are occupied. Compared with the existing LVDS interface acquisition method, it not only improves the signal transmission rate but also, while ensuring high resolution, does not consume too many FPGA pins. For application scenarios that require an ADC chip with high resolution, compared with the LVDS interface, the ADC acquisition solution with a JESD interface requires fewer I / O pins, facilitating the integration of other modules.

[0078] Considering the method in the prior art of using an FPGA to write the registers in the signal acquisition module, that is, configuring the registers through RTL design code and logic. When the register configuration needs to be modified, it is necessary to re-modify the RTL design to configure the registers, resulting in low debugging efficiency and high costs. To address this problem, in this embodiment, a soft-core processor is implemented inside the radar main control module. The soft-core processor can be understood as a CPU. The soft-core processor can be implemented by the MicroBlaze IP core, which has the advantages of fast operating speed, low resource occupancy, and strong configurability. The corresponding functions can be simply implemented without using an independent CPU solution. The MicroBlaze embedded soft-core is an optimized microprocessor soft-core that can be embedded in an FPGA. Based on the soft-core processor, developers can directly configure the registers in the signal acquisition module and slave devices in the SDK to drive the signal acquisition module and various slave devices, improving development efficiency.

[0079] Among them, the first configuration information is the configuration information for the registers in the signal acquisition module. Developers can configure the registers in the signal acquisition module through the SDK, and record this configuration information as the first configuration information. Among them, the first configuration information may include calibration information, reset information, etc. Specifically, the soft-core processor drives the signal acquisition module to collect the radar echo optical signal returned by the target object according to the first configuration information through the JESD module. Exemplarily, the soft-core processor transmits the first configuration information to the JESD module through the AXI bus, and the JESD module transmits the first configuration information to the signal acquisition module to drive the signal acquisition module to collect the radar echo optical signal.

[0080] S220. Through the signal acquisition module, determine the radar echo digital signal according to the collected radar echo optical signal.

[0081] In this embodiment, the soft-core processor drives the signal acquisition module to collect radar echo signals. After the signal acquisition module collects the radar echo optical signals returned by the target object, the radar echo optical signals need to be first converted into radar echo electrical signals, and then the radar echo electrical signals are converted into radar echo digital signals. The radar echo digital signals are transmitted to the radar main control module, so that the radar main control module processes the collected radar echo digital signals and sends the processed point cloud data to the host computer.

[0082] S230. Obtain the radar echo digital signals through the JESD module and convert the radar echo digital signals into parallel echo digital signals.

[0083] Specifically, the JESD module picks up the radar echo digital signals on each Lane and outputs them in the low clock domain; at the same time, configuration signals are output to ensure data synchronization during high-speed transmission without problems such as disorder and data loss. It can be understood that the JESD module gives a synchronization signal to the signal acquisition module, and data needs to be aligned when transmitting data. After alignment, data can be sent and received, that is, data synchronization from the signal acquisition module to the radar main control module is achieved, and the clocks are aligned. After synchronization is completed, the serial radar digital signals are converted into parallel signals, denoted as parallel echo digital signals.

[0084] S240. Through the data splicing module, splice and process the received parallel echo digital signals, and convert the spliced and processed radar echo digital signals into radar echo digital signals in the low clock domain through an asynchronous first-in-first-out buffer.

[0085] In this embodiment, considering the wiring problem of the signal acquisition module interface, there may be a situation where data arrives out of order, and the echo data output by the JESD module needs to be spliced. Exemplarily, the received echo digital signals may have high and low bit misalignments. For example, the signal that should originally be in the high eight bits is received in the low eight bits. At this time, splicing is required to move the low eight bits to the high eight bits and move the high eight bits to other places to sort them in the correct order. Specifically, the data output by the JESD module is spliced to obtain radar echo digital signals. On the premise of ensuring correct data sorting, the radar echo digital signals are converted into the required 12-bit data, that is, radar echo digital signals, through an asynchronous FIFO for the data transmitted by the JESD module, and the radar echo digital signals are sent to the subsequent processing module. The role of the FIFO is to perform cross-clock domain processing on the radar echo digital signals. Since the data acquisition module 20 collects data in the high-speed clock domain, and subsequent processing of the collected data cannot reach such a high rate, therefore, cross-clock domain processing needs to be performed through the FIFO to obtain radar echo digital signals in the low clock domain.

[0086] It should be noted that by using an ADC chip with an FPGA + JESD interface to collect lidar echo signals, the efficiency of echo data collection can be improved, the pins of the FPGA can be saved, the wiring complexity can be reduced, and the flexibility and scalability of the system can be enhanced. Based on the soft-core processor, developers can directly debug the registers and modify the configuration information through the SDK software, without having to configure the registers by modifying the RTL design, which improves the debugging efficiency of developers. Moreover, the operation of modifying the registers in the SDK is simple, and even those without FPGA development experience can configure the registers, facilitating joint debugging with other software developers. By using the method of implementing the CPU inside the FPGA to drive the registers of the ADC chip and various slave devices, the difficulty of module debugging is reduced, the debugging efficiency is improved, and it is also convenient for joint debugging with other software developers.

[0087] An embodiment of the present invention provides a method for collecting lidar echo signals, which includes: through a soft-core processor, according to pre-set first configuration information, driving a signal collection module to collect lidar echo optical signals through a JESD module, where the first configuration information is the configuration information of the registers in the signal collection module; through the signal collection module, determining lidar echo digital signals according to the collected lidar echo optical signals; through the JESD module, obtaining the lidar echo digital signals and converting the lidar echo digital signals into parallel echo digital signals; through a data splicing module, splicing and processing the received parallel echo digital signals, and converting the serial echo digital signals after splicing processing into lidar echo digital signals through an asynchronous first-in first-out buffer. In the above technical solution, a signal collection module with a JESD interface is used to collect lidar echo signals, improving the signal collection rate. In addition, by implementing a soft-core processor inside the field programmable gate array structure to drive and control the signal collection module, the convenience and efficiency of subsequent debugging are improved.

[0088] Note that the above is only the preferred embodiment of the present invention and the applied technical principle. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described here. Various obvious changes, re-adjustments, and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments. Without departing from the concept of the present invention, more other equivalent embodiments can be included, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A lidar echo signal acquisition system, characterized in that Including: A radar main control module and a signal acquisition module with a high-speed serial protocol JESD interface. The radar main control module is based on a field programmable gate array architecture and includes a soft-core processor, a JESD module, and a data splicing module. Among them, The soft-core processor is used to drive the signal acquisition module to collect radar echo optical signals through the JESD module according to pre-set first configuration information, and the first configuration information is the configuration information of the registers in the signal acquisition module; The signal acquisition module is used to determine radar echo digital signals according to the collected radar echo optical signals; The JESD module is used to obtain the radar echo digital signals and convert the radar echo digital signals into parallel echo digital signals; The data splicing module is used to splice the received parallel echo digital signals and convert the spliced radar echo digital signals into radar echo digital signals in a low clock domain through an asynchronous first-in first-out buffer.

2. The system according to claim 1, wherein The soft-core processor is used to transmit the first configuration information to the JESD module; the JESD module is used to transmit the first configuration information to the signal acquisition module to drive the signal acquisition module to collect the radar echo optical signals.

3. The system according to claim 1, wherein The signal acquisition module includes a front-end processing unit and a 12-bit dual-channel analog-to-digital conversion chip, and the 12-bit dual-channel analog-to-digital conversion chip has a total of 8 channels. Among them, The front-end processing unit is used to convert the radar echo optical signals reflected by the target object into radar echo electrical signals and transmit them to the 12-bit dual-channel analog-to-digital conversion chip; The 12-bit dual-channel analog-to-digital conversion chip is used to convert the radar echo electrical signals into radar echo digital signals.

4. The system according to claim 3, characterized in that, The JESD module is specifically used for: Sending data synchronization configuration information to the signal acquisition module; Picking up the radar echo digital signals on each channel of the 12-bit dual-channel analog-to-digital conversion chip respectively; Converting the radar echo digital signals into multi-channel parallel echo digital signals and outputting each path of the parallel echo digital signals to the data splicing module.

5. The system according to claim 1, wherein The radar main control module further includes a slave device driving module; The soft-core processor is further used to drive and control at least one slave device through the slave device driving module according to pre-set second configuration information, and the second configuration information is the configuration information of the registers in the slave device.

6. The system according to claim 5, wherein The soft-core processor is used to transmit the second configuration information to the slave device driving module; the slave device driving module is used to transmit the second configuration information to the slave device to drive the slave device to collect sensor signals.

7. The system according to claim 5, wherein The soft-core processor is further used for: Reading the first current configuration information of the registers in the signal acquisition module through the JESD module; Reading the second current configuration information of the registers in the slave device through the slave device driving module.

8. The system according to claim 1, characterized in that The radar main control module further includes: a signal processing module and a data transmission module. Among them, The signal processing module is configured to convert the radar echo digital signal into point cloud data and transmit it to the data transmission module; The data transmission module is configured to transmit the point cloud data to the host computer.

9. The system according to claim 5, characterized in that The radar main control module further includes a debugging module, which is specifically configured to: Receive the first modified configuration information of the registers in the signal acquisition module from the user to debug the registers in the signal acquisition module; Receive the second modified configuration information of the registers in the slave device from the user to debug the registers in the slave device.

10. A method for collecting lidar echo signals, characterized in that, Executed by the lidar echo signal acquisition system according to any one of claims 1-9, the method includes: Through the soft-core processor, according to the pre-set first configuration information, drive the signal acquisition module to collect the radar echo optical signal through the JESD module, and the first configuration information is the configuration information of the registers in the signal acquisition module; Through the signal acquisition module, determine the radar echo digital signal according to the collected radar echo optical signal; Through the JESD module, obtain the radar echo digital signal and convert the radar echo digital signal into a parallel echo digital signal; Through the data splicing module, splice and process the received parallel echo digital signal, and convert the spliced radar echo digital signal into a radar echo digital signal in a low clock domain through an asynchronous first-in first-out buffer.

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