Display panel

Abstract

A display panel includes a plurality of pairs of scan lines extending in a first direction, a plurality of data lines extending in a second direction transverse to the first direction, and a plurality of connection lines extending in the second direction. For each pair of scan lines, the scan lines are supplied with the same electrical signal. The data lines cooperate with the scan lines to define a plurality of pixel regions by interposing two of the data lines between two of the pixel regions adjacent to each other in the first direction in a plan view. Each connecting line is electrically connected to a corresponding pair of scan lines.

Description

[0001] This application is a divisional application of the application with the filing date of January 20, 2020, application number 202010064909.9, and invention title "Display Panel". Technical Field

[0002] The present invention relates to a display panel, and more particularly, to a display panel having a reduced frame size in the lateral direction. Background Art

[0003] In a conventional 1G1D (one-gate one-data) structure for a display panel (e.g., a liquid crystal display (LCD) panel, an organic light emitting diode (OLED) panel, etc.), one row of pixels corresponds to one scan line (also referred to as a gate line), and one column of pixels corresponds to one data line (also referred to as a source line). When a conduction voltage is provided to a scan line, the thin film transistors (TFTs) of the pixels in the corresponding row will conduct, and thus data can be written into the pixels of that row through the TFTs.

[0004] With the progress of technology, today's display panels have an increasingly high display resolution, which means that the number of rows of pixels in the display panel is increasing, resulting in a shorter data writing cycle for writing data into one row of pixels. One of the drawbacks of this trend is that the data writing cycle may become too short for the pixels to be charged to the required data voltage, which will lead to serious display quality problems.

[0005] Figure 1 Shows a conventional 1G2D (one-gate two-data) structure that has been developed to overcome the above problems. In the 1G2D structure, each column of pixels corresponds to two data lines 12, so a conduction voltage can be provided to two scan lines 11 simultaneously, thereby charging two rows of pixels simultaneously. Therefore, the data writing cycle of the 1G2D structure is twice that of the 1G1D structure. However, the increased number of data lines will reduce the aperture ratio of the pixels.

[0006] In addition to the display resolution, the size of the frame border is also of great concern in the display panel industry. A display panel typically includes more than a thousand scan lines extending horizontally. In a conventional design, a plurality of gate driver integrated circuits (ICs) connected to the scan lines are provided on one or two lateral sides of the display panel. The gate driver ICs and the connections between the gate driver ICs and the scan lines occupy a large amount of space in the lateral direction, which is not desirable.

[0007] As Figure 2As shown, to solve this problem, a panel structure is proposed in which a vertically extending connection line 23 is used in a 1G1D structure to connect the scan line 21 to the gate driving IC in the vertical direction. Although the size of the frame border of the display panel is reduced in this way, the vertically extending connection lines 23 arranged parallel to the data lines 22 in the horizontal direction reduce the aperture ratio of the pixels. Summary of the Invention

[0008] Therefore, an object of the present invention is to provide a display panel in which a vertically extending connection line is applied to a 1G2D structure.

[0009] According to the present invention, the display panel includes multiple pairs of scan lines, multiple data lines, and multiple connection lines. The scan lines extend in a first direction. For each pair of scan lines, the same electrical signal is provided to the scan lines. The data lines extend in a second direction transverse to the first direction, and cooperate with the scan lines to define a plurality of pixel regions in the following manner: in a plan view, two of the data lines are inserted between two pixel regions adjacent to each other in the first direction. The connection lines extend in the second direction. Each of the connection lines is electrically connected to a corresponding pair of the multiple pairs of scan lines. Description of the Drawings

[0010] Referring to the accompanying drawings, in the following detailed description of the embodiments, other features and advantages of the present invention will become apparent, where:

[0011] Figure 1 is a schematic diagram showing a conventional 1G2D structure for a display panel;

[0012] Figure 2 is a plan view showing a conventional pixel structure for a display panel, which uses a vertically extending connection line in a conventional 1G1D structure;

[0013] Figure 3 is a plan view of a first embodiment of a pixel structure for a display panel according to the present invention;

[0014] Figure 4 is showing along Figure 3 a cross-sectional view of a part of the first embodiment taken along line A1 - A2 in

[0015] Figure 5 is a plan view showing another implementation of the first embodiment;

[0016] Figure 6 is a plan view of a second embodiment of a pixel structure for a display panel according to the present invention;

[0017] Figure 7 is showing along Figure 6Cross-sectional view of a part of the second embodiment taken along line B1 - B2 in

[0018] Figure 8 is a plan view showing a third embodiment of a pixel structure for a display panel according to the present invention; and

[0019] Figure 9 is a plan view exemplarily showing another application of the embodiment. Detailed Description of the Invention

[0020] Before describing the present invention in more detail, it should be noted that, where appropriate, repeated reference numerals or the trailing parts of reference numerals in the drawings are used to indicate corresponding or similar elements, which may optionally have similar characteristics.

[0021] Figure 3 A plan view showing a first embodiment of a pixel structure for a display panel 30 (e.g., an LCD panel, etc.) according to the present invention is shown. In this embodiment, the display panel 30 is exemplified as an LCD panel using a multi-domain design (where pixel electrodes 35 of adjacent pixel columns extend in different directions), and includes a TFT substrate (in Figure 3(not shown) and a color filter substrate (not shown), and the TFT substrate and the color filter substrate may each be a glass substrate or a plastic substrate. The display panel 30 further includes a plurality of layers formed on the TFT substrate. The plurality of layers include a layer in which a plurality of pairs of scan lines 31 are located or formed (hereinafter referred to as a scan line layer), a layer in which a plurality of data lines 32 are located or formed (hereinafter referred to as a data line layer), and a layer in which a plurality of connection lines 33 are located or formed (hereinafter referred to as a connection line layer). The scan lines 31 extend in a first direction (I), the data lines 32 extend in a second direction (II) transverse to the first direction (I), and the connection lines 33 extend in the second direction (II) and are located between two outermost data lines 32. Generally, the scan lines 31, the data lines 32, and the connection lines 33 are metal lines, but the present invention is not limited in this regard. The scan lines 31 cooperate with the data lines 32 to define a plurality of pixel regions 34 in the following manner: in a plan view, two data lines 32 are interposed between any two pixel regions 34 adjacent to each other in the first direction (I) (i.e., there is no pixel region 34 between these two data lines 32), thereby forming a 1G2D structure. A gate driver IC (not shown) disposed on the upper side or the lower side of the display panel 30 supplies the same electrical signal to the pairs of scan lines 31. Each connection line 33 is electrically connected to one of the corresponding pairs of scan lines 31 (i.e., the corresponding pair of scan lines 31) among the plurality of pairs of scan lines 31 to connect the two corresponding scan lines 31 to the gate driver IC. In particular, each connection line 33 is electrically connected to the corresponding pair of scan lines 31 at two contact points 38. One of the two contact points 38 is a point where the connection line 33 intersects one of the two scan lines 31 in the corresponding pair of scan lines 31, and the other of the two contact points 38 is a point where the connection line 33 intersects the other of the two scan lines 31 in the corresponding pair of scan lines 31. Each contact point 38 may be implemented as a contact hole extending through an insulating layer between the scan line layer and the connection line layer. In this embodiment, for each connection line 33, the two scan lines 31 in the corresponding pair of scan lines are electrically connected to each other only via the two contact points 38 and the connection line 33, but the present invention is not limited in this regard. In another embodiment, the pairs of scan lines 31 may be electrically connected to each other via a metal line located outside the active area (also referred to as a display area) of the display panel 30, and only one contact point may be formed to interconnect the two scan lines 31 and the corresponding connection line 33.

[0022] In this embodiment, the connection line layer, the scanning line layer, and the data line layer are stacked in this order in a direction perpendicular to the screen surface of the display panel 30. Such a configuration can make the distance between the connection line 33 and the data line 32 relatively large to reduce the capacitance formed between the data line 32 and the connection line 33. However, the present invention is not limited in this regard. In another embodiment, the scanning line layer, the data line layer, and the connection line layer may be stacked in other desired orders. In addition, the color filter substrate includes a black matrix. In a plan view, the black matrix overlaps with the scanning line 31, the data line 32, the connection line 33, etc. The reference numeral 5 represents the edge of the black matrix in the plan view when the TFT substrate and the color filter substrate are joined.

[0023] Figure 4 A cross-sectional view showing a part of the pixel structure taken along line A1-A2 in Figure 3 is shown. In Figure 4 , the reference numerals 36 and 37 respectively represent the common electrode and the TFT substrate of the display panel 30, and a plurality of layers are located above the TFT substrate 37. The insulating layer 41 covers the connection line 33. The insulating layer 41 is provided between the connection line layer and the scanning line layer (see Figure 3 , not shown in Figure 4 ). The insulating layer 42 covers the scanning line 31. The insulating layer 42 is provided between the scanning line layer and the data line layer. The insulating layer 43 covers the data line 32. The insulating layer 43 is provided between the data line layer and the common electrode 36. The insulating layer 44 covers the common electrode 36. The insulating layer 44 is provided between the common electrode 36 and the pixel electrode 35.

[0024] In a plan view (viewed from the top of Figure 4 towards the bottom of Figure 4 ), each connection line 33 is disposed between the outer boundaries B A , B B of two adjacent data lines 32, thereby reducing the reduction in the pixel aperture ratio caused by the use of the connection line 33. In particular, in a plan view, each connection line 33 is disposed between the corresponding two data lines 32 and is spaced apart from the corresponding two data lines 32. In other words, in a plan view, the connection line 33 does not overlap with the corresponding two data lines 32. The advantage of this arrangement is that the signal delay on the data line 32 caused by the capacitance generated by the overlap between the data line 32 and the connection line 33 can be suppressed. In one implementation, in order to further reduce the influence of the use of the connection line 33 on the pixel aperture ratio, each connection line 33 may overlap with at least one of the corresponding two data lines 32 in a plan view, so that two adjacent data lines 32 are closer to each other.

[0025] Figure 5Another example is illustratively shown that adopts the first embodiment and an in-pixel multi-domain design, where the pixel electrode 35 of each pixel is configured not to extend along a straight line but to have multiple extension directions.

[0026] Figure 6 A plan view of a pixel structure of a second embodiment of a display panel 60 according to the present invention is shown. The second embodiment is different from the first embodiment in that the data lines 32 and the connection lines 33 are located on the same layer or formed on the same layer. In other words, in the second embodiment, the connection line layer and the data line layer are the same layer. Figure 7 A cross-sectional view of a part of the pixel structure taken along line B1 - B2 in Figure 6 is shown. Since each connection line 33 is disposed between two corresponding adjacent data lines 32 and spaced apart from the two corresponding adjacent data lines 32, the corresponding part of the black matrix for covering the opaque part of each pixel will be wider, which is beneficial for placing spacers between the TFT substrate and the color filter substrate of the display panel 60. The insulating layer 45 covers the data lines 32 and the connection lines 33. The insulating layer 45 is disposed between the layer of the data lines 32, the connection lines 33 and the common electrode 36.

[0027] Figure 8 A plan view of a pixel structure of a third embodiment of a display panel 80 according to the present invention is shown. In this embodiment, each connection line 33 extends through and partially overlaps the pixel region 34 of the pixels in the corresponding column. In such a configuration, the data lines 32 and the connection lines 33 can be located or formed on the same layer or different layers. In one implementation, the connection line layer is located under the scan line layer. Compared with the third embodiment, the advantage of the second embodiment is that when there is a deviation in the alignment between the TFT substrate and the color filter substrate, the resulting reduction in the aperture ratio will be smaller.

[0028] In the foregoing embodiments, the pixel regions 34 respectively corresponding to the sub-pixels are configured to have a major axis extending in the first direction (I), but the present invention is not limited thereto. The configurations respectively disclosed in the first to third embodiments are also applicable to the case where the major axis of the pixel region 34 extends in the second direction (II) as Figure 9 illustrated.

[0029] In summary, the embodiments of the present invention provide a display panel using a 1G2D structure, where the connection lines 33 extend in the same direction as the data lines 32 to connect the scan lines 31 to the gate driver IC in the second direction (II), so as to reduce the frame size of the display panel in the first direction (I). In some embodiments, the connection lines 33 overlap the data lines 32 in the plan view so as to minimize the impact of using the connection lines 33 on the aperture ratio.

[0030] In the foregoing description, for purposes of explanation, numerous specific details have been set forth in order to provide a thorough understanding of the embodiments. However, it will be apparent to one of ordinary skill in the art that one or more other embodiments may be practiced without some of these specific details. It should be understood that throughout the specification, references to "one embodiment", "an embodiment", embodiments with ordinal indication, etc. refer to specific features, structures, or characteristics that may be included in the practice of the present invention. It should be further understood that in the specification, for the sake of fluency of the disclosure of the present invention and to assist in understanding various aspects of the present invention, various features are sometimes combined in a single embodiment, drawing, or description thereof, and, where appropriate, in the practice of the present invention, one or more features or specific details of one embodiment may be practiced together with one or more features or specific details of another embodiment.

[0031] Although the present invention has been described in connection with what are considered to be exemplary embodiments, it is understood that the present invention is not limited to the disclosed embodiments, but is intended to cover various arrangements included within the spirit and scope of the broadest interpretation so as to encompass all such modifications and equivalent arrangements.

Claims

1. A display panel, characterized in that: The display panel includes: Multiple pairs of scan lines that extend in a first direction, wherein for each pair of scan lines, the scan lines are provided with the same electrical signal; Multiple data lines that extend in a second direction transverse to the first direction and, in cooperation with the scan lines, define multiple pixel regions in the following manner: In a plan view, two data lines are interposed between two of the pixel regions adjacent to each other in the first direction; and Multiple connection lines that extend in the second direction, wherein each of the connection lines is electrically connected to a corresponding pair of scan lines, wherein, in a plan view, one of the connection lines is disposed between the two data lines, one of the connection lines is electrically connected to the corresponding pair of scan lines at two contact points, a first contact point of the two contact points is located at a position where one of the connection lines intersects one of the two scan lines in the corresponding pair of scan lines, and a second contact point of the two contact points is located at a position where one of the connection lines intersects the other of the two scan lines in the corresponding pair of scan lines, and a first width of one of the two scan lines along the second direction at the first contact point is smaller than a second width of the other of the two scan lines along the second direction at the second contact point.

2. The display panel according to claim 1, wherein: In a plan view, one of the connection lines is disposed between the outer boundaries of the two data lines.

3. The display panel according to claim 1, wherein: The display panel includes multiple layers, wherein the data lines are located in a first layer of the multiple layers, and the connection lines are located in a second layer different from the first layer among the multiple layers.

4. The display panel according to claim 3, wherein: In a plan view, one of the connection lines at least partially overlaps at least one of the two data lines.

5. The display panel according to claim 3, wherein: In a plan view, one of the connection lines is disposed between the two data lines and is spaced apart from the two data lines.

6. The display panel according to claim 3, wherein: The multiple layers include a layer of the connection lines, a layer of the scan lines, and a layer of the data lines, and the layer of the connection lines, the layer of the scan lines, and the layer of the data lines are stacked in this order in a direction perpendicular to the screen surface of the display panel.

7. The display panel according to claim 2, characterized in that: The display panel further includes multiple layers, wherein the data lines and the connection lines are located in the same layer among the multiple layers; and wherein, in a plan view, one of the connection lines is disposed between the two data lines.

8. The display panel according to claim 1, wherein: The two scan lines in the corresponding pair of scan lines corresponding to one of the connection lines are electrically connected to each other only via the two contact points and one of the connection lines.

9. The display panel according to claim 1, wherein: The connection line is located between the two outermost data lines.

10. The display panel according to claim 1, wherein: The two data lines include a first data line and a second data line, the first data line has a first side and a second side opposite to the first side, and the first side and the second side extend along the second direction, The second data line has a third side and a fourth side opposite to the third side, the third side and the fourth side extend along the second direction, and the third side of the second data line faces the second side of the first data line. In a plan view, one of the connection lines is located between the first side of the first data line and the fourth side of the second data line.

11. The display panel according to claim 1, wherein: Further comprising: a first thin film transistor electrically connected to one of the two data lines and one of the connection lines, and a second thin film transistor electrically connected to the other of the two data lines and one of the connection lines, wherein the second contact point is disposed between the first thin film transistor and the second thin film transistor.

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