Band-gap reference circuit, temperature compensation method and integrated circuit

Abstract

The invention provides a band-gap reference circuit, a temperature compensation method and an integrated circuit, the circuit outputs a reference core current through a band-gap reference core unit in a working state, and a mirror image unit mirrors the reference core current and compensates a temperature coefficient in a mirror image current to obtain a band-gap reference current. Based on the band-gap reference current and the resistance value of the trimming resistor, band-gap reference voltage is output, the starting unit outputs starting voltage under the condition that the first power source supplies power, and the bias unit outputs bias voltage under the condition that the bias unit receives the starting voltage; the band-gap reference core unit is started through the bias voltage and the band-gap reference core unit is in a working state; the temperature drift influence of a high temperature coefficient in the mirror current on the band-gap reference voltage is reduced, the offset influence of a manufacturing process on the band-gap reference voltage is reduced, the output stability and precision of the band-gap reference voltage are improved, and the application universality of the band-gap reference circuit in a high-precision system is improved.

Description

Technical Field

[0001] This application relates to the field of microelectronics technology, and particularly to a bandgap reference circuit, a temperature compensation method, and an integrated circuit. Background Art

[0002] The bandgap reference circuit is an important module in modern analog integrated circuits and mixed-signal integrated circuits. Its performance characteristics directly affect the performance of the entire circuit, which requires that the bandgap voltage output by the bandgap reference circuit be sufficiently stable and have strong anti-interference ability.

[0003] Figure 1 For the bandgap reference circuit structure that outputs the bandgap reference voltage through the bandgap reference core unit in the related art, in Figure 1 the current of the two right branches is n times that of the two left branches. The resistors R1 and R2 are made of the same material. The ratio of the emitter areas of the bipolar transistor Q2 and the bipolar transistor Q3 (or the bipolar transistor Q1 and the bipolar transistor Q4) is m:1. Ignoring the influence of the current gain β of the bipolar transistor, the difference between the junction voltages of the bipolar transistor Q2 and the bipolar transistor Q3 can be expressed as:

[0004]

[0005] Where, ΔV BE represents the difference between the junction voltages of the bipolar transistor Q2 and the bipolar transistor Q3, V BEQ3 represents the junction voltage of the bipolar transistor Q3, V BEQ4 represents the junction voltage of the bipolar transistor Q4, V BEQ1 represents the junction voltage of the bipolar transistor Q1, V BEQ2 represents the junction voltage of the bipolar transistor Q2, V T represents the cut-off voltage of the bipolar transistor, I0 represents the collector current, I s represents the saturation current, k represents the Boltzmann constant, T represents the temperature coefficient, m represents the ratio of the emitter area of the bipolar transistor Q2 to the emitter area of the bipolar transistor Q3, or the ratio of the emitter area of the bipolar transistor Q1 to the emitter area of the bipolar transistor Q4, n represents the multiple relationship between the current of the two right branches and the current of the two left branches, and q represents the electric charge of an electron.

[0006] In Figure 1 the gate voltage of the PMOS transistor (Positive Channel Metal Oxide Semiconductor) is adjusted through an operational amplifier to ensure that the input node V X and the output node V YThe voltages are equal. At this time, the current flowing through resistor R1 can be expressed as:

[0007]

[0008] Among them, I PTAT represents the current flowing through resistor R1, k represents the Boltzmann constant, T represents the temperature coefficient, m represents the ratio of the emitter area of bipolar transistor Q2 to the emitter area of bipolar transistor Q3, or the ratio of the emitter area of bipolar transistor Q1 to the emitter area of bipolar transistor Q4, n represents the multiple relationship between the currents of the two right branches and the two left branches, q represents the charge of an electron, and the resistance value of resistor R1 is R1.

[0009] In Figure 1 , the output bandgap reference voltage can be expressed as:

[0010]

[0011] Among them, V BG represents the bandgap reference voltage, V BEQ1 represents the junction voltage of bipolar transistor Q1, V BEQ2 represents the junction voltage of bipolar transistor Q2, I PTAT represents the current flowing through resistor R1, the resistance value of resistor R1 is R1, the resistance value of resistor R2 is R2, V BEQ1,2 represents the junction voltage of bipolar transistor Q1 or the junction voltage of bipolar transistor Q2, ΔV BE represents the difference between the junction voltage of bipolar transistor Q2 and the junction voltage of bipolar transistor Q3.

[0012] Figure 1 The baseband reference voltage output through the bandgap reference core unit in includes a negative temperature coefficient voltage and a positive temperature coefficient voltage. The negative temperature coefficient voltage is generated by the base-emitter voltage (junction voltage) of the bipolar transistor (i.e., the junction voltage V BE ), and the positive temperature coefficient voltage is generated by two bipolar transistors operating at different current densities (the difference ΔV BE of the junction voltages V BE of the two bipolar transistors). Since the junction voltage V BE of the bipolar transistor does not change linearly with temperature, there are first-order temperature-related terms and higher-order temperature-related terms in V BE . Figure 1 The baseband reference voltage output through the bandgap reference core unit in is related to V BEThe related first-order temperature correlation term and high-order temperature correlation term are doubled. Therefore, the output voltage of the first-order bandgap reference circuit in the related art has the disadvantage of a high temperature coefficient, which causes problems such as the shift of the bandgap reference voltage, and easily leads to poor stability and accuracy of the bandgap reference voltage, making the application of the first-order bandgap reference circuit in the related art in high-precision systems greatly limited. Summary of the Invention

[0013] In view of the above-mentioned disadvantages of the prior art, the present application provides a bandgap reference circuit, a temperature compensation method and an integrated circuit to solve the above technical problems.

[0014] According to one aspect of the embodiments of the present application, a bandgap reference circuit is provided, including: a bandgap reference core unit for outputting a reference core current in a working state; a mirror unit for mirroring the reference core current and compensating the temperature coefficient in the mirrored current to obtain a bandgap reference current, and outputting a bandgap reference voltage based on the bandgap reference current and the resistance value of a trimming resistor.

[0015] In an embodiment of the present application, the bandgap reference circuit further includes: a startup unit for outputting a startup voltage when powered by a first power supply; a bias unit for outputting a bias voltage when receiving the startup voltage to start the bandgap reference core unit through the bias voltage and make the bandgap reference core unit in the working state.

[0016] In an embodiment of the present application, the bandgap reference core unit includes: a first switching transistor, the source of the first switching transistor is connected to a second power supply, the gate of the first switching transistor is connected to the output terminal of a first operational amplifier, and the drain of the first switching transistor is respectively connected to the sources of a first voltage regulator sub-unit, a second voltage regulator sub-unit, a third voltage regulator sub-unit, and a fourth voltage regulator sub-unit; the first switching transistor is configured to conduct and supply a second power supply voltage to the first voltage regulator sub-unit, the second voltage regulator sub-unit, the third voltage regulator sub-unit, and the fourth voltage regulator sub-unit respectively when powered by the second power supply; the first voltage regulator sub-unit, the second voltage regulator sub-unit, the third voltage regulator sub-unit, and the fourth voltage regulator sub-unit are all cascode structures formed by multiple switching transistors; the gate of the first voltage regulator sub-unit is connected to the bias unit, the gate of the second voltage regulator sub-unit is connected to the gate of the first voltage regulator sub-unit, the gate of the third voltage regulator sub-unit is connected to the gate of the second voltage regulator sub-unit, and the gate of the fourth voltage regulator sub-unit is connected to the gate of the third voltage regulator sub-unit; the first voltage regulator sub-unit, the second voltage regulator sub-unit, the third voltage regulator sub-unit, and the fourth voltage regulator sub-unit are all configured to output a drain voltage under the action of the second power supply voltage and the bias voltage; the fluctuation range of the drain voltage is less than a preset range threshold; the drain of the first voltage regulator sub-unit is connected to the emitter of a first triode, and both the base and the collector of the first triode are grounded; the first triode is configured to conduct under the action of the drain voltage; the drain of the second voltage regulator sub-unit is connected to one end of a first adjustable resistor, the other end of the first adjustable resistor is connected to the positive input terminal of the first operational amplifier, the other end of the first adjustable resistor is connected to one end of a first fixed resistor, the other end of the first fixed resistor is connected to the emitter of a second triode, the collector of the second triode is grounded, and the base of the second triode is connected to the emitter of the first triode; the second triode is configured to conduct under the action of the drain voltage, and the first operational amplifier is configured to obtain a positive input voltage when the second triode conducts; the drain of the third voltage regulator sub-unit is connected to the negative input terminal of the first operational amplifier, the drain of the third voltage regulator sub-unit is connected to the emitter of a third triode, and the collector of the third triode is grounded; the third triode is configured to conduct under the action of the drain voltage, and the first operational amplifier is configured to obtain a negative input voltage when the third triode conducts; the drain of the fourth voltage regulator sub-unit is connected to the base of the third triode, the drain of the fourth voltage regulator sub-unit is connected to the emitter of a fourth triode, and both the base and the collector of the fourth triode are grounded; the fourth triode is configured to conduct under the action of the drain voltage;The current output module is used to output the current of the first fixed-value resistor as the reference core current when the first triode, the second triode, the third triode, and the fourth triode are all turned on.

[0017] In an embodiment of the present application, the mirror unit includes: a fifth voltage stabilizing sub-unit, the source of the fifth voltage stabilizing sub-unit is connected to the drain of the first switching transistor, the gate of the fifth voltage stabilizing sub-unit is connected to the gate of the fourth voltage stabilizing sub-unit, the drain of the fifth voltage stabilizing sub-unit is connected to the positive input terminal of the second operational amplifier, the drain of the fifth voltage stabilizing sub-unit is connected to one end of a second fixed-value resistor, the drain of the fifth voltage stabilizing sub-unit is connected to one end of a third fixed-value resistor, the other end of the third fixed-value resistor is connected to one end of a fourth fixed-value resistor, and the other end of the fourth fixed-value resistor is used for grounding; the fifth voltage stabilizing sub-unit is used to output the drain voltage under the action of the second power supply voltage and the bias voltage; the fifth voltage stabilizing sub-unit is a cascode structure composed of multiple switching transistors; the number of switching transistors in the fifth voltage stabilizing sub-unit is the same as the number of switching transistors in the fourth voltage stabilizing sub-unit; a sixth voltage stabilizing sub-unit, the source of the sixth voltage stabilizing sub-unit is connected to the drain of the first switching transistor, the gate of the sixth voltage stabilizing sub-unit is connected to the gate of the fifth voltage stabilizing sub-unit, the drain of the sixth voltage stabilizing sub-unit is connected to the other end of the second fixed-value resistor, the drain of the sixth voltage stabilizing sub-unit is connected to the emitter of a fifth triode, the base of the fifth triode is connected to the output terminal of the second operational amplifier, the base of the fifth triode is connected to the negative input terminal of the second operational amplifier, and the collector of the fifth triode is used for grounding; the sixth voltage stabilizing sub-unit is used to output the drain voltage under the action of the second power supply voltage and the bias voltage; the fifth triode is turned on under the action of the drain voltage; the sixth voltage stabilizing sub-unit is a cascode structure composed of multiple switching transistors; the number of switching transistors in the sixth voltage stabilizing sub-unit is the same as the number of switching transistors in the fifth voltage stabilizing sub-unit; a voltage output module, which is used to output the voltage difference across the fourth fixed-value resistor as the bandgap reference voltage when the fifth triode is turned on; the process of determining the voltage difference across the fourth fixed-value resistor includes: compensating the temperature coefficient of the mirror current through the current of the second fixed-value resistor to obtain the bandgap reference current, and using the second fixed-value resistor and the fourth fixed-value resistor as the trimming resistors, and calculating the voltage difference across the fourth fixed-value resistor based on the bandgap reference current and the trimming resistors.

[0018] In an embodiment of the present application, the bias unit includes: a seventh voltage regulator subunit, the source of the seventh voltage regulator subunit is connected to the drain of the first switching transistor, the gate of the seventh voltage regulator subunit is connected to the startup unit, the gate of the seventh voltage regulator subunit is connected to the gate of the first voltage regulator subunit, the drain of the seventh voltage regulator subunit is connected to the startup unit, the drain of the seventh voltage regulator subunit is connected to the drain of the second switching transistor, the gate of the second switching transistor is connected to the startup unit, the source of the second switching transistor is grounded, and the gate of the second switching transistor is connected to the drain of the second switching transistor; the seventh voltage regulator subunit is a cascode structure composed of multiple switching transistors; the number of stages of the switching transistors in the seventh voltage regulator subunit is the same as that of the switching transistors in the first voltage regulator subunit; the seventh voltage regulator subunit is used to provide the bias voltage for the first voltage regulator subunit, the second voltage regulator subunit, the third voltage regulator subunit, and the fourth voltage regulator subunit under the action of the second power supply voltage and the startup voltage.

[0019] In an embodiment of the present application, the seventh voltage regulator subunit includes: a third switching transistor and a fourth switching transistor, the source of the third switching transistor is connected to the drain of the first switching transistor, the gate of the third switching transistor is connected to the gate of the first-stage switching transistor in the first voltage regulator subunit, the drain of the third switching transistor is connected to the source of the fourth switching transistor, the gate of the fourth switching transistor is connected to the gate of the second-stage switching transistor in the first voltage regulator subunit, the gate of the fourth switching transistor is connected to the startup unit, the drain of the fourth switching transistor is connected to the startup unit, and the drain of the fourth switching transistor is connected to the drain of the second switching transistor.

[0020] In an embodiment of the present application, the starting unit includes: a fifth switching tube, the source of the fifth switching tube is connected to the first power supply, the gate and the drain of the fifth switching tube are connected, the drain of the fifth switching tube is connected to the source of a sixth switching tube, the gate and the drain of the sixth switching tube are connected, the drain of the sixth switching tube is connected to the drain of a seventh switching tube, the drain and the gate of the seventh switching tube are connected, the drain of the seventh switching tube is connected to the drain of an eighth switching tube, the gate of the eighth switching tube is connected to the drain of the fourth switching tube, and the sources of the seventh switching tube and the eighth switching tube are grounded; the gate of the seventh switching tube is connected to the gate of a ninth switching tube, the source of the ninth switching tube is grounded, the drain of the ninth switching tube is connected to the drain of a tenth switching tube, the source of the tenth switching tube is grounded, the gate of the tenth switching tube is connected to the gate of the second switching tube, the drain of the tenth switching tube is connected to the drain of an eleventh switching tube, the source of the eleventh switching tube is connected to the drain of the first switching tube, the gate and the drain of the eleventh switching tube are connected, and the gate of the eleventh switching tube is connected to the gate of the fourth switching tube; the eleventh switching tube is configured to conduct and provide the starting voltage for the fourth switching tube when the fifth switching tube, the sixth switching tube, the seventh switching tube and the ninth switching tube are all conducting, or the eleventh switching tube is configured to conduct and provide the starting voltage for the fourth switching tube when the fifth switching tube, the sixth switching tube, the eighth switching tube and the tenth switching tube are all conducting.

[0021] According to one aspect of the embodiments of the present application, a temperature compensation method for a bandgap reference circuit is provided. The method includes: outputting a reference core current when the bandgap reference core unit is in a working state; mirroring the reference core current and compensating the temperature coefficient in the mirrored current to obtain a bandgap reference current, and outputting a bandgap reference voltage based on the bandgap reference current and the resistance value of a trimming resistor.

[0022] In an embodiment of the present application, the calculation formula for the bandgap reference current includes: I BG =I PTAT +I3, where I BG represents the bandgap reference current, I PTAT represents the reference core current, and I3 represents the current of a second fixed-value resistor; the calculation formula for the bandgap reference voltage includes: where V BG represents the bandgap reference voltage, R5 represents the resistance value of a fourth fixed-value resistor, I BG represents the bandgap reference current, I PTATrepresents the reference core current, I3 represents the current of the second fixed resistor, V BEQ5 represents the junction voltage of the fifth triode, R3 represents the resistance value of the second fixed resistor, V BEQ2,3 represents the junction voltage of the second triode or the third triode, and R1 represents the resistance value of the first fixed resistor.

[0023] According to one aspect of the embodiments of the present application, an integrated circuit is provided, and the integrated circuit includes the bandgap reference circuit described above.

[0024] Advantages of the present application: In the working state of the bandgap reference core unit in the present application, the reference core current is output, and the reference core current is mirrored by the mirror unit, and the temperature coefficient in the mirrored current is compensated to obtain the bandgap reference current. Based on the bandgap reference current and the resistance value of the trimming resistor, the bandgap reference voltage is output. By compensating the temperature coefficient in the mirrored current to obtain the bandgap reference current, the temperature drift effect caused by the high temperature coefficient in the mirrored current on the bandgap reference voltage is reduced, and based on the bandgap reference current and the resistance value of the trimming resistor, the bandgap reference voltage is output. By trimming the bandgap reference voltage with the trimming resistor, the offset effect caused by the manufacturing process on the bandgap reference voltage is reduced, thereby improving the stability and accuracy of the output of the bandgap reference voltage, and improving the wide application of the bandgap reference circuit in high-precision systems.

[0025] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts. In the drawings:

[0027] Figure 1 is a schematic structural diagram of a bandgap reference circuit structure in the related art;

[0028] Figure 2 is a block diagram of a bandgap reference circuit shown in an exemplary embodiment of the present application;

[0029] Figure 3 is a schematic structural diagram of a bandgap reference circuit shown in an exemplary embodiment of the present application;

[0030] Figure 4 is a schematic diagram of the simulation result of the power supply rejection ratio of a bandgap reference circuit shown in an exemplary embodiment of the present application;

[0031] Figure 5 It is a schematic diagram of the simulation result of the relationship between the bandgap reference voltage output by the bandgap reference circuit shown in an exemplary embodiment of the present application and temperature;

[0032] Figure 6 It is a flowchart of the temperature compensation method of the bandgap reference circuit shown in an exemplary embodiment of the present application;

[0033] Figure 7 It shows a schematic structural diagram of an integrated circuit system suitable for implementing the embodiments of the present application. Detailed implementation manners

[0034] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0035] The block diagrams shown in the drawings are only functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0036] The flowcharts shown in the drawings are only exemplary descriptions and do not necessarily include all contents and operations / steps, nor do they necessarily need to be executed in the described order. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined. Therefore, the actual execution order may change according to the actual situation.

[0037] In the present application, "a plurality of" means two or more. "And / or" describes the association relationship of associated objects and indicates that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after.

[0038] The technical solutions of the embodiments of the present application relate to related technologies such as microelectronics, and are specifically described through the following embodiments:

[0039] Figure 2 It is a block diagram of the bandgap reference circuit shown in an exemplary embodiment of the present application. As Figure 2 shown, the exemplary bandgap reference circuit 200 includes:

[0040] The bandgap reference core unit 201 is used to output a reference core current in the working state.

[0041] The mirror unit 202 is used to mirror the reference core current, compensate the temperature coefficient in the mirrored current to obtain a bandgap reference current, and output a bandgap reference voltage based on the bandgap reference current and the resistance value of the trimming resistor.

[0042] In an embodiment of the present application, the bandgap reference core unit outputs a reference core current in the working state, mirrors the reference core current through the mirror unit, compensates the temperature coefficient in the mirrored current to obtain a bandgap reference current, outputs a bandgap reference voltage based on the bandgap reference current and the resistance value of the trimming resistor. By compensating the temperature coefficient in the mirrored current to obtain a bandgap reference current, the temperature drift effect caused by the high temperature coefficient in the mirrored current on the bandgap reference voltage is reduced, and a bandgap reference voltage is output based on the bandgap reference current and the resistance value of the trimming resistor. By trimming the bandgap reference voltage through the trimming resistor, the offset effect caused by the manufacturing process on the bandgap reference voltage is reduced, thereby improving the stability and accuracy of the bandgap reference voltage output, and improving the wide application of the bandgap reference circuit in high-precision systems.

[0043] In an embodiment of the present application, the bandgap reference circuit further includes:

[0044] A startup unit, which is used to output a startup voltage when powered by a first power supply.

[0045] A bias unit, which is used to output a bias voltage when receiving the startup voltage, so as to start the bandgap reference core unit through the bias voltage and make the bandgap reference core unit in the working state.

[0046] In an embodiment of the present application, the startup unit outputs a startup voltage when powered by a first power supply, and the bias unit outputs a bias voltage when receiving the startup voltage, so as to start the bandgap reference core unit through the bias voltage, avoiding the situation that the voltage of the positive input terminal and the voltage of the negative input terminal of the first operational amplifier in the bandgap reference core unit are both zero, which may cause the input differential pair of the first operational amplifier to turn off, thereby ensuring that the first operational amplifier can work normally when powered on.

[0047] In an embodiment of the present application, the bandgap reference core unit includes:

[0048] The first switching transistor, the source of the first switching transistor is connected to the second power supply, the gate of the first switching transistor is connected to the output terminal of the first operational amplifier, and the drain of the first switching transistor is respectively connected to the sources of the first voltage stabilizing sub-unit, the second voltage stabilizing sub-unit, the third voltage stabilizing sub-unit and the fourth voltage stabilizing sub-unit; the first switching transistor is used to conduct and supply the second power supply voltage to the first voltage stabilizing sub-unit, the second voltage stabilizing sub-unit, the third voltage stabilizing sub-unit and the fourth voltage stabilizing sub-unit respectively under the power supply of the second power supply; the first voltage stabilizing sub-unit, the second voltage stabilizing sub-unit, the third voltage stabilizing sub-unit and the fourth voltage stabilizing sub-unit are all cascode structures composed of multiple switching transistors;

[0049] The gate of the first voltage stabilizing sub-unit is connected to the bias unit, the gate of the second voltage stabilizing sub-unit is connected to the gate of the first voltage stabilizing sub-unit, the gate of the third voltage stabilizing sub-unit is connected to the gate of the second voltage stabilizing sub-unit, and the gate of the fourth voltage stabilizing sub-unit is connected to the gate of the third voltage stabilizing sub-unit; the first voltage stabilizing sub-unit, the second voltage stabilizing sub-unit, the third voltage stabilizing sub-unit and the fourth voltage stabilizing sub-unit are all used to output the drain voltage under the action of the second power supply voltage and the bias voltage; the fluctuation range of the drain voltage is less than the preset range threshold;

[0050] The drain of the first voltage stabilizing sub-unit is connected to the emitter of the first triode, and both the base and the collector of the first triode are used for grounding; the first triode is used to conduct under the action of the drain voltage;

[0051] The drain of the second voltage stabilizing sub-unit is connected to one end of the first adjustable resistor, the other end of the first adjustable resistor is connected to the positive input terminal of the first operational amplifier, the other end of the first adjustable resistor is connected to one end of the first fixed resistor, the other end of the first fixed resistor is connected to the emitter of the second triode, the collector of the second triode is used for grounding, and the base of the second triode is connected to the emitter of the first triode; the second triode is used to conduct under the action of the drain voltage, and the first operational amplifier is used to obtain the positive input voltage when the second triode conducts;

[0052] The drain of the third voltage stabilizing sub-unit is connected to the negative input terminal of the first operational amplifier, the drain of the third voltage stabilizing sub-unit is connected to the emitter of the third triode, and the collector of the third triode is used for grounding; the third triode is used to conduct under the action of the drain voltage, and the first operational amplifier is used to obtain the negative input voltage when the third triode conducts;

[0053] The drain of the fourth voltage stabilizing sub-unit is connected to the base of the third triode, the drain of the fourth voltage stabilizing sub-unit is connected to the emitter of the fourth triode, and both the base and the collector of the fourth triode are used for grounding; the fourth triode is used to conduct under the action of the drain voltage;

[0054] The current output module is used to output the current of the first fixed-value resistor as the reference core current when the first triode, the second triode, the third triode, and the fourth triode are all turned on.

[0055] In an embodiment of the present application, the fluctuation range of the drain voltage is less than the preset range threshold, and the preset range threshold is set according to the actual situation. The first voltage stabilizing sub-unit, the second voltage stabilizing sub-unit, the third voltage stabilizing sub-unit, and the fourth voltage stabilizing sub-unit are all cascode structures composed of multiple switching transistors, and the number of stages of the switching transistors in the first voltage stabilizing sub-unit, the second voltage stabilizing sub-unit, the third voltage stabilizing sub-unit, and the fourth voltage stabilizing sub-unit is the same. Taking the cascode structures composed of two-stage switching transistors in the first voltage stabilizing sub-unit, the second voltage stabilizing sub-unit, the third voltage stabilizing sub-unit, and the fourth voltage stabilizing sub-unit as an example, the first voltage stabilizing sub-unit includes the twelfth switching transistor and the thirteenth switching transistor, the second voltage stabilizing sub-unit includes the fourteenth switching transistor and the fifteenth switching transistor, the third voltage stabilizing sub-unit includes the sixteenth switching transistor and the seventeenth switching transistor, and the fourth voltage stabilizing sub-unit includes the eighteenth switching transistor and the nineteenth switching transistor. Among them, the drain of the first switching transistor is connected to the source of the twelfth switching transistor, the gate of the twelfth switching transistor is connected to the gate of the third switching transistor, the drain of the twelfth switching transistor is connected to the source of the thirteenth switching transistor, the gate of the thirteenth switching transistor is connected to the gate of the fourth switching transistor, the drain of the thirteenth switching transistor is connected to the emitter of the first triode, and the drain of the thirteenth switching transistor is connected to the base of the second triode; the drain of the first switching transistor is connected to the source of the fourteenth switching transistor, the gate of the fourteenth switching transistor is connected to the gate of the twelfth switching transistor, the drain of the fourteenth switching transistor is connected to the source of the fifteenth switching transistor, the gate of the fifteenth switching transistor is connected to the gate of the thirteenth switching transistor, and the drain of the fifteenth switching transistor is connected to one end of the first adjustable resistor; the drain of the first switching transistor is connected to the source of the sixteenth switching transistor, the gate of the sixteenth switching transistor is connected to the gate of the fourteenth switching transistor, the drain of the sixteenth switching transistor is connected to the source of the seventeenth switching transistor, the gate of the seventeenth switching transistor is connected to the gate of the fifteenth switching transistor, the drain of the seventeenth switching transistor is connected to the emitter of the third triode, and the drain of the seventeenth switching transistor is connected to the inverting input terminal of the first operational amplifier; the drain of the first switching transistor is connected to the source of the eighteenth switching transistor, the gate of the eighteenth switching transistor is connected to the gate of the sixteenth switching transistor, the drain of the eighteenth switching transistor is connected to the source of the nineteenth switching transistor, the gate of the nineteenth switching transistor is connected to the gate of the seventeenth switching transistor, the drain of the nineteenth switching transistor is connected to the base of the third triode, and the drain of the nineteenth switching transistor is connected to the emitter of the fourth triode.

[0056] In some embodiments of the present application, the first switching transistor is a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), simply referred to as a MOS transistor. The twelfth, thirteenth, fourteenth, fifteenth, sixteenth, seventeenth, eighteenth, and nineteenth switching transistors are all MOS transistors. The first voltage stabilizing sub-unit, the second voltage stabilizing sub-unit, the third voltage stabilizing sub-unit, and the fourth voltage stabilizing sub-unit all form a cascode structure through two MOS transistors, which has the functions of stabilizing and maintaining the output voltage and improving the anti-interference ability of the bandgap reference circuit (for example, the power supply rejection ratio of the bandgap reference core unit).

[0057] In some embodiments of the present application, the first triode, the second triode, the third triode, and the fourth triode adopt a collector-grounded structure, which greatly reduces the influence of the offset voltage of the first operational method amplifier, thereby reducing the temperature coefficient of the bandgap reference voltage.

[0058] In an embodiment of the present application, the mirror unit includes:

[0059] A fifth voltage stabilizing sub-unit, the source of the fifth voltage stabilizing sub-unit is connected to the drain of the first switching transistor, the gate of the fifth voltage stabilizing sub-unit is connected to the gate of the fourth voltage stabilizing sub-unit, the drain of the fifth voltage stabilizing sub-unit is connected to the positive input terminal of the second operational amplifier, the drain of the fifth voltage stabilizing sub-unit is connected to one end of the second fixed resistor, the drain of the fifth voltage stabilizing sub-unit is connected to one end of the third fixed resistor, the other end of the third fixed resistor is connected to one end of the fourth fixed resistor, and the other end of the fourth fixed resistor is used for grounding; the fifth voltage stabilizing sub-unit is used to output a drain voltage under the action of the second power supply voltage and the bias voltage;

[0060] A sixth voltage stabilizing sub-unit, the source of the sixth voltage stabilizing sub-unit is connected to the drain of the first switching transistor, the gate of the sixth voltage stabilizing sub-unit is connected to the gate of the fifth voltage stabilizing sub-unit, the drain of the sixth voltage stabilizing sub-unit is connected to the other end of the second fixed resistor, the drain of the sixth voltage stabilizing sub-unit is connected to the emitter of the fifth triode, the base of the fifth triode is connected to the output terminal of the second operational amplifier, the base of the fifth triode is connected to the negative input terminal of the second operational amplifier, and the collector of the fifth triode is used for grounding; the sixth voltage stabilizing sub-unit is used to output a drain voltage under the action of the second power supply voltage and the bias voltage; the fifth triode conducts under the action of the drain voltage; the sixth voltage stabilizing sub-unit is a cascode structure composed of multiple switching transistors;

[0061] A voltage output module is configured to output the voltage difference across the fourth fixed resistor as a bandgap reference voltage when the fifth triode is turned on. The process of determining the voltage difference across the fourth fixed resistor includes: compensating the temperature coefficient of the mirror current with the current passing through the second fixed resistor to obtain a bandgap reference current, and using the second fixed resistor and the fourth fixed resistor as trimming resistors to calculate the voltage difference across the fourth fixed resistor based on the bandgap reference current and the trimming resistors.

[0062] In an embodiment of the present application, the fifth voltage stabilizing sub-unit is a cascode structure composed of multiple switching transistors; the number of switching transistors in the fifth voltage stabilizing sub-unit is the same as that in the fourth voltage stabilizing sub-unit, and the number of switching transistors in the sixth voltage stabilizing sub-unit is the same as that in the fifth voltage stabilizing sub-unit. Taking the cascode structures of the fifth voltage stabilizing sub-unit and the sixth voltage stabilizing sub-unit both composed of two switching transistors as an example, the fifth voltage stabilizing sub-unit includes a twentieth switching transistor and a twenty-first switching transistor, and the sixth voltage stabilizing sub-unit includes a twenty-second switching transistor and a twenty-third switching transistor. The source of the twentieth switching transistor is connected to the drain of the first switching transistor, the gate of the twentieth switching transistor is connected to the gate of the eighteenth switching transistor, the drain of the twentieth switching transistor is connected to the source of the twenty-first switching transistor, the gate of the twenty-first switching transistor is connected to the gate of the nineteenth switching transistor, the drain of the twenty-first switching transistor is connected to one end of the second fixed resistor, the drain of the twenty-first switching transistor is connected to the positive input terminal of the second operational amplifier, and the drain of the twenty-first switching transistor is connected to one end of the third fixed resistor; the source of the twenty-second switching transistor is connected to the drain of the first switching transistor, the gate of the twenty-second switching transistor is connected to the gate of the twentieth switching transistor, the drain of the twenty-second switching transistor is connected to the source of the twenty-third switching transistor, the gate of the twenty-third switching transistor is connected to the gate of the twenty-first switching transistor, the drain of the twenty-third switching transistor is connected to the other end of the second fixed resistor, and the drain of the twenty-third switching transistor is connected to the emitter of the fifth triode.

[0063] In some embodiments of the present application, the twentieth switching transistor, the twenty-first switching transistor, the twenty-second switching transistor, and the twenty-third switching transistor are all MOS transistors. The fifth voltage stabilizing sub-unit and the sixth voltage stabilizing sub-unit both form a cascode structure through two MOS transistors, which has the functions of stabilizing and maintaining the output voltage and improving the anti-interference ability of the bandgap reference circuit (for example, the power supply rejection ratio of the bandgap reference core unit).

[0064] In some embodiments of the present application, since the reference core current has a positive temperature coefficient and the current of the second fixed resistor is generated by the fifth triode and has a negative temperature coefficient, the process of compensating the temperature coefficient of the reference core current by the current passing through the second fixed resistor is the process of taking the sum of the current of the second fixed resistor and the reference core current as the bandgap reference current, which reduces the temperature drift effect on the bandgap reference voltage caused by the high temperature coefficient in the mirror current. During design, by changing the resistance value of the trimming resistor, the magnitude and slope of the current of the second fixed resistor are changed, thereby realizing the trimming of the higher-order temperature coefficient term in the bandgap reference voltage and reducing the offset effect on the bandgap reference voltage caused by the manufacturing process, thus improving the stability and accuracy of the bandgap reference voltage output and enhancing the wide application of the bandgap reference circuit in high-precision systems.

[0065] In one embodiment of the present application, the bias unit includes:

[0066] A seventh voltage stabilizing sub-unit, the source of the seventh voltage stabilizing sub-unit is connected to the drain of the first switching transistor, the gate of the seventh voltage stabilizing sub-unit is connected to the startup unit, the gate of the seventh voltage stabilizing sub-unit is connected to the gate of the first voltage stabilizing sub-unit, the drain of the seventh voltage stabilizing sub-unit is connected to the startup unit, the drain of the seventh voltage stabilizing sub-unit is connected to the drain of the second switching transistor, the gate of the second switching transistor is connected to the startup unit, the source of the second switching transistor is used for grounding, and the gate of the second switching transistor is connected to the drain of the second switching transistor;

[0067] The seventh voltage stabilizing sub-unit is configured to provide a bias voltage for the first voltage stabilizing sub-unit, the second voltage stabilizing sub-unit, the third voltage stabilizing sub-unit, and the fourth voltage stabilizing sub-unit under the action of the second power supply voltage and the startup voltage.

[0068] In one embodiment of the present application, the seventh voltage stabilizing sub-unit is a cascode structure composed of multiple switching transistors; the number of stages of the switching transistors in the seventh voltage stabilizing sub-unit is the same as that of the switching transistors in the first voltage stabilizing sub-unit. The seventh voltage stabilizing sub-unit includes a third switching transistor and a fourth switching transistor. The source of the third switching transistor is connected to the drain of the first switching transistor, the gate of the third switching transistor is connected to the gate of the twelfth switching transistor, the drain of the third switching transistor is connected to the source of the fourth switching transistor, the gate of the fourth switching transistor is connected to the gate of the thirteenth switching transistor, the gate of the fourth switching transistor is connected to the startup unit, the drain of the fourth switching transistor is connected to the startup unit, and the drain of the fourth switching transistor is connected to the drain of the second switching transistor.

[0069] In some embodiments of the present application, both the third switching transistor and the fourth switching transistor are MOS transistors. The seventh voltage stabilizing sub-unit forms a cascode structure through two MOS transistors, which has the function of stabilizing and maintaining the output voltage, and provides a stable bias voltage for the first voltage stabilizing sub-unit, the second voltage stabilizing sub-unit, the third voltage stabilizing sub-unit, the fourth voltage stabilizing sub-unit, the fifth voltage stabilizing sub-unit, and the sixth voltage stabilizing sub-unit under the action of the startup voltage and the output voltage of the second power supply.

[0070] In one embodiment of the present application, the seventh voltage stabilizing sub-unit includes:

[0071] The third switching transistor and the fourth switching transistor. The source of the third switching transistor is connected to the drain of the first switching transistor. The gate of the third switching transistor is connected to the gate of the first-stage switching transistor in the first voltage stabilizing sub-unit. The drain of the third switching transistor is connected to the source of the fourth switching transistor. The gate of the fourth switching transistor is connected to the gate of the second-stage switching transistor in the first voltage stabilizing sub-unit. The gate of the fourth switching transistor is connected to the startup unit. The drain of the fourth switching transistor is connected to the startup unit. The drain of the fourth switching transistor is connected to the drain of the second switching transistor.

[0072] In one embodiment of the present application, both the third switching transistor and the fourth switching transistor are MOS transistors. A stable voltage is provided for the gate of the twelfth switching transistor through the gate of the third switching transistor, and a stable voltage is provided for the gate of the thirteenth switching transistor through the gate of the fourth switching transistor, so as to stabilize the operating states of the twelfth switching transistor and the thirteenth switching transistor.

[0073] In one embodiment of the present application, the startup unit includes:

[0074] The fifth switching transistor. The source of the fifth switching transistor is connected to the first power supply. The gate and the drain of the fifth switching transistor are connected. The drain of the fifth switching transistor is connected to the source of the sixth switching transistor. The gate and the drain of the sixth switching transistor are connected. The drain of the sixth switching transistor is connected to the drain of the seventh switching transistor. The drain of the seventh switching transistor is connected to its own gate. The drain of the seventh switching transistor is connected to the drain of the eighth switching transistor. The gate of the eighth switching transistor is connected to the drain of the fourth switching transistor. The sources of the seventh switching transistor and the eighth switching transistor are grounded; the gate of the seventh switching transistor is connected to the gate of the ninth switching transistor. The source of the ninth switching transistor is grounded. The drain of the ninth switching transistor is connected to the drain of the tenth switching transistor. The source of the tenth switching transistor is grounded. The gate of the tenth switching transistor is connected to the gate of the second switching transistor. The drain of the tenth switching transistor is connected to the drain of the eleventh switching transistor. The source of the eleventh switching transistor is connected to the drain of the first switching transistor. The gate and the drain of the eleventh switching transistor are connected. The gate of the eleventh switching transistor is connected to the gate of the fourth switching transistor;

[0075] The eleventh switching transistor is configured to conduct when the fifth, sixth, seventh, and ninth switching transistors are all conducting, and provide a startup voltage for the fourth switching transistor. Alternatively, the eleventh switching transistor is configured to conduct when the fifth, sixth, eighth, and tenth switching transistors are all conducting, and provide a startup voltage for the fourth switching transistor.

[0076] In an embodiment of the present application, when the first power supply supplies power to the fifth switching transistor, the fifth, sixth, seventh, ninth, and eleventh switching transistors conduct, and the gate of the eleventh switching transistor provides a startup voltage for the fourth switching transistor. When the second switching transistor conducts, the eighth switching transistor conducts while the seventh switching transistor cuts off, and the tenth switching transistor conducts while the ninth switching transistor cuts off. When the fifth, sixth, eighth, and tenth switching transistors are all conducting, the gate of the eleventh switching transistor provides a startup voltage for the fourth switching transistor.

[0077] In some embodiments of the present application, the fifth, sixth, seventh, eighth, ninth, tenth, and eleventh switching transistors are all MOS transistors. In the startup unit, the eighth and seventh switching transistors conduct alternately, and the tenth and ninth switching transistors conduct alternately, which has the effect of reducing the loss of the switching transistors and protecting the eighth and seventh switching transistors, and the tenth and ninth switching transistors.

[0078] In some embodiments of the present application, after the eleventh switching transistor outputs a startup voltage, when the bias unit receives the startup voltage, it outputs a bias voltage through the fourth switching transistor to ensure that the voltages at the positive input terminal and the negative input terminal of the first operational amplifier in the bandgap reference core unit are both non-zero, so that the first operational amplifier can work normally when powered on.

[0079] Figure 3 is a schematic structural diagram of a bandgap reference circuit shown in an exemplary embodiment of the present application, as Figure 3 shown, the bandgap reference circuit includes: a startup circuit (i.e., a startup unit), a bias circuit (i.e., a bias unit), a bandgap reference core circuit (i.e., a bandgap reference core unit), and a mirror circuit (i.e., a mirror unit). Among them, the startup circuit includes: a fifth switching transistor M2, the source of the fifth switching transistor M2 is connected to the first power supply VDD, the gate and the drain of the fifth switching transistor M2 are connected, the drain of the fifth switching transistor M2 is connected to the source of the sixth switching transistor M3, the gate and the drain of the sixth switching transistor M3 are connected, the drain of the sixth switching transistor M3 is connected to the drain of the seventh switching transistor M5, the drain and the gate of the seventh switching transistor M5 are connected, the drain of the seventh switching transistor M5 is connected to the drain of the eighth switching transistor M4, and the gate of the eighth switching transistor M4 is connected to the fourth switching transistor M10 The drain of the seventh switching transistor M5 and the sources of the seventh switching transistor M5 and the eighth switching transistor M4 are grounded; the gate of the seventh switching transistor M5 is connected to the gate of the ninth switching transistor M6, the source of the ninth switching transistor M6 is grounded, the drain of the ninth switching transistor M6 is connected to the drain of the tenth switching transistor M7, the source of the tenth switching transistor M7 is grounded, the gate of the tenth switching transistor M7 is connected to the gate of the second switching transistor M8, the drain of the tenth switching transistor M7 is connected to the drain of the eleventh switching transistor M9, the source of the eleventh switching transistor M9 is connected to the drain of the first switching transistor M1, the gate of the eleventh switching transistor M9 is connected to the drain of the eleventh switching transistor M9, and the gate of the eleventh switching transistor M9 is connected to the gate of the fourth switching transistor M 10 ; The bias circuit includes: the second switching transistor M8, the third switching transistor M 11 and the fourth switching transistor M 10 , the source of the third switching transistor M 11 is connected to the drain of the first switching transistor M1, the gate of the third switching transistor M 11 is connected to the gate of the twelfth switching transistor M 13 , the drain of the third switching transistor M 11 is connected to the source of the fourth switching transistor M 10 , the gate of the fourth switching transistor M 10 is connected to the gate of the thirteenth switching transistor M 12 , the gate of the fourth switching transistor M 10 is connected to the gate of the eleventh switching transistor M9, the drain of the fourth switching transistor M 10 is connected to the gate of the eighth switching transistor M4, and the drain of the fourth switching transistor M 10 is connected to the drain of the second switching transistor M8; The bandgap reference core circuit includes: the drain of the first switching transistor M1 is connected to the source of the twelfth switching transistor M 13 , the gate of the twelfth switching transistor M 13 is connected to the gate of the third switching transistor M 11 , the drain of the twelfth switching transistor M 13 is connected to the source of the thirteenth switching transistor M 12 , the gate of the thirteenth switching transistor M 12 is connected to the gate of the fourth switching transistor M 10 , the drain of the thirteenth switching transistor M 12 is connected to the emitter of the first triode Q1, and the drain of the thirteenth switching transistor M 12 is connected to the base of the second triode Q2. The base and the collector of the first triode Q1 are both grounded; The drain of the first switching transistor M1 is connected to the source of the fourteenth switching transistor M 15 , the gate of the fourteenth switching transistor M 15 is connected to the gate of the twelfth switching transistor M 13 , and the gate of the fourteenth switching transistor M15 The drain of which is connected to the fifteenth switching transistor M 14 The source of which, and the gate of the fifteenth switching transistor M 14 Is connected to the gate of the thirteenth switching transistor M 12 The gate of which, and the drain of the fifteenth switching transistor M 14 Is connected to one end of the first adjustable resistor R1, the other end of the first adjustable resistor R1 is connected to the positive input terminal of the first operational amplifier, the other end of the first adjustable resistor R1 is connected to one end of the first fixed resistor R2, the other end of the first fixed resistor R2 is connected to the emitter of the second triode Q2, the collector of the second triode Q2 is grounded, and the base of the second triode Q2 is connected to the emitter of the first triode Q1; The drain of the first switching transistor M1 is connected to the sixteenth switching transistor M 17 The source of which, and the gate of the sixteenth switching transistor M 17 Is connected to the gate of the fourteenth switching transistor M 15 The gate of which, and the drain of the sixteenth switching transistor M 17 Is connected to the source of the seventeenth switching transistor M 16 The gate of which, and the drain of the seventeenth switching transistor M 16 Is connected to the gate of the fifteenth switching transistor M 14 The gate of which, and the drain of the seventeenth switching transistor M 16 Is connected to the emitter of the third triode Q3, the drain of the seventeenth switching transistor M 16 The drain of which is connected to the negative input terminal of the first operational amplifier, and the collector of the third triode Q3 Is grounded; The drain of the first switching transistor M1 is connected to the eighteenth switching transistor M 19 The source of which, and the gate of the eighteenth switching transistor M 19 Is connected to the gate of the sixteenth switching transistor M 17 The gate of which, and the drain of the eighteenth switching transistor M 19 Is connected to the source of the nineteenth switching transistor M 18 The gate of which, and the drain of the nineteenth switching transistor M 18 Is connected to the gate of the seventeenth switching transistor M 16 The gate of which, and the drain of the nineteenth switching transistor M 18 Is connected to the base of the third triode Q3, the drain of the nineteenth switching transistor M 18 The drain of which is connected to the emitter of the fourth triode Q4, and the base and collector of the fourth triode Q4 are both grounded.

[0080] In an embodiment of the present application, by introducing the current I3 of the second fixed-value resistor with a negative temperature coefficient into the bandgap reference circuit, the reference core current is compensated, reducing the influence of the temperature coefficient of the higher-order term in the reference core current on the bandgap reference voltage. The formula for compensating the reference core current is shown in Equation (4); when designing the circuit, by reasonably changing the resistance value R3 of the second fixed-value resistor, the magnitude and slope of the current I3 of the second fixed-value resistor can be changed, and further, the junction voltage V of the fifth triode BEQ5 The trimming of the higher-order temperature coefficient term in BEQ5 The result of trimming the higher-order temperature coefficient term in is shown in Equation (5). Compared with Figure 1 the output bandgap reference voltage, the junction voltage V of the fifth triode in the bandgap reference voltage output by Equation (5) BEQ5 is halved, reducing the offset influence caused by the manufacturing process on the bandgap reference voltage, thereby improving the stability and accuracy of the bandgap reference voltage output, and improving the wide application of the bandgap reference circuit in high-precision systems;

[0081] In addition, since the first voltage regulator sub-unit, the second voltage regulator sub-unit, the third voltage regulator sub-unit, and the fourth voltage regulator sub-unit all adopt the cascode structure, the power supply rejection ratio of the bandgap reference core is improved. Moreover, the collector-grounded structure of the triodes Q1~Q4 greatly reduces the influence of the offset voltage of the first operational amplifier

[0082] Figure 4 is a schematic diagram of the simulation result of the power supply rejection ratio of the bandgap reference circuit shown in an exemplary embodiment of the present application. In Figure 4 , the abscissa represents the frequency, and the ordinate represents the power supply rejection ratio. It can be seen from Figure 4 that when the frequency range is 1 - 100 Hz, the power supply rejection ratio of the bandgap reference circuit is less than -105 dB, and when the frequency is 18.197 Hz, the power supply rejection ratio of the bandgap reference circuit is -109.054 dB. Thus, it can be known that the power supply rejection ratio of the bandgap reference circuit shown in an exemplary embodiment of the present application can reach an ideal level during implementation.

[0083] Figure 5 is a schematic diagram of the simulation result of the relationship between the bandgap reference voltage output by the bandgap reference circuit and temperature shown in an exemplary embodiment of the present application. In Figure 5 , the abscissa represents the temperature, and the ordinate represents the voltage. When the temperature is -55 °C, the bandgap reference voltage is 999.3892 mV, and when the temperature is 45.8 °C, the bandgap reference voltage is 998.4435 mV. Therefore, in the temperature range of -55 °C to 125 °C, the maximum change in the bandgap reference output voltage is 0.945 mV, and according to Figure 5The relationship between the medium voltage and temperature is calculated, and the temperature coefficient is about 5.26 ppm / °C. Thus, it can be known that the voltage of the bandgap reference circuit shown in an exemplary embodiment of the present application changes little with temperature during implementation, and the output accuracy and stability of the bandgap reference voltage are good.

[0084] The following introduces the method embodiments of the present application, which can be applied to the bandgap reference circuit in the above embodiments of the present application. For details not disclosed in the method embodiments of the present application, please refer to the embodiments of the bandgap reference circuit above of the present application.

[0085] The implementation details of the technical solutions of the embodiments of the present application are elaborated in detail below:

[0086] Figure 6 is a flowchart of the temperature compensation method of the bandgap reference circuit shown in an exemplary embodiment of the present application. Refer to Figure 6 As shown, the temperature compensation method of the bandgap reference circuit at least includes steps S610 to S620, which are introduced in detail as follows:

[0087] In step S610, when the bandgap reference core unit is in the working state, a reference core current is output. In an embodiment of the present application, the reference core current is the current of the first fixed-value resistor, and the reference core current carries a positive temperature coefficient.

[0088] In step S620, the reference core current is mirrored, and the temperature coefficient in the mirrored current is compensated to obtain a bandgap reference current. Based on the bandgap reference current and the resistance value of the trimming resistor, a bandgap reference voltage is output. In an embodiment of the present application, when the bandgap reference core unit is in the working state, it outputs a reference core current, and the reference core current is mirrored by a mirror unit, and the temperature coefficient in the mirrored current is compensated to obtain a bandgap reference current. Based on the bandgap reference current and the resistance value of the trimming resistor, a bandgap reference voltage is output. By compensating the temperature coefficient in the mirrored current, the temperature drift influence of the high temperature coefficient in the mirrored current on the bandgap reference voltage is reduced, and based on the bandgap reference current and the resistance value of the trimming resistor, a bandgap reference voltage is output. By trimming the bandgap reference voltage with the trimming resistor, the offset influence caused by the manufacturing process on the bandgap reference voltage is reduced, thereby improving the stability and accuracy of the output of the bandgap reference voltage, and improving the universality of the application of the bandgap reference circuit in a high-precision system.

[0089] In an embodiment of the present application, the calculation formula of the bandgap reference current includes:

[0090] I BG =I PTAT +I3 Equation (4)

[0091] where, I BGrepresents the bandgap reference current, I PTAT represents the reference core current, and I3 represents the current of the second fixed-value resistor.

[0092] In an embodiment of the present application, since the reference core current has a positive temperature coefficient and the current of the second fixed-value resistor is generated by the fifth triode and has a negative temperature coefficient, the current passing through the second fixed-value resistor compensates for the reference core current, reducing the influence of the temperature coefficient of the higher-order term in the reference core current on the bandgap reference voltage.

[0093] The calculation formula of the bandgap reference voltage includes:

[0094]

[0095] where, V BG represents the bandgap reference voltage, R5 represents the resistance value of the fourth fixed-value resistor, I BG represents the bandgap reference current, I PTAT represents the reference core current, I3 represents the current of the second fixed-value resistor, V BEQ5 represents the junction voltage of the fifth triode, R3 represents the resistance value of the second fixed-value resistor, V BEQ2,3 represents the junction voltage of the second triode or the third triode, and R1 represents the resistance value of the first fixed-value resistor.

[0096] In an embodiment of the present application, during design, by reasonably changing the resistance value R3 of the second fixed-value resistor, the magnitude and slope of the current I3 of the second fixed-value resistor can be changed, thereby trimming the higher-order temperature coefficient terms in V BEQ5 , reducing the offset influence on the bandgap reference voltage caused by the manufacturing process, thereby improving the stability and accuracy of the bandgap reference voltage output and the wide application of the bandgap reference circuit in high-precision systems.

[0097] It should be noted that the temperature compensation method of the bandgap reference circuit provided in the above embodiment and the bandgap reference circuit provided in the above embodiment belong to the same concept. The specific ways in which each module and unit perform operations have been described in detail in the method embodiment and will not be elaborated here. In practical applications, the temperature compensation method of the bandgap reference circuit provided in the above embodiment can, according to needs, allocate the above functions to different functional modules, that is, divide the internal structure of the device into different functional modules to complete all or part of the functions described above. This is not limited here either.

[0098] An embodiment of the present application further provides an integrated circuit, and the integrated circuit includes the bandgap reference circuit provided in each of the above embodiments.

[0099] Figure 7The structural schematic diagram of an integrated circuit system suitable for implementing the embodiments of the present application is shown. It should be noted that Figure 7 The illustrated integrated circuit system 700 is only an example and should not impose any limitations on the functions and usage scope of the embodiments of the present application.

[0100] As Figure 7 shown, the integrated circuit system 700 includes a central processing unit (CPU) 701, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 702 or the program loaded from the storage section 708 into the random access memory (RAM) 703, such as executing the method in the above embodiments. In the RAM 703, various programs and data required for system operation are also stored. The CPU 701, ROM 702, and RAM 703 are connected to each other via a bus 704. The input / output (I / O) interface 705 is also connected to the bus 704.

[0101] The following components are connected to the I / O interface 705: an input section 706 including a keyboard, a mouse, etc.; an output section 707 including, for example, a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 708 including a hard disk, etc.; and a communication section 709 including a network interface card such as a LAN (Local Area Network) card, a modem, etc. The communication section 709 performs communication processing via a network such as the Internet. The drive 710 is also connected to the I / O interface 705 as needed. A removable medium 711, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 710 as needed, so that the computer program read from it can be installed into the storage section 708 as needed.

[0102] Particularly, according to the embodiments of the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, the embodiments of the present application include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a computer program for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the network through the communication section 709, and / or installed from the removable medium 711. When the computer program is executed by the central processing unit (CPU) 701, various functions defined in the system of the present application are executed.

[0103] It should be noted that the computer-readable medium shown in the embodiments of the present application can be a computer-readable signal medium, a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable computer program. Such a propagated data signal can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The computer program contained on the computer-readable medium can be transmitted using any appropriate medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

[0104] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present application. Among them, each block in the flowchart or block diagram can represent a module, a program segment, or a part of code, and the above module, program segment, or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than that marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram or flowchart, and the combination of blocks in the block diagram or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions.

[0105] The units involved in the embodiments described in this application can be implemented in software or in hardware, and the described units can also be provided in a processor. Among them, the names of these units do not, in some cases, constitute a limitation on the unit itself.

[0106] Another aspect of this application also provides an image device on which computer-readable instructions are stored. When the computer-readable instructions are executed by a processor of a computer, the computer is caused to execute the temperature compensation method of the bandgap reference circuit provided in each of the above embodiments. The image device may include the image sensor described in the above embodiments, or may exist alone without assembling the image sensor described in the above embodiments into the image device.

[0107] It should be noted that although several modules or units of a device for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of this application, the features and functions of two or more of the above-described modules or units can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0108] From the description of the above embodiments, those skilled in the art can easily understand that the example embodiments described herein can be implemented by software or by a combination of software and necessary hardware. Therefore, the technical solution according to the embodiments of this application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, including several instructions to cause a computing device (which can be a personal computer, a server, a touch terminal, or a network device, etc.) to execute the method according to the embodiments of this application.

[0109] After considering the specification and practicing the embodiments disclosed herein, those skilled in the art will readily conceive of other embodiments of this application. This application is intended to cover any variations, uses, or adaptations of this application, which follow the general principles of this application and include known common knowledge or conventional technical means in the technical field not disclosed in this application.

[0110] It should be understood that the above content is only a preferred exemplary embodiment of this application and is not used to limit the implementation of this application. Those of ordinary skill in the art can make corresponding adaptations or modifications very conveniently according to the main concept and spirit of this application. Therefore, the protection scope of this application should be subject to the protection scope required by the claims.

Claims

1. A bandgap reference circuit, characterized in that: include: The bandgap reference core unit is used to output a reference core current in a working state; The mirror unit is used to mirror the reference core current and compensate the temperature coefficient in the mirror current to obtain a bandgap reference current, and output a bandgap reference voltage based on the bandgap reference current and the resistance value of the trimming resistor.

2. The bandgap reference circuit according to claim 1, characterized in that: The bandgap reference circuit further includes: A starting unit, used for outputting a starting voltage when the first power supply is supplied; The bias unit is used to output a bias voltage when receiving the startup voltage, so as to start the bandgap reference core unit through the bias voltage and put the bandgap reference core unit into the working state.

3. The bandgap reference circuit according to claim 2, characterized in that: The bandgap reference core unit comprises: a first switch tube, wherein the source of the first switch tube is connected to the second power supply, the gate of the first switch tube is connected to the output end of the first operational amplifier, and the drain of the first switch tube is respectively connected to the source of the first voltage stabilizing subunit, the source of the second voltage stabilizing subunit, the source of the third voltage stabilizing subunit, and the source of the fourth voltage stabilizing subunit; the first switch tube is used to be turned on and provide the second power supply voltage to the first voltage stabilizing subunit, the second voltage stabilizing subunit, the third voltage stabilizing subunit, and the fourth voltage stabilizing subunit respectively when the second power supply is supplied; the first voltage stabilizing subunit, the second voltage stabilizing subunit, the third voltage stabilizing subunit, and the fourth voltage stabilizing subunit are all of a common source and common gate structure formed by a multi-stage switch tube; The gate of the first voltage stabilizing subunit is connected to the bias unit, the gate of the second voltage stabilizing subunit is connected to the gate of the first voltage stabilizing subunit, the gate of the third voltage stabilizing subunit is connected to the gate of the second voltage stabilizing subunit, and the gate of the fourth voltage stabilizing subunit is connected to the gate of the third voltage stabilizing subunit; the first voltage stabilizing subunit, the second voltage stabilizing subunit, the third voltage stabilizing subunit and the fourth voltage stabilizing subunit are all used to output a drain voltage under the action of the second power supply voltage and the bias voltage; the fluctuation range of the drain voltage is less than a preset range threshold; The drain of the first voltage stabilizing subunit is connected to the emitter of the first transistor, the base of the first transistor and the collector of the first transistor are both grounded; the first transistor is used to be turned on under the action of the drain voltage; The drain of the second voltage stabilizing subunit is connected to one end of the first adjustable resistor, the other end of the first adjustable resistor is connected to the positive input end of the first operational amplifier, the other end of the first adjustable resistor is connected to one end of the first fixed resistor, the other end of the first fixed resistor is connected to the emitter of the second triode, the collector of the second triode is used for grounding, and the base of the second triode is connected to the emitter of the first triode; the second triode is used for being turned on under the action of the drain voltage, and the first operational amplifier is used for obtaining a positive input voltage when the second triode is turned on; The drain of the third voltage stabilizing subunit is connected to the reverse input terminal of the first operational amplifier, the drain of the third voltage stabilizing subunit is connected to the emitter of the third triode, and the collector of the third triode is used for grounding; the third triode is used for being turned on under the action of the drain voltage, and the first operational amplifier is used for obtaining a reverse input voltage when the third triode is turned on; The drain of the fourth voltage stabilizing subunit is connected to the base of the third triode, the drain of the fourth voltage stabilizing subunit is connected to the emitter of the fourth triode, the base of the fourth triode and the collector of the fourth triode are both used for grounding; the fourth triode is used for conducting under the action of the drain voltage; A current output module is used to output the current of the first fixed resistor as the reference core current when the first transistor is turned on, the second transistor is turned on, the third transistor is turned on and the fourth transistor is turned on.

4. The bandgap reference circuit according to claim 3, characterized in that: The mirror unit comprises: A fifth voltage stabilizing subunit, wherein the source of the fifth voltage stabilizing subunit is connected to the drain of the first switch tube, the gate of the fifth voltage stabilizing subunit is connected to the gate of the fourth voltage stabilizing subunit, the drain of the fifth voltage stabilizing subunit is connected to the positive input terminal of the second operational amplifier, the drain of the fifth voltage stabilizing subunit is connected to one end of the second fixed resistor, the drain of the fifth voltage stabilizing subunit is connected to one end of the third fixed resistor, the other end of the third fixed resistor is connected to one end of the fourth fixed resistor, and the other end of the fourth fixed resistor is used for grounding; the fifth voltage stabilizing subunit is used to output the drain voltage under the action of the second power supply voltage and the bias voltage; the fifth voltage stabilizing subunit is a common source and common gate structure formed by a multi-stage switch tube; the number of stages of the switch tube in the fifth voltage stabilizing subunit is the same as the number of stages of the switch tube in the fourth voltage stabilizing subunit; A sixth voltage stabilizing subunit, wherein the source of the sixth voltage stabilizing subunit is connected to the drain of the first switch tube, the gate of the sixth voltage stabilizing subunit is connected to the gate of the fifth voltage stabilizing subunit, the drain of the sixth voltage stabilizing subunit is connected to the other end of the second fixed resistor, the drain of the sixth voltage stabilizing subunit is connected to the emitter of the fifth triode, the base of the fifth triode is connected to the output end of the second operational amplifier, the base of the fifth triode is connected to the reverse input end of the second operational amplifier, and the collector of the fifth triode is grounded; the sixth voltage stabilizing subunit is used to output the drain voltage under the action of the second power supply voltage and the bias voltage; the fifth triode is turned on under the action of the drain voltage; the sixth voltage stabilizing subunit is a common source and common gate structure formed by multiple stages of switch tubes; the number of stages of the switch tubes in the sixth voltage stabilizing subunit is the same as the number of stages of the switch tubes in the fifth voltage stabilizing subunit; A voltage output module is used to output the voltage difference between the two ends of the fourth fixed resistor as the bandgap reference voltage when the fifth transistor is turned on; the process of determining the voltage difference between the two ends of the fourth fixed resistor includes: performing temperature coefficient compensation on the mirror current through the current of the second fixed resistor to obtain the bandgap reference current, and using the second fixed resistor and the fourth fixed resistor as the adjustment resistor, and calculating the voltage difference between the two ends of the fourth fixed resistor based on the bandgap reference current and the adjustment resistor.

5. The bandgap reference circuit according to claim 3, characterized in that: The bias unit comprises: a seventh voltage stabilizing subunit, wherein the source of the seventh voltage stabilizing subunit is connected to the drain of the first switch tube, the gate of the seventh voltage stabilizing subunit is connected to the startup unit, the gate of the seventh voltage stabilizing subunit is connected to the gate of the first voltage stabilizing subunit, the drain of the seventh voltage stabilizing subunit is connected to the startup unit, the drain of the seventh voltage stabilizing subunit is connected to the drain of the second switch tube, the gate of the second switch tube is connected to the startup unit, the source of the second switch tube is used for grounding, and the gate of the second switch tube is connected to the drain of the second switch tube; the seventh voltage stabilizing subunit is a common source and common gate structure formed by multiple stages of switch tubes; the number of stages of switch tubes in the seventh voltage stabilizing subunit is the same as the number of stages of switch tubes in the first voltage stabilizing subunit; The seventh voltage stabilizing subunit is used to provide the bias voltage for the first voltage stabilizing subunit, the second voltage stabilizing subunit, the third voltage stabilizing subunit and the fourth voltage stabilizing subunit under the action of the second power supply voltage and the startup voltage.

6. The bandgap reference circuit according to claim 5, characterized in that: The seventh voltage stabilizing subunit comprises: a third switch tube and a fourth switch tube, wherein the source of the third switch tube is connected to the drain of the first switch tube, the gate of the third switch tube is connected to the gate of the first-stage switch tube in the first voltage stabilizing subunit, the drain of the third switch tube is connected to the source of the fourth switch tube, the gate of the fourth switch tube is connected to the gate of the second-stage switch tube in the first voltage stabilizing subunit, the gate of the fourth switch tube is connected to the startup unit, the drain of the fourth switch tube is connected to the startup unit, and the drain of the fourth switch tube is connected to the drain of the second switch tube.

7. The bandgap reference circuit according to claim 6, characterized in that: The startup unit comprises: a fifth switch tube, wherein the source of the fifth switch tube is connected to the first power supply, the gate of the fifth switch tube is connected to the drain of the fifth switch tube, the drain of the fifth switch tube is connected to the source of the sixth switch tube, the gate of the sixth switch tube is connected to the drain of the sixth switch tube, the drain of the sixth switch tube is connected to the drain of the seventh switch tube, the drain of the seventh switch tube is connected to the gate of the seventh switch tube, the drain of the seventh switch tube is connected to the drain of the eighth switch tube, the gate of the eighth switch tube is connected to the drain of the fourth switch tube, the source of the seventh switch tube is connected to the drain of the eighth switch tube The source of the seventh switch tube is used for grounding; the gate of the seventh switch tube is connected to the gate of the ninth switch tube, the source of the ninth switch tube is used for grounding, the drain of the ninth switch tube is connected to the drain of the tenth switch tube, the source of the tenth switch tube is used for grounding, the gate of the tenth switch tube is connected to the gate of the second switch tube, the drain of the tenth switch tube is connected to the drain of the eleventh switch tube, the source of the eleventh switch tube is connected to the drain of the first switch tube, the gate of the eleventh switch tube is connected to the drain of the eleventh switch tube, and the gate of the eleventh switch tube is connected to the gate of the fourth switch tube; The eleventh switch tube is used to be turned on and provide the starting voltage to the fourth switch tube when the fifth switch tube, the sixth switch tube, the seventh switch tube and the ninth switch tube are all turned on, or the eleventh switch tube is used to be turned on and provide the starting voltage to the fourth switch tube when the fifth switch tube, the sixth switch tube, the eighth switch tube and the tenth switch tube are all turned on.

8. A temperature compensation method for a bandgap reference circuit, characterized in that: The method comprises: When the bandgap reference core unit is in working state, a reference core current is output; The reference core current is mirrored, and the temperature coefficient in the mirrored current is compensated to obtain a bandgap reference current. Based on the bandgap reference current and the resistance value of the trimming resistor, a bandgap reference voltage is output.

9. The temperature compensation method of the bandgap reference circuit according to claim 8, characterized in that: The calculation formula of the bandgap reference current is include: I BG =I PTAT +I3, Among them, I BG represents the bandgap reference current, I PTAT represents the reference core current, I3 represents the current of the second fixed value resistor; The calculation formula of the bandgap reference voltage includes: Among them, V BG represents the bandgap reference voltage, R5 represents the resistance of the fourth fixed resistor, I BG represents the bandgap reference current, I PTAT represents the reference core current, I3 represents the current of the second fixed value resistor, V BEQ5 represents the junction voltage of the fifth transistor, R3 represents the resistance of the second fixed resistor, V BEQ2,3 represents the junction voltage of the second transistor or the third transistor, and R1 represents the resistance value of the first fixed resistor.

10. An integrated circuit, characterized in that: The integrated circuit comprises a bandgap reference circuit as claimed in any one of claims 1 to 7.

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