Time synchronization method based on inter-chip communication and chip communication system

Abstract

The invention provides an inter-chip communication-based time synchronization method and a chip communication system, and the time synchronization method is applied to the chip communication system in which a host end and a slave end establish communication connection under a preset IPC communication protocol through an SPI interface. Sending a time synchronization request signal to the slave end; the slave end captures the timing interruption, interrupts the chip process when the synchronization moment arrives, and sends a feedback signal to the host end; when the host side detects that the timestamp reaches the synchronization moment, a synchronization pulse signal is generated and sent to the slave side; and the slave end determines the sum of the synchronization moment and the calibration time value as a time synchronization result, and sets the time of a second local clock of the slave end according to the time synchronization result to complete time synchronization between chips. Through the method, the deployment difficulty and cost of time synchronization between chips are reduced, and the efficiency and flexibility of time synchronization are improved.

Description

Technical Field

[0001] This application relates to the technical fields of chip communication and time synchronization, and particularly to a time synchronization method and a chip communication system based on inter-chip communication. Background Art

[0002] Currently, exclusive communication protocols for time synchronization of chips may include gPTP, CANTsyn, etc., and the chips can be deployed on communication media such as CAN or Eth. Deploying such time synchronization communication technologies among chips in a chip communication system is very cumbersome, and targeted hardware modules are required, increasing the cost of time synchronization based on inter-chip communication.

[0003] In addition, the inter-chip time synchronization technology and protocol stack of the above method are relatively complex. For example, time synchronization technologies based on Ethernet or CAN communication are difficult to apply in an embedded environment, reducing the applicability of time synchronization, and thus reducing the efficiency of time synchronization between chips. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a time synchronization method and a chip communication system based on inter-chip communication. In the chip communication system, a communication connection between a host end and a slave end is established through an SPI interface under the IPC communication protocol. The host end determines the synchronization moment and sets a timing interrupt using the CS pin configured by the SPI interface. The slave end captures the timing interrupt through the CS pin and interrupts the chip process. Then, the host end calls an interrupt service function and sends a synchronization pulse signal to the slave end, so that the slave end performs time synchronization based on the synchronization moment and a pre-calibrated calibration time value, achieving the efficient coordination of IPC communication technology and time synchronization, realizing high-precision time synchronization and data synchronization between chips, reducing the deployment difficulty and cost of time synchronization based on inter-chip communication, and improving the efficiency and flexibility of time synchronization between chips.

[0005] An embodiment of this application provides a time synchronization method based on inter-chip communication. The time synchronization method is applied to a chip communication system, and the chip communication system includes a host end and a slave end. The host end and the slave end establish a communication connection through an SPI interface under a preset IPC communication protocol; wherein, the host end is connected to a first CS pin configured by the SPI interface; the host end is connected to a second CS pin configured by the SPI interface, and the time synchronization method includes:

[0006] Based on a configured first local clock, the host end determines a synchronization moment for inter-chip time synchronization, controls the first CS pin to set a timing interrupt based on the synchronization moment, and sends a time synchronization request signal including the synchronization moment to the slave end;

[0007] Upon receiving the time synchronization request signal, the slave device captures the timing interrupt using the second CS pin. In response to capturing the timing interrupt, when the synchronization moment arrives, the slave interrupt service function is called to interrupt the chip process, and a feedback signal indicating that the time synchronization request has been accepted is sent to the master device.

[0008] Upon receiving the feedback signal, the master device detects the timestamp. When it detects that the timestamp has reached the synchronization moment, the master interrupt service function is called to interrupt the chip process. In the state where the chip process is interrupted, a synchronization pulse signal is generated using the first CS pin and sent to the slave device.

[0009] Upon receiving the synchronization pulse signal, the slave device uses the slave interrupt service function to determine the time synchronization result as the sum of the synchronization moment and the pre-calibrated calibration time value, and sets the time of the second local clock configured in the slave device according to the time synchronization result, so that the slave device completes the inter-chip time synchronization with the master device.

[0010] Further, based on the configured first local clock, the master device determines the synchronization moment for inter-chip time synchronization, controls the first CS pin to set a timing interrupt based on the synchronization moment, and sends a time synchronization request signal including the synchronization moment to the slave device, including:

[0011] The master device calculates the next integer second moment at which time synchronization can be performed based on the configured first local clock, and determines the integer second moment as the synchronization moment for inter-chip time synchronization.

[0012] Controls the first CS pin to set a timing interrupt according to the synchronization moment, and sets the first CS pin to the low-level output mode.

[0013] Based on the synchronization moment, determines the time synchronization request signal, and sends the time synchronization request signal to the slave device.

[0014] Further, the pre-calibrated calibration time value is determined through the following steps:

[0015] The master device determines the agreed calibration moment for calibrating the time error existing between the master device and the slave device, and sends a time calibration request signal including the agreed calibration moment to the slave device.

[0016] Upon receiving the time calibration request signal, the slave device generates a first calibration pulse signal for measuring the time error using the CLK pin configured by the SPI interface when the agreed calibration moment arrives;

[0017] The master device measures the time difference between the first calibration pulse signal and the second calibration pulse signal generated by the master device at the agreed calibration moment using a preset signal measuring device;

[0018] The master device repeats the measurement of the time difference according to a preset number of measurements, determines a calibration time value representing the time error between the master device and the slave device, and inputs the calibration time value into the slave device to calibrate the time error of the slave device.

[0019] Further, the step of determining the pre-calibrated calibration time value further includes:

[0020] Upon receiving the time calibration request signal by the slave device, the master device generates a second calibration pulse signal using the first CS pin when the agreed calibration moment arrives.

[0021] Further, after the slave device completes the inter-chip time synchronization with the master device, the time synchronization method further includes:

[0022] The master device sends a clock synchronization confirmation signal to the slave device at a preset time interval;

[0023] Upon receiving the clock synchronization confirmation signal, the slave device generates a time setting result of the second local clock and returns the time setting result to the master device.

[0024] Further, the IPC communication protocol at least includes data frames, frame timing, sending rules, interaction timing, and communication control architecture.

[0025] An embodiment of the present application further provides a chip communication system, which includes:

[0026] A master device, configured to determine a synchronization moment for inter-chip time synchronization based on a configured first local clock, control the first CS pin to set a timing interrupt based on the synchronization moment, and send a time synchronization request signal including the synchronization moment to a slave device; upon receiving a feedback signal, detect a timestamp, and when detecting that the timestamp has reached the synchronization moment, call a master interrupt service function to interrupt the chip process, and in the state of the interrupted chip process, generate a synchronization pulse signal using the first CS pin and send the synchronization pulse signal to the slave device;

[0027] The slave side is used to, in response to receiving the time synchronization request signal, capture the timing interrupt using the second CS pin, and in response to capturing the timing interrupt, when the synchronization moment arrives, call the slave interrupt service function to interrupt the chip process, and send a feedback signal indicating that the time synchronization request has been accepted to the host side; in response to receiving the synchronization pulse signal, use the slave interrupt service function to determine the sum of the synchronization moment and a pre-calibrated calibration time value as the time synchronization result, and set the time of the second local clock configured on the slave side according to the time synchronization result, so that the slave side completes the inter-chip time synchronization with the host side.

[0028] Further, the host side includes:

[0029] A synchronization request module, which is used to, based on the configured first local clock, determine the synchronization moment for inter-chip time synchronization, control the first CS pin to set a timing interrupt based on the synchronization moment, and send a time synchronization request signal including the synchronization moment to the slave side;

[0030] A synchronization pulse module, which is used to, in response to receiving a feedback signal, detect a time stamp, and when it detects that the time stamp has reached the synchronization moment, call the host interrupt service function to interrupt the chip process, and in the state where the chip process is interrupted, generate a synchronization pulse signal using the first CS pin and send the synchronization pulse signal to the slave side.

[0031] Further, when the synchronization request module is used to, based on the configured first local clock, determine the synchronization moment for inter-chip time synchronization, control the first CS pin to set a timing interrupt based on the synchronization moment, and send a time synchronization request signal including the synchronization moment to the slave side, the synchronization request module is used for:

[0032] The host side calculates the next integer second moment at which time synchronization can be performed based on the configured first local clock, and determines the integer second moment as the synchronization moment for inter-chip time synchronization;

[0033] Control the first CS pin to set a timing interrupt according to the synchronization moment, and set the first CS pin to the low-level output mode;

[0034] Based on the synchronization moment, determine the time synchronization request signal, and send the time synchronization request signal to the slave side.

[0035] Further, the host side further includes a first confirmation module, and the first confirmation module is used for:

[0036] Send a clock synchronization confirmation signal to the slave side at a preset time interval.

[0037] Further, the slave device includes:

[0038] An interrupt control module, configured to respond to receiving the time synchronization request signal, capture the timing interrupt by using a second CS pin, and in response to capturing the timing interrupt, when the synchronization moment arrives, call a slave interrupt service function to interrupt the chip process, and send a feedback signal indicating that the time synchronization request has been accepted to the host device;

[0039] A time synchronization module, configured to respond to receiving the synchronization pulse signal, use the slave interrupt service function to determine the sum of the synchronization moment and a pre-calibrated calibration time value as a time synchronization result, and set the time of a second local clock configured by the slave device according to the time synchronization result, so that the slave device completes chip-level time synchronization with the host device.

[0040] Further, the slave device further includes a second confirmation module, and the second confirmation module is configured to:

[0041] Respond to receiving the clock synchronization confirmation signal, generate a time setting result of the second local clock, and return and send the time setting result to the host device.

[0042] An embodiment of the present application further provides an electronic device, including: a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device runs, the processor communicates with the memory through the bus. When the machine-readable instructions are executed by the processor, the steps of the time synchronization method based on inter-chip communication as described above are executed.

[0043] An embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is run by a processor, the steps of the time synchronization method based on inter-chip communication as described above are executed.

[0044] The time synchronization method and chip communication system based on inter-chip communication provided by the embodiments of the present application. The time synchronization method includes: The host side determines a synchronization moment for inter-chip time synchronization based on a configured first local clock, controls the first CS pin to set a timing interrupt based on the synchronization moment, and sends a time synchronization request signal including the synchronization moment to the slave side; In response to receiving the time synchronization request signal, the slave side uses the second CS pin to capture the timing interrupt. In response to capturing the timing interrupt, when the synchronization moment arrives, the slave side calls the slave interrupt service function to interrupt the chip process, and sends a feedback signal indicating that the time synchronization request has been accepted to the host side; In response to receiving the feedback signal, the host side detects the time stamp. When it detects that the time stamp has reached the synchronization moment, the host side calls the host interrupt service function to interrupt the chip process. In the state where the chip process is interrupted, the host side generates a synchronization pulse signal using the first CS pin and sends the synchronization pulse signal to the slave side; In response to receiving the synchronization pulse signal, the slave side uses the slave interrupt service function to determine the sum of the synchronization moment and a pre-calibrated calibration time value as the time synchronization result, and sets the time of the second local clock configured by the slave side according to the time synchronization result, so that the slave side completes the inter-chip time synchronization with the host side.

[0045] Compared with the prior art method of using an exclusive communication protocol and deploying chips on communication media such as CAN or Eth, in the chip communication system, a communication connection between the host side and the slave side is established through the SPI interface under the IPC communication protocol. The host side determines the synchronization moment and uses the CS pin configured by the SPI interface to set a timing interrupt. The slave side captures the timing interrupt through the CS pin and interrupts the chip process. Then, the host side calls the interrupt service function and sends a synchronization pulse signal to the slave side, so that the slave side performs time synchronization based on the synchronization moment and the pre-calibrated calibration time value, realizing the efficient cooperation between the IPC communication technology and time synchronization, achieving high-precision time synchronization and data synchronization between chips, reducing the deployment difficulty and cost of time synchronization based on inter-chip communication, and improving the efficiency and flexibility of time synchronization between chips.

[0046] To make the above objects, features, and advantages of the present application more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, makes a detailed description as follows. Description of the Drawings

[0047] To more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and should not be regarded as a limitation of the scope. For those of ordinary skill in the art, without creative efforts, other relevant drawings can also be obtained based on these drawings.

[0048] Figure 1 It is a schematic structural diagram of a chip communication system provided by an embodiment of the present application;

[0049] Figure 2(a) is a schematic diagram of a data frame of an IPC communication protocol provided by an embodiment of the present application;

[0050] Figure 2(b) is a schematic diagram of frame timing of an IPC communication protocol provided by an embodiment of the present application;

[0051] Figure 2(c) is a schematic diagram of interaction timing of an IPC communication protocol provided by an embodiment of the present application;

[0052] Figure 2(d) is a schematic diagram of a communication control architecture of an IPC communication protocol provided by an embodiment of the present application;

[0053] Figure 3 It is one of the flowcharts of a time synchronization method based on inter-chip communication provided by an embodiment of the present application;

[0054] Figure 4 It is the second flowchart of a time synchronization method based on inter-chip communication provided by an embodiment of the present application;

[0055] Figure 5 It is one of the schematic structural diagrams of a host end provided by an embodiment of the present application;

[0056] Figure 6 It is the second schematic structural diagram of a host end provided by an embodiment of the present application;

[0057] Figure 7 It is one of the schematic structural diagrams of a slave end provided by an embodiment of the present application;

[0058] Figure 8 It is the second schematic structural diagram of a slave end provided by an embodiment of the present application;

[0059] Figure 9 It is a schematic structural diagram of an electronic device provided by an embodiment of the present application. Detailed implementation manners

[0060] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of this application. Apparently, the described embodiments are only a part rather than all of the embodiments of this application. Components of the embodiments of this application described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. Based on the embodiments of this application, every other embodiment obtained by those skilled in the art without creative efforts falls within the scope of protection of this application.

[0061] It has been found through research that currently, exclusive communication protocols for time synchronization of chips may include gPTP, CANTsyn, etc., and the chips can be deployed on communication media such as CAN or Eth. Deploying such time synchronization communication technologies among chips in a chip communication system is very cumbersome, and targeted hardware modules are required, increasing the cost of time synchronization based on inter-chip communication. In addition, the inter-chip time synchronization technology and protocol stack of the above methods have a high complexity. For example, time synchronization technologies based on Ethernet or CAN communication are difficult to apply in an embedded environment, reducing the applicability of time synchronization and thus reducing the efficiency of time synchronization between chips.

[0062] To address the problems in at least one of the above aspects, the embodiments of this application provide a time synchronization method based on inter-chip communication. In a chip communication system, a communication connection between a host end and a slave end is established through an SPI interface under the IPC communication protocol. The host end determines the synchronization moment and sets a timing interrupt using the CS pin configured by the SPI interface. The slave end captures the timing interrupt through the CS pin and performs a chip process interrupt. Then, the host end calls an interrupt service function and sends a synchronization pulse signal to the slave end, so that the slave end performs time synchronization based on the synchronization moment and a pre-calibrated calibration time value, achieving efficient coordination between IPC communication technology and time synchronization, realizing high-precision time synchronization and data synchronization between chips, reducing the deployment difficulty and cost of time synchronization based on inter-chip communication, and improving the efficiency and flexibility of time synchronization between chips.

[0063] Please refer to Figure 1 , Figure 1 which is a schematic structural diagram of a chip communication system provided by the embodiments of this application. As Figure 1 shown in it, the chip communication system 10 provided by the embodiments of this application includes a host end 100 and a slave end 200. Among them, the host end 100 and the slave end 200 establish a communication connection through an SPI interface under a preset IPC communication protocol.

[0064] In an embodiment of the present application, the chips performing communication in the chip communication system adopt full-duplex point-to-point communication, that is, no start bit and stop bit are required to identify the start and end of the data frame, and two-way transmission of the chip can be achieved at the same time. Among multiple chip ends in the chip communication system, a chip end with a larger data transmission volume is selected as the host end 100, and at least one of the other chip ends will be used as the slave end 200.

[0065] Here, the SPI (Serial Peripheral Interface) interface is an interface applying the synchronous serial communication interface specification, usually used for short-distance communication, mainly for data transmission between a master device (usually a microcontroller) and one or more slave devices (such as sensors, memory chips, etc.).

[0066] Among them, the SPI interface is at least configured with four pins, specifically including: CLK pin, MOSI pin, MISO pin, and CS pin.

[0067] Specifically, the CLK pin represents the serial clock line pin. The signal line of this pin is generated by the host end and is used to synchronize the data transmission. The clock signal of this pin determines when the data bit is sampled or sent, and the data is usually read or written at the rising edge or falling edge of the clock signal.

[0068] The MOSI pin is used to send data from the host end to the slave end, serving as an output in the host end and an input in the slave end; the MISO pin is used to send data from the slave end to the host end, serving as an input in the host end and an output in the slave end. In the full-duplex mode, the signal lines of the MOSI pin and the MISO pin can be used simultaneously for two-way data transmission.

[0069] The CS pin represents the chip select signal line pin, used to select a specific slave end for communication. In the chip communication system, each slave end has a CS signal line corresponding to the CS pin connected to the host end. When the host end wants to communicate with a specific slave end, the host end will pull down the CS pin corresponding to this slave end (usually converted to a low level), while the CS pins of other slave ends not participating in the communication remain at a high level.

[0070] In an implementation manner of the present application, during specific implementation, the preset IPC communication protocol at least includes a data frame, frame timing, sending rules, interaction timing, and a communication control architecture.

[0071] Please refer to FIG. 2(a). FIG. 2(a) is a schematic diagram of a data frame of an IPC communication protocol provided by an embodiment of the present application. As shown in FIG. 2(a), the data frame is used to define the data frame structure when the host side and the slave side in a chip communication system perform signal data communication. The data frame includes a data header (Header), a payload (Payload), and a checksum integrity data (Checksum).

[0072] Among them, the data header (Header) includes Start (2 bytes), ID (2 bytes), Timestamp (4 bytes), and Len (2 bytes). Start is used to identify the start of the data frame to ensure that the receiving party can correctly identify the starting position of the data frame. For example, 0x5A, 0xA5; ID is used to identify the unique identifier or type of the data frame to help the receiving party identify the type or source of the data frame, such as device ID, command type, etc. The highest bit is used as the control frame and data frame flag bit, 1 for the control frame, 0 for the data frame; Timestamp is used to record the timestamp when the data frame is generated, providing time information for synchronization, sorting, or recording the time when an event occurs. The accuracy can be set to 1 ms, and it starts counting from 0 again after power-on reset or overflow; Len represents the number of bytes of the payload (Payload) (not more than 512 bytes), telling the receiving party how many bytes the payload has to correctly parse the subsequent data.

[0073] The payload (Payload) contains the actual data content of the data frame, and the stored data length is at most 512 bytes, which is used to store specific application data, such as sensor readings, control instructions, etc.

[0074] The checksum integrity data (Checksum) is used to verify the integrity of the data frame, with a length of 1 byte. It is calculated through a cyclic redundancy check (CRC) algorithm, such as reserved or by cumulative summation, and is used to detect possible errors during transmission.

[0075] As an example of forwarding CAN message data through the data frame defined in the IPC protocol, "Payload = (CAN_CHN + CAN_ID + CAN_LEN + CAN_DATA) * N, N >= 1", which means that the slave side parses the specific CAN Frame through DBC. Among them, CAN_LEN represents the length of CAN_DATA.

[0076] As an example of a data frame CAN / CANFD message, an extended frame CAN / CANFD message can be expressed as "ID = 0x0002, CAN_CHN = 1Byte, CAN_ID = 4Byte (lower 29 bits), CAN_LEN = 1Byte"; a standard frame CAN / CANFD message can be expressed as "ID = 0x0001, CAN_CHN = 1Byte, CAN_ID = 2Byte (lower 11 / 12 bits), CAN_LEN = 1Byte".

[0077] Further, please refer to FIG. 2(b). FIG. 2(b) is a schematic diagram of the frame timing of an IPC communication protocol provided by an embodiment of the present application. As shown in FIG. 2(b), the data frame performs data communication through the frame timing. The four pins of the SPI interface correspond to four signal lines, namely CS, CLK, MOSI, and MISO. slave_flag (the signal line corresponding to the CS pin): remains low to indicate that the slave end is selected. The CLK signal line represents the clock signal, which is generated by the master device and is used to synchronize the transmission of data; the MOSI signal line represents that the master end sends a data frame to the slave end through this signal line; MISO represents that the slave end sends a data frame to the master end through this line.

[0078] Among them, the SPI interface is in a 3-wire mode. The signal line corresponding to the CS pin is used as an indication of whether there is data at the slave end. If the storage area inside the slave end for temporarily storing data to be sent or already received is not empty, the level of the CS pin is pulled low.

[0079] Furthermore, the sending rule specifically includes: if the data stored at the master end is not empty or the CS pin is low, the master end continuously sends data signals using the CLK pin; if the data stored at the master end is empty, the master end alternately sends data in the data format "0xFF, 0x00" by default; if the data stored at the slave end is not empty, the slave end pulls the level of the CS pin low and sends data to the master end; if the data stored at the slave end is empty, the slave end alternately sends data in the data format "0xFF, 0x00" by default.

[0080] Here, the line system scheme of the IPC communication protocol can include: the CS pin is used as an indication of the start and end of frame data for the slave end. For example, the CS pin starts sending at the falling edge and ends sending at the rising edge; the line system scheme can also include: the CS pin is used as an indication of the start and end of frame data for the master end, and an additional signal line is used as an indication of the start and end of the frame for the slave end.

[0081] Further, please refer to FIG. 2(c). FIG. 2(c) is a schematic diagram of the interaction timing sequence of an IPC communication protocol provided by an embodiment of the present application. As shown in FIG. 2(c), the interaction timing sequence between the host side and the slave side specifically includes power-on, status synchronization, and data transmission.

[0082] Among them, power-on means that the host side and the slave side respectively initialize the SPI interface and internal status; status synchronization means that the host side sends a status synchronization control frame to determine whether the slave side is ready to receive data; data transmission means that after the host side and the slave side enter the data transceiver state, full-duplex data exchange starts; here, if data transmission errors or abnormalities occur, status synchronization can be re-performed.

[0083] Further, please refer to FIG. 2(d). FIG. 2(d) is a schematic diagram of the communication control architecture of an IPC communication protocol provided by an embodiment of the present application. As shown in FIG. 2(d), the communication control architecture is an IPC software architecture, which specifically includes: Interface, that is, docking with external modules, used for sending feedback status (for example, Ipc_msg_send(*pdu)) and receiving data (for example, Ipc_msg_receive(*pdu)), etc.; State Management, that is, initializing a circular buffer, used for managing synchronization status, processing control frames, and monitoring abnormal status; Data Management, that is, a data management module, used for processing data frames PDU, buffering, packing, encoding and decoding, etc.; Transport is used for processing the communication frame structure of the SPI interface; Share RAM represents shared memory.

[0084] Please refer to Figure 3 , Figure 3 is one of the flowcharts of a time synchronization method based on inter-chip communication provided by an embodiment of the present application. The time synchronization method based on inter-chip communication provided by an embodiment of the present application is generally applied to a chip communication system as Figure 1 shown. The host side and the slave side establish a communication connection through the SPI interface under a preset IPC communication protocol; among them, the SPI interface is configured with CS pins, and the CS pins include a first CS pin and a second CS pin. The host side is connected to the first CS pin configured by the SPI interface; the host side is connected to the second CS pin configured by the SPI interface.

[0085] As Figure 3 shown, the time synchronization method includes:

[0086] S101. The host determines a synchronization moment for inter-chip time synchronization based on the configured first local clock, controls the first CS pin to set a timing interrupt based on the synchronization moment, and sends a time synchronization request signal including the synchronization moment to the slave.

[0087] It should be noted that the host can respond to a preset time synchronization program or an externally input time synchronization indication signal to perform a time synchronization method for the slave, so as to start determining a synchronization moment for inter-chip time synchronization based on the first local clock configured by the host, and further perform other steps of the time synchronization method.

[0088] Here, the host configures a first local clock, which is a hardware timer with high time accuracy; the timing interrupt is used to interrupt the processes of the host and the slave to perform time synchronization in the state of chip process interruption.

[0089] In an embodiment of the present application, in specific implementation, step S101 may include:

[0090] S1011. The host calculates the next integer second moment for time synchronization based on the configured first local clock, and determines the integer second moment as the synchronization moment for inter-chip time synchronization.

[0091] In this step, in specific implementation, first, the host obtains the current precise moment of the time stamp of the first local clock of the host based on the configured first local clock; then, determines how much time is left until the next whole second from the precise moment, and calculates the next integer second moment for time synchronization; finally, determines the integer second moment as the synchronization moment for chip time synchronization.

[0092] Wherein, the synchronization moment may include year, month, day, hour, minute, and second, and the synchronization moment may also include hour, minute, and second.

[0093] S1012. Control the first CS pin to set a timing interrupt according to the synchronization moment, and set the first CS pin to a low-level output mode.

[0094] In this step, according to the synchronization moment, control the first CS pin configured by the SPI interface to set a timing interrupt, and set the first CS pin to a low-level output mode, so that the slave responds to the low-level output mode of the CS pin to perform interrupt setting, and then perform time synchronization in the interrupt.

[0095] S1013. Based on the synchronization moment, determine a time synchronization request signal, and send the time synchronization request signal to the slave.

[0096] In this step, the synchronization moment and the request information for time synchronization with the slave end are integrated into a time synchronization request signal, and the time synchronization request signal is sent to the slave end, waiting for an affirmative response from the slave end.

[0097] S102. In response to receiving the time synchronization request signal, the slave end uses the second CS pin to capture the timing interrupt. In response to capturing the timing interrupt, when the synchronization moment arrives, the slave interrupt service function is called to interrupt the chip process, and a feedback signal indicating that the time synchronization request has been accepted is sent to the host end.

[0098] In this step, after the slave end receives the time synchronization request signal sent by the host end, first, the second CS pin configured by the SPI interface is controlled to capture the timing interrupt set by the host end; then, in the case where the second CS pin captures the timing interrupt, when it is detected that the time stamp reaches the synchronization moment, a preset slave interrupt service function is called to interrupt the chip process of the slave end; finally, preparations for time synchronization are carried out, and a feedback signal indicating that the time synchronization request has been accepted is sent to the host end.

[0099] Here, the slave interrupt service function refers to the preset interrupt service function at the slave end; among them, the interrupt service function (Interrupt Service Routine, ISR), that is, an interrupt handling program or interrupt service routine, is a special function used to respond to hardware interrupts in an operating system or an embedded system. When an interrupt occurs, the chip end will pause the task being executed in the current process, save the current state, and jump to the corresponding interrupt service function to handle the interrupt event. After processing, the chip end restores the previous state and continues to execute the interrupted task.

[0100] S103. In response to receiving the feedback signal, the host end detects the time stamp. When it is detected that the time stamp has reached the synchronization moment, the host interrupt service function is called to interrupt the chip process. In the state where the chip process is interrupted, a synchronization pulse signal is generated using the first CS pin and the synchronization pulse signal is sent to the slave end.

[0101] In this step, after the host end receives the feedback signal indicating an affirmative response sent by the slave end, it is necessary to detect whether the time stamp of the first local clock of the host end reaches the synchronization moment. When the time stamp has reached the synchronization moment (i.e., the time of the timing interrupt), the host interrupt service function is called to interrupt the chip process; then, in the state where the chip process is interrupted, that is, in the host interrupt service function, a synchronization pulse signal is generated using the first CS pin; finally, the synchronization pulse signal is sent to the slave end.

[0102] Among them, the synchronization pulse signal is presented as a rising edge signal; the host interrupt service function represents the interrupt service function preset on the host side.

[0103] In an embodiment of the present application, the first CS pin is used as a chip select pin during SPI communication and is multiplexed as the pin for generating the synchronization pulse signal during time synchronization.

[0104] S104. In response to receiving the synchronization pulse signal, the slave side uses the slave interrupt service function to determine the sum of the synchronization moment and the pre-calibrated calibration time value as the time synchronization result, and sets the time of the second local clock configured on the slave side according to the time synchronization result, so that the slave side completes the inter-chip time synchronization with the host side.

[0105] In this step, after the slave side receives the synchronization pulse signal sent by the host side, the slave interrupt service function is called to make the slave side enter the state of chip process interruption; then, in the state of chip process interruption, the slave interrupt service function adds the synchronization moment and the pre-calibrated calibration time value, and determines the sum as the time synchronization result; finally, the time of the second local clock configured on the slave side is set according to the obtained time synchronization result.

[0106] Among them, the second local clock configured on the slave side is a high-precision hardware timer locally configured on the slave side.

[0107] Here, since there will be a certain error in the data communication transmission between the host side and the slave side, it is necessary to set a sufficiently high capture interrupt priority and the calibration of the calibration time value to solve this error. The purpose of pre-calibrating the calibration time value is to measure the time required for the host side to initiate time synchronization to the slave side to complete time synchronization, and then calibrate this time into the local clock configured on the slave side.

[0108] In an implementation manner of the present application, during specific implementation, the step of determining the pre-calibrated calibration time value in step S104 may include:

[0109] S1041. The host side determines the agreed calibration moment for calibrating the time error existing between the host side and the slave side, and sends a time calibration request signal including the agreed calibration moment to the slave side.

[0110] In this step, during specific implementation, first, the host side determines the agreed calibration moment for calibrating the time error existing between the host side and the slave side; then, the agreed calibration moment is integrated into the time calibration request signal; finally, the time calibration request signal is sent to the slave side.

[0111] In the embodiment of the present application, the agreed calibration moment is generally selected as the next whole second moment of the current moment. Here, if the time from the current moment to the next whole second moment is short and cannot meet the subsequent instruction execution of the chip communication system, the agreed calibration moment is selected as the next integer second moment after the next whole second moment of the current moment. The agreed calibration moment can also be determined according to the hardware and software development of the chip side.

[0112] S1042. In response to receiving the time calibration request signal, when the agreed calibration moment arrives, the slave end generates a first calibration pulse signal for measuring the time error by using the CLK pin configured by the SPI interface.

[0113] In this step, when the slave end receives the time calibration request signal sent by the master end and detects that the time stamp has reached the agreed calibration moment, a first calibration pulse signal for measuring the time error is generated by using the CLK pin configured by the SPI interface.

[0114] Optionally, in an implementation manner of the present application, in specific implementation, step S104 further includes:

[0115] S1043. In response to the slave end receiving the time calibration request signal, when the agreed calibration moment arrives, the master end generates a second calibration pulse signal by using the first CS pin.

[0116] In this step, when the master end responds to determining that the slave end has received the time calibration request signal sent by the master end and detects that the time stamp has reached the agreed calibration moment, a second calibration pulse signal for measuring the time error is generated by using the first CS pin to measure the time error of the signal transmission between the master end and the slave end.

[0117] Among them, the master end generates a second calibration pulse signal by using the first CS pin of the SPI interface, and the slave end generates a first calibration pulse signal by using the CLK pin configured by the SPI interface; here, the multiplexed pin of the slave end uses the CLK pin in the SPI interface communication.

[0118] S1044. The master end measures the time difference between the first calibration pulse signal and the second calibration pulse signal generated by the master end at the agreed calibration moment by using a preset signal measuring device.

[0119] In this step, a preset signal measuring device is used to measure the time difference between the first calibration pulse signal and the second calibration pulse signal; among them, the signal measuring device may include an oscilloscope, etc.

[0120] S1045. The host repeats measuring the time difference according to a preset number of measurements, determines a calibration time value representing the time error existing between the host and the slave, and inputs the calibration time value into the slave to calibrate the time error of the slave.

[0121] In the embodiments of the present application, repeating the measurement of the time difference according to a preset number of measurements is to determine the errors caused by the execution time of the software code embedded in the chip and the hardware response time during the time synchronization interaction between the host and the slave, so as to calibrate the time error through calibration.

[0122] In this step, in specific implementation, first, repeatedly use a signal measurement device to measure the time difference corresponding to the calibration pulse signals generated by the host and the slave until the number of measurements reaches the preset number of measurements; then, based on the repeatedly measured time differences, calculate a calibration time value representing the time error existing between the host and the slave; finally, input the calibration time value into the software corresponding to the slave to calibrate the second local clock of the slave.

[0123] Optionally, please refer to Figure 4 , Figure 4 is the second flowchart of a time synchronization method based on chip - to - chip communication provided by the embodiments of the present application. As Figure 4 shown, in addition to the time synchronization method based on chip - to - chip communication described in steps S101 to S104, the embodiments of the present application further include steps S105 to S106. Specifically, steps S105 to S106 are used to illustrate whether the host and the slave have completed the time synchronization setting, so as to improve the stability of the chip communication system for time synchronization.

[0124] S105. The host sends a clock synchronization confirmation signal to the slave at a preset time interval.

[0125] In the embodiments of the present application, since both the synchronization moment and the agreed calibration moment are integer seconds, the time interval can generally be set to 2 seconds; further, the host can also determine this time interval according to the time required for the slave to perform time synchronization settings, so as to send a clock synchronization confirmation signal to the slave.

[0126] S106. In response to receiving the clock synchronization confirmation signal, the slave generates a time setting result of the second local clock and returns the time setting result to the host.

[0127] In this step, after the slave device responds to the received clock synchronization confirmation signal, the slave device generates a time setting result of the second local clock according to the result of capturing the timing interrupt and setting the second local clock; then, the time setting result is returned and sent to the host device to complete the time synchronization process in sequence, and wait for the next time synchronization initiated by the host device.

[0128] The time synchronization method based on inter-chip communication provided by the embodiments of the present application establishes a communication connection between the host device and the slave device through the SPI interface under the IPC communication protocol in the chip communication system. The host device determines the synchronization moment and sets a timing interrupt by using the CS pin configured by the SPI interface. The slave device captures the timing interrupt through the CS pin and performs a chip process interrupt. Then, the host device calls an interrupt service function and sends a synchronization pulse signal to the slave device, so that the slave device performs time synchronization based on the synchronization moment and the pre-calibrated calibration time value, realizing the efficient cooperation between the IPC communication technology and time synchronization, achieving high-precision time synchronization and data synchronization between chips, reducing the deployment difficulty and cost of time synchronization based on inter-chip communication, and improving the efficiency and flexibility of time synchronization between chips.

[0129] Refer back to Figure 1 , Figure 1 which is a schematic structural diagram of a chip communication system provided by the embodiments of the present application. As Figure 1 shown in

[0130] The host device 100 is used to determine the synchronization moment for inter-chip time synchronization based on the configured first local clock, control the first CS pin to set a timing interrupt based on the synchronization moment, and send a time synchronization request signal including the synchronization moment to the slave device; in response to receiving a feedback signal, detect the time stamp, and when it is detected that the time stamp has reached the synchronization moment, call the host interrupt service function to interrupt the chip process. In the state of the chip process interrupt, generate a synchronization pulse signal by using the first CS pin and send the synchronization pulse signal to the slave device;

[0131] The slave device 200 is used to respond to receiving the time synchronization request signal, capture the timing interrupt by using the second CS pin, and in response to capturing the timing interrupt, when the synchronization moment arrives, call the slave interrupt service function to interrupt the chip process and send a feedback signal indicating that the time synchronization request has been accepted to the host device; in response to receiving the synchronization pulse signal, use the slave interrupt service function to determine the sum of the synchronization moment and the pre-calibrated calibration time value as the time synchronization result, and set the time of the second local clock configured by the slave device according to the time synchronization result, so that the slave device completes the inter-chip time synchronization with the host device.

[0132] Further, please refer to Figure 5 and Figure 6 , Figure 5 which is one of the schematic structural diagrams of a host end provided by an embodiment of the present application, Figure 6 and is the second schematic structural diagram of a host end provided by an embodiment of the present application. As Figure 5 shown in

[0133] A synchronization request module 110, configured to determine a synchronization moment for performing inter-chip time synchronization based on a configured first local clock, control a first CS pin to set a timing interrupt based on the synchronization moment, and send a time synchronization request signal including the synchronization moment to a slave end;

[0134] A synchronization pulse module 120, configured to detect a timestamp in response to receiving a feedback signal, call a host interrupt service function to interrupt a chip process when it is detected that the timestamp has reached the synchronization moment, and generate a synchronization pulse signal using the first CS pin and send the synchronization pulse signal to the slave end in a state where the chip process is interrupted.

[0135] Further, when the synchronization request module 110 is configured to determine a synchronization moment for performing inter-chip time synchronization based on a configured first local clock, control the first CS pin to set a timing interrupt based on the synchronization moment, and send a time synchronization request signal including the synchronization moment to the slave end, the synchronization request module 110 is configured to:

[0136] The host end calculates the next integer second moment at which time synchronization can be performed based on the configured first local clock, and determines the integer second moment as the synchronization moment for performing inter-chip time synchronization;

[0137] Control the first CS pin to set a timing interrupt according to the synchronization moment, and set the first CS pin to a low-level output mode;

[0138] Based on the synchronization moment, determine a time synchronization request signal, and send the time synchronization request signal to the slave end.

[0139] Further, as Figure 6 shown in

[0140] The host end 100 further includes a first confirmation module 130, and the first confirmation module 130 is configured to:

[0141] Send a clock synchronization confirmation signal to the slave end at a preset time interval. Figure 7 and Figure 8 ,Figure 7 One of the schematic structural diagrams of the slave device provided by the embodiment of the present application Figure 8 Two of the schematic structural diagrams of the slave device provided by the embodiment of the present application. As Figure 7 shown, the slave device 200 includes:

[0142] An interrupt control module 210, configured to respond to receiving the time synchronization request signal, capture the timing interrupt by using the second CS pin, and in response to capturing the timing interrupt, when the synchronization moment arrives, call the slave interrupt service function to interrupt the chip process, and send a feedback signal indicating that the time synchronization request has been accepted to the host device;

[0143] A time synchronization module 220, configured to respond to receiving the synchronization pulse signal, use the slave interrupt service function to determine the sum of the synchronization moment and a pre-calibrated calibration time value as the time synchronization result, and set the time of the second local clock configured by the slave device according to the time synchronization result, so that the slave device completes the inter-chip time synchronization with the host device.

[0144] Further, as Figure 8 shown, the slave device 200 further includes a second confirmation module 230, and the second confirmation module 230 is configured to:

[0145] Respond to receiving the clock synchronization confirmation signal, generate a time setting result of the second local clock, and return and send the time setting result to the host device.

[0146] The chip communication system provided by the embodiment of the present application establishes a communication connection between the host device and the slave device through the SPI interface under the IPC communication protocol in the chip communication system. The host device determines the synchronization moment and sets a timing interrupt by using the CS pin configured by the SPI interface. The slave device captures the timing interrupt through the CS pin and interrupts the chip process. Then, the host device calls the interrupt service function and sends a synchronization pulse signal to the slave device, so that the slave device performs time synchronization based on the synchronization moment and a pre-calibrated calibration time value, realizing the efficient cooperation of the IPC communication technology and time synchronization, achieving high-precision time synchronization and data synchronization between chips, reducing the deployment difficulty and cost of time synchronization based on inter-chip communication, and improving the efficiency and flexibility of time synchronization between chips.

[0147] Please refer to Figure 9 , Figure 9 which is a schematic structural diagram of an electronic device provided by the embodiment of the present application. As Figure 9 shown, the electronic device 900 includes a processor 910, a memory 920, and a bus 930.

[0148] The memory 920 stores machine-readable instructions executable by the processor 910. When the electronic device 900 runs, the processor 910 communicates with the memory 920 via the bus 930. When the machine-readable instructions are executed by the processor 910, they can execute the steps of the time synchronization method based on inter-chip communication in the method embodiments as described above Figure 3 and Figure 4 shown in the method embodiments. For the specific implementation manner, reference may be made to the method embodiments and will not be elaborated herein.

[0149] Embodiments of the present application further provide a computer-readable storage medium. A computer program is stored on the computer-readable storage medium. When the computer program is run by a processor, it can execute the steps of the time synchronization method based on inter-chip communication in the method embodiments as described above Figure 3 and Figure 4 shown in the method embodiments. For the specific implementation manner, reference may be made to the method embodiments and will not be elaborated herein.

[0150] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0151] In several embodiments provided in the present application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there may be other division methods in actual implementation. For another example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some communication interfaces. The indirect couplings or communication connections of the devices or units can be in electrical, mechanical, or other forms.

[0152] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place, or they can be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0153] In addition, in each embodiment of the present application, the functional units can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit.

[0154] When the above-mentioned functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium executable by a processor. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present application. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM), random access memories (RAM), magnetic disks, or optical discs that can store program codes.

[0155] Finally, it should be noted that: the above-mentioned embodiments are only specific implementation manners of the present application, used to illustrate the technical solutions of the present application, rather than limiting it. The protection scope of the present application is not limited thereto. Although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: any person skilled in the art within the technical scope disclosed by the present application can still modify the technical solutions recorded in the foregoing embodiments, or can easily think of changes, or perform equivalent replacements on some of the technical features; and these modifications, changes, or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A time synchronization method based on inter-chip communication, characterized in that: The time synchronization method is applied to a chip communication system, the chip communication system includes a host end and a slave end, the host end and the slave end establish a communication connection under a preset IPC communication protocol through an SPI interface; wherein the host end is connected to a first CS pin configured with the SPI interface; the host end is connected to a second CS pin configured with the SPI interface, and the time synchronization method includes: The host end determines a synchronization moment for inter-chip time synchronization based on a configured first local clock, controls the first CS pin to set a timing interrupt based on the synchronization moment, and sends a time synchronization request signal including the synchronization moment to the slave end; In response to receiving the time synchronization request signal, the slave end uses the second CS pin to capture the timing interrupt, and in response to capturing the timing interrupt, when the synchronization time arrives, calls the slave interrupt service function to interrupt the chip process, and sends a feedback signal to the host end indicating that the time synchronization request has been accepted; The host end detects the timestamp in response to receiving the feedback signal, and when detecting that the timestamp has reached the synchronization moment, calls the host interrupt service function to interrupt the chip process, and in the state of the chip process interruption, generates a synchronization pulse signal using the first CS pin, and sends the synchronization pulse signal to the slave end; In response to receiving the synchronization pulse signal, the slave end uses the slave interrupt service function to determine the sum of the synchronization moment and a pre-calibrated calibration time value as a time synchronization result, and sets the time of the second local clock configured on the slave end according to the time synchronization result, so that the slave end completes the inter-chip time synchronization with the host end.

2. The method according to claim 1, characterized in that The host end determines a synchronization moment for inter-chip time synchronization based on a configured first local clock, controls the first CS pin to set a timing interrupt based on the synchronization moment, and sends a time synchronization request signal including the synchronization moment to the slave end, including: The host side calculates the next integer second moment at which time synchronization can be performed based on the configured first local clock, and determines the integer second moment as the synchronization moment at which time synchronization between chips will be performed; Controlling the first CS pin to set a timing interrupt according to the synchronization time, and setting the first CS pin to a low level output mode; Based on the synchronization moment, a time synchronization request signal is determined, and the time synchronization request signal is sent to the slave end.

3. The method according to claim 1, characterized in that The pre-calibrated calibration time value is determined by the following steps: The host end determines an agreed calibration time for calibrating the time error between the host end and the slave end, and sends a time calibration request signal including the agreed calibration time to the slave end; In response to receiving the time calibration request signal, the slave terminal generates a first calibration pulse signal for measuring the time error using the CLK pin configured by the SPI interface when the agreed calibration time arrives; The host terminal uses a preset signal measuring device to measure the time difference between the first calibration pulse signal and the second calibration pulse signal generated by the host terminal at the agreed calibration time; The host end repeatedly measures the time difference according to a preset number of measurements, determines a calibration time value representing the time error between the host end and the slave end, and inputs the calibration time value into the slave end to calibrate the time error of the slave end.

4. The method according to claim 3, characterized in that The step of determining the pre-calibrated calibration time value also includes: In response to the slave receiving the time calibration request signal, the host generates a second calibration pulse signal using the first CS pin when the agreed calibration time arrives.

5. The method according to claim 1, characterized in that: After the slave end completes inter-chip time synchronization with the host end, the time synchronization method further includes: The host terminal sends a clock synchronization confirmation signal to the slave terminal at a preset time interval; In response to receiving the clock synchronization confirmation signal, the slave generates a time setting result of the second local clock, and returns the time setting result to the host.

6. The method according to claim 1, characterized in that The IPC communication protocol at least includes data frames, frame timing, sending rules, interaction timing and communication control architecture.

7. A chip communication system, characterized in that: The chip communication system comprises: The host side is used to determine the synchronization moment for inter-chip time synchronization based on the configured first local clock, control the first CS pin to set a timing interrupt based on the synchronization moment, and send a time synchronization request signal including the synchronization moment to the slave side; in response to receiving a feedback signal, detect the timestamp, and when it is detected that the timestamp has reached the synchronization moment, call the host interrupt service function to interrupt the chip process, and in the state of the chip process interruption, use the first CS pin to generate a synchronization pulse signal, and send the synchronization pulse signal to the slave side; The slave end is used to respond to receiving the time synchronization request signal, capture the timing interrupt using the second CS pin, and in response to capturing the timing interrupt, when the synchronization moment arrives, call the slave interrupt service function to interrupt the chip process, and send a feedback signal to the host end indicating that the time synchronization request has been accepted; in response to receiving the synchronization pulse signal, use the slave interrupt service function to determine the sum of the synchronization moment and a pre-calibrated calibration time value as the time synchronization result, and set the time of the second local clock configured on the slave end according to the time synchronization result, so that the slave end completes the inter-chip time synchronization with the host end.

8. The system according to claim 7, characterized in that The host side includes: A synchronization request module, used to determine a synchronization moment for inter-chip time synchronization based on a configured first local clock, control a first CS pin to set a timer interrupt based on the synchronization moment, and send a time synchronization request signal including the synchronization moment to a slave end; A synchronization pulse module is used to detect a timestamp in response to receiving a feedback signal. When it is detected that the timestamp has reached the synchronization moment, a host interrupt service function is called to interrupt the chip process. When the chip process is interrupted, a synchronization pulse signal is generated using the first CS pin, and the synchronization pulse signal is sent to the slave end.

9. The system according to claim 7, characterized in that The slave end comprises: an interrupt control module, configured to, in response to receiving the time synchronization request signal, capture the timing interrupt using the second CS pin, and in response to capturing the timing interrupt, call the slave interrupt service function to interrupt the chip process when the synchronization time arrives, and send a feedback signal to the host end indicating that the time synchronization request has been accepted; A time synchronization module is used to respond to receiving the synchronization pulse signal, use the slave interrupt service function to determine the sum of the synchronization moment and a pre-calibrated calibration time value as a time synchronization result, and set the time of the second local clock configured on the slave side according to the time synchronization result, so that the slave side completes the inter-chip time synchronization with the host side.

10. An electronic device, characterized in that: include: A processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the memory communicate through the bus, and the machine-readable instructions are executed by the processor to execute the steps of the time synchronization method based on inter-chip communication as described in any one of claims 1 to 6.

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