Power-off management method and device for multi-core system
Through an independent control system, the processor core in the multi-core system is independently powered down, which solves the problems of complex powered down process and low efficiency in the existing technology, and achieves a more efficient powered down process.
Patent Information
- Application Number
- CN202311816064.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-26
- Publication Date
- 2025-06-27
AI Technical Summary
The power-down process of existing multi-core systems is complex, and the power-down process of each processor core is closely linked, resulting in low power-down efficiency. Once one of the processor cores’ power-down process reports an error, the other processor cores will also be affected and cannot be powered off smoothly.
Through a control system independent of the multi-core system, each processor core in the multi-core system is independently powered down to control it independently, and in response to the processor core's powered down request, determine whether the powered down condition is met, and perform the powered down operation based on the powered down configuration information.
The power-down process is simplified, the power-down efficiency of the processor core is improved, and the power-down failure problem is avoided due to the error in the main core selection.
Smart Images
Figure CN120215664A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of computer technologies, and in particular, to a power-down management method, apparatus, electronic device, and machine-readable storage medium for a multi-core system. Background Art
[0002] A multi-core system adopting a multi-core architecture may include multiple processor cores. The multiple processor cores are woken up for business processing when needed and enter a sleep state when not needed.
[0003] In the existing power-down process, since it is necessary to first select a main core and the main core controls the synchronous power-down of multiple slave cores, it can be seen that the power-down process is complex, and the power-down processes of each processor core are closely related. As long as an error occurs in the power-down process of one processor core, other processor cores will also be affected and cannot be powered down smoothly, resulting in low power-down efficiency of the processor cores. Summary of the Invention
[0004] The present disclosure provides a power-down management method for a multi-core system, where the multi-core system is a system adopting a multi-core architecture; wherein, the multi-core system is connected to a control system; the control system is configured to perform power-down control on each processor core in the multi-core system; the method includes:
[0005] The control system determines whether the processor core satisfies a power-down condition in response to a power-down request sent by a target processor core in the multi-core system;
[0006] If it is determined that the target processor core satisfies the power-down condition, a power-down operation for the target processor core is performed based on the power-down configuration information for the target processor core; wherein, the power-down operation is used to control the power-down of the target processor core.
[0007] Optionally, the method further includes:
[0008] When the target processor core satisfies the power-down condition, a wake-up function for the target processor core is started; wherein, the wake-up function is used to wake up the target processor core when the target processor core is in a power-down state.
[0009] Optionally, determining whether the target processor core satisfies the power-down condition includes:
[0010] Determining whether the target processor core enters the WFI state;
[0011] If the target processor core satisfies the power-down condition, performing a power-down operation for the target processor core based on the power-down configuration information for the target processor core includes:
[0012] If it is determined that the target processor core has entered the WFI state, perform a power-down operation on the target processor core based on the power-down configuration information for the target processor core.
[0013] Optionally, when the processor core has entered the WFI state, the processor core completes the backup of the device configuration information corresponding thereto, and the sleep lock corresponding to the processor core has been released; or,
[0014] The processor core completes the backup of the device configuration information corresponding thereto, and the sleep lock corresponding to the processor core and the sleep lock of the multi-core system have been released; wherein, the sleep lock is used to lock the current state of the processor core when the processor core executes a service task; the device configuration information includes the configuration information of the device used to support the operation of the processor core.
[0015] Optionally, the method further includes:
[0016] Determine whether other processor cores in the multi-core system are in the power-down state;
[0017] If all other processor cores in the multi-core system are in the power-down state, back up the common peripheral configuration information of the multi-core system; wherein, the common peripheral configuration information is used to support multiple cores of the multi-core system to access the shared peripheral resources corresponding to the multi-core system;
[0018] Perform a power-down operation on the multi-core system based on the power-down configuration information for the multi-core system; wherein, the power-down operation is used to power down the multi-core system.
[0019] Optionally, the control system is equipped with a listening function;
[0020] Starting the wake-up function for the target processor core includes:
[0021] Start the listening function for the wake-up source pre-configured corresponding to the target processor core.
[0022] Optionally, the method further includes:
[0023] In response to a wake-up request for the multi-core system, determine a target processor core corresponding to the wake-up request from among the multiple processor cores of the multi-core system;
[0024] Perform a power-on operation on the processor core based on the power-on configuration information for the target processor core; wherein, the power-on operation is used to power on the control of the processor core.
[0025] Optionally, before determining the target processor core corresponding to the wake-up request, the method further includes:
[0026] Determining whether all processor cores in the multi-core system are in a powered-down state;
[0027] If it is determined that all processor cores in the multi-core system are in a powered-down state, based on the power-on configuration information for the multi-core system, perform a power-on operation for the multi-core system; wherein, the power-on operation is used to control the multi-core system to power on.
[0028] Optionally, the method further includes:
[0029] After completing the power-on operation for the multi-core system, load the backed-up common peripheral configuration information corresponding to the multi-core system to restore the common peripheral configuration information of the multi-core system after power-on.
[0030] Optionally, the method further includes:
[0031] After completing the power-on operation for the processor core, perform a reset release on the processor core to trigger the processor core to transition from a reset state to an execution state and restore the device configuration information corresponding to the processor core.
[0032] Optionally, the multi-core system includes a multi-core system based on a real-time operating system.
[0033] The present disclosure further provides a power-down management device for a multi-core system, where the multi-core system is a system adopting a multi-core architecture; wherein, the multi-core system is connected to a control system; the control system is used to perform power-down control on each processor core in the multi-core system; the device includes:
[0034] A determination unit, configured to, in response to a power-down request sent by a target processor core in the multi-core system, determine whether the processor core meets the power-down conditions;
[0035] An execution unit, configured to, if it is determined that the target processor core meets the power-down conditions, based on the power-down configuration information for the target processor core, perform a power-down operation for the target processor core; wherein, the power-down operation is used to control the target processor core to power down.
[0036] The present disclosure further provides an electronic device, including a communication interface, a processor, a memory, and a bus, where the communication interface, the processor, and the memory are interconnected through the bus;
[0037] Machine-readable instructions are stored in the memory, and the processor executes the power-down management method for the multi-core system by invoking the machine-readable instructions.
[0038] The present disclosure also provides a machine-readable storage medium storing machine-readable instructions, which, when invoked and executed by a processor, implement the power-down management method for the multi-core system.
[0039] The technical solution provided by the present disclosure may at least include the following beneficial effects:
[0040] The external system independent of the multi-core system and docked with the multi-core system, that is, the control system, performs power-down control on each processor core in the multi-core system; the control system can respond to the power-down request sent by the target processor core in the multi-core system, determine whether the processor core meets the power-down condition, and can, when determining that the target processor core meets the power-down condition, perform a power-down operation on the target processor core based on the power-down configuration information for the target processor core, where the power-down operation is used to control the target processor core to power down. Thus, there is no need to first select a main core and then have the main core control the synchronous power-down of each slave core, but rather the control system independent of the multi-core system controls the independent power-down of each processor core in the multi-core system, simplifying the power-down process as a whole and improving the power-down efficiency of the processor core. Description of the Drawings
[0041] Figure 1 It is a system architecture diagram of a power-down management method for a multi-core system shown in an exemplary embodiment.
[0042] Figure 2 It is a flowchart of a power-down management method for a multi-core system shown in an exemplary embodiment.
[0043] Figure 3 It is a flowchart of another power-down management method for a multi-core system shown in an exemplary embodiment.
[0044] Figure 4 It is a hardware structure diagram of an electronic device where a power-down management device for a multi-core system is located shown in an exemplary embodiment.
[0045] Figure 5 It is a block diagram of a power-down management device for a multi-core system shown in an exemplary embodiment. Detailed Embodiments
[0046] Exemplary embodiments will be described in detail herein, and examples thereof are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.
[0047] It should be noted that: in other embodiments, the steps of the corresponding methods are not necessarily executed in the order shown and described in the present disclosure. In some other embodiments, the steps included in the method may be more or less than those described in the present disclosure. In addition, a single step described in the present disclosure may be decomposed into multiple steps for description in other embodiments; and multiple steps described in the present disclosure may also be combined into a single step for description in other embodiments.
[0048] SOC (System-on-a-Chip) refers to the technology of integrating multiple hardware components onto a single chip. These hardware components may include a central processing unit (CPU), a graphics processing unit, a memory controller, a peripheral controller, and the like.
[0049] An SOC chip refers to a chip that integrates complete system functions. The chip may include multiple systems such as an AP (Application Processor) system, a processor system, a graphics system, a storage system, and a communication system, and various computing, communication, and control functions are implemented by these multiple systems.
[0050] Among them, the above-mentioned processor system may be a multi-core system adopting a multi-core architecture. The CPU in the multi-core system may include multiple processor cores, and these multiple processor cores will be awakened for business processing when they need to work and will enter the sleep state when they do not need to work.
[0051] Specifically, taking three processor cores as an example, the multiple processor cores may include processor core_1, processor core_2, and processor core_3. When processor core_1 finishes executing the current task and enters the idle state, it can execute the idle task. At this time, processor core_1 can obtain the states of other processor cores from the shared resources and determine whether it is the last processor core to enter the idle task. If processor core_1 is the last one to enter the idle task, it will act as the master core and notify other slave cores to prepare for synchronous power-down. At this time, processor core_2 and processor core_3 will respectively determine whether the sleep lock of the multi-core system is released to determine whether other slave cores meet the sleep conditions. If all slave cores meet the sleep conditions, processor core_2 and processor core_3 can execute the sleep process. After execution, the above-mentioned master core can control the two slave cores to power down synchronously. Then the master core saves the common peripheral configuration and sends a power-down request to the control system connected to the multi-core system. In response to this power-down request, the control system can control the master core to power down and further control the multi-core system to power down.
[0052] In this power-down process, since it is necessary to first select the master core and have the master core control the multiple slave cores to power down synchronously, in this case, each of the multiple slave cores needs to access the shared resources to obtain the state information of other slave cores or the sleep lock information of the multi-core system before entering the sleep process, and based on this, determine that all other slave cores meet the power-down conditions before the master core controls the synchronous power-down. Since this power-down process is complex and the power-down processes of each processor core are closely related, as long as there is an error in the power-down process of one processor core, other processor cores will also be affected and cannot power down smoothly, resulting in low power-down efficiency of the processor cores.
[0053] The following introduces the power-down management method for a multi-core system provided by the present disclosure through specific embodiments in combination with specific application scenarios. This method simplifies the power-down process of the processor cores by having the control system control each processor core in the multi-core system to power down independently.
[0054] In implementation, the above multi-core system can be a system adopting a multi-core architecture. Among them, the multi-core system can be connected to a control system. The control system can be used to control the power-down of each processor core in the multi-core system. The control system can determine whether the processor core meets the power-down conditions in response to the power-down request sent by the target processor core in the multi-core system.
[0055] Further, if it is determined that the target processor core meets the power-down condition, the control system may perform a power-down operation on the target processor core based on the power-down configuration information for the target processor core, where the power-down operation is used to control the power-down of the target processor core.
[0056] Through the above embodiments, an external system independent of the multi-core system and docked with the multi-core system, that is, the control system, can perform power-down control on each processor core in the multi-core system; the control system can respond to a power-down request sent by a target processor core in the multi-core system, determine whether the processor core meets the power-down condition, and can, when it is determined that the target processor core meets the power-down condition, perform a power-down operation on the target processor core based on the power-down configuration information for the target processor core, where the power-down operation is used to control the power-down of the target processor core. Thus, there is no need to first select a master core and then have the master core control the synchronous power-down of each slave core. Instead, the control system independent of the multi-core system controls the independent power-down of each processor core in the multi-core system, which simplifies the power-down process as a whole and improves the power-down efficiency of the processor core.
[0057] The present disclosure will be described below through specific embodiments and in combination with specific application scenarios.
[0058] Please refer to Figure 1 , Figure 1 which is an architectural diagram of a power-down management method for a multi-core system shown in an exemplary embodiment. As Figure 1 shown, the method can be docked by the control system with the multi-core system, and the multi-core system can be a system adopting a multi-core architecture. The multi-core system can include three processor cores, namely: Processor Core_1, Processor Core_2, and Processor Core_3. Each of the three processor cores can send a power-down request to the control system when it needs to sleep after completing a service task; the above control system can receive the power-down request of any target processor core among the three processor cores and perform independent power-down on the target processor core. Specifically, the control system can respond to the power-down request of the target processor core, determine whether the target processor core meets the power-down condition, and if the target processor core meets the power-down condition, perform a power-down operation on the target processor core based on the power-down configuration information for the target processor core; where the power-down operation can be used to control the power-down of the target processor core.
[0059] Please refer to Figure 2 , Figure 2 which is a flowchart of a power-down management method for a multi-core system shown in an exemplary embodiment.
[0060] As Figure 2As shown, the above control system can perform the following steps:
[0061] Step 202, the above control system determines whether the target processor core satisfies the power-down condition in response to a power-down request sent by the target processor core in the above multi-core system.
[0062] The above multi-core system can adopt a multi-core architecture. When any one of the multiple processor cores included in the multi-core system needs to be powered down, it can send a power-down request to the above control system separately, and the control system controls independent power-down.
[0063] For example, the above multi-core system can include three processor cores, namely: Processor Core_1, Processor Core_2, and Processor Core_3. Among them, when Processor Core_1 needs to be powered down, it can send a power-down request to the above control system, and the control system performs independent power-down on this Processor Core_1.
[0064] In an illustrated implementation, the above multi-core system can include a multi-core system based on a real-time operating system.
[0065] A real-time operating system (RTOS, Real-Time Operating System) is an operating system dedicated to real-time applications, mainly used in time-sensitive application scenarios, such as aerospace, automotive, medical equipment, industrial automation and other fields. A real-time operating system usually runs on an embedded system or a real-time system platform, such as an SOC platform, which has a small memory and processing power and meets strict real-time requirements.
[0066] Step 204, if it is determined that the above target processor core satisfies the power-down condition, perform a power-down operation on the above target processor core based on the power-down configuration information for the above target processor core; wherein, the above power-down operation is used to control the above target processor core to power down.
[0067] When the above control system receives a power-down request sent by a target processor core, it needs to first determine that the target processor core satisfies the power-down condition before controlling the target processor core to power down.
[0068] The above control system can also be configured with power-down configuration information for each processor core in the above multi-core system. When it is necessary to power down any one of the processor cores in the multi-core system, a power-down operation for the any one of the processor cores can be performed based on the power-down configuration information corresponding to the any one of the processor cores to power down the any one of the processor cores.
[0069] For example, the above multi-core system may include three processor cores, namely: processor core_1, processor core_2, and processor core_3. Among them, when the control system receives a power-down request sent by the above processor core_1, it can first determine whether the processor core_1 meets the power-down conditions. If the processor core_1 meets the power-down conditions, it can perform a power-down operation for the processor core_1 based on the power-down configuration information for the processor core_1, and this power-down operation is used to control the processor core_1 to power down.
[0070] In this way, it is possible to independently power down each processor core in the multi-core system to avoid mutual influence between the power-down processes of each processor core, thereby simplifying the power-down process as a whole and improving the power-down efficiency of the processor core.
[0071] In an illustrated embodiment, when the above target processor core meets the power-down conditions, the control system can activate the wake-up function for the above target processor core; wherein, the above wake-up function is used to wake up the above target processor core when the above target processor core is in a power-down state.
[0072] The control system can independently power down each processor core in the above multi-core system, or can independently power on each processor core in the above multi-core system.
[0073] The control system can activate the wake-up function for the above target processor core so that when the target processor core is in a power-down state, the target processor core can be woken up.
[0074] Specifically, the control system can activate the wake-up function for the above target processor core when the above target processor core meets the power-down conditions, and then power down the above target processor core; or it can activate the wake-up function for the above target processor core after the power-down of the above target processor core is completed.
[0075] For example, the above multi-core system may include three processor cores, namely: processor core_1, processor core_2, and processor core_3. When the control system receives a power-down request sent by the above processor core_1, it can first determine whether the processor core_1 meets the power-down conditions. If the processor core_1 meets the power-down conditions, it can activate the wake-up function for the processor core_1 to facilitate powering on the processor core_1 in a subsequent power-down state.
[0076] In this way, it is possible to control the target processor core in a power-down state to power on independently.
[0077] Regarding the specific manner of starting the wake-up function of the control system, it can be set according to actual requirements, and the present disclosure does not limit this.
[0078] In an illustrated embodiment, the above control system may be equipped with a listening function; the above control system may start the listening function for a wake-up source pre-configured corresponding to the above target processor core.
[0079] The above control system may be pre-configured with wake-up sources respectively corresponding to each processor core in the above multi-core system. When the control system receives a power-down request sent by a target processor core in the multi-core system and determines that the target processor core meets the power-down condition, it may start the listening function for the wake-up source corresponding to the target processor core.
[0080] For example, the above multi-core system may include three processor cores, namely: processor core_1, processor core_2, and processor core_3. The control system may be pre-configured with a wake-up source_1 corresponding to the processor core_1, a wake-up source_2 corresponding to the processor core_2, and a wake-up source_3 corresponding to the processor core_3; when the control system receives a power-down request sent by the processor core_1 and determines that the target processor core_1 meets the power-down condition, it may start the listening function for the wake-up source_1 of the target processor core.
[0081] In this way, it is possible to timely control the target processor core in the power-down state to perform independent power-on.
[0082] Regarding the above power-down condition, it can be set according to actual requirements, and the present disclosure does not limit this.
[0083] In an illustrated embodiment, the above control system may determine whether the target processor core meets the power-down condition by determining whether the target processor core enters the WFI state; if it is determined that the target processor core enters the WFI state, it may be determined that the target processor core meets the power-down condition, and then the power-down operation for the target processor core may be further executed based on the power-down configuration information for the target processor core.
[0084] Among them, the WFI (Wait for Interrupt) state refers to a low-power standby state, which is often used in the energy-saving mode of embedded systems. In the WFI state, the processor core stops executing business instructions and enters the low-power mode, waiting for an external interrupt to trigger. When an interrupt event occurs, the CPU will immediately wake up from the WFI state and start executing the interrupt handler. After the execution of the interrupt handler is completed, the CPU can continue to enter the WFI state to wait for the next interrupt event. The main function of this WFI state is to reduce the power consumption of the system and extend the battery life of embedded devices. In this disclosure, the processor cores in the multi-core system may be idle for a long time, and at this time, they can enter the WFI state to reduce the power consumption of the system.
[0085] That is to say, if the target processor core enters the WFI state, it indicates that the target processor core is not executing business tasks and is in an idle state, meeting the power-down condition.
[0086] For example, the above multi-core system may include three processor cores, namely: processor core_1, processor core_2, and processor core_3. When the control system receives a power-down request sent by processor core_1, it can determine whether processor core_1 enters the WFI state. If processor core_1 enters the WFI state, it can be determined that processor core_1 meets the power-down condition, and further, based on the power-down configuration information for processor core_1, perform the power-down operation for processor core_1.
[0087] In this way, it is possible to accurately determine whether the processor core meets the power-down condition, and based on the judgment result, determine whether to power down the processor core, improving the accuracy of powering down the processor core.
[0088] In an illustrated embodiment, when the above processor core enters the WFI state, the above processor core completes the backup of the device configuration information corresponding to it, and the sleep lock corresponding to the above processor core has been released; or,
[0089] The above processor core completes the backup of the device configuration information corresponding to it, and the sleep lock corresponding to the above processor core and the sleep lock of the above multi-core system have been released; where the above sleep lock is used to lock the current state of the above processor core when the above processor core executes business tasks; the above device configuration information includes the configuration information of the devices used to support the operation of the processor core.
[0090] Among them, a sleep lock is a mechanism used to synchronize access to shared resources in a multi-threaded or multi-process environment. It is mainly used to prevent race conditions and avoid resource conflicts. In the present disclosure, the sleep lock is used to lock the current execution state of the processor core when the processor core executes a service task. When the sleep lock corresponding to the processor core is released, it indicates that the processor core is not currently in an execution state and can enter the sleep state.
[0091] In practical applications, when the processor core enters the WFI state, it indicates that the processor core is in an idle state and is ready for power-down. This power-down preparation includes backing up the device configuration information corresponding to it and determining that the relevant sleep lock has been released.
[0092] Specifically, if the processor core is not the last processor core in the multi-core system to perform power-down, the processor core needs to back up the device configuration information corresponding to it and only needs to determine that the sleep lock corresponding to the processor core has been released; when the processor core is the last processor core in the multi-core system to perform power-down, the processor core needs to back up the device configuration information corresponding to it and needs to determine that the sleep lock corresponding to the processor core has been released. At the same time, since if the sleep lock corresponding to the multi-core system is not released, it indicates that there are still service tasks to be processed, the processor core cannot perform power-down. Therefore, it is also necessary to determine that the sleep lock corresponding to the multi-core system has been released.
[0093] In this way, it is possible to avoid powering down the processor core when the processor core is in an execution state, and improve the accuracy of powering down the processor core.
[0094] In an illustrated embodiment, the control system can determine whether other processor cores in the multi-core system are in a power-down state; if all other processor cores in the multi-core system are in a power-down state, the control system can back up the common peripheral configuration information of the multi-core system; wherein, the common peripheral configuration information can be used to support multiple cores of the multi-core system to access the shared peripheral resources corresponding to the multi-core system; the control system can perform a power-down operation on the multi-core system based on the power-down configuration information for the multi-core system; wherein, the power-down operation is used to power down the multi-core system.
[0095] The control system can back up the common peripheral configuration information of the multi-core system, which is convenient for subsequent powering up the multi-core system and being able to restore the common peripheral configuration information based on the backed-up common peripheral configuration information to support multiple cores of the multi-core system to access the shared peripheral resources corresponding to the multi-core system.
[0096] When all other processor cores in the above multi-core system are in the powered-down state, the control system can power down the multi-core system. Specifically, the control system can back up the common peripheral configuration information of the multi-core system and then perform a power-down operation on the multi-core system based on the power-down configuration information for the multi-core system; where the above power-down operation can be used to control the multi-core system to power down.
[0097] In one illustrated embodiment, the control system can, in response to a wake-up request for the multi-core system, determine a target processor core corresponding to the wake-up request from among the multiple processor cores of the multi-core system; the control system can perform a power-on operation on the target processor core based on the power-on configuration information for the target processor core; where the above power-on operation is used to control the processor core to power on.
[0098] Where the above wake-up request can be a wake-up interrupt sent by a wake-up source for the multi-core system, and the control system can receive the wake-up interrupt for the multi-core system and, in response to the wake-up interrupt for the multi-core system, determine a target processor core corresponding to the wake-up interrupt from among the multiple processor cores of the multi-core system.
[0099] Further, the control system can perform a power-on operation on the target processor core based on the power-on configuration information for the target processor core; where the above power-on operation is used to control the processor core to power on.
[0100] For example, the above multi-core system can include three processor cores, namely: Processor Core_1, Processor Core_2, and Processor Core_3. The control system can, in response to a wake-up interrupt for the multi-core system, determine that the target processor core corresponding to the wake-up interrupt among the three processor cores of the multi-core system is Processor Core_1; and can perform a power-on operation on Processor Core_1 based on the power-on configuration information for Processor Core_1 to power on Processor Core_1.
[0101] In this way, independent power-on of each processor core can be achieved.
[0102] In one illustrated embodiment, before determining the target processor core corresponding to the wake-up request, the control system can also determine whether all processor cores in the multi-core system are in the powered-down state; if it is determined that all processor cores in the multi-core system are in the powered-down state, perform a power-on operation on the multi-core system based on the power-on configuration information for the multi-core system; where the above power-on operation is used to control the multi-core system to power on.
[0103] Since the multi-core system is also powered down when all processor cores in the multi-core system are in the powered-down state, before powering on a target processor core in the multi-core system, it is necessary to power on the multi-core system first.
[0104] Specifically, the control system can perform a power-on operation on the multi-core system based on the power-on configuration information for the multi-core system to power on the multi-core system.
[0105] In an illustrated embodiment, after completing the power-on operation for the above multi-core system, the backup public peripheral configuration information corresponding to the above multi-core system is loaded to restore the public peripheral configuration information of the multi-core system after the power-on is completed.
[0106] After the control system powers on the multi-core system, it can restore the public peripheral configuration information based on the backup public peripheral configuration information to support multiple cores of the above multi-core system to access the shared peripheral resources corresponding to the multi-core system.
[0107] In this way, it can be ensured that after the above multi-core system is powered on, each processor core in the multi-core system can normally access the shared peripheral resources corresponding to the multi-core system, improving the integrity of the multi-core system.
[0108] After completing the power-on operation for the above target processor core, the target processor core is de-reset to trigger the target processor core to transition from the reset state to the execution state, and the device configuration information corresponding to the target processor core is restored.
[0109] After the control system powers on the above target processor core, the target processor core is de-reset to trigger the above target processor core to transition from the reset state to the execution state, so that the target processor core can execute business tasks. At the same time, to ensure the normal operation of the target processor core, it is necessary to restore the device configuration information corresponding to the target processor core.
[0110] In this way, it can be ensured that after the above target processor core is powered on, the target processor core can operate normally, execute business tasks, and improve the integrity of the power-on of the processor core.
[0111] To enable those skilled in the art to better understand the technical solutions in the embodiments of the present disclosure, the following takes the multi-core system including three processor cores as an example, and combines the Figure 3 flowchart of the power-down management method for the multi-core system as shown to illustrate the embodiments in the present disclosure.
[0112] Please refer to Figure 3 , Figure 3It is a flowchart of another power-down management method for a multi-core system shown in an exemplary embodiment.
[0113] The above multi-core system may include three processor cores, namely: processor core_1, processor core_2, and processor core_3. Among them, when processor core_1 needs to power down, it can send a power-down request to the above control system. The control system can respond to this power-down request and determine whether the above processor core_1 enters the WFI state to determine whether the processor core_1 meets the power-down conditions.
[0114] The control system may be pre-configured with a wake-up source_1 corresponding to the processor core_1, a wake-up source_2 corresponding to the processor core_2, and a wake-up source_3 corresponding to the processor core_3. The above control system is equipped with a monitoring function; if the processor core_1 enters the WFI state, that is, the processor core_1 meets the conditions, the control system can activate the monitoring function for the wake-up source_1.
[0115] The control system can perform a power-down operation for the processor core_1 based on the power-down configuration information for the processor core_1, and this power-down operation is used to control the processor core_1 to power down.
[0116] The control system can also determine whether other processor cores in the above multi-core system are in the power-down state; if all other processor cores in the above multi-core system are in the power-down state, the control system can back up the common peripheral configuration information of the multi-core system and perform a power-down operation for the above multi-core system based on the power-down configuration information for the above multi-core system.
[0117] After the above power-down process is completed, the control system can also receive a wake-up interrupt for the above multi-core system to execute a power-up process for the above multi-core system. It should be noted that before executing the above power-down process, a power-up process for the above multi-core system can also be executed. In this disclosure, there is no necessary order of execution between the power-up process and the power-down process.
[0118] When the control system receives a wake-up interrupt for the above multi-core system, it can respond to the wake-up interrupt for the multi-core system and determine whether all processor cores in the above multi-core system are in the power-down state; if it is determined that all processor cores in the above multi-core system are in the power-down state, a power-up operation for the above multi-core system can be performed based on the power-up configuration information for the above multi-core system; among them, the above power-up operation is used to control the above multi-core system to power up.
[0119] After the control system powers on the multi-core system, it can restore the common peripheral configuration information based on the backed-up common peripheral configuration information to support multiple cores of the multi-core system to access the shared peripheral resources corresponding to the multi-core system.
[0120] Further, the control system can determine a target processor core corresponding to the wake-up interrupt from multiple processor cores of the multi-core system.
[0121] The control system can perform a power-on operation for the target processor core based on the power-on configuration information for the target processor core; wherein, the above power-on operation can be used to control the power-on of the processor core.
[0122] After the control system powers on the above target processor core, it can de-reset the processor core, triggering the target processor core to transition from the reset state to the execution state, so that the target processor core can execute business tasks. At the same time, to ensure the normal operation of the target processor core, it is necessary to restore the device configuration information corresponding to the processor core.
[0123] Corresponding to the embodiment of the power-down management method for a multi-core system, the present disclosure also provides an embodiment of a power-down management device for a multi-core system.
[0124] Please refer to Figure 4 , Figure 4 , which is a hardware structure diagram of an electronic device where a power-down management device for a multi-core system shown in an exemplary embodiment is located. At the hardware level, the device includes a processor 402, an internal bus 404, a network interface 406, a memory 408, and a non-volatile memory 410. Of course, it may also include other hardware required for other services. One or more embodiments of the present disclosure can be implemented in a software manner, for example, the processor 402 reads a corresponding computer program from the non-volatile memory 410 into the memory 408 and then runs it. Of course, in addition to the software implementation manner, one or more embodiments of the present disclosure do not exclude other implementation manners, such as logic devices or a combination of software and hardware, etc. That is, the execution subject of the following processing flow is not limited to each logic unit, and can also be hardware or logic devices.
[0125] Please refer to Figure 5 , Figure 5 , which is a block diagram of a power-down management device for a multi-core system shown in an exemplary embodiment. The power-down management device for a multi-core system can be applied to Figure 4In the electronic device shown, the technical solution of the present disclosure is implemented. Among them, the above multi-core system can be a system adopting a multi-core architecture; among them, the above multi-core system can be connected to a control system; the above control system can be used to perform power-down control on each processor core in the above multi-core system; the above device may include:
[0126] A determination unit 502, configured to, when the control system responds to a power-down request sent by a target processor core in the multi-core system, determine whether the processor core meets the power-down condition;
[0127] An execution unit 504, configured to, if it is determined that the target processor core meets the power-down condition, perform a power-down operation on the target processor core based on the power-down configuration information for the target processor core; wherein, the above power-down operation is used to control the power-down of the target processor core.
[0128] In this embodiment, the above device further includes a startup unit, configured to:
[0129] When the target processor core meets the power-down condition, start the wake-up function for the target processor core; wherein, the above wake-up function is used to wake up the target processor core when the target processor core is in a power-down state.
[0130] In this embodiment, the above determination unit 502 may specifically be configured to:
[0131] Determine whether the target processor core enters the WFI state;
[0132] If the target processor core meets the power-down condition, performing a power-down operation on the target processor core based on the power-down configuration information for the target processor core includes:
[0133] If it is determined that the target processor core enters the WFI state, perform a power-down operation on the target processor core based on the power-down configuration information for the target processor core.
[0134] In this embodiment, when the processor core enters the WFI state, the processor core completes the backup of the device configuration information corresponding to it, and the sleep lock corresponding to the processor core has been released; or,
[0135] The processor core completes the backup of the device configuration information corresponding to it, and the sleep lock corresponding to the processor core and the sleep lock of the multi-core system have been released; wherein, the above sleep lock is used to lock the current state of the processor core when the processor core executes a service task; the above device configuration information includes the configuration information of the device used to support the operation of the processor core.
[0136] In this embodiment, the above-mentioned determination unit 502 may further be configured to:
[0137] Determine whether other processor cores in the above multi-core system are in a powered-down state;
[0138] If all other processor cores in the above multi-core system are in a powered-down state, back up the common peripheral configuration information of the above multi-core system; wherein, the above common peripheral configuration information is used to support multiple cores of the above multi-core system to access shared peripheral resources corresponding to the above multi-core system;
[0139] Execute a power-down operation for the above multi-core system based on the power-down configuration information for the above multi-core system; wherein, the above power-down operation is used to power down the above multi-core system.
[0140] In this embodiment, the above control system may be equipped with a monitoring function;
[0141] The above start-up unit may further be configured to:
[0142] Start the monitoring function for a pre-configured wake-up source corresponding to the above target processor core.
[0143] In this embodiment, the above execution unit 504 may further be configured to:
[0144] In response to a wake-up request for the above multi-core system, determine a target processor core corresponding to the above wake-up request from among the multiple processor cores of the above multi-core system;
[0145] Execute a power-on operation for the above target processor core based on the power-on configuration information for the above target processor core; wherein, the above power-on operation is used to power on the above target processor core.
[0146] In this embodiment, before determining the target processor core corresponding to the above wake-up request, the above determination unit 502 may further be configured to:
[0147] Determine whether all processor cores in the above multi-core system are in a powered-down state;
[0148] If it is determined that all processor cores in the above multi-core system are in a powered-down state, execute a power-on operation for the above multi-core system based on the power-on configuration information for the above multi-core system; wherein, the above power-on operation is used to power on the above multi-core system.
[0149] In this embodiment, the above device may further include a recovery unit, configured to:
[0150] After completing the power-on operation for the above multi-core system, load the backed-up common peripheral configuration information corresponding to the above multi-core system, and restore the common peripheral configuration information of the above multi-core system after the power-on is completed.
[0151] In this embodiment, the above restoration unit can also be used for:
[0152] After completing the power-on operation for the above target processor core, perform a reset release on the above target processor core to trigger the above target processor core to transition from the reset state to the execution state, and restore the device configuration information corresponding to the above target processor core.
[0153] In this embodiment, the above multi-core system can include a multi-core system based on a real-time operating system.
[0154] The specific implementation process of the functions and roles of each unit in the device can be specifically referred to in the implementation process of the corresponding steps in the method, which will not be elaborated here.
[0155] For the device embodiment, since it basically corresponds to the method embodiment, the relevant parts can be referred to the partial description of the method embodiment. The device embodiments described above are only illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the present disclosure. Those of ordinary skill in the art can understand and implement it without creative work.
[0156] The system, device or unit illustrated in the embodiment can be specifically implemented by a computer chip or entity, or by a product with certain functions. A typical implementation device is a computer, and the specific form of the computer can be a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email transceiver device, a game console, a tablet computer, a wearable device, or a combination of any several of these devices.
[0157] In a typical configuration, a computer includes one or more processors (CPUs), an input / output interface, a network interface, and a memory.
[0158] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of, for example, read-only memory (ROM) or flash memory (flash RAM). The memory is an example of a computer-readable medium.
[0159] A computer-readable medium includes both permanent and non-permanent, removable and non-removable media that can store information by any method or technology. The information can be computer-readable instructions, data structures, program units, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassette tapes, disk storage, quantum memory, graphene-based storage media or other magnetic storage devices, or any other non-transitory medium that can store information accessible by a computing device. As defined herein, a computer-readable medium does not include transitory computer-readable media such as modulated data signals and carrier waves.
[0160] It should also be noted that the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, such that a process, method, article or apparatus comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or apparatus. Without further limitation, an element defined by the statement "comprising a..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising the element.
[0161] The specific embodiments of the present disclosure have been described. Other embodiments are within the scope of the appended claims. In some cases, the acts or steps recited in the claims can be performed in a different order than in the embodiments and still achieve the desired result. Additionally, the processes depicted in the figures do not necessarily require the particular order or sequential order shown to achieve the desired result. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.
[0162] The terms used in one or more embodiments of the present disclosure are for the purpose of describing particular embodiments only and are not intended to limit one or more embodiments of the present disclosure. The singular forms "a", "the", and "that" used in one or more embodiments of the present disclosure and the appended claims are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
[0163] It should be understood that although the terms first, second, third, etc. may be used in one or more embodiments of the present disclosure to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of one or more embodiments of the present disclosure, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "when" or "while" or "in response to determining".
[0164] The above are only the preferred embodiments of one or more embodiments of the present disclosure, and are not intended to limit one or more embodiments of the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of one or more embodiments of the present disclosure shall be included within the scope of protection of one or more embodiments of the present disclosure.
[0165] The user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present disclosure are all information and data that have been authorized by the user or fully authorized by all parties. The collection, use, and processing of relevant data need to comply with the relevant laws, regulations, and standards of the relevant countries and regions, and corresponding operation entrances are provided for users to choose to authorize or reject.
Claims
1. A power-down management method for a multi-core system, characterized in that The multi-core system is a system adopting a multi-core architecture; wherein, the multi-core system is connected to a control system; the control system is used for performing power-down control on each processor core in the multi-core system; the method includes: The control system determines whether the processor core meets the power-down condition in response to a power-down request sent by a target processor core in the multi-core system; If it is determined that the target processor core meets the power-down condition, based on the power-down configuration information for the target processor core, perform a power-down operation on the target processor core; wherein, the power-down operation is used to control the target processor core to power down.
2. The method according to claim 1, characterized in that, The method further includes: When the target processor core meets the power-down condition, start the wake-up function for the target processor core; wherein, the wake-up function is used to wake up the target processor core when the target processor core is in a power-down state.
3. The method according to claim 1, characterized in that, Determining whether the target processor core meets the power-down condition includes: Determining whether the target processor core enters the WFI state; If the target processor core meets the power-down condition, based on the power-down configuration information for the target processor core, performing a power-down operation on the target processor core includes: If it is determined that the target processor core enters the WFI state, based on the power-down configuration information for the target processor core, perform a power-down operation on the target processor core.
4. The method according to claim 3, wherein When the processor core enters the WFI state, the processor core completes the backup of the device configuration information corresponding to it, and the sleep lock corresponding to the processor core has been released; Or, The processor core completes the backup of the device configuration information corresponding to it, and the sleep lock corresponding to the processor core and the sleep lock of the multi-core system have been released; wherein, the sleep lock is used to lock the current state of the processor core when the processor core executes a business task; The device configuration information includes the configuration information of the device used to support the operation of the processor core.
5. The method according to claim 1, characterized in that The method further includes: Determine whether other processor cores in the multi-core system are in a power-down state; If all other processor cores in the multi-core system are in a power-down state, back up the common peripheral configuration information of the multi-core system; wherein, the common peripheral configuration information is used to support multiple cores of the multi-core system to access the shared peripheral resources corresponding to the multi-core system; Based on the power-down configuration information for the multi-core system, perform a power-down operation on the multi-core system; wherein, the power-down operation is used to power down the multi-core system.
6. The method according to claim 1, wherein The control system is equipped with a listening function; Starting the wake-up function for the target processor core includes: Start the listening function for the wake-up source pre-configured corresponding to the target processor core.
7. The method according to any one of claims 1 to 6, characterized in that, The method further includes: In response to a wake-up request for the multi-core system, determine the target processor core corresponding to the wake-up request from multiple processor cores of the multi-core system; Perform a power-on operation for the processor core based on the power-on configuration information for the target processor core; wherein, the power-on operation is used to power on the processor core.
8. The method according to claim 7, characterized in that Before determining the target processor core corresponding to the wake-up request, the method further includes: Determine whether all processor cores in the multi-core system are in a powered-down state; If it is determined that all processor cores in the multi-core system are in a powered-down state, perform a power-on operation for the multi-core system based on the power-on configuration information for the multi-core system; wherein, the power-on operation is used to power on the multi-core system.
9. The method according to claim 8, wherein The method further includes: After completing the power-on operation for the multi-core system, load the backed-up common peripheral configuration information corresponding to the multi-core system, and restore the common peripheral configuration information of the multi-core system after power-on.
10. The method according to claim 8, characterized in that, The method further includes: After completing the power-on operation for the target processor core, perform a reset release on the target processor core to trigger the target processor core to transition from the reset state to the execution state, and restore the device configuration information corresponding to the target processor core.
11. The method according to claim 1, characterized in that, The multi-core system includes a multi-core system based on a real-time operating system.
12. A power-down management device for a multi-core system, characterized in that, The multi-core system is a system adopting a multi-core architecture; wherein, the multi-core system is connected to a control system; the control system is used to perform a power-down control on each processor core in the multi-core system; the device includes: A determination unit, configured to, in response to a power-down request sent by a target processor core in the multi-core system, determine whether the processor core meets the power-down conditions; An execution unit, configured to, if it is determined that the target processor core meets the power-down conditions, perform a power-down operation for the target processor core based on the power-down configuration information for the target processor core; wherein, the power-down operation is used to power down the target processor core.
13. A user equipment, characterized in that, Includes: A processor; A memory for storing processor-executable instructions; Wherein, the processor is used to implement the method according to any one of claims 1 to 11.
14. A machine-readable storage medium, characterized in that, The machine-readable storage medium stores machine-readable instructions, and when the machine-readable instructions are called and executed by a processor, the method according to any one of claims 1 to 11 is implemented.