Synchronization method, synchronization device, electronic device and storage medium

Abstract

Embodiments of the present disclosure provide a synchronization method, a synchronization device, an electronic device, and a storage medium. The synchronization method includes: allocating a synchronization channel to a first instruction for a thread bundle including multiple threads; synchronizing the first instruction and the second instruction based on the synchronization channel, wherein there is a dependency relationship between the first instruction and the second instruction, the thread bundle corresponds to multiple synchronization channel groups, each synchronization channel group includes at least one synchronization channel, and different synchronization channel groups correspond to different types of instructions. The synchronization method uses a synchronization channel mechanism based on instruction type to synchronize instructions within the thread bundle, effectively decoupling the synchronization channels used by different types of instructions, expanding the number of synchronization channels, thereby improving the thread bundle's processing capacity for workloads, and being able to effectively cope with the challenges brought about by the increasing workload in the thread bundle.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a synchronization method, a synchronization device, an electronic device, and a storage medium. Background Art

[0002] Operand dependency refers to the situation in computer architecture, particularly in the context of instruction-level parallelism and pipelining, where the operands (i.e., input data) of an instruction depend on the execution results of previous instructions. Handling operand dependencies is crucial for correct program execution and significantly impacts program performance and compiler scheduling strategies. Optimizing operand dependency handling can improve program execution efficiency and help the compiler develop more effective instruction scheduling strategies, thereby maximizing processor resource utilization, reducing latency, and improving throughput. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a synchronization method, comprising: allocating a synchronization channel to a first instruction for a thread bundle including multiple threads; synchronizing the first instruction and a second instruction based on the synchronization channel, wherein a dependency relationship exists between the first instruction and the second instruction, the thread bundle corresponds to multiple synchronization channel groups, each synchronization channel group includes at least one synchronization channel, and different synchronization channel groups correspond to different types of instructions.

[0004] For example, in the synchronization method provided in at least one embodiment of the present disclosure, allocating a synchronization channel to the first instruction includes: determining a synchronization channel group corresponding to the first instruction based on the type of the first instruction; and allocating a synchronization channel in the synchronization channel group to the first instruction.

[0005] For example, in the synchronization method provided in at least one embodiment of the present disclosure, the first instruction includes a synchronization channel identifier, and allocating a synchronization channel in the synchronization channel group to the first instruction includes: according to the synchronization channel identifier, allocating a synchronization channel in the synchronization channel group corresponding to the synchronization channel identifier to the first instruction.

[0006] For example, in the synchronization method provided in at least one embodiment of the present disclosure, each synchronization channel includes at least one synchronization counter, and the synchronization counter is used to count based on the instruction execution status.

[0007] For example, in the synchronization method provided in at least one embodiment of the present disclosure, for a synchronization channel including a synchronization counter, synchronizing the first instruction and the second instruction based on the synchronization channel includes: increasing the count of the synchronization counter in response to issuing the first instruction; decreasing the count of the synchronization counter in response to completion of the task corresponding to the first instruction; waiting for the synchronization counter to be cleared, and, in response to the synchronization counter being cleared, allowing the second instruction to start execution.

[0008] For example, in the synchronization method provided in at least one embodiment of the present disclosure, for a synchronization channel including multiple synchronization counters, the synchronization of the first instruction and the second instruction based on the synchronization channel includes: in response to issuing the first instruction, increasing the count of the current synchronization counter; in response to the count of the current synchronization counter reaching a preset value, jumping to the next synchronization counter as the current synchronization counter for subsequent counting; in response to the completion of the task corresponding to the first instruction, reducing the count of the corresponding synchronization counter; waiting for a preset number of synchronization counters to be cleared or waiting for all counted synchronization counters to be cleared, and, in response to clearing, allowing the second instruction to start execution.

[0009] For example, in the synchronization method provided in at least one embodiment of the present disclosure, the instruction types corresponding to the same synchronization channel group are the same.

[0010] For example, in the synchronization method provided in at least one embodiment of the present disclosure, the first instruction is a variable-length instruction.

[0011] For example, in the synchronization method provided in at least one embodiment of the present disclosure, the first instruction includes a data transfer instruction, a general matrix multiplication instruction, a transcendental function instruction, or a cache operation instruction.

[0012] For example, in the synchronization method provided in at least one embodiment of the present disclosure, the synchronization method is executed by a warp instruction scheduler.

[0013] At least one embodiment of the present disclosure provides a synchronization device, including: an allocation module, configured to allocate a synchronization channel to a first instruction for a thread bundle including multiple threads; a synchronization module, configured to synchronize the first instruction and the second instruction based on the synchronization channel, wherein there is a dependency relationship between the first instruction and the second instruction, the thread bundle corresponds to multiple synchronization channel groups, each synchronization channel group includes at least one synchronization channel, and different synchronization channel groups correspond to different types of instructions.

[0014] At least one embodiment of the present disclosure provides an electronic device, comprising: at least one processor; at least one memory storing one or more computer program modules; wherein the one or more computer program modules are configured to be executed by the at least one processor to execute instructions for implementing the synchronization method described in any embodiment of the present disclosure.

[0015] At least one embodiment of the present disclosure provides a non-transitory computer-readable storage medium having computer-readable instructions stored thereon, wherein the computer-readable instructions, when executed by at least one processor, perform the synchronization method described in any embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0017] Figure 1A A schematic block diagram of a streaming multiprocessor provided for at least one embodiment of the present disclosure.

[0018] Figure 1B A flowchart of a synchronization method provided in at least one embodiment of the present disclosure.

[0019] Figure 1C A flowchart of a synchronization method provided in at least one embodiment of the present disclosure.

[0020] Figure 1D A flowchart of a synchronization method provided in at least one embodiment of the present disclosure.

[0021] Figure 2 An exemplary schematic diagram of a synchronization method provided for at least one embodiment of the present disclosure;

[0022] Figure 3 An exemplary schematic diagram of a synchronization method provided for at least one embodiment of the present disclosure;

[0023] Figure 4 A schematic block diagram of a synchronization device provided in at least one embodiment of the present disclosure;

[0024] Figure 5 A schematic block diagram of an electronic device provided in at least one embodiment of the present disclosure;

[0025] Figure 6 A schematic block diagram of another electronic device provided for at least one embodiment of the present disclosure; and

[0026] Figure 7 A schematic block diagram of a non-transitory computer-readable storage medium is provided for at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0028] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0029] The present disclosure is described below using several specific embodiments. To maintain clarity and conciseness in the following description of the embodiments of the present disclosure, detailed descriptions of known functions and components may be omitted. When any component of an embodiment of the present disclosure appears in more than one drawing, that component is represented by the same or similar reference numeral in each drawing.

[0030] Operand dependency refers to the situation in computer architecture, particularly in the context of instruction-level parallelism and pipelining, where the operands (i.e., input data) of an instruction depend on the execution results of previous instructions. Handling operand dependencies is crucial for correct program execution and significantly impacts program performance and compiler scheduling strategies. Optimizing operand dependency handling can improve program execution efficiency and help the compiler develop more effective instruction scheduling strategies, thereby maximizing processor resource utilization, reducing latency, and improving throughput.

[0031] Based on the determinism of their completion time, instructions can be categorized as fixed-length and variable-length instructions. For fixed-length instructions, such as arithmetic operations (addition, subtraction, multiplication, and division), the number of cycles required to execute is fixed. The number of cycles required for each instruction to complete can be determined at compile time, enabling the compiler to efficiently schedule instructions. For example, if an addition instruction is known to complete in three cycles, and the result of the addition instruction is dependent on subsequent instructions, the compiler can schedule the subsequent instructions to begin executing at least in the fourth cycle. For variable-length instructions, such as memory load instructions, the completion time is affected by various factors, including but not limited to bus contention, cache hit rates, and main memory access latency. Therefore, the actual completion time of such instructions cannot be accurately determined at compile time. Due to this uncertainty, the compiler struggles to directly schedule subsequent instructions with operand dependencies. With increasing demand for complex computations, variable-length instructions are increasingly used in scenarios such as memory reads and writes, general matrix multiplication (GEMM), transcendental functions (such as square, root, and trigonometric functions), and cache operations.

[0032] When using accelerators such as graphics processing units (GPUs) or general-purpose graphics processing units (GPGPUs) for high-performance parallel computing, a large number of threads is employed to achieve high concurrency. These threads are grouped into warps, each consisting of a fixed number (or less), for example, 32 threads. These threads execute the same instructions using a single instruction multiple thread (SIMT) approach, processing different data. Within a warp, each thread can share some register resources with other threads, while also having independent register resources for loading or computing different data. Warps are scheduled and allocated within each compute unit so that they can be run by the unit's multiple cores. Depending on the number of cores in the unit, multiple warps within a thread block can execute simultaneously or in a time-sharing manner. Direct data exchange between warps is not supported, but data exchange and synchronization can be achieved through the use of shared memory.

[0033] The core concept of traditional GPU programming is to achieve high-throughput computing through a large number of concurrently executing threads and warps. When one warp is in a waiting state, other warps can continue executing, thus masking latency through thread scheduling and improving operational efficiency. In recent years, with the growing demand for artificial intelligence (AI) and large-scale model processing, such as those involving complex operations like large-scale matrix multiplication, the tasks required of a single warp have become more complex and intensive, making it difficult to mask latency by relying on a large number of warps as in traditional approaches. Therefore, current GPU programming models tend to enable fewer warps. For example, if a compute unit can theoretically support up to 16 active warps, current GPU programming models may choose to enable only three warps. These programming model adjustments significantly increase the workload of a single warp. Faced with this large workload, the growing number of variable-length instructions, and the development of double and triple buffering technologies, optimizing internal warp synchronization mechanisms has become a pressing issue.

[0034] At least one embodiment of the present disclosure provides a synchronization method, which includes: allocating a synchronization channel to a first instruction for a thread bundle including multiple threads; synchronizing the first instruction and the second instruction based on the synchronization channel, wherein there is a dependency relationship between the first instruction and the second instruction, the thread bundle corresponds to multiple synchronization channel groups, each synchronization channel group includes at least one synchronization channel, and different synchronization channel groups correspond to different types of instructions.

[0035] The synchronization method provided by at least one embodiment of the present disclosure uses a synchronization channel mechanism based on instruction type to achieve synchronization of instructions within a thread bundle, effectively decoupling the synchronization channels used by different types of instructions, expanding the number of synchronization channels, thereby improving the thread bundle's processing capability for workloads, and effectively coping with the challenges brought about by the increasing workload in the thread bundle.

[0036] For example, the synchronization method provided in at least one embodiment of the present disclosure may be applied to a processor, including a graphics processor or a general-purpose graphics processor. Of course, the embodiments of the present disclosure are not limited thereto, and the processor may also be any other type of processor.

[0037] Figure 1AThis is a schematic block diagram of a streaming multiprocessor (SM) provided in at least one embodiment of the present disclosure. Each streaming multiprocessor 10 can execute multiple thread warps simultaneously. The execution of different thread warps can be independent or sequential. In some examples, the synchronization method provided in at least one embodiment of the present disclosure can be applied to Figure 1A Streaming multiprocessor 10 is shown.

[0038] like Figure 1A As shown, the streaming multiprocessor 10 includes an instruction cache 11 for storing multiple instructions for the kernel. The streaming multiprocessor 10 also includes a warp instruction scheduler 12, which extracts a series of instructions for each warp and stores them in the instruction cache 11. It then retrieves the instructions to be executed from the instruction cache 11 for each warp based on the program counter. Each warp has an independent program counter (PC) register that records the location (i.e., the address) of the instruction currently being executed. Whenever an instruction is extracted from the instruction cache for a warp, the corresponding program counter is incremented by one. The warp instruction scheduler 12 sends the instructions to the arithmetic logic unit (ALU) 13, the special function unit (SFU) 14, or the load store unit (LSU) 15 for execution at the appropriate time. These instructions are defined in the instruction set architecture (ISA) of a particular computing system.

[0039] The arithmetic logic unit 13 can perform a variety of operations, such as integer and floating-point addition and multiplication, comparison operations, Boolean operations, and bit shifts. During execution, the arithmetic logic unit 13 can read data from a specified location (also called the source address) in the general-purpose register 16 (GPR) and write back the execution result to a specified location (also called the destination address) in the GPR 16. The special function unit 14 can perform various mathematical operations (such as reciprocal, square root, trigonometric functions, etc.). The load / store unit 15 can execute load and store instructions and is responsible for handling memory load and store operations.

[0040] The stream multiprocessor 10 also includes barrier registers 17 (Barriers Register), which can be used to allow software to synchronize the execution of different warps, and resource registers 18 (Resource-per-warp Register), which can be used to allow software to dynamically configure the space range of general registers 16 that can be used by each warp during execution. It should be noted that Figure 1A The streaming multiprocessor shown is only an example, and persons skilled in the art will appreciate that the streaming multiprocessor may include more or fewer components. For example, the streaming multiprocessor may also include shared memory, a Level 1 cache, and other components.

[0041] For example, the synchronization method provided by at least one embodiment of the present disclosure can be performed by Figure 1A The warp instruction scheduler 12 is shown executing.

[0042] Figure 1B A flowchart of a synchronization method provided in at least one embodiment of the present disclosure.

[0043] For example, Figure 1B As shown, the synchronization method provided by at least one embodiment of the present disclosure includes the following steps S101-S102.

[0044] Step S101: allocating a synchronization channel to a first instruction for a warp including multiple threads.

[0045] For example, in step S101, a first instruction is executed by a thread in a warp. For example, the first instruction may be an instruction that needs to be synchronized, such as an instruction that has operand dependencies with other instructions. For example, instructions that need to be synchronized in the instruction stream of the warp may be identified based on the instruction type, and a synchronization channel may be allocated to the instruction. For example, the synchronization channel may be located at Figure 1A The barrier register 17 is shown.

[0046] For example, the first instruction may be a variable-length instruction, and the definition of the variable-length instruction has been introduced above and will not be repeated here. For example, variable-length instructions include, but are not limited to, data transfer instructions, general matrix multiplication instructions, transcendental function instructions, or cache operation instructions. For example, data transfer instructions may include load instructions and store instructions for reading and writing memory. For example, general matrix multiplication instructions include, but are not limited to, load instructions and store instructions required when performing general matrix multiplication calculations, as well as calculation instructions when performing general matrix multiplication, such as Fused Multiply Add (FMA) instructions. For example, transcendental function instructions may be instructions for calculating special functions such as square functions, root functions, trigonometric functions, etc. Transcendental function instructions may be instructions such as Figure 1AThe special function unit 14 shown in FIG. For example, cache operation instructions may include a flush instruction, an ack instruction, an invalidate instruction, a fence instruction, etc. Depending on the actual situation, variable-length instructions may also include more instructions. The above are only some examples and are not limited in the present embodiment.

[0047] Step S102: Synchronize the first instruction and the second instruction based on the synchronization channel, wherein there is a dependency relationship between the first instruction and the second instruction, the thread warp corresponds to multiple synchronization channel groups, each synchronization channel group includes at least one synchronization channel, and different synchronization channel groups correspond to different types of instructions.

[0048] For example, in step S102, each warp has multiple corresponding synchronization channel groups. These synchronization channel groups are configured to achieve synchronization within the warp. GPU hardware can maintain multiple synchronization channel groups for each warp. Different synchronization channel groups can include different numbers of synchronization channels. Furthermore, different synchronization channel groups correspond to different types of instructions, while the same synchronization channel group corresponds to the same instruction type.

[0049] For example, instructions can be divided into different types based on their functions. In some examples, instruction types can be classified into data transfer instructions, general matrix multiplication instructions, transcendental function instructions, cache operation instructions, etc. In some examples, the above instruction types can also be further divided. For example, cache operation instructions can be divided into more fine-grained instruction types, such as flush instructions, response instructions, invalidation instructions, fence instructions, etc. The division method of instruction types can be set according to actual needs and is not limited in the embodiments of the present disclosure.

[0050] For example, the number of synchronization channels in the synchronization channel group corresponding to a certain type of instruction can be determined based on the usage frequency of the instruction. The number of synchronization channels in different synchronization channel groups can be determined based on actual task requirements, and the embodiments of the present disclosure do not limit this.

[0051] For example, in step S102, there is an operand dependency relationship between the first instruction and the second instruction, that is, the operand of the second instruction depends on the execution result of the first instruction. The first instruction is also called a producer instruction, and the second instruction is also called a consumer instruction. The consumer instruction uses the data generated by the producer instruction to complete its operation. Based on the synchronization channel assigned to the first instruction, it is possible to determine when the task corresponding to the first instruction is completed, and execute the second instruction in a timely manner, thereby achieving synchronization between the first instruction and the second instruction. For example, if the first instruction is a load instruction and 100 items of data need to be loaded, the same synchronization channel can be assigned to the 100 load instructions. The second instruction is an arithmetic operation instruction and needs to be calculated based on the 100 items of data. Based on the synchronization channel assigned to the load instruction, it is possible to determine when the 100 items of data are loaded, and then execute the arithmetic operation instruction to calculate them, thereby achieving synchronization between the load instruction and the arithmetic operation instruction.

[0052] In some examples, the first instruction and the second instruction can both be variable-length instructions, and the operand of the second instruction depends on the execution result of the first instruction, and the operand of the third instruction depends on the execution result of the second instruction. In this case, different synchronization channels can be allocated to the first instruction and the second instruction, respectively. The synchronization of the first instruction and the second instruction can be achieved based on the synchronization channel allocated to the first instruction, and the synchronization of the second instruction and the third instruction can be achieved based on the synchronization channel allocated to the second instruction. By analogy, the synchronization of more instructions can also be achieved, and the embodiments of the present disclosure are not limited to this.

[0053] The synchronization method provided by at least one embodiment of the present disclosure uses a synchronization channel mechanism based on instruction type to synchronize instructions within a warp, effectively decoupling synchronization channels used by instructions of different types, as will be specifically described in the following examples.

[0054] For example, in some traditional solutions, a fixed number of synchronization channels (e.g., M, where M is a positive integer) can be set for each warp. This solution forces different types of instructions to contend for these M synchronization channels for instruction synchronization. Assuming three synchronization channels are set for each warp, different types of instructions will contend for these three synchronization channels. If the three synchronization channels are already occupied by three groups of data transfer instructions, other data transfer instructions or other types of instructions (such as transcendental function instructions) must wait for one of the data transfer instructions to complete its task and release the occupied synchronization channel before they can acquire that synchronization channel for subsequent processing.

[0055] In the synchronization method provided in the above-mentioned embodiment of the present disclosure, different types of instructions use different synchronization channels. For example, the synchronization channel group corresponding to the data transmission instruction (referred to as the first synchronization channel group) includes three synchronization channels, and the synchronization channel group corresponding to the transcendental function instruction (referred to as the second synchronization channel group) includes one synchronization channel. At this time, if the three groups of data transmission instructions occupy the three synchronization channels of the first synchronization channel group respectively, it will not have any impact on other types of instructions. For example, the transcendental function instruction will use the synchronization channel of the second synchronization channel group, and there is no need to wait for the synchronization channel of the first synchronization channel group to be unoccupied. Compared with the solution of setting a fixed number of synchronization channels for each thread bundle, the synchronization method provided in the embodiment of the present disclosure effectively realizes the decoupling of the synchronization channels used by different types of instructions, expands the number of synchronization channels, thereby improving the thread bundle's processing capacity for workload, and can effectively cope with the challenges brought by the increasing workload in the thread bundle.

[0056] Figure 1C A flowchart of a synchronization method provided in at least one embodiment of the present disclosure.

[0057] For example, Figure 1C As shown, in the synchronization method provided by at least one embodiment of the present disclosure, an example of the above-mentioned step S101 may include the following steps S201 to S202.

[0058] Step S201: Determine a synchronization channel group corresponding to the first instruction based on the type of the first instruction.

[0059] Step S202: Allocate a synchronous channel in the synchronous channel group to the first instruction.

[0060] In the synchronization method provided in at least one embodiment of the present disclosure, the first instruction includes a synchronization channel identifier, and an example of the above-mentioned step S202 may include the following step S2021.

[0061] Step S2021: According to the synchronization channel identifier, a synchronization channel in the synchronization channel group corresponding to the synchronization channel identifier is allocated to the first instruction.

[0062] For example, instructions typically include information such as an opcode field and an operand field. In embodiments of the present disclosure, instructions also include a synchronization channel identifier. For example, if the synchronization channel group corresponding to a first instruction includes P synchronization channels, the synchronization channel identifier will occupy P bits of the encoding position in the first instruction.

[0063] The width of a GPU instruction set is typically 32, 64, or 128 bits. This fixed width means that the number of bits available for each instruction is limited, so the required logic must be expressed as efficiently as possible within this limited number of bits. This means that the number of bits used to identify synchronization channels in instructions cannot be increased indefinitely, and it is necessary to add more synchronization channels without increasing the number of bits.

[0064] For example, in the aforementioned scheme of setting a fixed number of synchronization channels for each thread warp, only P synchronization channels can be identified using the P-bit encoding bits in the instruction. If the number of synchronization channels needs to be expanded, one bit needs to be added to the instruction for each additional synchronization channel to identify the synchronization channel.

[0065] In the above-described embodiments of the present disclosure, within an instruction, the instruction type can be determined based on the opcode field, thereby determining the corresponding synchronization channel group, and the corresponding synchronization channel can be determined based on the synchronization channel identifier. Therefore, under the same circumstances where P bits of coding bits are used as synchronization channel identifiers, the synchronization method provided in the embodiments of the present disclosure can provide up to G×P synchronization channels, where G is the number of synchronization channel groups corresponding to the current thread warp, effectively expanding the number of synchronization channels while avoiding occupying too many coding bits in the instruction.

[0066] In the synchronization method provided in at least one embodiment of the present disclosure, each synchronization channel includes at least one synchronization counter. The synchronization counter is used, for example, to count based on instruction execution status. For example, different synchronization channels may include different numbers of synchronization counters, and the number of synchronization counters may be one or more, and may be set based on actual needs. For example, the number of synchronization counters may be determined based on factors such as workload size, the granularity and rate of instruction processing data, and the present disclosure does not impose any restrictions on this.

[0067] For a synchronization channel including a synchronization counter, an example of the above step S102 may include the following steps S301 to S303.

[0068] Step S301: In response to issuing a first instruction, increase the count of the synchronization counter.

[0069] Step S302: In response to the task corresponding to the first instruction being completed, the count of the synchronization counter is reduced.

[0070] Step S303: Wait for the synchronization counter to be cleared, and in response to the synchronization counter being cleared, allow the second instruction to start executing.

[0071] For example, in steps S301 to S302 , the synchronization counter is used to track how many issued instructions are waiting to be completed. In an initial state, the count value of the synchronization counter may be initialized to 0.

[0072] For example, multiple first instructions can be assigned to the same synchronization channel. Since each synchronization channel in this example includes a synchronization counter, multiple instructions are equivalently assigned to the same synchronization counter. For these first instructions, the synchronization counter is incremented by one each time a first instruction is issued, and the synchronization counter is decremented by one each time a task corresponding to a first instruction is completed.

[0073] For example, in step S303, assuming that the second instruction depends on the execution results of C first instructions (C is a positive integer), after the C first instructions have been issued, the synchronization counter is cleared to zero, indicating that all tasks corresponding to the above C first instructions are completed, and the second instruction that has a dependency relationship with the above C first instructions can be executed.

[0074] A specific example of the above steps S301 to S303 is given below.

[0075] For example, assuming that the first instruction is a load instruction, the second instruction is an arithmetic operation instruction, and the arithmetic operation instruction needs to be calculated based on the 100 items of data returned by the 100 load instructions, then the same synchronization channel can be allocated to the 100 load instructions. Execute the above step S301, and increase the count value of the synchronization counter by one each time a load instruction is issued. For the 100 load instructions issued above, execute the above step S302, and reduce the count value of the synchronization counter by one each time an item of data is loaded. Assuming that the second instruction is an arithmetic operation instruction, it needs to be calculated based on the above 100 items of data. Execute the above step S303, and wait for the synchronization counter to be cleared. When the synchronization counter is cleared, it means that all 100 items of data have been loaded, and then the arithmetic operation instruction can be executed to calculate them, thereby realizing the synchronization of the load instruction and the arithmetic operation instruction.

[0076] Figure 1D A flowchart of a synchronization method provided in at least one embodiment of the present disclosure.

[0077] For example, Figure 1D As shown, for a synchronization channel including multiple synchronization counters, another example of the above step S102 may include the following steps S311 to S314.

[0078] Step S311: In response to issuing the first instruction, increase the count of the current synchronization counter.

[0079] Step S312: In response to the count of the current synchronization counter reaching the preset value, jump to the next synchronization counter as the current synchronization counter for subsequent counting.

[0080] Step S313: In response to the task corresponding to the first instruction being completed, the count of the corresponding synchronization counter is reduced.

[0081] Step S314: Wait for a preset number of synchronization counters to be cleared or wait for all counted synchronization counters to be cleared, and, in response to being cleared, allow the second instruction to start executing.

[0082] For example, in step S311, the current synchronization counter refers to the synchronization counter currently counting. Initially, the current synchronization counter serving as the starting point can be any synchronization counter in the synchronization channel, which can be selected as needed. The synchronization counter is used to track how many issued instructions are waiting to be completed. Initially, the count values of all synchronization counters in the synchronization channel can be initialized to 0.

[0083] For example, multiple first instructions may be assigned to the same synchronization channel. For these first instructions, each time a first instruction is issued, the count value of the current synchronization counter is increased by one.

[0084] For example, in step S312, the next synchronous counter refers to the next synchronous counter that will perform counting operations in a predetermined order (such as the storage order of the synchronous counters in the storage space) after the "current synchronous counter" described in step S311. For example, the preset value can be 10, 20, 50, etc., which can be set according to actual needs. The embodiment of the present disclosure does not limit this. For example, it is assumed that the current synchronous channel includes synchronous counters C0~C7. If the synchronous counter C0 is currently being used for counting, and the count of the synchronous counter C0 reaches the preset value, it jumps to the next synchronous counter C1, and the synchronous counter C1 is used as the current synchronous counter for subsequent counting. When the count of the synchronous counter C1 reaches the preset value, it jumps to the next synchronous counter C2, and the synchronous counter C2 is used as the current synchronous counter for subsequent counting, and so on, until the counting stops.

[0085] For example, in step S312, a write pointer can be maintained, and the write pointer can be used to determine which synchronization counter's count needs to be increased. For example, when the count of the current synchronization counter reaches a preset value, the thread bundle instruction scheduler can perform an INCREASE operation, which can control the movement of the write pointer. For example, the jump from the synchronization counter C0 to the next synchronization counter C1 in the above text can be understood as the write pointer moving from the synchronization counter C0 to the synchronization counter C1. It should be noted that in the example disclosed in the present invention, it is not necessary to start counting from the synchronization counter C0, and it is also possible to start counting from other synchronization counters. When the count of the synchronization counter C7 reaches the preset value, the write pointer will move from the synchronization counter C7 to the synchronization counter C0, thereby realizing the circular use of the synchronization counter.

[0086] For example, in step S313, the operation of decrementing the synchronous counter can be implemented by hardware. When the task corresponding to the first instruction is completed, the synchronous counter corresponding to the first instruction is decremented. The synchronous counter corresponding to the first instruction is the synchronous counter that was incremented when the first instruction was issued. This means that for the same first instruction, both incrementing and decrementing the synchronous counter value operate on the same synchronous counter.

[0087] For example, step S314 can be divided into the following step S314A and step S314B, which correspond to two different situations respectively.

[0088] Step S314A: Wait for all the counted synchronization counters to be cleared, and, in response to being cleared, allow the second instruction to start executing.

[0089] Step S314B: Wait for a preset number of synchronization counters to be cleared, and, in response to being cleared, allow the second instruction to start executing.

[0090] For example, in step S314A, execution of the second instruction begins only after all synchronized counters have been cleared. For example, if synchronized counters C0-C7 are all involved in counting, execution of the second instruction begins only after all synchronized counters C0-C7 are cleared. If synchronized counters C3-C6 are involved in counting, execution of the second instruction begins only after all synchronized counters C3-C6 are cleared, and so on.

[0091] For example, in step S314A, the warp instruction scheduler can execute a WAIT ALL operation, which maintains a read pointer whose position coincides with the final position of the write pointer. The scheduler waits for the synchronization counter between the read and write pointers to clear before allowing the second instruction to begin execution. This approach improves reliability and ensures that all synchronization counters that have been counted are cleared.

[0092] For example, in step S314B, it is only necessary to wait for a preset number of synchronous counters to be cleared to allow the second instruction to start executing. The preset number can be set according to actual needs, and the embodiments of the present disclosure are not limited to this. For example, assuming that the preset number is 3 and the synchronous counters C0~C7 all participate in counting, it is necessary to wait for the synchronous counters C0~C2 to be cleared to allow the second instruction to start executing. For example, assuming that the preset number is 2 and the synchronous counters C3~C6 participate in counting, it is necessary to wait for the synchronous counters C3~C4 to be cleared to allow the second instruction to start executing, and so on.

[0093] For example, in step S314B, the thread warp instruction scheduler can execute a WAIT LESSTHAN N operation. This operation maintains a read pointer and sets the read pointer position to the final position of the write pointer minus N. The operation then waits for the synchronization counter between the read pointer and the write pointer to clear before starting to execute the second instruction. The WAIT LESSTHAN N operation provides a more flexible method, allowing only a portion of the counted synchronization counters to clear, rather than waiting for all of the counted synchronization counters to clear. For example, the value of N in the WAIT LESSTHAN N operation can be equal to the number of synchronization counters participating in the counting minus a preset number. For example, assuming there are five synchronization counters participating in the counting, when N = 0, the preset number is 5, and the process needs to wait for all five synchronization counters to clear. When N = 1, the preset number is 4, and the process needs to wait for the first four synchronization counters to clear. When N = 2, the preset number is 3, and the process needs to wait for the first three synchronization counters to clear, and so on.

[0094] Figure 2 An exemplary schematic diagram of a synchronization method provided for at least one embodiment of the present disclosure. Figure 2 A specific example of the above steps S311 to S314A is given.

[0095] Assuming that the first instruction is a load instruction, the second instruction is an arithmetic operation instruction, and the arithmetic operation instruction needs to perform operations based on 70 data items returned by the 70 load instructions Ld0 to Ld70, the same synchronization channel can be allocated to the 70 load instructions.

[0096] For example, Figure 2As shown, the synchronization channel allocated to the above 70 load instructions includes synchronization counters C0~C7, and the preset value of the synchronization counter is 20. In this example, the initial position of the write pointer is at the synchronization counter C0, that is, counting starts from the synchronization counter C0. Each time a load instruction is issued, the thread bundle instruction scheduler adds one to the count value of the synchronization counter C0 until the count value of the synchronization counter C0 reaches the preset value 20. At this time, the thread bundle instruction scheduler performs an INCREASE operation, and the write pointer moves from the synchronization counter C0 to the synchronization counter C1, and uses the synchronization counter C1 as the current synchronization counter for subsequent counting, and so on, until all 70 load instructions are issued, at which time the write pointer should be located at the synchronization counter C3. In addition, for the 70 load instructions issued above, each time a data load is completed, the count value of the synchronization counter corresponding to the load instruction is reduced by one.

[0097] For example, Figure 2 As shown, the warp instruction scheduler executes a WAIT ALL operation, aligning the read pointer position with the final write pointer position (i.e., synchronization counter C3). To ensure data consistency, it waits for all synchronization counters between the read and write pointers to clear. Specifically, it waits for synchronization counters C4, C5, C6, C7, C0, C1, C2, and C3 to clear. When all synchronization counters are cleared, the 70 data items have been loaded, and arithmetic operations can be executed on them. This synchronizes the load and arithmetic operations.

[0098] Figure 3 An exemplary schematic diagram of a synchronization method provided for at least one embodiment of the present disclosure. Figure 3 A specific example of the above steps S311 to S314B is given.

[0099] Assuming that the first instruction is a load instruction, the second instruction is an arithmetic operation instruction, and the arithmetic operation instruction needs to perform operations based on 70 data items returned by the 70 load instructions Ld0 to Ld70, the same synchronization channel can be allocated to the 70 load instructions.

[0100] For example, Figure 3As shown, the synchronization channel allocated to the above 70 load instructions includes synchronization counters C0~C7, and the preset value of the synchronization counter is 20. In this example, the initial position of the write pointer is at the synchronization counter C0, that is, counting starts from the synchronization counter C0. Each time a load instruction is issued, the count value of the synchronization counter C0 is increased by one until the count value of the synchronization counter C0 reaches the preset value 20. At this time, the thread bundle instruction scheduler performs an INCREASE operation, and the write pointer moves from the synchronization counter C0 to the synchronization counter C1, and the synchronization counter C1 is used as the current synchronization counter for subsequent counting, and so on, until all 70 load instructions are issued, at which time the write pointer should be located at the synchronization counter C3. In addition, for the 70 load instructions issued above, each time a data load is completed, the count value of the synchronization counter corresponding to the load instruction is reduced by one.

[0101] For example, Figure 3 As shown, the thread warp instruction scheduler executes the WAIT LESSTHAN N operation, where N=2 in this example, sets the read pointer position to the final position of the write pointer - N, and waits for the synchronization counters between the read pointer (located at the synchronization counter C1) and the write pointer to be cleared, that is, waits for the synchronization counters C4, C5, C6, C7, C0, and C1 to be cleared. This means that the 40 data items corresponding to the synchronization counters C0 and C1 have been loaded, and arithmetic operation instructions can be executed to operate on these 40 data items. The loading of the remaining 30 data items is also carried out at the same time. Figure 2 Compared to the example, this method does not need to wait for both C2 and C3 synchronization counters to clear. This means that the loading of the remaining 30 data items can continue while the computation is being processed, thus achieving pipeline operation of the loading and computation tasks. Furthermore, the WAIT LESSTHAN N operation provides a programming method that is more suitable for loop iterations.

[0102] In the synchronization method provided in at least one embodiment of the present disclosure, by setting multiple synchronization counters within a single synchronization channel, data loading tasks and computing tasks can be effectively organized into a pipeline, providing sufficient synchronization resources, significantly improving processing efficiency and resource utilization. This method not only optimizes the time matching between computing tasks and data loading tasks, but also maintains a smooth task processing flow even under high load conditions, thereby enhancing overall responsiveness and work efficiency.

[0103] It should be noted that, in the embodiments of the present disclosure, the synchronization method may include more or fewer steps, and the execution order of the steps is not limited, which can be determined according to actual needs.

[0104] Figure 4A schematic block diagram of a synchronization device provided by at least one embodiment of the present disclosure. For example, the synchronization device provided by at least one embodiment of the present disclosure can be Figure 1A The thread warp instruction scheduler 12 shown, or embedded in Figure 1A In the thread warp instruction scheduler 12 shown.

[0105] For example, Figure 4 As shown, the synchronization device 400 provided by at least one embodiment of the present disclosure includes a distribution module 401 and a synchronization module 402 .

[0106] For example, the allocation module 401 is configured to allocate a synchronization channel to a first instruction for a warp including multiple threads. For details about the allocation module 401 , reference may be made to the description of step S101 in the embodiment of the synchronization method, which will not be repeated here.

[0107] For example, the synchronization module 402 is configured to synchronize the first instruction and the second instruction based on the synchronization channel. For relevant contents of the synchronization module 402, reference may be made to the relevant description of step S102 in the embodiment of the synchronization method, which will not be repeated here.

[0108] For example, there is a dependency relationship between the first instruction and the second instruction, the thread warp corresponds to multiple synchronization channel groups, each synchronization channel group includes at least one synchronization channel, and different synchronization channel groups correspond to different types of instructions.

[0109] For example, in at least one embodiment of the present disclosure, the same synchronous channel group corresponds to the same instruction type.

[0110] For example, in at least one embodiment of the present disclosure, the allocation module 401 is further configured to: determine a synchronization channel group corresponding to the first instruction based on the type of the first instruction; and allocate a synchronization channel in the synchronization channel group to the first instruction.

[0111] For example, in at least one embodiment of the present disclosure, the first instruction includes a synchronization channel identifier, and the allocation module 401 is further configured to allocate a synchronization channel corresponding to the synchronization channel identifier in the synchronization channel group to the first instruction according to the synchronization channel identifier.

[0112] For example, in at least one embodiment of the present disclosure, each synchronization channel includes at least one synchronization counter, and the synchronization counter is used to count based on instruction execution status.

[0113] For example, in at least one embodiment of the present disclosure, for a synchronization channel including a synchronization counter, the synchronization module 402 is further configured to: increase the count of the synchronization counter in response to issuing a first instruction; decrease the count of the synchronization counter in response to completion of the task corresponding to the first instruction; wait for the synchronization counter to be cleared, and, in response to the synchronization counter being cleared, allow the second instruction to start execution.

[0114] For example, in at least one embodiment of the present disclosure, for a synchronization channel including multiple synchronization counters, the synchronization module 402 is further configured to: in response to issuing a first instruction, increase the count of the current synchronization counter; in response to the count of the current synchronization counter reaching a preset value, jump to the next synchronization counter as the current synchronization counter for subsequent counting; in response to the completion of the task corresponding to the first instruction, reduce the count of the corresponding synchronization counter; wait for a preset number of synchronization counters to be cleared or wait for all counted synchronization counters to be cleared, and, in response to clearing, allow the second instruction to start execution.

[0115] For example, in at least one embodiment of the present disclosure, the first instruction is a variable-length instruction.

[0116] For example, in at least one embodiment of the present disclosure, the first instruction includes a data transfer instruction, a general matrix multiplication instruction, a transcendental function instruction, or a cache operation instruction.

[0117] It should be noted that the above-mentioned various modules and units can be implemented by software, hardware, firmware or any combination thereof. For example, the distribution module and the synchronization module can be implemented as a distribution circuit and a synchronization circuit respectively. The embodiments of this disclosure do not limit their specific implementation methods.

[0118] It should be understood that the synchronization device 400 provided in at least one embodiment of the present disclosure can be used to implement the aforementioned synchronization method, and can also achieve technical effects similar to those of the aforementioned synchronization method, which will not be elaborated here.

[0119] It should be noted that in the embodiments of the present disclosure, the synchronization device 400 may include more or fewer modules or units, and the connection relationship between the modules or units is not limited and can be determined according to actual needs. The specific configuration of each module or unit is not limited and can be composed of analog devices according to circuit principles, or can be composed of digital chips, or constructed in other applicable ways.

[0120] Figure 5 A schematic block diagram of an electronic device provided in accordance with at least one embodiment of the present disclosure.

[0121] For example, Figure 5As shown, electronic device 500 includes at least one processor 501 and at least one memory 502. The at least one memory 502 includes one or more computer program modules. The one or more computer program modules are stored in memory 502 and configured to be executed by the at least one processor 501. The one or more computer program modules include instructions for executing the synchronization method described above. When executed by the at least one processor 501, the one or more computer program modules can perform one or more steps of the synchronization method provided in at least one embodiment of the present disclosure. The memory 502 and processor 501 can be interconnected via a bus system and / or other form of connection mechanism (not shown).

[0122] For example, the processor 501 may be a central processing unit (CPU), a digital signal processor (DSP), a graphics processing unit (GPU), a general-purpose graphics processing unit (GPGPU), an artificial intelligence (AI) accelerator, or other processing units with data processing and / or program execution capabilities, such as a field programmable gate array (FPGA). For example, the central processing unit (CPU) may be an X86, ARM, or RISC-V architecture. The processor 501 may be a general-purpose processor or a dedicated processor, and may control other components in the electronic device 500 to perform desired functions.

[0123] For example, memory 502 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), a USB memory, a flash memory, and the like.

[0124] Figure 6 A schematic block diagram of another electronic device provided for at least one embodiment of the present disclosure.

[0125] The electronic devices in at least one embodiment of the present disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, personal digital assistants (PDAs), tablet computers (PADs), portable multimedia players (PMPs), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), wearable electronic devices, etc., as well as fixed terminals such as digital TVs, desktop computers, etc. Figure 6 The electronic device shown is only an example and should not limit the functions and scope of use of the embodiments of the present disclosure.

[0126] The electronic device includes at least one processor and memory. The processor herein may be referred to as processing device 601, described below. The memory may include at least one of read-only memory (ROM), random access memory (RAM), and storage device 608, described below. The memory is used to store programs for executing the methods described in the various method embodiments described above; the processor is configured to execute the programs stored in the memory. The processor may include a central processing unit (CPU) or other form of processing unit with data processing and / or instruction execution capabilities, and may control other components in the electronic device to perform desired functions.

[0127] like Figure 6 As shown, electronic device 600 may include a processing device 601 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to programs stored in ROM 602 or programs loaded from storage device 608 into RAM 603. RAM 603 also stores various programs and data required for the operation of electronic device 600. Processing device 601, ROM 602, and RAM 603 are interconnected via bus 604. An input / output (I / O) interface is also connected to bus 604.

[0128] Typically, the following devices may be connected to the I / O interface 605: an input device 606 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 607 including, for example, a display, a speaker, a vibrator, etc.; a storage device 608 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 609. The communication device 609 may allow the electronic device 600 to communicate with other devices wirelessly or by wire to exchange data. Figure 6 The electronic device 600 is shown with various devices, but it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed instead.

[0129] In particular, according to at least one embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, at least one embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a non-transitory computer-readable medium, and the computer program includes program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the network through the communication device 609, or installed from the storage device 608, or installed from the ROM 602. When the computer program is executed by the processing device 601, the above-mentioned functions defined in the method of at least one embodiment of the present disclosure are performed.

[0130] It should be noted that the computer-readable medium described above in the present disclosure may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. Computer-readable storage media may include, but are not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or components, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to, an electrical connection having one or more conductors, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In at least one embodiment of the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, device, or component. Furthermore, in at least one embodiment of the present disclosure, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. This propagated data signal may take a variety of forms, including, but not limited to, electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer-readable medium may be transmitted using any suitable medium, including but not limited to wire, optical cable, radio frequency (RF), or any suitable combination thereof.

[0131] The computer-readable medium may be included in the electronic device 600 , or may exist independently without being incorporated into the electronic device 600 .

[0132] Figure 7 A schematic block diagram of a non-transitory computer-readable storage medium is provided for at least one embodiment of the present disclosure.

[0133] For example, Figure 7 As shown, a non-transitory computer-readable storage medium 700 stores computer-readable instructions 701 , which, when executed by at least one processor, perform one or more steps of the above-mentioned synchronization method.

[0134] For example, the storage medium may include a memory card of a smart phone, a storage component of a tablet computer, a hard disk of a personal computer, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), a flash memory, or any combination of the above storage media, or other suitable storage media. For example, the readable storage medium may also be Figure 5 For the memory 502 in the embodiment, the related description can be referred to the aforementioned content and will not be repeated here.

[0135] Although the present disclosure has been described in detail above using general descriptions and specific embodiments, it will be apparent to those skilled in the art that modifications or improvements may be made based on the embodiments of the present disclosure. Therefore, such modifications or improvements, as long as they do not depart from the spirit of the present disclosure, are within the scope of protection claimed by the present disclosure.

[0136] Regarding this disclosure, the following points need to be explained:

[0137] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0138] (2) For the sake of clarity, the thickness of layers or regions in the drawings used to describe the embodiments of the present disclosure are enlarged or reduced, that is, these drawings are not drawn according to the actual scale.

[0139] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0140] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A synchronization method, comprising: Allocating a synchronization channel for a first instruction for a warp including a plurality of threads; Synchronize the first instruction and the second instruction based on the synchronization channel, There is a dependency relationship between the first instruction and the second instruction, the thread warp corresponds to multiple synchronization channel groups, each synchronization channel group includes at least one synchronization channel, and different synchronization channel groups correspond to different types of instructions. Among them, each synchronization channel includes at least one synchronization counter, which is used to count based on the instruction execution status, determine when the task corresponding to the first instruction is completed, and execute the second instruction in time, thereby achieving synchronization of the first instruction and the second instruction.

2. The synchronization method according to claim 1, wherein: Allocating a synchronization channel for the first instruction includes: Determine, based on the type of the first instruction, a synchronization channel group corresponding to the first instruction; A synchronization channel in the synchronization channel group is allocated to the first instruction.

3. The synchronization method according to claim 2, wherein: The first instruction includes a synchronization channel identifier, Allocating a synchronization channel in the synchronization channel group to the first instruction includes: According to the synchronization channel identifier, a synchronization channel in the synchronization channel group corresponding to the synchronization channel identifier is allocated to the first instruction. The synchronization method according to claim 1 , wherein: For a synchronous channel that includes a synchronous counter, The synchronizing the first instruction and the second instruction based on the synchronization channel includes: In response to issuing the first instruction, increasing the count of the synchronization counter; In response to completion of the task corresponding to the first instruction, decrementing the count of the synchronization counter; Waiting for the synchronization counter to be cleared, and, in response to the synchronization counter being cleared, allowing the second instruction to begin execution. The synchronization method according to claim 1 , wherein: For a synchronous channel consisting of multiple synchronous counters, The synchronizing the first instruction and the second instruction based on the synchronization channel includes: In response to issuing the first instruction, increasing the count of the current synchronization counter; In response to the count of the current synchronization counter reaching a preset value, jumping to the next synchronization counter as the current synchronization counter for subsequent counting; In response to the task corresponding to the first instruction being completed, reducing the count of the corresponding synchronization counter; Waiting for a preset number of synchronization counters to be cleared or waiting for all counted synchronization counters to be cleared, and, in response to being cleared, allowing the second instruction to start execution. The synchronization method according to claim 1 , wherein: The same synchronous channel group corresponds to the same instruction type.

7. The synchronization method according to claim 1, wherein: The first instruction is a variable-length instruction. The synchronization method according to claim 1 , wherein: The first instruction includes a data transfer instruction, a general matrix multiplication instruction, a transcendental function instruction or a cache operation instruction.

9. The synchronization method according to claim 1, wherein: The synchronization method is executed by a warp instruction scheduler.

10. A synchronization device comprising: an allocation module configured to allocate a synchronization channel to a first instruction for a warp including a plurality of threads; a synchronization module, configured to synchronize the first instruction and the second instruction based on the synchronization channel, There is a dependency relationship between the first instruction and the second instruction, the thread warp corresponds to multiple synchronization channel groups, each synchronization channel group includes at least one synchronization channel, and different synchronization channel groups correspond to different types of instructions. Among them, each synchronization channel includes at least one synchronization counter, which is used to count based on the instruction execution status, determine when the task corresponding to the first instruction is completed, and execute the second instruction in time, thereby achieving synchronization of the first instruction and the second instruction.

11. An electronic device comprising: at least one processor; at least one memory storing one or more computer program modules; The one or more computer program modules are configured to be executed by the at least one processor to execute instructions of the synchronization method according to any one of claims 1 to 9.

12. A non-transitory computer-readable storage medium having computer-readable instructions stored thereon, wherein: When the computer-readable instructions are executed by at least one processor, the synchronization method according to any one of claims 1 to 9 is performed.

Images