Watchdog circuit for embedded system

Abstract

The invention discloses a watchdog circuit for an embedded system, belongs to the field of embedded systems, and can set delay starting time. After the system is powered on, a pin 4 of the phase inverter D1 outputs a high level, the timing capacitor C7 is charged through the current-limiting resistor R5, the timing circuit outputs the high level outwards, and the embedded system is normally started; when a dog feeding signal is changed from a high level to a low level, the triode VT3 is kept closed; when a dog feeding signal is changed from a low level to a high level, the collector electrode and the emitter electrode of the triode VT3 are conducted, and the dog feeding circuit outputs a low-level pulse; the low-level pulse discharges the timing capacitor C7 and resets the timing time, and after the pulse interruption is overtime, the voltage values at the two ends of the timing capacitor C7 exceed a high-level threshold value input by the pin 2 of the phase inverter D1, the pin 4 of the phase inverter D1 outputs a low level, the timing capacitor C7 is discharged through the current-limiting resistor R5, the timing circuit outputs the low level outwards, and the embedded system enters a reset state.

Description

Technical Field

[0001] The present invention relates to the technical field of embedded systems, and particularly relates to a watchdog circuit for an embedded system. Background Art

[0002] Currently, for embedded system applications, a watchdog function is often added to monitor the system to deal with problems such as system crashes and faults. However, in system applications, the delay start time of conventional watchdog chips cannot be set currently, and it is relatively short, about 1.6 s. For systems with slow startup, they cannot be used or only chips with a longer delay start time need to be sourced again, but the time of the chips can mostly not be set, and too long startup time will also affect the response speed of the device. Therefore, a watchdog protection circuit for setting the delay start time is needed. Summary of the Invention

[0003] In view of the deficiencies and defects existing in the prior art, the present invention provides a watchdog circuit for an embedded system. The purpose of the present invention is to provide a watchdog protection circuit that can set the delay start time and has a wide range of applications.

[0004] The purpose of the present invention can be achieved through the following technical solutions: A watchdog circuit for an embedded system includes a timing circuit and a dog-feeding circuit: Among them, the timing circuit includes an inverter D1, a timing capacitor C7, and a current-limiting resistor R5; the dog-feeding circuit includes a triode VT3, a resistor R6, a capacitor C8, and a resistor R7.

[0005] Further, in the timing circuit, the dog-feeding signal from the dog-feeding circuit is connected to the upper end of the timing capacitor C7. The upper end of the timing capacitor C7 is connected to the input of the inverter D1, the lower end is connected to GND, one end of the current-limiting resistor R5 is connected to the output of the 4th pin of the inverter D1, and the other end is connected to the input of the 2nd pin of the inverter D1.

[0006] Further, in the timing circuit, after power-on, the voltage across the timing capacitor C7 is initially 0 V, the input of the 2nd pin of the inverter D1 is at a low level, the output of the 4th pin of the inverter D1 is at a high level, and the timing capacitor C7 is charged through the current-limiting resistor R5. At this time, the timing circuit outputs a high level externally, and the embedded system can start normally; the low-level pulse from the dog-feeding circuit discharges the timing capacitor C7 and resets the timing time; after the timeout of the low-level pulse interruption from the dog-feeding circuit, the voltage value across the timing capacitor C7 exceeds the high-level threshold input to the 2nd pin of the inverter D1, the output of the 4th pin of the inverter D1 is at a low level, and the timing capacitor C7 is discharged through the current-limiting resistor R5. At this time, the timing circuit outputs a low level externally, and the embedded system enters the reset state.

[0007] Further, for the watchdog circuit, the PWM_WDT watchdog signal passes through the series resistor R7, the DC-blocking capacitor C8, and is connected to the base of the triode VT3. The base of the triode VT3 is connected to GND through R6, and the emitter of the triode VT3 is connected to the input of the inverter D1 of the timing circuit.

[0008] Further, for the watchdog circuit, when the PWM_WDT watchdog signal remains at a low level or a high level, since the capacitor C8 isolates the DC signal, the triode VT3 remains off; when the PWM_WDT watchdog signal jumps from a high level to a low level, after passing through the series resistor R7 and the DC-blocking capacitor C8, the signal reaching the base of the triode VT3 is still at a low level, and the triode VT3 remains off; when the PWM_WDT watchdog signal jumps from a low level to a high level, after passing through the series resistor R7 and the DC-blocking capacitor C8, the base voltage of the triode VT3 increases, the collector and emitter of the triode VT3 conduct, and the watchdog circuit outputs a low-level pulse.

[0009] The beneficial technical effects of the present invention: Through continuous exploration and experiments, the watchdog circuit of the present invention sets a delay startup time and has a wide range of applications. Description of the Drawings

[0010] Figure 1 is a block diagram of the working principle of the watchdog circuit for an embedded system according to the present invention.

[0011] Figure 2 is a specific circuit diagram of the watchdog circuit for an embedded system according to the present invention. Detailed Embodiments

[0012] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and do not limit the present invention.

[0013] On the contrary, the present invention covers any alternatives, modifications, equivalent methods and solutions made within the spirit and scope of the present invention defined by the claims. Further, in order to enable the public to better understand the present invention, in the following detailed description of the present invention, some specific details are described in detail. Those skilled in the art can fully understand the present invention without the description of these details.

[0014] As Figure 1-2 shown, a watchdog circuit for an embedded system includes a timing circuit and a watchdog circuit: Among them, the timing circuit includes an inverter D1 (RS1G14XC5), a timing capacitor C7 (10 μF), and a current-limiting resistor R5 (1 MΩ); Further, for the timing circuit, the watchdog signal from the watchdog circuit is connected to the upper end of the timing capacitor C7. The upper end of the timing capacitor C7 is connected to the input of the inverter D1, and the lower end is connected to GND. One end of the current-limiting resistor R5 is connected to the output of the 4th pin of the inverter D1, and the other end is connected to the input of the 2nd pin of the inverter D1; Further, for the timing circuit, after power-on, the voltage across the timing capacitor C7 is initially 0V. The input of the 2nd pin of the inverter D1 is at a low level, and the output of the 4th pin of the inverter D1 is at a high level. The capacitor C7 is charged through the current-limiting resistor R5. At this time, the timing circuit outputs a high level externally, and the embedded system can start normally. The low-level pulse from the watchdog circuit discharges the timing capacitor C7 and resets the timing time. After the low-level pulse from the watchdog circuit times out, the voltage value across the timing capacitor C7 exceeds the high-level threshold of the input of the 2nd pin of the inverter D1, and the output of the 4th pin of the inverter D1 is at a low level. The capacitor C7 is discharged through the current-limiting resistor R5. At this time, the timing circuit outputs a low level externally, and the embedded system enters the reset state. The formula for calculating the timing start time is:

[0015] Among them, the watchdog circuit includes a triode VT3 (2SCR523EB), a resistor R6 (10 kΩ), a capacitor C8 (1 μF), and a resistor R7 (1 kΩ); Further, for the watchdog circuit, the PWM_WDT watchdog signal passes through the series resistor R7, the DC-blocking capacitor C8, and is connected to the base of the triode VT3. The base of the triode VT3 is connected to GND through R6, and the emitter of the triode VT3 is connected to the input of the inverter D1 of the timing circuit; Further, for the watchdog circuit, when the PWM_WDT watchdog signal remains at a low level or a high level, since the capacitor C8 isolates the DC signal, the triode VT3 remains off. When the PWM_WDT watchdog signal jumps from a high level to a low level, after passing through the series resistor R7 and the DC-blocking capacitor C8, the base of the triode VT3 is still at a low level, and the triode VT3 remains off. When the PWM_WDT watchdog signal jumps from a low level to a high level, after passing through the series resistor R7 and the DC-blocking capacitor C8, the base voltage of the triode VT3 increases, and the collector and emitter of the triode VT3 conduct, and the watchdog circuit outputs a low-level pulse.

[0016] The specific working process of the present invention is as follows: After the system is powered on, when the PWM_WDT watchdog signal of the watchdog circuit remains low or high, since the capacitor C8 isolates the DC signal, the triode VT3 remains off; the voltage across the timing capacitor C7 of the timing circuit is initially 0V, the input of pin 2 of the inverter D1 is low, and the output of pin 4 of the inverter D1 is high. The capacitor C7 is charged through the current-limiting resistor R5. At this time, the timing circuit outputs a high level externally, and the embedded system can start normally; after the system starts, when the PWM_WDT watchdog signal jumps from high to low, after passing through the series resistor R7 and the DC-blocking capacitor C8, the base of the triode VT3 is still low, and the triode VT3 remains off; when the PWM_WDT watchdog signal jumps from low to high, after passing through the series resistor R7 and the DC-blocking capacitor C8, the base voltage of the triode VT3 increases, and the collector and emitter of the triode VT3 conduct, and the watchdog circuit outputs a low-level pulse; the low-level pulse from the watchdog circuit discharges the timing capacitor C7 and resets the timing time; after the low-level pulse from the watchdog circuit times out, the voltage value across the timing capacitor C7 exceeds the high-level threshold input to pin 2 of the inverter D1, and the output of pin 4 of the inverter D1 is low. The capacitor C7 is discharged through the current-limiting resistor R5. At this time, the timing circuit outputs a low level externally, and the embedded system enters the reset state.

[0017] Those skilled in the art should understand that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0018] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: the specific implementation manners of the present invention can still be modified or equivalently replaced, and any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered within the protection scope of the claims of the present invention.

Claims

1. A watchdog circuit for an embedded system, characterized in that, It includes a timing circuit and a watchdog circuit: Among them, the timing circuit includes an inverter D1, a timing capacitor C7, and a current-limiting resistor R5; the watchdog circuit includes a triode VT3, a resistor R6, a capacitor C8, and a resistor R7.

2. The watchdog circuit for an embedded system according to claim 1, characterized in that, For the said timing circuit, the watchdog signal from the watchdog circuit is connected to the upper end of the timing capacitor C7. The upper end of the timing capacitor C7 is connected to the input of the inverter D1, the lower end is connected to GND, one end of the current-limiting resistor R5 is connected to the output of the 4th pin of the inverter D1, and the other end is connected to the input of the 2nd pin of the inverter D1.

3. The watchdog circuit for an embedded system according to claim 1, characterized in that, After the said timing circuit is powered on, the voltage across the timing capacitor C7 is initially 0V, the input of the 2nd pin of the inverter D1 is at a low level, the output of the 4th pin of the inverter D1 is at a high level, and the timing capacitor C7 is charged through the current-limiting resistor R5. At this time, the timing circuit outputs a high level externally, and the embedded system can be started normally; the low-level pulse from the watchdog circuit discharges the timing capacitor C7 to reset the timing time; after the low-level pulse interruption from the watchdog circuit times out, the voltage value across the timing capacitor C7 exceeds the high-level threshold of the input of the 2nd pin of the inverter D1, the output of the 4th pin of the inverter D1 is at a low level, and the timing capacitor C7 is discharged through the current-limiting resistor R5. At this time, the timing circuit outputs a low level externally, and the embedded system enters the reset state.

4. The watchdog circuit for an embedded system according to claim 1, characterized in that, For the said watchdog circuit, the PWM_WDT watchdog signal passes through the series resistor R7, the DC-blocking capacitor C8, and is connected to the base of the triode VT3. The base of the triode VT3 is connected to GND through R6, and the emitter of the triode VT3 is connected to the input of the inverter D1 of the timing circuit.

5. The watchdog circuit for an embedded system according to claim 1, characterized in that, For the said watchdog circuit, when the PWM_WDT watchdog signal remains at a low level or a high level, since the capacitor C8 isolates the DC signal, the triode VT3 remains off; when the PWM_WDT watchdog signal jumps from a high level to a low level, after passing through the series resistor R7 and the DC-blocking capacitor C8, the voltage at the base of the triode VT3 is still at a low level, and the triode VT3 remains off; when the PWM_WDT watchdog signal jumps from a low level to a high level, after passing through the series resistor R7 and the DC-blocking capacitor C8, the base voltage of the triode VT3 increases, the collector and emitter of the triode VT3 conduct, and the watchdog circuit outputs a low-level pulse.

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