Processing unit testing method and device, electronic equipment and storage medium

Abstract

The invention provides a processing unit testing method, and relates to the technical field of artificial intelligence, in particular to the technical field of random instruction generation, chip testing and chip verification. According to the specific implementation scheme, the method comprises the steps of generating to-be-processed data for a to-be-tested instruction stream according to a simulation address interval for the to-be-tested instruction stream; obtaining a to-be-tested file according to the to-be-processed data and to-be-executed instruction data for the to-be-tested instruction stream; and executing the to-be-tested file by using a to-be-tested processing unit to obtain a test result of the to-be-tested processing unit. The invention further provides a processing unit testing device, electronic equipment and a storage medium.

Description

Technical Field

[0001] The present disclosure relates to the field of artificial intelligence technology, and in particular, to the fields of random instruction generation (RIG), chip testing, and chip verification technology. More specifically, the present disclosure provides a processing unit testing method, apparatus, electronic device, and storage medium. Background Art

[0002] With the development of artificial intelligence technology, the application of large models is constantly increasing. Artificial intelligence chips can be used to implement the inference and training of large models. The computing power requirements and general-purpose requirements of artificial intelligence chips are also constantly increasing. Summary of the Invention

[0003] The present disclosure provides a processing unit testing method, apparatus, device, and storage medium.

[0004] According to one aspect of the present disclosure, there is provided a processing unit testing method, the method comprising: generating, according to a simulated address range for a to-be-tested instruction stream, to-be-processed data for the to-be-tested instruction stream; obtaining a to-be-tested file according to the to-be-processed data and to-be-executed instruction data for the to-be-tested instruction stream; and using a to-be-tested processing unit to execute the to-be-tested file to obtain a test result of the to-be-tested processing unit.

[0005] According to another aspect of the present disclosure, there is provided a processing unit testing apparatus, the apparatus comprising: a first generation module for generating, according to a simulated address range for a to-be-tested instruction stream, to-be-processed data for the to-be-tested instruction stream; a first obtaining module for obtaining a to-be-tested file according to the to-be-processed data and to-be-executed instruction data for the to-be-tested instruction stream; and an execution unit for using a to-be-tested processing unit to execute the to-be-tested file to obtain a test result of the to-be-tested processing unit.

[0006] According to another aspect of the present disclosure, there is provided an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the method provided by the present disclosure.

[0007] According to another aspect of the present disclosure, there is provided a non-transitory computer-readable storage medium storing computer instructions for causing a computer to execute the method provided by the present disclosure.

[0008] According to another aspect of the present disclosure, there is provided a computer program product comprising a computer program which, when executed by a processor, implements the method provided by the present disclosure.

[0009] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. Description of the Drawings

[0010] The drawings are used to better understand the solution and do not constitute a limitation to the present disclosure. Among them:

[0011] Figure 1 is a flowchart of a processing unit testing method according to an embodiment of the present disclosure;

[0012] Figure 2 is a schematic diagram of a random instruction generation device according to an embodiment of the present disclosure;

[0013] Figure 3 is a schematic diagram of a device-side program according to an embodiment of the present disclosure;

[0014] Figure 4 is a schematic diagram of the effect of a processing unit testing method according to an embodiment of the present disclosure;

[0015] Figure 5 is a schematic block diagram of a processing unit testing device according to an embodiment of the present disclosure; and

[0016] Figure 6 is a block diagram of an electronic device to which the processing unit testing method can be applied according to an embodiment of the present disclosure. Detailed Embodiments

[0017] The following describes exemplary embodiments of the present disclosure with reference to the accompanying drawings. Various details of the embodiments of the present disclosure are included to assist understanding, and they should be considered merely exemplary. Therefore, those of ordinary skill in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, descriptions of well-known functions and structures are omitted in the following description for clarity and conciseness.

[0018] As described above, the computing power requirements and general-purpose requirements of artificial intelligence chips are increasing continuously. It is difficult to design artificial intelligence chips for general computing. For example, the complexity of chip design verification for general computing is high, the sub-modules in the processing unit of the chip are severely fragmented, and the reuse frequency of the processing unit is high. It can be understood that the artificial intelligence chip can be an artificial intelligence processor. The artificial intelligence processor can be various types of processors such as a general-purpose graphics processing unit (GPGPU), a tensor processing unit (TPU), or a neural network processing unit (NPU).

[0019] Chips can be verified and tested based on random instruction generation technology. Random instruction generation technology can generate instruction sequences that can cover a large number of processor states and behaviors. Some test tools based on random instruction generation technology perform well in certain scenarios. Taking the fifth-generation reduced instruction set computer design verification (RISCV-DV) tool as an example, the fifth-generation reduced instruction set computer design verification tool has the ability to tailor the instruction set corresponding to the fifth-generation reduced instruction set computer (RISC-V) instruction set architecture, and can support advanced vector (Vector) instruction sets and memory management unit (MMU) privileged modes.

[0020] However, when dealing with more complex or emerging instruction set architectures, test tools based on random instruction generation technology have problems with insufficient flexibility and adaptability. The device-side kernel is different from the host program running on the host. The kernel parameters are separated from the device-side program. The device-side kernel also has a scenario of continuous delivery. The device-side kernel has a memory allocation (Memory Malloc) function, which can be aimed at ensuring memory consistency in software. Test tools based on random instruction generation technology have difficulty in implementing independent parameter generation functions, do not have the ability to continuously generate multiple kernels, and do not support memory functions.

[0021] In addition, the assembly file generated by the fifth-generation reduced instruction set computer design verification tool contains all the data required by the program, resulting in the problem that the instruction data and the data to be processed cannot be separated over a long distance. After the file is compiled and linked, the bubble between the address of the instruction data and the address of the data to be processed can be filled with a preset value of 0. If the distance between the address of the instruction data and the address of the data to be processed is too large (for example, 100 GB), the server or artificial intelligence acceleration device cannot afford such a large storage space overhead.

[0022] Therefore, in order to efficiently test one or more processing units of a chip, the present disclosure provides a testing method for a processing unit, which will be described below.

[0023] Figure 1 is a flowchart of a testing method of a processing unit according to an embodiment of the present disclosure.

[0024] like Figure 1 As shown, the method 100 may include operations S110 to S130.

[0025] In operation S110 , to-be-processed data for the instruction stream to be tested is generated according to the simulated address interval for the instruction stream to be tested.

[0026] In an embodiment of the present disclosure, the simulated address of the instruction to be tested in the instruction stream to be tested may be located within the simulated address range. The data volume of the data to be processed may be consistent with the capacity of the simulated address range. It can be understood that the instruction stream to be tested may be randomly generated, or may be generated based on a directed instruction stream or a semi-directed instruction stream that can implement a preset function.

[0027] In operation S120, a test file to be tested is obtained according to the data to be processed and the instruction data to be executed for the instruction stream to be tested.

[0028] In an embodiment of the present disclosure, the instruction data to be executed may include data related to the program such as the simulated address of the instruction to be tested, the operation to be executed, etc.

[0029] In an embodiment of the present disclosure, by fusing the data to be processed and the instruction data to be executed, a test file to be tested can be obtained. For example, the fusion method may be splicing. Another example is that the data to be processed and the instruction data to be executed can also be added to the same file to obtain the test file to be tested.

[0030] In operation S130, the test file to be tested is executed by the processing unit to be tested, and the test result of the processing unit to be tested is obtained.

[0031] In an embodiment of the present disclosure, the processing unit to be tested may be a processor core of an artificial intelligence chip.

[0032] In an embodiment of the present disclosure, when the processing unit to be tested executes the test file to be tested, a verification execution result can be obtained. According to the verification execution result, the test result can be determined. The test result can represent the accuracy of the processing unit to be tested. For example, if the verification execution result is consistent with the true value (golden value) of the test file to be tested, it can be determined that the accuracy of the processing unit to be tested is high. Another example is that if the verification execution result is inconsistent with the true value of the test file to be tested, it can be determined that the accuracy of the processing unit to be tested is low.

[0033] Through the embodiment of the present disclosure, the test file to be tested is obtained according to the data to be processed and the instruction data to be executed, realizing the separation of instructions and data, and a test file to be tested closer to the real working scenario of the artificial intelligence chip can be generated, enabling efficient and accurate testing, improving the test efficiency, and also effectively reducing the storage resources required for the test file to be tested.

[0034] It can be understood that the method of the present disclosure has been described above, and the instruction stream to be tested of the present disclosure will be described below.

[0035] In some embodiments, the instruction stream to be tested includes at least one instruction to be tested. The instruction to be tested is a basic instruction unit and is modeled based on the instructions defined by the instruction set architecture. Instruction models constructed based on different instruction set architectures may be different. Different instruction models may have the same or similar information. Based on this same information, an instruction class can be formed. The instruction class may include an instruction name, instruction operands, an instruction type, and instruction preset domain data. For example, the instruction names of different instruction set architectures may be different, and the instruction types of different instruction set architectures may also be different. However, the instructions of different instruction set architectures all have fields similar to the instruction name and fields similar to the instruction type. The instruction operands can indicate one of the source address and the destination address of the instruction. The instruction preset domain data can indicate at least one of the available data and available hardware units of the instruction to be tested.

[0036] In some embodiments, the abstracted instruction class can represent an instruction to be tested.

[0037] In some embodiments, the instruction to be tested is generated based on at least one of the instruction name, instruction operands, instruction type, and instruction preset domain data. For example, when the random instruction generation module generates an instruction to be tested, it can generate an instruction corresponding to the required instruction set architecture according to the instruction name, instruction operands, instruction type, and instruction preset domain data provided by the user. If the user does not provide at least one of the instruction name, instruction operands, instruction type, and instruction preset domain data, the random instruction generation module can generate random instructions under one or more preset constraint conditions. The preset constraint conditions may include a preset name constraint condition, a preset type constraint condition, and a preset operand constraint condition. The preset name constraint condition can indicate randomly determining one from multiple instruction names corresponding to the instruction set architecture. The preset type constraint condition can indicate randomly determining one type from multiple instruction types corresponding to the instruction set architecture. The preset operand constraint condition can indicate determining one or more operands based on a preset simulated address range. In one example, if the user provides an instruction name, instruction operation data, and instruction preset domain data, an instruction type can be generated based on the preset type constraint condition. Next, an instruction to be tested can be generated.

[0038] It can be understood that the instructions to be tested of the present disclosure have been described above, and the instruction stream to be tested of the present disclosure will be described below.

[0039] In some embodiments, the instruction stream to be tested is obtained by adding at least one instruction to be tested to a preset instruction stream, and the preset instruction stream includes at least one preset instruction. The preset instruction stream can also be referred to as a semi-directed instruction stream, which can make the execution result of the instruction stream have practical significance and the execution process have a purpose. For example, the preset instruction stream can be a preset memory access instruction stream, a jump instruction stream, etc.

[0040] In some embodiments, a preset instruction stream has instruction addition information, and the instruction addition information is used to indicate at least one of the position and quantity of test instructions to be added to the preset instruction stream. For example, the instruction addition information may include at least one instruction marker for at least one preset instruction. The at least one instruction marker for the preset instruction includes at least one of a first instruction marker and a second instruction marker. The first instruction marker may indicate that one or more test instructions can be added before the preset instruction. The second instruction marker may indicate that one or more test instructions can be added after the preset instruction. Thus, test instructions to be added can be added to the preset instruction stream according to the at least one instruction marker for the preset instruction.

[0041] It can be understood that the above description of the present disclosure is given by taking the test instruction stream being generated according to the preset instruction stream as an example. However, the present disclosure is not limited thereto, and the following will be described.

[0042] In other embodiments, the test instruction stream may be randomly generated according to one or more test instructions. For example, multiple generated test instructions can be randomly combined into a test instruction stream.

[0043] It can be understood that the above description of the test instruction stream of the present disclosure has been given, and the random instruction generation device of the present disclosure will be described below.

[0044] Figure 2 is a schematic diagram of a random instruction generation device according to an embodiment of the present disclosure.

[0045] In some embodiments, the random instruction generation device may include an instruction-side sub-device and a data-side sub-device. The instruction-side sub-device can process the test instruction stream and output instruction data to be executed. The data-side sub-device can output data to be processed. As Figure 2 shown, the random instruction generation device may include an assembly module asm201, a toolchain module tl202, an address pool module ap203, and a data generation module dp204. It can be understood that the instruction-side sub-device may include the assembly module asm201 and the toolchain module tl202. The data-side sub-device may include the address pool module ap203 and the data generation module dp204.

[0046] As Figure 2 shown, multiple test instruction streams can be used as multiple sequence-like objects. The assembly module asm201 can sort the multiple test instruction streams. The assembly module asm201 can obtain the instruction stream information of the test instruction stream.

[0047] In some embodiments, the above method may further include: generating instruction assembly data for an instruction stream to be tested. For example, as Figure 2 shown, the assembly module asm201 may generate instruction assembly data for the instruction stream to be tested according to the instruction assembly data. As described above, the instruction stream to be tested includes a plurality of instructions to be tested. The instruction to be tested is generated by at least one of an instruction name, an instruction type, and an instruction operand. The data to be processed by the instruction to be tested indicated by the instruction operand is not included in the instruction stream to be tested. Thus, the instruction assembly data does not include one or more data to be processed by the instruction stream to be tested. If the instruction assembly data is directly compiled and linked, the resulting file may not be executable.

[0048] In some embodiments, the above method may further include: obtaining instruction data to be executed according to the instruction assembly data. For example, as Figure 2 shown, the toolchain module tl202 may be used to compile the instruction assembly data to obtain a compilation result. The toolchain module tl202 may also be used to link the compilation result to obtain the instruction data to be executed. The instruction data to be executed includes at least one instruction sub-data to be executed for at least one instruction to be tested. The instruction sub-data to be executed may be obtained according to the instruction information of the above-mentioned instruction to be tested.

[0049] It can be understood that instruction assembly data for one or more instruction streams to be tested may be generated. In some other embodiments, taking the generation of instruction assembly data for multiple instruction streams to be tested as an example, according to the instruction assembly data for multiple instruction streams to be tested, instruction data to be executed for multiple instruction streams to be tested may be obtained. The multiple instruction sub-data included in the instruction data to be executed may correspond to the instructions to be tested in different instruction streams to be tested.

[0050] It can be understood that the instruction-side sub-device of the present disclosure has been described above, and the data-side sub-device of the present disclosure will be described below.

[0051] In some embodiments, the address pool module may generate simulated storage units according to the respective simulated address ranges of at least one instruction stream to be tested. The simulated storage units include at least one simulated address range. For example, the host side may execute instructions in a single-threaded and sequential manner, and there will be no scenario where multiple threads read and write to the same address simultaneously. During the generation of the instruction stream to be tested, based on the instruction operands provided by the user, a scenario where multiple threads read and write to the same address simultaneously can be avoided. If the user does not provide instruction operands, a scenario where multiple threads read and write to the same address simultaneously can be avoided based on the preset operand constraint conditions. But in such as Figure 2Before the multiple instruction streams to be tested shown are completed, new instruction streams to be tested may be generated according to user requirements. In this case, one or more simulated addresses required for the new instruction streams to be tested can be allocated using the address pool module ap203 to avoid scenarios where multiple threads read and write the same address simultaneously.

[0052] In some embodiments, in some implementations of the above operation S110, data to be processed is generated according to the simulated address range and the simulated data pattern for the instruction stream to be tested. As Figure 2 shown, the data generation module dp204 can generate data to be processed according to the simulated address range and the simulated data pattern for the instruction stream to be tested. The simulated data pattern can indicate that the data to be processed is all 0s, all 1s, or data that meets the requirements of the scenario to be tested. In one example, data to be processed can be generated based on one or more sample data corresponding to the simulated data pattern, and the amount of data to be processed can be consistent with the capacity of the simulated address range.

[0053] In some embodiments, the data to be processed can include at least one sub-data to be processed. The data to be processed for the instruction stream to be tested includes the sub-data to be processed for the instructions to be tested in the instruction stream to be tested. For example, the instruction to be tested can include instruction operands. The instruction operands can indicate a simulated address in the simulated address range used to generate the data to be processed.

[0054] It can be understood that, according to the simulated address range for one or more instruction streams to be tested, data to be processed for one or more instruction streams to be tested can be generated. In other embodiments, according to multiple simulated address ranges for multiple instruction streams to be tested and multiple simulated data patterns for multiple instruction streams to be tested, data to be processed can be generated. The multiple sub-data to be processed included in the data to be processed can correspond to the instructions to be tested in different instruction streams to be tested.

[0055] It can be understood that the data-side sub-device of the present disclosure has been described above, and the file to be tested will be described below.

[0056] In some embodiments, in some implementations of the above operation S120, a file to be tested is obtained according to the data to be processed and the instruction data to be executed for the instruction stream to be tested. The file to be tested includes multiple independent test data, and the multiple independent test data includes the instruction data to be executed and the data to be processed. For example, the data to be processed and the instruction data to be executed for the instruction stream to be tested can be used as two independent test data and added to the file to be tested respectively.

[0057] It can be understood that in some other embodiments, a file to be tested can also be obtained according to the data to be processed for multiple instruction streams to be tested and the instruction data to be executed for the multiple instruction streams to be tested.

[0058] It can be understood that some ways of obtaining the file to be tested are described above, and some ways of executing the file to be tested will be described below.

[0059] In some embodiments, in some implementations of the above operation S130, using the processing unit to be tested to execute the file to be tested to obtain the test result of the processing unit to be tested includes: using the processing unit to be tested to execute the file to be tested to obtain the execution result to be verified. According to the simulated execution result and the execution result to be verified of the file to be tested, determine the test result of the processing unit to be tested. For example, various simulators can be used to execute the file to be tested to obtain the simulated execution result as the true value. Next, according to the simulated execution result and the execution result to be verified, the test result can be determined. For another example, the instruction operand can instruct the processing unit to be tested to obtain the sub-data to be processed for the instruction to be tested from the data to be processed. During the execution, the processing unit to be tested can obtain the sub-data to be processed based on the instruction operand.

[0060] It can be understood that the processing unit to be tested in the present disclosure can be one or more. The following will be combined with Figure 3 to further illustrate the present disclosure.

[0061] Figure 3 is a schematic diagram of a program executed by a processing unit to be tested according to an embodiment of the present disclosure.

[0062] As Figure 3 shown, the program prog30 can include multiple kernel streams. The multiple kernel streams can include the kernel stream ks30 and the kernel stream ks31. Taking the kernel stream ks30 as an example, the kernel stream ks31 can include multiple kernels. The multiple kernels can include kernel kernel301, kernel kernel302,... kernel kernel303. The kernels can be obtained from the above file to be tested.

[0063] In some embodiments, there are multiple processing units to be tested, and the multiple processing units to be tested are determined from multiple processing units of the chip to be tested. For example, multiple processing units in the chip to be tested can be used as the processing units to be tested. The multiple processing units can include various processing units such as matrix processing units and vector processing units.

[0064] In some embodiments, the above-mentioned random instruction generation device may further include a program management side sub-device. The program management side sub-device may include a control module. The control module may determine the number of files to be tested according to the number of processing units to be tested. The number of files to be tested may be the same as or greater than the number of processing units to be tested. For example, if there are multiple processing units to be tested, there may be multiple files to be tested. Another example is that if there is 1 processing unit to be tested, there may be at least one file to be tested.

[0065] In some embodiments, in some other embodiments of the above operation S130, multiple processing units to be tested are respectively used to execute multiple files to be tested, and respective test results of the multiple processing units to be tested are obtained. For example, by using multiple processing units to be tested to execute multiple files to be tested respectively, multiple execution results to be verified can be obtained. Each execution result to be verified corresponds to a processing unit to be tested. According to the respective simulated execution results of the multiple files to be tested and the multiple execution results to be verified, multiple test results can be determined. Through the embodiments of the present disclosure, when there are multiple processing units to be tested, multiple processing units to be tested can be fully tested.

[0066] It can be understood that the method of the present disclosure has been described above, and the effects of the present disclosure will be described below.

[0067] In some embodiments, the processing unit test method provided by the present disclosure has been applied in the actual chip design process and can effectively test and verify the chip. Based on the processing unit test method of the present disclosure, the development of the random instruction generation device, the register transfer level (RTL) design of the processor, and the development of the register transfer level test platform (bench) are decoupled. The development of the random instruction generation device can be carried out in parallel with the development of the register transfer level without affecting each other. The random instruction generation device based on the processing unit test method of the present disclosure can, for example, complete the smoke test from scratch in about one month. As the project progresses, the random instruction generation device can quickly adapt to the evolution of the instruction set architecture. After the instruction set architecture is updated, the verification and testing of the updated part can be completed within 2 days.

[0068] Based on the processing unit test method provided by the present disclosure, the entire processor core can be verified. Thus, the key functional modules of the processor core can be fully verified, and some supporting modules can be effectively verified jointly, thereby significantly saving human resources. These supporting modules usually have no dedicated person responsible for verification. For example, during the design process of the processor core, there are dozens of main functional modules, and 6 modules with higher importance are verified by dedicated personnel. At least 3 developers are required to verify these 6 modules with higher importance. However, based on the processing unit test method of the present disclosure, with 4 developers, a comprehensive test of the processor core including all dozens of modules can be achieved, and the utilization rate of human resources can be significantly improved and the human resource cost can be reduced during the entire verification and delivery process from the test plan to the coverage convergence.

[0069] During the R & D cycle of the processor core, the verification scheme based on the random instruction generation device has played a significant positive role in the development progress and quality control of the processor core. For example, when the R & D process reaches about 60% of the time node, after the processor core has been verified multiple times based on the processing unit test method provided by the present disclosure, the processor core has shown basic stability. Most of the expected functions of the processor core have been realized and meet the preliminary design specifications. Determining the stability during the early R & D process of the processor core can provide sufficient time for subsequent optimization and adjustment, enabling the processor core to reach or even exceed the expected performance indicators. In addition, through the embodiments of the present disclosure, the human resource allocation of the project can be optimized, bringing double advantages in terms of time and cost to the project. The following will be combined with Figure 4 to further illustrate the effects of the present disclosure.

[0070] Figure 4 is a schematic diagram of the effects of the processing unit test method according to an embodiment of the present disclosure.

[0071] As Figure 4 shown, during the 16 - month R & D process of the processor core, based on the processing unit test method of the present disclosure, when it is determined that the result to be verified for execution is inconsistent with the true value of the file to be tested, it can be determined that the processing unit to be tested has a bug. During the R & D process, more than 300 bugs have been detected based on the processing unit test method of the present disclosure. In addition, during the R & D process, developers found more than 150 bugs based on disassembling and verifying sub - modules. Based on the processing unit test method of the present disclosure, at least more than 100 bugs not covered by module - level verification have been found, effectively making up for the deficiencies of the module - level verification method and improving the overall verification coverage and depth.

[0072] In addition, through the embodiments of the present disclosure, if the instruction stream to be tested is a special instruction stream such as a thread sync instruction stream, a memory fence instruction stream, or a while loop instruction stream, through the embodiments of the present disclosure, it can be determined that the accuracy represented by the test result is relatively low, so as to determine the errors of the processor core. These errors are difficult to be discovered in module-level verification. Thus, through the embodiments of the present disclosure, the reliability and performance of the product can be further improved.

[0073] In addition, the processing unit test method provided by the present disclosure can be used to test a processing unit, or to verify all processing units of a system-on-chip (SoC), and provide assembly data to cover the functional and performance tests of the system-on-chip.

[0074] Through the embodiments of the present disclosure, in the process of verifying a system-on-chip, taking 150 cores as an example, based on the processing unit test method provided by the present disclosure, it is possible to complete the verification and release of all cores in only 1.5 months, saving time costs. It can be understood that these cores are obtained based on a preset instruction stream. During the test process, these cores can maintain a certain degree of randomness, which can effectively improve the comprehensiveness of the test. Compared with testing cores written in a programming language, the method provided by the present disclosure saves more than 2 months of time.

[0075] It can be understood that the method of the present disclosure has been described above, and the apparatus of the present disclosure will be described below.

[0076] Figure 5 is a schematic block diagram of a processing unit test apparatus according to an embodiment of the present disclosure.

[0077] As Figure 5 shown, the apparatus 500 may include a first generation module 510, a first acquisition module 520, and an execution module 530.

[0078] The first generation module 510 is configured to generate data to be processed for the instruction stream to be tested according to the simulated address range for the instruction stream to be tested.

[0079] The first acquisition module 520 is configured to obtain a test file to be tested according to the data to be processed and the instruction data to be executed for the instruction stream to be tested.

[0080] The execution unit 530 is configured to execute the test file to be tested by using the processing unit to be tested, and obtain the test result of the processing unit to be tested.

[0081] In some embodiments, the first generation module includes: a first generation sub-module, configured to generate data to be processed according to the simulated address range and the simulated data pattern for the instruction stream to be tested.

[0082] In some embodiments, the above-mentioned device further includes: a second generation module, configured to generate instruction assembly data for an instruction stream to be tested. A second acquisition module, configured to obtain instruction data to be executed according to the instruction assembly data.

[0083] In some embodiments, the file to be tested includes a plurality of mutually independent test data, and the plurality of mutually independent test data includes instruction data to be executed and data to be processed. The instruction data to be executed includes at least one instruction sub-data to be executed for at least one instruction to be tested, and the instruction sub-data to be executed includes at least one instruction operand, and the instruction operand is used to instruct the processing unit to be tested to obtain the sub-data to be processed for the instruction to be tested from the data to be processed.

[0084] In some embodiments, the execution module includes: a first execution sub-module, configured to execute the file to be tested by using the processing unit to be tested to obtain an execution result to be verified. A determination sub-module, configured to determine the test result of the processing unit to be tested according to the simulated execution result and the execution result to be verified of the file to be tested.

[0085] In some embodiments, the instruction stream to be tested includes at least one instruction to be tested, and the instruction to be tested is generated according to at least one of an instruction name, an instruction operand, an instruction type, and instruction preset domain data, and the instruction preset domain data is used to indicate at least one of available data and available hardware units of the instruction to be tested.

[0086] In some embodiments, the instruction stream to be tested is obtained by adding at least one instruction to be tested to a preset instruction stream, the preset instruction stream includes at least one preset instruction, and the preset instruction stream has instruction addition information, and the instruction addition information is used to indicate at least one of a position and a quantity for adding the instruction to be tested to the preset instruction stream.

[0087] In some embodiments, there are multiple processing units to be tested, and the multiple processing units to be tested are determined from multiple processing units of a chip to be tested. The execution module is further configured to respectively execute multiple files to be tested by using the multiple processing units to be tested to obtain test results of the multiple processing units to be tested respectively.

[0088] In the technical solution of the present disclosure, the processing of collection, storage, use, processing, transmission, provision, and disclosure of the user's personal information involved all complies with the provisions of relevant laws and regulations and does not violate public order and good customs.

[0089] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0090] Figure 6FIG. 0 is a schematic block diagram of an exemplary electronic device 600 that can be used to implement embodiments of the present disclosure. The electronic device is intended to represent various forms of digital computers, such as, for example, laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as, for example, personal digital assistants, cellular telephones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely exemplary and are not intended to limit the implementations of the present disclosure described and / or claimed herein.

[0091] As Figure 6 shown, the device 600 includes a computing unit 601 that can perform various appropriate actions and processes in accordance with a computer program stored in a read-only memory (ROM) 602 or a computer program loaded from a storage unit 608 into a random access memory (RAM) 603. In the RAM 603, various programs and data required for the operation of the device 600 can also be stored. The computing unit 601, the ROM 602, and the RAM 603 are connected to each other via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0092] A plurality of components in the device 600 are connected to the I / O interface 605, including: an input unit 606, such as a keyboard, a mouse, etc.; an output unit 607, such as various types of displays, speakers, etc.; a storage unit 608, such as a magnetic disk, an optical disk, etc.; and a communication unit 609, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 609 allows the device 600 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0093] The computing unit 601 can be various general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 601 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 601 executes the various methods and processes described above, such as the test method of the processing unit. For example, in some embodiments, the test method of the processing unit can be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as the storage unit 608. In some embodiments, part or all of the computer program can be loaded and / or installed onto the device 600 via the ROM 602 and / or the communication unit 609. When the computer program is loaded into the RAM 603 and executed by the computing unit 601, one or more steps of the test method of the processing unit described above can be executed. Alternatively, in other embodiments, the computing unit 601 can be configured to execute the test method of the processing unit in any other suitable manner (e.g., by means of firmware).

[0094] The various embodiments of the systems and techniques described above in this document can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard parts (ASSPs), system on chip (SOC) systems, complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a dedicated or general programmable processor, and can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit the data and instructions to the storage system, the at least one input device, and the at least one output device.

[0095] The program code for implementing the methods of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing devices, such that when the program codes are executed by the processor or controller, the functions / operations specified in the flowchart and / or block diagram are implemented. The program codes can be executed entirely on the machine, partially on the machine, executed partially on the machine as an independent software package and partially on a remote machine, or executed entirely on a remote machine or server.

[0096] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media would include electrical connections based on one or more wires, portable computer disks, hard disks, random access memories, read-only memories, erasable programmable read-only memories (EPROMs) or flash memories, optical fibers, portable compact disc read-only memories (CD-ROMs), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0097] In order to provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a cathode ray tube (CRT) display or a liquid crystal display (LCD)); and a keyboard and a pointing device (e.g., a mouse or a trackball), through which the user can provide input to the computer. Other kinds of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and the input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0098] The systems and techniques described herein can be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system can be interconnected to each other by digital data communication in any form or medium (e.g., a communication network). Examples of communication networks include: Local Area Network (LAN), Wide Area Network (WAN), and the Internet.

[0099] A computer system can include a client and a server. The client and the server are generally far from each other and typically interact through a communication network. The client - server relationship is created by computer programs that run on the respective computers and have a client - server relationship with each other.

[0100] It should be understood that various forms of the processes shown above can be used, with steps reordered, added, or deleted. For example, the steps recited in this disclosure can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved. No limitations are imposed herein.

[0101] The above - described specific embodiments do not constitute a limitation on the protection scope of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub - combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure shall be included within the protection scope of this disclosure.

Claims

1. A processing unit testing method, comprising: Generate data to be processed for the instruction stream to be tested according to the simulated address interval for the instruction stream to be tested; Obtaining a file to be tested according to the data to be processed and the instruction data to be executed for the instruction stream to be tested; The file to be tested is executed by the processing unit to be tested to obtain a test result of the processing unit to be tested.

2. The method according to claim 1, wherein: The step of generating the to-be-processed data for the instruction stream to be tested according to the simulated address interval for the instruction stream to be tested comprises: The data to be processed is generated according to the simulated address range and the simulated data pattern for the instruction stream to be tested.

3. The method according to claim 1, further comprising: generating instruction assembly data for the instruction stream to be tested; The instruction data to be executed is obtained according to the instruction assembly data.

4. The method according to claim 3, wherein: The file to be tested includes a plurality of test data that are independent of each other, and the plurality of test data that are independent of each other include the instruction data to be executed and the data to be processed. The to-be-executed instruction data includes at least one to-be-executed instruction sub-data for at least one to-be-tested instruction, and the to-be-executed instruction sub-data includes at least one instruction operand, and the instruction operand is used to instruct the to-be-tested processing unit to obtain the to-be-processed sub-data for the to-be-tested instruction from the to-be-processed data.

5. The method according to claim 1, wherein: The step of executing the file to be tested by the processing unit to be tested to obtain the test result of the processing unit to be tested includes: Utilizing the processing unit to be tested to execute the file to be tested, and obtaining an execution result to be verified; The test result of the processing unit to be tested is determined according to the simulation execution result of the file to be tested and the execution result to be verified.

6. The method according to claim 1, wherein: The instruction stream to be tested includes at least one instruction to be tested, and the instruction to be tested is generated based on at least one of an instruction name, an instruction operand, an instruction type, and instruction preset domain data, and the instruction preset domain data is used to indicate at least one of available data and available hardware units of the instruction to be tested.

7. The method according to claim 6, wherein: The instruction stream to be tested is obtained by adding at least one of the instructions to be tested to a preset instruction stream, the preset instruction stream includes at least one preset instruction, and the preset instruction stream has instruction addition information, and the instruction addition information is used to indicate at least one of the position and quantity of adding the instructions to be tested to the preset instruction stream.

8. The method according to claim 1, wherein: There are multiple processing units to be tested, and the multiple processing units to be tested are determined from multiple processing units of the chip to be tested. The step of executing the file to be tested by the processing unit to be tested to obtain the test result of the processing unit to be tested includes: The plurality of processing units to be tested are used to respectively execute the plurality of files to be tested, and test results of the plurality of processing units to be tested are obtained.

9. A processing unit testing device, comprising: A first generating module, used for generating to-be-processed data for the instruction stream to be tested according to a simulated address interval for the instruction stream to be tested; A first obtaining module, configured to obtain a file to be tested according to the data to be processed and the instruction data to be executed for the instruction stream to be tested; The execution unit is used to execute the file to be tested by using the processing unit to be tested to obtain the test result of the processing unit to be tested.

10. An electronic device comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 8.

11. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to cause the computer to execute the method according to any one of claims 1 to 8.

12. A computer program product comprising a computer program, which, when executed by a processor, implements the method according to any one of claims 1 to 8.

Images