Smart storage integrated memory storage architecture

Abstract

The present application discloses an integrated memory storage architecture. The integrated memory storage architecture includes: a computational memory semantic solid-state drive, which is used to provide a unified memory address space based on a computational expression link protocol, supporting the host to perform byte-granularity access through load / store instructions; and is provided with an internal intelligent tiering and granularity management mechanism; and is provided with a flexible data placement mechanism that perceives semantics; a host operating system, connected to the computational memory semantic solid-state drive, is used to receive long-latency prompts sent by the computational memory semantic solid-state drive and perform context switching; and is provided with a unified abstract interface layer to uniformly manage byte-granularity memory access to the computational memory semantic solid-state drive, the delivery of data placement semantic prompts, and the submission of unloading task requests to the embedded computing engine. Through the above-mentioned method, the multiple impedance mismatch problems of traditional tiered storage in performance, cost, energy efficiency and intelligent processing can be overcome.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to an integrated memory storage architecture. Background Art

[0002] Current data centers and edge computing face an increasingly acute conflict between the explosive growth of data volumes and the performance, capacity, cost, and energy efficiency of storage / memory. New interconnect technologies, such as computational expressive links, provide a foundation for memory expansion and the memorization of storage devices (e.g., memory-semantic solid-state drives). These technologies enable SSDs to provide near-memory access semantics and massive capacity expansion at a lower cost. Furthermore, the trend in computational storage technology is to offload some computing tasks to storage devices to reduce data movement, latency, and power consumption. However, existing storage architectures, memory management, and operating system mechanisms are still largely based on traditional block interfaces and processor-centric computing models, failing to fully exploit the potential of these new hardware technologies. This leads to performance bottlenecks (e.g., high latency, write amplification, interface mismatch) and resource waste (e.g., CPU stalls, cache inefficiency, and underutilized hardware). Summary of the Invention

[0003] The intelligent storage integrated memory storage architecture provided in this application can build a unified, adaptive, and computationally enhanced memory-storage continuum to overcome the multiple impedance mismatch problems of traditional tiered storage in performance (speed, latency), cost, energy efficiency, and intelligent processing, thereby meeting the comprehensive requirements of next-generation data-intensive applications (such as large-scale language model training / inference, real-time data analysis, and high-performance key-value storage) for ultra-large capacity, extremely low latency, ultra-high throughput, and deeply embedded intelligent processing.

[0004] In the first aspect, the present application provides an integrated intelligent storage memory storage architecture, which includes: a computational memory semantic solid-state drive, which is used to provide a unified memory address space based on a computational expression link protocol, supporting the host to perform byte-granularity access through load / store instructions; and is provided with an internal intelligent layering and granularity management mechanism; and is provided with a flexible data placement mechanism that perceives semantics, and is provided with an embedded computing engine; a host operating system, connected to the computational memory semantic solid-state drive, is used to receive long-latency prompts sent by the computational memory semantic solid-state drive and perform context switching; and is provided with a unified abstract interface layer, which uniformly manages byte-granularity memory access to the computational memory semantic solid-state drive, the transmission of data placement semantic prompts, and the submission of requests for offloading tasks to the embedded computing engine, and is provided with a semantically aware intelligent scheduling and offloading decision-making mechanism.

[0005] Among them, the computational memory semantic solid-state drive includes: a unified interconnection and memory semantics module, which is used to provide a unified memory address space based on the computational expression link protocol, and supports byte-granularity access by the host through load / store instructions; an internal intelligent tiering and granularity management mechanism module, which builds a fine-grained write log with cache line granularity to absorb byte writes and reduce write amplification; at the same time, it maintains a page-granularity read / data cache to utilize spatial locality; and is responsible for managing log merging, garbage collection and data flow between the internal cache and flash memory; a semantically aware flexible data placement mechanism module, which is used to use data semantic hints and combine the status of its internal write log / data cache to place data with different semantics in the optimal physical area inside the flash memory; an embedded computing engine, which is used to perform hardware acceleration for specific tasks; among them, specific tasks include at least one of data compression / decompression, data encryption / decryption, data filtering / aggregation, index assistance, and format conversion.

[0006] The unified interconnect and memory semantics module is also used to provide a logically continuous and extended physical address space to the host through CXL.mem mapping.

[0007] Among them, the internal intelligent tiering and granularity management mechanism module is also used to append data directly and quickly to the internal DRAM write log area when the host issues a storage instruction of cache line size, and to find the latest data copy of a specific address in the log through an optimized index structure; and new writes will logically overwrite the old version of the same address by updating the index.

[0008] Among them, when the host read request does not hit the write log and needs to obtain data from the flash memory, the internal intelligent tiering and granularity management mechanism module will read the entire flash memory page into the page granularity cache area, and then extract the required cache line from it and return it to the host; and when the data in the write log is processed by the background to form a complete data page ready to be written back to the flash memory, the data page will be temporarily stored in the page granularity cache area.

[0009] The data semantic hints include at least one of data life cycle, access mode, hot and cold attributes, and object size category.

[0010] Among them, the semantic-aware flexible data placement mechanism module uses the recycling unit provided by the flexible data placement mechanism in the NVMe standard as the basic management unit of physical placement.

[0011] Among them, the host operating system includes: a collaborative context switching module, which is used to receive long-delay prompts sent by the computational memory semantic solid-state drive and perform context switching; a semantic-aware intelligent scheduling and offloading decision mechanism module, which is used to make data placement decisions, computation offloading decisions and task collaboration.

[0012] Among them, the semantic-aware intelligent scheduling and offloading decision-making mechanism module includes: a data placement decision unit, which is used to generate corresponding semantic hints and pass them to the computational memory semantic solid-state drive after making data placement decisions; a computation offloading decision unit, which is used to identify tasks suitable for offloading to the embedded computing engine and submit tasks through a unified interface; and a task collaboration unit, which is used to coordinate task execution between the host and the embedded computing engine.

[0013] Among them, the data placement decision unit is used to make data placement decisions based on explicit application instructions, runtime intelligent analysis, and system status feedback; the computational offloading decision unit is used to offload tasks based on task characteristic analysis, system real-time status and / or performance / energy efficiency modeling; and the task collaboration unit is used to adopt pre-processing / post-processing, pipeline operation and / or asynchronous execution collaboration modes.

[0014] The beneficial effects of the present application are: different from the existing technology, the present application provides an integrated intelligent storage memory storage architecture, which includes: a computational memory semantic solid-state drive, which is used to provide a unified memory address space based on a computational expression link protocol, supporting the host to perform byte-granularity access through load / store instructions; and is provided with an internal intelligent layering and granularity management mechanism; and is provided with a flexible data placement mechanism that perceives semantics, and is provided with an embedded computing engine; a host operating system, connected to the computational memory semantic solid-state drive, is used to receive long-latency prompts sent by the computational memory semantic solid-state drive and perform context switching; and is provided with a unified abstract interface layer to uniformly manage byte-granularity memory access to the computational memory semantic solid-state drive, the transmission of data placement semantic prompts, and the submission of requests for unloading tasks to the embedded computing engine, as well as a semantically aware intelligent scheduling and unloading decision-making mechanism. That is, the intelligent storage integrated memory storage architecture provided in this application can build a unified, adaptive, and computationally enhanced memory-storage continuum to overcome the multiple impedance mismatch problems of traditional tiered storage in performance (speed, latency), cost, energy efficiency, and intelligent processing, thereby meeting the comprehensive requirements of next-generation data-intensive applications (such as large-scale language model training / inference, real-time data analysis, and high-performance key-value storage) for ultra-large capacity, extremely low latency, ultra-high throughput, and deeply embedded intelligent processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. Among them:

[0016] Figure 1 This is a structural diagram of an embodiment of the smart storage integrated memory storage architecture provided by this application;

[0017] Figure 2 This is a schematic diagram of the structure of an embodiment of a computational memory semantic solid-state drive provided by the present application;

[0018] Figure 3 This is a schematic diagram of the structure of an embodiment of a host operating system provided by this application;

[0019] Figure 4 It is a structural diagram of an embodiment of the semantic-aware intelligent scheduling and offloading decision-making mechanism module provided by this application. DETAILED DESCRIPTION

[0020] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It will be understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some, rather than all, structures related to the present application are shown in the drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0021] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0022] See Figure 1 , Figure 1 1 is a schematic diagram of an embodiment of an integrated memory storage architecture for intelligence and storage provided by the present application. The integrated memory storage architecture 100 includes: a computational memory semantic solid-state drive 10 and a host operating system 20.

[0023] The computational memory semantic solid-state drive 10 is used to provide a unified memory address space based on a computational expression link protocol, supporting byte-granularity access by the host through load / store instructions; and is provided with an internal intelligent layering and granularity management mechanism; and is provided with a flexible data placement mechanism that perceives semantics, and is provided with an embedded computing engine.

[0024] See Figure 2The computational memory semantic solid-state drive 10 includes: a unified interconnection and memory semantics module 11, an internal intelligent tiering and granularity management mechanism module 12, a semantic-aware flexible data placement mechanism module 13, and an embedded computing engine 14.

[0025] The unified interconnection and memory semantics module 11 is used to provide a unified memory address space based on the computing expression link protocol, and supports the host to perform byte-granularity access through load / store instructions.

[0026] The unified interconnect and memory semantics module 11 is further configured to provide a logically continuous and extended physical address space to the host through CXL.mem mapping.

[0027] In some embodiments, the unified interconnection and memory semantics module 11 mainly uses the computational expression link protocol to innovate memory access.

[0028] In traditional computer architecture, main memory (DRAM) and external storage (such as solid-state drives (SSDs)) exist as two separate "worlds." The CPU directly accesses DRAM in byte units using load / store instructions via a low-latency memory bus, which is referred to in this application as "memory semantics." Accessing an SSD, on the other hand, requires an I / O bus (such as PCIe), relying on the intervention of the operating system and driver. Data is transferred using read / write commands in blocks (typically 4KB or larger), following "storage semantics." These two distinct interfaces, access methods, and data granularity create a significant performance gap and software processing complexity, creating an "impedance mismatch" in the system.

[0029] The Compute Express Link (CXL) protocol, specifically its CXL.mem component, is a key technology designed to break down this barrier. It empowers PCIe devices like SSDs with a revolutionary ability: mapping (partially or fully) their internal storage resources into the host's physical memory address space. This means that from the perspective of the CPU and operating system, these SSD storage areas appear to be part of the system memory, even though their physical location and performance characteristics (such as latency) differ from those of DRAM.

[0030] The core changes are reflected in the following aspects: unified address space, memory semantic access and byte-granularity access.

[0031] The unified address space is primarily reflected in the fact that, through CXL.mem mapping, the host CPU obtains a logically continuous and expanded physical address space that seamlessly encompasses both the existing DRAM and the newly mapped SSD storage area. This greatly simplifies data management for applications requiring ultra-large memory capacity, as software no longer needs to deliberately distinguish between data stored in DRAM and the mapped SSD.

[0032] The key change in memory semantics lies in the access method. Once the SSD storage is mapped, the CPU can directly access this space using its native load / store instructions, completely eliminating the complex and expensive I / O process for traditional SSD access (including operating system calls, driver intervention, NVMe command transmission and processing, interrupt handling, etc.). Load / store instructions are extremely lightweight operations executed directly by the CPU.

[0033] Byte-granular access is primarily reflected in the fact that load / store instructions natively support byte- or word-level read and write access to memory addresses. This stands in stark contrast to the fixed-block-size operations of traditional SSD interfaces. Byte-granular access is crucial for processing fine-grained data structures such as metadata, small objects, and partial updates to database logs, significantly improving efficiency.

[0034] Contribution to overcoming impedance mismatch:

[0035] This unified interconnection and memory semantics based on CXL makes a fundamental contribution to overcoming the multiple impedance mismatch problems of traditional tiered storage: such as performance improvement, cost-effectiveness, energy efficiency optimization and intelligent processing foundation.

[0036] The performance improvement is mainly reflected in: reducing interface latency, improving fine-grained access efficiency, and laying the foundation for latency hiding.

[0037] The reduction in interface latency is primarily reflected in the fact that load / store instructions bypass the lengthy traditional I / O software stack, significantly reducing the "interface" latency and software overhead associated with accessing the SSD. Although physical flash read and write latency remains the primary bottleneck, the shortened interaction path delivers significant performance improvements.

[0038] Improving fine-grained access efficiency is mainly reflected in the following aspects: Byte-granularity access avoids unnecessary "read-modify-write" whole-block operations when updating small data, reduces write amplification, and improves access efficiency.

[0039] Laying the foundation for latency hiding is mainly reflected in the following: the memory semantic interface enables the CPU and OS to more accurately track which instruction is waiting for data at which memory address, which is the prerequisite for implementing advanced latency hiding technologies such as "cooperative context switching".

[0040] The cost-effectiveness is primarily reflected in low-cost memory expansion. Its core contribution is that it enables the use of SSDs, which have a significantly lower cost per GB than DRAM, to expand system memory capacity. Applications can now place large data sets (such as AI model parameters and large database caches) that would otherwise have to reside in expensive DRAM on SSDs with memory semantics, significantly reducing the hardware cost of building large memory systems.

[0041] Energy efficiency optimization is mainly reflected in: reducing invalid data transmission and simplifying software stack overhead.

[0042] The reduction of invalid data transmission is mainly reflected in the following aspects: byte-granularity access allows only the data that is really needed to be transmitted, avoiding the large amount of invalid data movement caused by reading and writing the entire block under the traditional block interface, thereby saving energy consumption of the bus and device interface.

[0043] Simplifying the software stack overhead is mainly reflected in the following aspects: lighter-weight access methods reduce the burden on the CPU in executing I / O-related software instructions, indirectly reducing CPU power consumption.

[0044] The foundation of intelligent processing lies primarily in providing memory operation primitives, enabling the CPU to perform pointer arithmetic, traverse complex data structures, and perform in-place modifications directly on the mapped SSD area. This provides the necessary foundational primitives for running more complex algorithms requiring fine-grained random access (such as algorithms in diagrams and in-place data conversion) directly on the SSD. This enables the "sinking" of more intelligent processing logic close to the data, something that traditional block interfaces struggle to efficiently support.

[0045] Summary: "Unified interconnection and memory semantics" is the cornerstone of the "Intelligent Storage Integrated Memory Storage Architecture 100". It uses the CXL protocol to seamlessly integrate SSDs into the host's memory layout, replacing traditional bulky block I / O operations with CPU-native, efficient load / store instructions, and enabling critical byte-granularity access capabilities. This transformation directly optimizes performance (reducing interface latency and software overhead), opens the door to low-cost large-capacity memory expansion, improves energy efficiency by reducing invalid data transmission, and lays the foundation for more sophisticated and intelligent data processing on storage devices. Although it cannot eliminate the latency of the physical media itself, it completely changes the rules of the game for host-storage interaction, paving the way for subsequent innovative technologies such as deeper internal cache optimization, intelligent data placement, compute offloading, and collaborative scheduling.

[0046] The internal intelligent tiering and granularity management mechanism module 12 builds a fine-grained write log at the cache line granularity to absorb byte writes and reduce write amplification; at the same time, it maintains a page-granular read / data cache to exploit spatial locality; and is responsible for managing log merging, garbage collection, and data flow between the internal cache and flash memory.

[0047] In some embodiments, the internal intelligent tiering and granularity management mechanism module 12 is also used to directly and quickly append data to the write log area of ​​the internal DRAM when the host issues a storage instruction of cache line size, and to find the latest data copy of a specific address in the log through an optimized index structure; and the new write will logically overwrite the old version of the same address by updating the index.

[0048] In some embodiments, when a host read request misses the write log and needs to obtain data from the flash memory, the internal intelligent tiering and granularity management mechanism module 12 reads the entire flash memory page into the page granularity cache area, and then extracts the required cache line from it and returns it to the host; and when the data in the write log is processed by the background to form a complete data page ready to be written back to the flash memory, the data page will be temporarily stored in the page granularity cache area.

[0049] In some embodiments, internal intelligent tiering and granularity management (at the firmware level) primarily involves redesigning the SSD's internal dynamic random access memory (DRAM) cache management. A fine-grained write log at the cache line level is constructed to rapidly absorb byte writes and reduce write amplification, while maintaining a page-level read / data cache to exploit spatial locality. The firmware manages log merging, garbage collection, and data flow between the internal cache and flash memory, effectively resolving the granularity mismatch between host byte accesses and flash page accesses.

[0050] Modern host CPUs, using the Compute Express Link (CXL) protocol, can access computational memory semantic solid-state drives (CMS-SSDs) at fine byte granularity (typically a 64-byte cache line). However, the core storage medium of CMS-SSDs—NAND flash memory—is physically limited to read and write in larger pages (typically 4KB to 16KB). This significant disparity between host access requirements (small granularity) and the physical limitations of flash memory (large granularity) is the core challenge facing traditional SSD designs when it comes to memory semantic access.

[0051] Without any processing, simply mapping the host's byte write request directly to the flash page operation will lead to serious consequences:

[0052] For example, write amplification is extremely high: even if the host only wants to modify a small portion of a page (such as 64 bytes), the SSD must first read the entire flash page into the internal cache, modify the corresponding bytes, and then write the entire modified page to a new location in the flash memory (because flash memory cannot be updated in place). This means that a small write may trigger thousands of bytes of flash memory read and write operations, greatly increasing the amount of data written. This is known as "write amplification."

[0053] For example, performance bottlenecks: This complex "read-modify-write" process is not only inefficient, but also occupies the flash memory channel for a long time, seriously blocking subsequent write requests and becoming a performance bottleneck.

[0054] Solution: Firmware-level intelligent tiered caching.

[0055] To address this challenge, this application redesigns the dynamic random access memory (DRAM) cache management mechanism within the CMS-SSD controller, introducing the concept of intelligent tiering. The goal is to build an internal cache system that can efficiently process byte writes, effectively leverage data locality to service read requests, and intelligently manage data persistence. This application logically divides the SSD's internal DRAM into two key, collaborative components: a cache line-granularity write log and a page-granularity read / data cache.

[0056] The cache line granularity write log (Cacheline-Granular Write Log) is described as follows:

[0057] Positioning: This is an area designed specifically to quickly absorb byte-granularity (cache line) write requests from the host.

[0058] Operation methods include: lightning-fast writing, efficient indexing, and version coverage.

[0059] Lightning Write is primarily characterized by the fact that when the host issues a cache-line-sized store instruction, the data is directly and rapidly appended to the internal DRAM write log area, approaching the speed of DRAM itself and much faster than operating flash memory.

[0060] Efficient indexing is mainly reflected in the following: through an optimized index structure (such as a two-level hash table or skip list SkipList, also located in internal DRAM), the firmware can quickly find the latest data copy of a specific address in the log.

[0061] Version overwriting is mainly reflected in the fact that new writes will logically overwrite the old version of the same address by updating the index.

[0062] The core advantage lies in extremely low write latency and elimination of read-modify-write.

[0063] The extremely low write latency is mainly reflected in the fact that the host's write operation is completed almost instantly, and only needs to wait for the internal DRAM to be written.

[0064] Eliminating read-modify-writes essentially avoids the high performance overhead of directly operating flash memory through byte writes.

[0065] The Page-Granular Read / Data Cache is described as follows:

[0066] Positioning: Mainly responsible for caching the entire page of data read from the flash memory and serving as a temporary storage area for background write-back operations.

[0067] Operation modes include: read cache acceleration and write back forwarding.

[0068] Read cache acceleration primarily occurs when a host read request misses the write log and needs to retrieve data from flash memory. The firmware reads the entire flash page and stores it in this cache. It then extracts the required cache line and returns it to the host. Subsequent host access to other data within the same page can be quickly served directly from this cache, effectively leveraging spatial locality.

[0069] Write-back transit is mainly reflected in the following: when the data in the write log is processed (merged) in the background to form complete data pages ready to be written back to the flash memory, these pages will be temporarily stored in this area.

[0070] The core advantages are: accelerating read operations and supporting background write-back.

[0071] The main feature of accelerated read operations is that one flash memory page read serves multiple same-page accesses, reducing the number of reads from the flash memory.

[0072] Supporting background writeback mainly provides the necessary space for background data organization and persistence of the firmware.

[0073] The core data management responsibilities of the firmware (internal intelligent tiering and granularity management mechanism module 12) are as follows:

[0074] The SSD firmware plays the role of an intelligent data dispatcher, responsible for managing these two layers of cache and data interaction with the flash memory: for example, log merging, garbage collection, end-to-end data flow management, and ensuring data consistency.

[0075] Log coalescing is a key background mechanism that makes the write log work. The firmware proactively scans the write log periodically or when log space is limited, identifying multiple, scattered cache line updates to the same flash page. It then intelligently merges these updates (combining them with unmodified portions read from flash when necessary) to construct a complete, up-to-date version of the page in the internal DRAM cache.

[0076] Garbage collection (Log Cleaning / Destaging) primarily involves efficiently writing the latest data page generated by the merge to a new physical location in the flash memory. Once the write is successful, the corresponding old entries and indexes in the write log are cleaned up, freeing up valuable log space. This is similar to the segment cleanup mechanism in the Log Structured File System (LFS), but occurs within the firmware.

[0077] End-to-end data flow management: The firmware orchestrates the entire process: receive host request → prioritize service from write log / read cache → trigger flash read when necessary → perform background log merge → write merged page back to flash → update internal address mapping table (FTL).

[0078] Data consistency is primarily ensured by the firmware, which uses transactional operations (for example, ensuring the atomicity of log writes and index updates) and confirmation mechanisms (ensuring that the log is cleared after the flash write is complete) to ensure data integrity and persistence. The internal DRAM battery backup capability is crucial to prevent log data loss due to power outages.

[0079] The contributions to overcoming impedance mismatch are as follows:

[0080] This intelligent hierarchical caching and granularity management mechanism makes a key contribution to overcoming multiple impedance mismatches at the firmware level:

[0081] The performance contributions are as follows:

[0082] Write Latency Revolution: Write logging reduces byte-write latency from microseconds / milliseconds for flash memory to nanoseconds for internal DRAM.

[0083] Sharp reduction in write amplification and improved throughput: Log merging aggregates a large number of small writes into a small number of large writes, significantly reducing write amplification, improving effective write throughput, and alleviating wear on flash memory.

[0084] Mitigating granularity mismatch: The granularity difference between host byte access and flash page operation is seamlessly translated within the firmware.

[0085] Read operation acceleration: Page-granularity read cache reduces the number of flash reads by exploiting spatial locality.

[0086] The contributions at the cost level are as follows:

[0087] Extended SSD lifespan: Significantly reduced write amplification directly extends the lifespan of flash media, reducing replacement frequency and total cost of ownership.

[0088] Optimize internal DRAM utilization: The hierarchical design makes the expensive internal DRAM resources more rational and efficient.

[0089] The contributions to energy efficiency are as follows:

[0090] Reduced Flash operation energy consumption: Fewer Flash program and erase operations directly reduce device operating power consumption.

[0091] Reduce internal data movement: Log merging can usually organize data flow more efficiently than raw read-modify-write.

[0092] The contributions of intelligent processing are as follows:

[0093] Providing “fresh” data for internal calculations: Well-managed internal caches (especially the latest data in the write log) provide the embedded computing engine 14 with the convenience of fast access to the latest data, allowing it to operate directly on the efficient cache.

[0094] In summary, "Internal Intelligent Tiering and Granularity Management" is the core engine of the Computational Memory Semantic SSD 10 (CMS-SSD) firmware. By ingeniously reconstructing the structure and functionality of the SSD's internal DRAM cache—specifically, introducing a cache line-granular write log, combined with a page-granular read cache and intelligent background data merging and cleanup processes—it fundamentally resolves the core conflict between host byte access requirements and the physical page operation limitations of flash memory. This innovation directly leads to a leap in write performance (low latency, high throughput), significantly reduces write amplification (improves performance, extends lifespan, and reduces costs), and reduces operating power consumption (improves energy efficiency). It also provides a better data foundation for internal intelligent processing. It is the key internal mechanism that supports the high performance and efficiency of the CMS-SSD.

[0095] The semantically aware flexible data placement mechanism module 13 is used to place data with different semantics into the optimal physical area within the flash memory by utilizing data semantic hints and combining the status of its internal write log / data cache.

[0096] In some embodiments, the data semantic hints include at least one of data lifecycle, access pattern, hot and cold attributes, and object size category.

[0097] In some embodiments, the semantic-aware flexible data placement mechanism module 13 utilizes the recycling unit provided by the flexible data placement mechanism in the NVMe standard as the basic management unit of physical placement.

[0098] In some embodiments, semantically-aware flexible data placement (firmware-level, host-booted): Integrates and extends the concept of flexible data placement. The host operating system 20 or application provides data semantic hints (e.g., data lifecycle, access patterns, hot / cold attributes, object size categories) to the firmware through a unified interface. The firmware uses these hints, combined with the state of its internal write log / data cache, to intelligently place data with different semantics (e.g., write log data, read cache data, and data with different lifecycles) into optimal physical areas within the flash memory (e.g., different reclaim units), further reducing garbage collection interference and write amplification.

[0099] Traditional solid-state drive (SSD) firmware is like a diligent but inconsiderate warehouse manager. It cares only about the mapping between logical block addresses (LBAs) and physical flash memory locations, but has little knowledge of the stored data's content (i.e., the data's "semantics"). All data, regardless of its nature, is treated equally and randomly intermixed within physical flash blocks. When garbage collection (GC) is needed to free up space, the firmware relies solely on low-level physical information (such as the ratio of valid to invalid data within a block) to make decisions, failing to leverage more valuable higher-level data characteristics.

[0100] Data semantics is about unlocking key information for efficient storage.

[0101] However, different types of data are born with different "characters" and "destinies", which are their semantic information: such as life cycle, access mode, size, shape and "gang" characteristics.

[0102] Lifetime: Some data is as short-lived as a meteor (such as temporary caches and session logs) and will soon become invalid; some data is as persistent as a rock (such as user configuration and core records).

[0103] Access Pattern: Some data is highly social, frequently read and written (hot data); others are rarely seen (cold data). Write patterns also vary, with some data being written sequentially (such as logs) and others being updated randomly at precise locations (such as database indexes).

[0104] Object Size: The system may process both "small and exquisite" (small objects) and "large and bulky" (large objects) data.

[0105] "Invalidation Correlation" feature: Some data blocks have a natural tendency to "live and die together". For example, all cached data belonging to the same user session will often become invalid together.

[0106] The goal of intelligent placement: like attracts like, and efficient recycling.

[0107] If the SSD firmware could "understand" these data semantics and intelligently cluster data with similar characteristics (especially similar lifespans) in physically adjacent or related flash memory areas, it would bring huge benefits. Imagine placing all short-lived data in the same physical block. When they collectively "die," reclaiming the block becomes incredibly easy and efficient, as there is almost no "live" data to laboriously relocate. This is the core goal of intelligent data placement: maximizing garbage collection efficiency.

[0108] Technology Implementation: Host-guided, firmware-implemented Flexible Data Placement (FDP) upgrade.

[0109] To achieve this goal, this application draws on and extends the Flexible Data Placement (FDP) mechanism in the NVMe standard:

[0110] Basic Framework (Integrated FDP): This application utilizes the Reclaim Unit (RU) provided by the FDP as the basic management unit for physical placement. The SSD firmware divides the internal flash memory resources into multiple RUs. The host can use the Reclaim Unit Handle (RUH) to suggest which logical grouping data should be placed in.

[0111] Core Upgrade (Extended - Semantic Awareness): Unlike traditional FDP, which mainly relies on the host to explicitly specify the RUH, the solution of this application goes a step further: including the host providing "semantic hints" and firmware intelligent decision-making.

[0112] The host provides "semantic hints" primarily by allowing the host operating system 20 or application to attach "semantic hints" describing data characteristics when writing data (whether byte-wise or block-wise) through the "unified abstract interface layer" designed in this application. These hints are higher-level information, such as:

[0113] Lifetime: short / long (LIFETIME_SHORT / LONG).

[0114] Access temperature: hot / cold (ACCESS_HOT / COLD).

[0115] Write mode: sequential / random (STREAM_SEQUENTIAL / RANDOM).

[0116] Object size: small / large (OBJECT_SMALL / LARGE).

[0117] Even application-defined tags, such as cache metadata, user session X data, etc.

[0118] Intelligent firmware decision-making is primarily reflected in the fact that after receiving these prompts, the CMS-SSD firmware doesn't blindly execute them. Instead, it comprehensively considers the host's intent (semantic prompts) and its own internal state (such as cache / log status, wear and free space on each RU, and current GC pressure) to intelligently determine the most appropriate physical RU to place data on.

[0119] Host "guides" rather than "forces": In this model, the host acts as an information provider and advisor, conveying high-level semantics to the firmware. The final physical placement decision remains with the firmware. This leverages the host's application-layer knowledge while avoiding the risks and complexity of having the host directly manage the complexities of underlying flash memory.

[0120] Smart placement in action:

[0121] When the CMS-SSD firmware needs to write data in the internal DRAM cache (whether it is a page merged after write log or a modified read cache page) back to the flash memory, its decision engine will:

[0122] Interpretation hints: View the semantic hints associated with this data page.

[0123] Evaluate status: Combine internal cache, logs, and the health status of each RU.

[0124] Execution strategy: For example, a page with a LIFETIME_SHORT hint? Put it in the reserved RU that is easy to reclaim quickly.

[0125] For ACCESS_HOT pages, if they must be written back, they are placed in the flash memory area with the best performance first, and are considered to be read back into the cache as soon as possible.

[0126] For pages from the same application with the USER_SESSION_X tag, aggregate them into the same or adjacent RUs to increase the possibility of them failing together in the future.

[0127] For a page generated by log merging, its "destination" is determined based on the most important semantic hints of the log entries contained in the page.

[0128] Collaboration with internal cache / logging:

[0129] Intelligent placement primarily occurs at the backend of the data flow—when data is persisted from internal DRAM to flash memory. It works in tandem with the frontend write log and read cache mechanisms that quickly respond to host requests. While the frontend mechanisms address real-time access and granularity mismatches, backend intelligent placement focuses on optimizing long-term data storage efficiency and management costs.

[0130] The core contributions to overcoming impedance mismatch are as follows:

[0131] The semantically aware and flexible data placement mechanism provides powerful backend support for overcoming multiple impedance mismatch issues:

[0132] The performance contributions are as follows:

[0133] Reduce GC interference and tame long-tail latency: Through efficient GC, its interference with normal read and write operations is significantly reduced, reducing performance jitter and unpredictable long-tail latency.

[0134] Improved sustained write capabilities: Faster space recovery means better support for high-intensity sustained write loads.

[0135] The contributions at the cost level are as follows:

[0136] Sharply reducing write amplification and extending SSD lifespan: This is the core value. Intelligent placement is one of the fundamental means of reducing write amplification to near 1. Extremely low write amplification means significantly slower wear on flash media, significantly extending SSD lifespan, thereby reducing device replacement costs and total cost of ownership (TCO).

[0137] Reduced physical redundancy requirements: Efficient GC may eliminate the need for large internal over-provisioning to maintain performance, which can theoretically reduce the manufacturing cost of physical flash memory.

[0138] The contributions to energy efficiency are as follows:

[0139] Reduced GC energy consumption: Fewer internal data transfers and flash memory erase and write operations directly reduce the energy consumed by the device during background self-maintenance.

[0140] Increased idle time: Reducing GC interference allows the device to enter a low-power idle state faster and more frequently, reducing overall operating power consumption.

[0141] The contributions of intelligent processing are as follows:

[0142] Providing physical data insights: The firmware internally understands the correlation between data semantics and physical layout. This provides valuable context for future, more intelligent internal computing engines. For example, computing tasks can be prioritized and executed on RUs containing relevant semantic data.

[0143] Drive smart caching / prefetching: Firmware can leverage semantic hints to optimize internal read cache management strategies, for example, to more intelligently prefetch data pages with the same semantic tags.

[0144] In summary, "semantically aware flexible data placement" is the key backend engine for achieving high performance, high efficiency, and long lifespan in CMS-SSDs. It transcends the "blind" storage model of traditional SSDs by intelligently planning data placement on the physical flash media by leveraging upper-layer data semantics provided by the host and combining it with the firmware's own internal state awareness. Its core goal is to maximize garbage collection efficiency by "grouping like" (particularly by lifecycle). This mechanism directly contributes to significantly reducing write amplification (thus improving performance, extending lifespan, and reducing costs), reducing GC interference (improving latency and stability), and lowering device energy consumption. It works closely with the front-end's internal caching / logging mechanisms, forming a powerful solution to overcome the multiple impedance mismatch issues of traditional storage.

[0145] The embedded computing engine 14 is used to perform hardware acceleration for specific tasks; wherein the specific tasks include at least one of data compression / decompression, data encryption / decryption, data filtering / aggregation, index assistance, and format conversion.

[0146] Embedded specialized computing engines primarily involve integrating lightweight, programmable specialized computing units (such as small field-programmable gate arrays (FPGAs) or application-specific integrated circuit (ASIC) cores) into the SSD controller. These engines are not general-purpose processors, but rather provide hardware acceleration for specific tasks (such as data compression / decompression, encryption / decryption, filtering / aggregation, indexing assistance, and format conversion).

[0147] The host operating system 20 is connected to the computational memory semantic solid-state drive 10, and is used to receive long-delay prompts sent by the computational memory semantic solid-state drive 10 and perform context switching; and a unified abstract interface layer is set up to uniformly manage byte-granularity memory access to the computational memory semantic solid-state drive 10, the delivery of data placement semantic prompts, and the submission of offload task requests to the embedded computing engine 14, as well as the setting of a semantic-aware intelligent scheduling and offload decision-making mechanism.

[0148] In some embodiments, the unified abstract interface layer primarily provides a high-level software library, drawing on xNVMe. This library shields complex hardware details from upper-layer applications and uniformly manages byte-granular memory access to the computational memory semantic SSD 10, the delivery of data placement semantic hints, and the submission of offload task requests to the embedded computing engine 14.

[0149] The "Intelligent Storage Integrated Memory Storage Architecture 100" and its core hardware, the "Computational Memory Semantic Solid-State Drive 10 (CMS-SSD)," undoubtedly bring unprecedented power, but also introduce significant underlying complexity. These complexities are reflected in:

[0150] New access method: Instead of a single block device, it supports byte-granularity access (load / store instructions) with memory semantics through Compute Express Link (CXL).

[0151] New control dimension: Added the ability to provide semantic hints for data placement, requiring upper-layer software (application or operating system) to pass information about data lifecycle, access mode, etc. to the firmware.

[0152] New computing paradigm: The integration of an embedded computing engine 14 provides the possibility of offloading computing tasks to the storage device for execution, which requires corresponding task submission and management interfaces.

[0153] Potential cooperative details: While cooperative context switching is primarily handled by the operating system and firmware, upper-level software libraries may need to provide configuration options or status query interfaces to optimize their behavior.

[0154] Requiring every application developer to directly understand and manipulate these underlying hardware details—for example, delving into the CXL protocol, mastering flash media characteristics, adapting to specific firmware interfaces, and learning the instruction set of the embedded computing engine14—would undoubtedly create an extremely high technical barrier to entry. This would significantly hinder the promotion and application of this advanced hardware technology, hindering its potential from being translated into real productivity.

[0155] Solution: Build a "translator" that masks complexity.

[0156] To solve this problem, this application must build a bridge between complex hardware and upper-layer applications. This is called a "Uniform Abstract Interface Layer." This interface layer typically exists in the form of a software library (for example, a .so file in Linux or a .dll file in Windows). Its core goals are:

[0157] Encapsulate low-level details: Encapsulate all complex operations related to specific hardware implementations (such as CXL protocol interaction, firmware command encoding, memory mapping management, task packaging, etc.) within the library.

[0158] Provides a stable and easy-to-use API: This provides upper-level applications with a set of high-level, semantically clear, stable, and easy-to-use function or method calls. Application developers only need to learn and use this standard API to leverage CMS-SSD's advanced features.

[0159] Ensure portability: Ideally, this interface should be cross-platform or cross-vendor CMS-SSD hardware (if the hardware follows a common specification). Applications only need to be programmed against this interface to run on different compatible hardware, without having to rewrite code for each hardware type.

[0160] Learning from and surpassing: Starting from the successful experience of xNVMe.

[0161] The xNVMe project provided valuable experience for this application. It successfully provided a unified API for previously fragmented NVMe storage access paths (such as the traditional POSIX interface, asynchronous libaio / io_uring, and user-mode SPDK). The ingenuity of xNVMe lies in that it does not forcibly introduce a new abstraction layer. Instead, it acts as a flexible "adapter," intelligently mapping upper-layer unified calls to the optimal underlying I / O path currently available on the system or specified by the user, while maintaining extremely low performance overhead.

[0162] This application's "unified abstract interface layer" draws on the principles of xNVMe—providing a unified API, masking underlying differences, maintaining flexibility, and maintaining low overhead. However, this application presents a greater challenge, as it requires managing not only different I / O paths but also three new dimensions: memory access semantics, data placement semantics, and the management of compute offload tasks.

[0163] The functions of the unified abstract interface layer are detailed as follows:

[0164] This software library needs to have the following core functions: unified access interface, management of data placement semantic hints, management of computational offload tasks, and device feature query and configuration.

[0165] The unified access interface is mainly reflected in:

[0166] Memory semantics interface: This interface provides interfaces similar to standard memory operations (such as memcpy), pointer access, or higher-level data structure interfaces (for example, a CMS-SSD-aware persistent key-value store). The underlying library automatically translates these operations into efficient CXL load / store instructions to access CMS-SSD regions mapped into memory space. It handles details such as address translation and necessary cache synchronization.

[0167] (Optional) Block Interface Compatibility: To facilitate the migration of legacy applications, the library can also provide a traditional block-based read / write interface. The underlying interface is still accessed through CXL, but the semantics of block devices are simulated to ensure compatibility.

[0168] The management of data placement semantic hints is mainly reflected in:

[0169] Standardization tip: Define a set of clear, application-specific semantic labels (e.g., “temporary data,” “hot data,” “archived data,” etc.).

[0170] API Integration: Provides a concise API that allows applications to easily attach these semantic tags when performing write operations, for example, write_with_hint(address, data, size, HINT_TEMPORARY | HINT_HOT);.

[0171] Low-level delivery: The library is responsible for translating these high-level semantic labels into low-level signals that the CMS-SSD firmware can understand (perhaps through specific CXL messages, register writes, or other mechanisms).

[0172] The management of computation offloading tasks is mainly reflected in:

[0173] Task description and submission: Provides an API that allows applications to clearly describe the computing tasks they want to offload (for example, specifying the firmware built-in function ID to be executed, the address and size of input / output data on the CMS-SSD, and other specific parameters) and submit the tasks to the library.

[0174] Interface encapsulation: The library is responsible for packaging the application layer’s task requests into a command format that complies with the CMS-SSD Embedded Computing Engine 14 interface specification and sending it to the device through the appropriate CXL channel (which may be CXL.io or a specific “doorbell” mechanism).

[0175] Result acquisition and synchronization: Provide synchronous or asynchronous APIs to wait for calculation completion, obtain result data, and handle possible errors.

[0176] Device feature query and configuration are mainly reflected in:

[0177] Capability discovery: Provides an API that allows applications to query the specific capabilities of the connected CMS-SSD hardware (for example, which data placement semantic tags are supported, which computing acceleration functions are available, how large the internal cache is, etc.).

[0178] Behavior configuration: allows applications or system administrators to configure some default behaviors of the library (for example, default data placement strategy, priority of computing tasks, etc.).

[0179] The implementation considerations are as follows:

[0180] Form: Usually a user-mode shared library or static library to facilitate application linking and deployment.

[0181] Interaction: It may be necessary to communicate with specific device drivers in the operating system kernel (for resource management, interrupt handling, etc.), or in specific scenarios (if permissions and design allow), directly interact with the hardware through user-mode driver mechanisms (such as UIO, VFIO).

[0182] Intelligence: The library itself can detect hardware characteristics at runtime and dynamically select the optimal underlying execution path based on system load and configuration, achieving a certain degree of adaptive optimization.

[0183] The core contributions to overcoming impedance mismatch are as follows:

[0184] The "unified abstract interface layer" plays a vital enabling and catalytic role in overcoming multiple impedance mismatches: mainly in performance impedance mismatch (indirect contribution), cost impedance mismatch (core contribution), energy efficiency impedance mismatch (indirect contribution) and intelligent processing impedance mismatch (core contribution).

[0185] The performance impedance mismatch (indirect contribution) is mainly reflected in: by simplifying the use of underlying high-performance features (such as low-latency byte access and computational offloading), application developers can more easily and widely integrate these features into applications, thereby fully unleashing the potential of the hardware and indirectly overcoming the performance bottleneck caused by using traditional interfaces to access new hardware.

[0186] Cost impedance mismatch (core contribution) is mainly reflected in:

[0187] Significantly reduces software costs: This is the most direct and important contribution. It frees developers from the arduous task of adapting to the underlying hardware, significantly reducing the cost of developing, testing, debugging, and maintaining the software required to support this new hardware.

[0188] Promoting the ecosystem and reducing hardware costs: Standardized or widely adopted interfaces can promote competition and interoperability among hardware manufacturers, accelerate the maturity of the ecosystem, and ultimately reduce the cost of the hardware itself through economies of scale and competition.

[0189] The energy efficiency impedance mismatch (indirect contribution) is mainly reflected in: by simplifying the call of energy-saving features such as computational offloading, it makes it easier for applications to build and deploy more energy-efficient systems.

[0190] Intelligent handling of impedance mismatch (core contribution) is primarily reflected in: Providing a standardized intelligent entry point: This provides applications with a stable, easy-to-use "call entry point" to access the intelligent processing capabilities (computation offload) embedded in storage devices. This makes it more realistic and efficient to deeply integrate intelligent computing into storage-intensive applications.

[0191] In short, the "Uniform Abstract Interface Layer" plays the indispensable role of "translator" and "adapter" connecting upper-layer application software with the underlying complex and innovative hardware. By providing a set of carefully designed high-level, stable, and easy-to-use APIs, it effectively shields the underlying complexity of accessing memory semantic storage, delivering data placement hints, and managing computational offload tasks. Its core value lies in greatly reducing the threshold and cost of software development and adaptation, and improving the availability and portability of the system. This enables the revolutionary performance, cost, energy efficiency, and intelligent advantages brought by the "Intelligent Storage Integrated Memory Storage Architecture 100" to be truly adopted and utilized by a wide range of applications, and is the key software infrastructure that drives the development and maturity of the entire technology ecosystem.

[0192] See Figure 3 The host operating system 20 includes: a collaborative context switching module 21 and a semantic-aware intelligent scheduling and offloading decision mechanism module 22.

[0193] The collaborative context switching module 21 is used to receive the long delay prompt sent by the computational memory semantic solid state drive 10 and perform context switching.

[0194] In some embodiments, collaborative context switching (OS level): When the computational memory semantic SSD 10 firmware predicts that access will encounter significant delays (such as flash memory access or internal computing tasks), it sends a "long delay hint" to the host via an extended CXL response, triggering the operating system to perform opportunistic context switching, effectively hiding the delay.

[0195] In traditional computing models, when a central processing unit (CPU) executes a memory-access instruction (such as a load or store), if the required data is not in the cache, the CPU's execution pipeline typically stalls, passively waiting for the data to be returned from main memory (such as dynamic random access memory, DRAM). While this waiting time exists, it is relatively manageable.

[0196] However, the situation changes fundamentally when this application introduces new types of storage devices, such as computational memory semantic solid-state drives (CMS-SSDs). While these devices provide memory access semantics through interfaces like Compute Express Link (CXL), allowing the CPU to access it like memory, the physical latency of their underlying technologies (such as flash memory access or internal embedded computing) is much higher than that of DRAM. This means that if an access request fails to hit the CMS-SSD's internal cache (such as its own DRAM), the CPU may face extremely long pauses.

[0197] A more complex problem is that this "memory-like" access via CXL.mem is transparent to traditional operating systems. Unlike traditional driver- and interrupt-based block device I / O, the operating system cannot proactively detect this potentially long latency. Therefore, it cannot proactively context switch and allocate CPU resources to other ready threads when I / O waits are detected. As a result, the CPU core appears to be "stuck" on the CMS-SSD memory access instruction, wasting valuable computing cycles.

[0198] Based on this, this application proposes a "tacit" collaboration between the operating system and the solid-state drive.

[0199] The "cooperative context switching" mechanism is designed to overcome this dilemma. It establishes an innovative collaborative channel between the operating system and the firmware of the computational memory-semantic SSD 10. Its core concept is to have the firmware, which best understands its own state, proactively send a "warning signal" to the host when it foresees an impending long-latency operation. The operating system then interprets this signal as an opportunity to perform a task switch, effectively utilizing time that would otherwise be wasted due to CPU stalls to perform other computational tasks. This effectively conceals the long latency of memory-semantic storage accesses.

[0200] Technical implementation process:

[0201] The specific implementation process of this cross-layer collaboration mechanism is as follows:

[0202] The process of firmware prediction and issuing "long delay prompt" is as follows:

[0203] Timing: When the host CPU sends a memory access request to the CMS-SSD through CXL.mem.

[0204] Prediction: The CMS-SSD firmware quickly checks internal status (such as cache hit, flash queue status, background task status, and whether internal calculations need to be started) to estimate the time required to process the request.

[0205] Decision-making and Signaling: If the firmware predicts that latency will significantly exceed a pre-set threshold (typically equivalent to the time required for a host context switch), it does not wait for the operation to complete before returning data as usual. Instead, it immediately sends a special "no data response" message back to the host via the CXL.mem protocol. The key to this message is the embedded "long latency indication." This signal means, "The request was received, but it will take some time to process. Please note, host."

[0206] The host receives the signal and triggers the hardware abnormality as follows:

[0207] Receive: The CXL controller on the host side receives this special response with the "long delay hint".

[0208] Notify Core: The CXL controller associates this signal to the CPU core that originally issued the request.

[0209] Precise triggering: When the CPU core prepares to "retire" the load / store instruction that causes long latency access (this is done to avoid incorrectly handling speculatively executed instructions), it recognizes this "long latency hint" signal and triggers a specific type of hardware exception (called a "CXL long latency exception"). This exception mechanism ensures that the application can accurately locate the instruction that causes the problem.

[0210] The operating system takeover process is as follows: The exception handling and task switching process is as follows:

[0211] Exception response: The processor pre-registered by the operating system for this new exception is activated and takes over CPU control.

[0212] State save and yield: The exception handler quickly saves the complete execution context (register state, instruction pointer, etc.) of the currently interrupted thread, marks it as "waiting for long-latency store response", and then removes it from the CPU's run queue.

[0213] Opportunistic Scheduling: The exception handler then calls the operating system scheduler. The scheduler is aware that the current thread is paused due to a long external delay and can immediately select another thread with the highest priority from the ready queue to run, maximizing CPU utilization.

[0214] The task recovery and access retry process is as follows:

[0215] Background processing: Meanwhile, the CMS-SSD continues to perform the time-consuming operation (e.g., reading flash memory or performing internal calculations) undisturbed in the background.

[0216] Data ready: When the operation is completed and the data is ready, the CMS-SSD sends a standard memory data response to the host through CXL.mem.

[0217] Thread wakeup and retry: When the OS scheduler decides to rerun a previously interrupted thread, it restores the thread's context and redirects execution back to the load / store instruction that caused the exception. The thread resumes execution from that instruction. Because the required data is likely already prepared by the CMS-SSD and cached in the CPU cache, host memory, or the CMS-SSD's internal DRAM, this memory access completes very quickly, eliminating the long-latency exception and allowing the thread to continue executing seamlessly.

[0218] The core contributions to overcoming impedance mismatch are as follows:

[0219] The "cooperative context switching" mechanism makes a key contribution to overcoming the impedance mismatch problem of traditional tiered storage through the above-mentioned sophisticated cross-layer collaboration:

[0220] The contribution of impedance mismatch to performance is:

[0221] Hiding Long-Tail Latency: This is a key contribution. It converts long access latencies (whether for flash reads or writes or internal computations) that would otherwise cause prolonged CPU pauses into time windows for running other threads, significantly improving effective CPU utilization and overall system throughput. For applications that require fast response times, this significantly improves the user experience.

[0222] Improving Concurrency Efficiency: This allows multiple threads to access the CMS-SSD concurrently and more easily. Waiting for one thread does not block other threads from using the CPU, while other threads can continue to issue requests to the CMS-SSD, helping to fully utilize the device's internal parallelism and CXL link bandwidth.

[0223] The contribution of cost impedance mismatch is:

[0224] Enhancing Hardware Value: By reducing the ineffective waiting time of the CPU, the actual utilization efficiency of expensive CPU resources is improved, making the overall system hardware investment return higher.

[0225] The contribution of energy-efficient impedance mismatch lies in: Reducing CPU Idle Power: It avoids the CPU idling or inefficient waiting during long delays, reducing this part of energy consumption and helping to improve the performance per watt of the entire system.

[0226] Intelligent handling of impedance mismatch contributes to enabling longer in-storage computations. This mechanism not only hides data access latency but also the latency associated with executing lengthy computations in the CMS-SSD's embedded compute engine 14. This provides critical latency tolerance for offloading more complex computations (such as data preprocessing, compression, and partial query logic) to the storage device. This allows the host CPU to work asynchronously with the device's internal compute engine, fully leveraging the advantages of "intelligent storage integration."

[0227] In summary, "cooperative context switching" is a key technology for achieving the high-performance, high-efficiency "Intelligent Storage Integrated Memory Storage Architecture 100." It's more than a simple task switch; rather, it's an intelligent latency-hiding mechanism based on device prediction and system collaboration. It leverages extended interconnect protocol signals and specific hardware exceptions as an information bridge to precisely transform the inevitable long latency associated with accessing memory semantic storage into "golden time" for efficient operating system scheduling, thereby systematically alleviating the constraints that storage latency places on CPU performance, energy efficiency, and intelligent potential.

[0228] The semantically aware intelligent scheduling and offloading decision mechanism module 22 is used to make data placement decisions, computation offloading decisions, and task collaboration.

[0229] See Figure 4 The semantic-aware intelligent scheduling and offloading decision mechanism module 22 includes: a data placement decision unit 221, a computation offloading decision unit 222 and a task coordination unit 223.

[0230] After making a data placement decision, the data placement decision unit 221 generates corresponding semantic hints and transmits them to the computational memory semantic solid-state drive 10. The data placement decision unit 221 makes data placement decisions based on explicit application instructions, runtime intelligent analysis, and system status feedback.

[0231] The computation offloading decision unit 222 is used to identify tasks suitable for offloading to the embedded computing engine 14 and submit the tasks through a unified interface. The computation offloading decision unit 222 is used to offload tasks based on task characteristic analysis, system real-time status, and / or performance / energy efficiency modeling.

[0232] The task coordination unit 223 is used to coordinate the execution of tasks between the host and the embedded computing engine 14. The task coordination unit 223 is used to adopt pre-processing / post-processing, pipeline operation and / or asynchronous execution coordination modes.

[0233] In some embodiments, semantically aware intelligent scheduling and offloading decisions (OS / runtime level): The operating system or runtime system (which may incorporate application-level hints or online profiling) is responsible for:

[0234] Data placement decision: Decide which data resides in host memory and which resides in CMS-SSD, and generate corresponding semantic hints to pass to the firmware.

[0235] Computation offloading decision: Identify tasks that are suitable for offloading to the CMS-SSD embedded computing engine 14 (for example, those with strong data locality, computationally intensive and parallelizable, and involving a large amount of storage IO), and submit the tasks through a unified interface.

[0236] Task collaboration: Coordinates task execution between the host CPU and the CMS-SSD embedded computing engine 14. For example, the host handles control flow and complex logic, and the CMS-SSD handles data-intensive computing.

[0237] When this application combines high-speed host memory (DRAM) with a computational memory semantic solid-state drive 10 (CMS-SSD) with memory access capabilities, massive capacity, and embedded computing power, the system becomes a powerful heterogeneous memory / storage architecture. However, mastering this architecture is not easy. Simply piling all data on the CMS-SSD or relying entirely on application developers to manually move data between DRAM and the CMS-SSD fails to fully realize its potential and may increase development complexity and even lead to performance degradation. Similarly, given the embedded computing power provided by the CMS-SSD, how to wisely decide which computing tasks should be handled by the traditional host CPU and which should be "sunk" to the storage device for execution has become a critical optimization challenge.

[0238] Core concept: Let the system better understand the application and optimize automatically.

[0239] The "semantically aware intelligent scheduling and offload decision-making" mechanism is designed to address these challenges. It serves as the "intelligent brain" and "command center" of the entire "Intelligent Storage Integrated Memory Storage Architecture 100." Its core mission is to leverage deeper information (i.e., "semantics") to dynamically and automatically optimize two key aspects through the operating system (OS) or application-specific runtime:

[0240] Where should data be placed? (Smart Data Placement)

[0241] Where should the computation be performed? (Intelligent Compute Offloading)

[0242] The goal is to maximize the performance, energy efficiency, and resource utilization of the entire system. The key here is "semantic awareness"—the decision-making process no longer relies solely on underlying physical indicators (such as access speed and bandwidth utilization), but instead deeply understands and utilizes the data characteristics of upper-level applications and the intention information of computing tasks.

[0243] Decision executors: collaboration between the operating system and the runtime system.

[0244] This "smart brain" can work on two levels:

[0245] The operating system (OS) layer maintains a global view of resource usage across all processes in the system. It can formulate global data placement and task offloading policies, which are relatively transparent to applications. However, this typically requires modifying the OS kernel and may lack a detailed understanding of the internal logic of specific applications.

[0246] Runtime systems, such as the Java Virtual Machine (JVM), database management systems (DBMS), big data processing frameworks (such as Spark), and machine learning frameworks (such as TensorFlow), have a deeper understanding of the data structures they manage and the computational models they execute. Therefore, they can make more precise optimization decisions that better suit application needs. However, this typically requires development for different runtime environments.

[0247] In practice, a hybrid model may be the most effective: the operating system provides the basic resource management and scheduling framework, while the runtime system provides more specific application semantic information and optimization suggestions, and the two work together.

[0248] The specific content and execution of intelligent decision-making include: intelligent data placement, intelligent computing offloading and task collaboration.

[0249] The contents of intelligent data placement are as follows:

[0250] The goal: Put the "right data" in the "right place." The core principle is to prioritize placing the most frequently accessed, latency-sensitive "hot" data in the fastest host DRAM; while placing less frequently accessed, bulky, or latency-insensitive "cold" data in the lower-cost, higher-capacity CMS-SSD.

[0251] Decision-making basis:

[0252] Application Hints: Application developers can use a unified interface (such as the aforementioned software library API) to directly "tell" the system which data is critical hotspot and which is suitable for long-term storage in CMS-SSD.

[0253] Runtime Intelligent Profiling (Online Profiling): The system automatically monitors data access patterns at runtime, such as access frequency and recency: tracking which memory pages are frequently accessed and which have been accessed recently (similar to the principle of cache eviction algorithm).

[0254] Dynamic "temperature" identification: Based on historical access records, dynamically "label" data to distinguish hot data from cold data.

[0255] System status feedback: Dynamically adjust strategies based on current system resources (such as whether DRAM is tight or CMS-SSD access is congested).

[0256] Implementation methods include:

[0257] Transparent Page Migration: Once a decision is made, the system (OS or Runtime) automatically migrates the selected data pages between DRAM and CMS-SSD and updates the corresponding address mapping (such as page tables), keeping it as transparent as possible to upper-layer applications.

[0258] Guiding firmware optimization: When deciding data placement (especially data newly allocated or written to the CMS-SSD), the system generates corresponding semantic hints (such as "hot data," "temporary data," etc.) and passes them to the CMS-SSD firmware through an interface, allowing the firmware to perform optimizations at the physical storage level (such as placing hot data in a better-performing flash area).

[0259] The contents of intelligent computing offloading are as follows:

[0260] The goal: to assign computing tasks to the computing unit best suited to perform them—be it a powerful but general-purpose host CPU or a CMS-SSD embedded engine close to the data, possibly with specialized acceleration capabilities—to achieve optimal performance or energy efficiency.

[0261] Decision-making basis:

[0262] Task characteristic analysis: Understand the characteristics of the computing task itself: Data locality: Where is the data that the computing task needs to process primarily stored? If a large amount of data is on CMS-SSD, offloading it can reduce data movement.

[0263] Computational complexity and type: Is the task compute-intensive or I / O-intensive? Can its computational pattern (such as simple filtering, aggregation, encryption, decryption, and compression) be efficiently accelerated by CMS-SSD's dedicated computing engine?

[0264] Parallel potential: Is the task suitable for parallel processing and can it utilize the parallel computing resources within CMS-SSD?

[0265] Real-time system status: Whether the host CPU is currently busy. Whether the CMS-SSD computing engine is idle. Whether the CXL link bandwidth is sufficient.

[0266] (Optional) Performance / energy efficiency modeling: Use simple models to estimate the time and energy consumption of tasks executed in different locations, helping to make optimal decisions.

[0267] Implementation methods include:

[0268] Task identification: Identify candidate computing tasks suitable for offloading through compile-time analysis, explicit marking by developers (using specific APIs), or dynamic detection at runtime.

[0269] Submit for execution: Once the decision to offload is made, the system calls the unified interface API to submit the task description and required data information (usually the address of the data on the CMS-SSD) to the CMS-SSD for execution.

[0270] The content of task coordination is as follows:

[0271] Goal: Ensure that the host CPU and CMS-SSD computing engine can correctly and efficiently divide the work and collaborate to complete a complex application logic.

[0272] Common collaboration modes: Pre-processing / post-processing: The host is responsible for data preparation and task control, calling CMS-SSD to perform core calculations, and then retrieving the results for subsequent processing.

[0273] Pipeline operation: The data flow passes through the host (for complex logical judgment) and CMS-SSD (for data-intensive processing) in sequence.

[0274] Asynchronous execution: After the host submits a task, there is no need to wait and it can continue to process other transactions and obtain the results later through callbacks or polling.

[0275] The supporting mechanisms are as follows:

[0276] Dependency management: The system needs to manage the dependencies between host tasks and offloaded tasks to ensure the correct execution order (for example, using synchronization mechanisms such as semaphores, Future / Promise, etc.).

[0277] Data sharing and consistency: The hardware cache consistency provided by CXL.mem is fundamental. More advanced memory allocation and synchronization services may also be required at the system level to ensure application data correctness.

[0278] Control flow coordination: The host CPU usually leads the control flow of the entire application and decides the next action based on the execution status and results of the CMS-SSD task.

[0279] The core contribution to overcoming impedance mismatch: "Semantic-aware intelligent scheduling and offloading decision-making" is the key driving force for overcoming multiple impedance mismatch problems:

[0280] The contributions of performance impedance mismatch are: minimizing access latency through intelligent data placement, leveraging dedicated hardware acceleration through computational offloading, and enabling parallel work between the host and device through task collaboration, thereby comprehensively improving system speed and throughput.

[0281] The contribution of cost-impedance mismatch is to maximize the value of DRAM and only use it to store the most critical hot data, so that a more economical DRAM configuration can be used with a large-capacity CMS-SSD to achieve the target performance, thereby reducing the overall hardware cost.

[0282] The contribution of energy-efficiency impedance mismatch lies in: Reducing data movement (a key effect of intelligent placement and computation offloading) is the primary way to reduce energy consumption. At the same time, assigning computational tasks to dedicated engines with higher energy efficiency further improves system energy efficiency.

[0283] The contribution of intelligent impedance mismatch handling lies in: Its core value lies in: It transforms the "near-data processing" process, which previously required developers to manage laboriously, into automated, intelligent decision-making and execution by the system. This significantly improves the practicality and efficiency of in-storage intelligent processing and paves the way for upper-layer applications to build more complex and innovative applications that leverage in-storage computing power.

[0284] In summary, the "semantically aware intelligent scheduling and offload decision-making" mechanism is the "intelligent brain" that enables the efficient operation of the "Intelligent Storage Integrated Memory Storage Architecture 100." By deeply understanding application-level information (semantics), it makes dynamic, intelligent decisions at the operating system or runtime level regarding data storage location and computation execution. This not only optimizes the utilization of heterogeneous resources, directly improving performance, reducing costs, and enhancing energy efficiency, but more importantly, it truly transforms the computing power embedded in storage into an easy-to-use, automatically optimized system-level capability, becoming the core software-enabling technology that enables the transition from "storage" to "intelligent storage."

[0285] The synergy mechanism and unexpected technical effects work together as follows:

[0286] Synergy between write logging and data placement: Fine-grained write logging naturally aggregates frequent small write operations, which not only reduces write amplification but also facilitates semantically aware data placement for firmware. For example, entire log segments can be placed in specific flash memory regions based on their lifecycle or access frequency.

[0287] Context Switching and Internal Cache Collaboration: The write log and read cache within the Computational Memory Semantics SSD 10 attempt to service requests first. Only when the internal cache misses and flash memory access or a lengthy computational task is required does a long latency prompt and potential context switch occur. This mechanism makes context switching a "last resort" rather than a frequent operation, improving switch effectiveness while the internal cache provides a first-tier, fast response.

[0288] Compute offload and data flow coordination: Firmware can leverage its knowledge of internal data layout (guided by placement hints) and cache state to optimize data access paths for offloaded tasks. For example, data can be compressed or filtered directly in the internal DRAM cache or write log, avoiding unnecessary flash reads and writes, something that traditional host CPUs cannot do.

[0289] Balance between unified interface and system complexity: Although the underlying hardware and firmware integrate multiple complex mechanisms (layered caching, data placement, computation offloading, and collaborative scheduling), the unified abstract interface layer provides a relatively concise and consistent view for upper-layer applications, lowering the threshold for development and use.

[0290] How do the various technologies in the "Intelligent Storage Integrated Memory Storage Architecture 100" contribute to overcoming the impedance mismatch issues faced by traditional tiered storage in four dimensions: performance (speed, latency), cost, energy efficiency, and intelligent processing?

[0291] 1. Overcome performance impedance mismatch.

[0292] Problem manifestations: A huge access latency gap between host memory (DRAM) and solid-state drives (SSDs); a bandwidth bottleneck between the host CPU and storage devices; performance jitter and long-tail latency caused by internal SSD operations (such as garbage collection); I / O amplification and inefficiency caused by the mismatch between byte access and page access granularity.

[0293] Technical contribution:

[0294] Unified computing expression link protocol interface and memory semantics: Providing a byte-granularity access interface reduces the protocol overhead and latency caused by traditional block interface conversion, making SSD access closer to memory semantics.

[0295] Internal intelligent tiering and granular management:

[0296] Write Logging: Absorbs byte write requests at speeds close to internal DRAM, significantly reducing write latency and eliminating the performance bottleneck of direct host writes to Flash. Background merging reduces the total number of writes and the amount of data written to Flash, mitigating the impact of write amplification on throughput.

[0297] Data cache: Caches hot data pages read from flash memory to reduce read latency.

[0298] Granularity management: Effectively bridges the host's byte access requirements and the flash memory's page access physical limitations at the firmware level, reducing inefficient I / O and performance loss caused by granularity mismatch.

[0299] Semantic-aware flexible data placement: By physically clustering data with similar lifecycles, garbage collection efficiency is significantly improved, the interference of garbage collection operations on foreground I / O is reduced, and performance jitter and long-tail latency are reduced.

[0300] Embedded dedicated computing engine: Offloads computing tasks to a location close to the data, reducing the latency of data traveling back and forth between the host and device, and improving the processing speed of specific computing tasks through dedicated hardware acceleration.

[0301] Cooperative context switching: Specifically targets unavoidable long delays (such as flash memory access and internal calculations), hides long-tail delays by switching CPU execution threads, and improves CPU utilization and system responsiveness.

[0302] 2. Overcome cost-impedance mismatch.

[0303] Problem manifestations: The cost per bit of DRAM is much higher than that of SSD; the large-capacity DRAM cache configured to compensate for the insufficient performance of SSD is expensive; SSDs require a large amount of internal over-provisioning and host-side over-provisioning to ensure performance and lifespan, which increases the actual cost of use; the cost of developing and adapting software for complex storage hierarchies is high.

[0304] Technical contribution:

[0305] Unified computing expression link protocol interface and memory semantics: This makes it possible to use lower-cost SSDs to expand memory capacity, reducing the high hardware costs associated with relying solely on DRAM expansion.

[0306] Semantic-aware flexible data placement: By significantly reducing write amplification, this significantly extends the lifespan of SSDs and reduces the frequency of device replacement. More importantly, it eliminates the need for significant host-side over-provisioning to achieve high performance, significantly improving the effective capacity-to-cost ratio of SSDs.

[0307] Unified abstract interface layer: reduces the development and maintenance costs of adapting applications to this new type of complex hardware and improves software portability.

[0308] Internal intelligent tiering and granular management: Reducing write amplification also indirectly extends SSD lifespan and reduces total cost of ownership (TCO).

[0309] 3. Overcome energy efficiency impedance mismatch.

[0310] Problem manifestations: Frequent data transfer between different storage tiers consumes a lot of energy; the host CPU performs storage-related calculations (such as compression and verification) that could be offloaded inefficiently and with high power consumption; inefficient garbage collection operations within the SSD increase device active time and consume more power; high write amplification leads to more flash memory write operations, increasing energy consumption.

[0311] Technical contribution:

[0312] Internal intelligent tiering and granularity management: The write log merging mechanism reduces the total amount and frequency of data ultimately written to the flash memory, thereby reducing flash write power consumption.

[0313] Semantic-aware flexible data placement: Efficient garbage collection reduces unnecessary internal data movement and flash memory erase and write times, lowering device operating power consumption.

[0314] Embedded dedicated computing engine: Offloads computing tasks to dedicated hardware with more optimized power consumption, reduces the energy consumption of data transmission across the CXL link, and improves computing energy efficiency.

[0315] Cooperative context switching: By improving CPU utilization when waiting for long delays, CPU idling is avoided, indirectly improving the overall energy efficiency of the system.

[0316] 4. Overcome impedance mismatch through intelligent processing.

[0317] Problem manifestation: Traditional storage devices are "passive". All data processing (such as filtering, aggregation, format conversion, encryption and decryption, compression and decompression) requires moving data to the host CPU, which limits the ability to process local data and increases latency and bandwidth consumption.

[0318] Technical contribution:

[0319] Embedded dedicated computing engines: These engines directly empower storage devices with inherent computing capabilities. These engines allow specific computing tasks (particularly those that are data-intensive and suitable for streaming or hardware acceleration) to be completed directly within the storage device, achieving the fusion of computing and storage.

[0320] Semantic-aware flexible data placement: This provides a foundation for optimization within the internal computing engine. For example, the firmware knows which data blocks contain specific types of data or recently accessed data, and can guide the computing engine to access and process this data more efficiently.

[0321] Semantic-aware intelligent scheduling and offload decisions: This provides a mechanism for effectively mapping application-level intelligent processing requirements to the CMS-SSD's embedded computing capabilities. This determines which computations should be performed close to the data, enabling an end-to-end intelligent processing flow.

[0322] Unified abstract interface layer: provides a standard way for upper-layer applications to call these storage-embedded intelligent processing functions.

[0323] Summary: The Smart Storage Integrated Memory Storage Architecture 100 systematically addresses the multiple impedance mismatches faced by traditional tiered storage in terms of performance, cost, energy efficiency, and intelligent processing through the synergistic effect of its various technical approaches. Rather than focusing on single-dimensional optimization, it leverages hardware innovation and software collaboration to build a new infrastructure layer that integrates memory and storage features, embeds intelligent computing capabilities, and enables adaptive optimization.

[0324] 4. Technical Effects / Results

[0325] The "Intelligent Storage Integrated Memory Storage Architecture 100" is expected to bring about the following creative and non-obvious comprehensive effects:

[0326] Extreme performance and capacity expansion: TB-level memory semantic capacity expansion is achieved through the computational expression link protocol. At the same time, internal intelligent caching, write log merging, collaborative context switching and computational offloading are utilized to significantly reduce access latency (especially write latency and long-tail read latency), improve effective throughput, and approach ideal memory performance.

[0327] Unprecedented Resource Efficiency: This significantly reduces device-level write amplification, ensuring performance and longevity without requiring large-scale host overprovisioning, significantly increasing the actual usable capacity and lifecycle of SSDs. Computational offload reduces host CPU load and data transfer overhead, significantly improving overall system energy efficiency.

[0328] Deeply intelligent data processing: Seamlessly embedding specific computing tasks (compression, encryption, filtering, preprocessing, etc.) into the storage access process realizes the true meaning of "computing close to data" and provides new optimization possibilities for upper-layer applications (such as databases, big data analysis, and artificial intelligence), such as executing some query predicates or data transformations directly in the storage layer.

[0329] The unity of adaptability and ease of use: The system can perform adaptive optimization (data placement, cache management, task scheduling) based on the data semantic hints and internal monitoring status provided by the application, while simplifying the development complexity of upper-level applications through a unified abstract interface.

[0330] Enhanced sustainability: By improving hardware utilization (reducing over-provisioning), extending device lifespan (reducing write amplification), and reducing overall energy consumption (reducing data movement and offloading computation).

[0331] Summary: This solution is more than a simple technology stack. Rather, it leverages the core innovation of the Computational Memory Semantic SSD 10, combined with deep software and hardware collaboration (OS, firmware, and runtime), to achieve unified and intelligent interfaces, data management, and computing paradigms. This approach aims to fundamentally address the multiple impedance mismatches between memory and storage, forming an efficient, intelligent, and adaptive memory-storage continuum. The close coordination of these technical approaches (such as logging and data placement, internal caching and context switching, and compute offloading and internal data flow) delivers systemic gains and unexpected synergies beyond the optimization of individual technologies.

[0332] In the several embodiments provided in this application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules or units is merely a logical functional division. In actual implementation, other division methods may be used, such as combining or integrating multiple units or components into another system, or ignoring or not implementing certain features.

[0333] If the integrated units in the other embodiments described above are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) or a processor to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program code, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0334] The above description is only an implementation method of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. An integrated memory storage architecture, characterized in that: The smart storage integrated memory storage architecture includes: A computational memory semantic solid-state drive comprises a unified interconnect and memory semantics module for providing a unified memory address space based on a computational expression link protocol, supporting byte-granularity access by a host through load / store instructions. The computational memory semantic solid-state drive also comprises an internal intelligent tiering and granularity management mechanism module, which is provided with an internal intelligent tiering and granularity management mechanism for constructing a fine-grained write log at the cache line granularity to absorb byte writes and reduce write amplification, maintaining a page-granularity read / data cache to exploit spatial locality, and managing log merging, garbage collection, and data flow between the internal cache and flash memory. The computational memory semantic solid-state drive also comprises a semantically-aware flexible data placement mechanism module, which is provided with a semantically-aware flexible data placement mechanism for utilizing data semantic hints to place data with different semantics into the optimal physical area within the flash memory, wherein the data semantic hints include at least one of data lifecycle, access pattern, hot / cold attribute, and object size category. The computational memory semantic solid-state drive also comprises an embedded computing engine for hardware acceleration of specific tasks, wherein the specific tasks include at least one of data compression / decompression, data encryption / decryption, data filtering / aggregation, index assistance, and format conversion. A host operating system is connected to the computational memory semantic solid-state drive and is used to receive long-latency prompts sent by the computational memory semantic solid-state drive and perform context switching; and a unified abstract interface layer is provided to uniformly manage byte-granularity memory access to the computational memory semantic solid-state drive, the transmission of data placement semantic prompts, and the submission of offload task requests to the embedded computing engine, as well as the provision of a semantically aware intelligent scheduling and offload decision-making mechanism.

2. The intelligent storage integrated memory storage architecture according to claim 1, characterized in that: The unified interconnect and memory semantics module is further configured to provide a logically continuous and extended physical address space to the host through CXL.mem mapping.

3. The integrated memory storage architecture according to claim 1, characterized in that: The internal intelligent tiering and granularity management mechanism module is also used to directly and quickly append data to the write log area of ​​the internal DRAM when the host issues a storage instruction of the cache line size, and to find the latest data copy of a specific address in the log through an optimized index structure; and the new write will logically overwrite the old version of the same address by updating the index.

4. The integrated memory storage architecture according to claim 1, characterized in that: When a host read request misses the write log and needs to obtain data from the flash memory, the internal intelligent tiering and granularity management mechanism module reads the entire flash memory page into the page granularity cache area, and then extracts the required cache line from it and returns it to the host; And when the data in the write log is processed in the background to form a complete data page ready to be written back to the flash memory, the data page will be temporarily stored in the page granularity cache area.

5. The intelligent storage integrated memory storage architecture according to claim 1, characterized in that: The semantically aware flexible data placement mechanism module utilizes the recycling unit provided by the flexible data placement mechanism in the NVMe standard as the basic management unit for physical placement.

6. The intelligent storage integrated memory storage architecture according to claim 1, characterized in that: The host operating system includes: A collaborative context switching module, configured to receive a long latency prompt sent by the computational memory semantic solid-state drive and perform context switching; The semantically aware intelligent scheduling and offloading decision mechanism module is used to make data placement decisions, computation offloading decisions, and task collaboration.

7. The integrated intelligence and storage memory storage architecture according to claim 6, characterized in that: The semantically aware intelligent scheduling and offloading decision-making mechanism module includes: The data placement decision unit is used to generate corresponding semantic hints and pass them to the computational memory semantic solid-state drive after making data placement decisions; The computing offloading decision unit is used to identify tasks suitable for offloading to the embedded computing engine and submit the tasks through a unified interface; The task coordination unit is used to coordinate the task execution between the host and the embedded computing engine.

8. The integrated intelligence and storage memory storage architecture according to claim 7, characterized in that: The data placement decision unit is used to make data placement decisions based on explicit instructions from applications, runtime intelligent analysis, and system status feedback; The computation offloading decision unit is used to perform task offloading based on task characteristic analysis, system real-time status and / or performance / energy efficiency modeling; The task coordination unit is configured to adopt a pre-processing / post-processing, pipeline operation and / or asynchronous execution coordination mode.

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