Simulation method, system and equipment and storage medium

Abstract

The embodiment of the invention relates to the technical field of power electronic simulation, and discloses a simulation method, system and device and a storage medium. The simulation method is applied to a field programmable logic gate array, and comprises the following steps: based on at least two paths of clock signals, sampling pulse signals to be measured respectively to obtain at least two paths of sampling data; according to the at least two paths of sampling data, feature data of the to-be-measured pulse signal are extracted, and the feature data are used for representing the to-be-measured pulse signal; and sending the feature data to a central processing unit, so that the central processing unit performs simulation calculation according to the feature data. The hardware capability requirement on the central processing unit in a high-frequency pulse signal simulation scene is at least reduced, so that the hardware complexity, the system design difficulty, the system power consumption and the system cost of a simulation system based on the central processing unit are reduced.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of power electronics simulation, and particularly to a simulation method, system, device, and storage medium. Background Art

[0002] Simulation refers to using a model to reproduce the essential processes occurring in an actual system and studying the existing or designed system through experiments on the system model, also known as "simulation". Currently, a large number of simulation test software or systems are built based on a Central Processing Unit (CPU).

[0003] However, in simulation scenarios involving high-frequency pulse signals, the simulation system based on the central processing unit has a high hardware complexity, a large system design difficulty, and high system power consumption and system cost. Summary of the Invention

[0004] The embodiments of the present application provide a simulation method, system, device, and storage medium, which are at least beneficial to reducing the hardware capability requirements for the central processing unit in high-frequency pulse signal simulation scenarios, thereby reducing the hardware complexity, system design difficulty, system power consumption, and system cost of the simulation system based on the central processing unit.

[0005] According to some embodiments of the present application, in a first aspect of the embodiments of the present application, a simulation method is provided, which is applied to a Field Programmable Gate Array (FPGA). The method includes: sampling a to-be-tested pulse signal based on at least two clock signals respectively to obtain at least two sets of sampling data; extracting characteristic data of the to-be-tested pulse signal according to the at least two sets of sampling data, where the characteristic data is used to characterize the to-be-tested pulse signal; and sending the characteristic data to a central processing unit for the central processing unit to perform simulation calculations according to the characteristic data.

[0006] In some embodiments, the extracting the characteristic data of the to-be-tested pulse signal according to the at least two sets of sampling data includes: merging and rearranging the data in the at least two sets of sampling data in sequence; and extracting the characteristic data of the at least two sets of sampling data according to the result of the merging and rearrangement.

[0007] In some embodiments, the characteristic data includes at least one of the following: the timestamp of the rising edge of the to-be-tested pulse signal, the timestamp of the falling edge of the to-be-tested pulse signal, the high-level and low-level durations of the to-be-tested pulse signal, and the frequency of the to-be-tested pulse signal.

[0008] In some embodiments, the at least two clock signals include: clock signals with the same frequency but different initial phases, and / or, clock signals with different frequencies.

[0009] In some embodiments, sending the feature data to the central processing unit includes: encapsulating the feature data according to a preset format; and sending the encapsulation result to the central processing unit through a high-speed data bus.

[0010] According to some embodiments of the present application, a second aspect of the embodiments of the present application further provides a simulation method, which is applied to a central processing unit. The method includes: receiving feature data sent by a field programmable gate array, where the feature data is sent by the field programmable gate array to the central processing unit according to the simulation method described in any one of the first aspect; and performing simulation calculations according to the feature data.

[0011] In some embodiments, the method further includes: generating and outputting a control signal according to the current simulation result, so that after the pulse signal to be measured is adjusted according to the control signal, simulation calculations are continued according to the feature data corresponding to the adjusted pulse signal to be measured received.

[0012] According to some embodiments of the present application, a third aspect of the embodiments of the present application further provides a simulation system, including: a field programmable gate array and a central processing unit, where the field programmable gate array and the central processing unit are connected at least through a high-speed data bus, the field programmable gate array is used to implement the simulation method described in any one of the first aspect, and the central processing unit is used to implement the simulation method described in any one of the second aspect.

[0013] According to some embodiments of the present application, a fourth aspect of the embodiments of the present application further provides a device, including: a device body; and the simulation system described in the third aspect provided on the device body; where the simulation system is used to receive an externally input pulse signal to be measured and perform simulation to output a simulation result.

[0014] According to some embodiments of the present application, a fifth aspect of the embodiments of the present application further provides a computer-readable storage medium, storing a computer program, where when the computer program is executed by a processor, it implements the simulation method described in any one of the first aspect, or implements the simulation method described in any one of the second aspect.

[0015] The technical solutions provided in the embodiments of the present application have at least the following advantages:

[0016] By sampling at least two clock signals, on the premise of ensuring accurate sampling of the pulse signal to be measured, the pulse signal to be measured can be sampled at a lower frequency, so as to obtain low-frequency sampling data. At the same time, through feature extraction of the sampling data, the frequency of the data is further reduced. In this way, the data frequency input to the central processor is relatively low, and the central processor can perform calculation processing at a relatively low frequency during simulation, reducing the hardware capability requirements of the central processor for simulating high-frequency pulse signals, thereby reducing the hardware complexity, system design difficulty, system power consumption and system cost of the simulation system based on the central processor. Description of the Drawings

[0017] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the drawings in the drawings do not constitute a proportional limitation.

[0018] Figure 1 is the flow of the simulation method applied to the field programmable gate array provided in the embodiments of the present application Figure 1 ;

[0019] Figure 2 is the flow of the simulation method applied to the field programmable gate array provided in the embodiments of the present application Figure 2 ;

[0020] Figure 3 is the flow of the simulation method applied to the field programmable gate array provided in the embodiments of the present application Figure 3 ;

[0021] Figure 4 is the flow of the simulation method applied to the central controller provided in the embodiments of the present application Figure 1 ;

[0022] Figure 5 is the flow of the simulation method applied to the central controller provided in the embodiments of the present application Figure 2 ;

[0023] Figure 6 is the structural schematic diagram of the simulation system provided in the embodiments of the present application. Detailed Embodiments

[0024] As can be seen from the background art, in the simulation scenario involving high-frequency pulse signals, the simulation system based on the central processor has problems such as high hardware complexity, great system design difficulty, high system power consumption and high system cost.

[0025] Upon analysis, it is found that the reasons for the above problems are at least as follows: in a simulation scenario involving high-frequency pulse signals, due to the bottleneck of signal sampling frequency and accuracy of a general central processing unit, it is unable to efficiently process high-frequency pulse signals. To solve this problem, usually the hardware capabilities of the central processing unit are improved to adapt to the data calculation and processing frequencies of high-frequency pulse signals. Taking an efficient DC-DC (Direct Current-Direct Current) converter as an example, it has important applications in the field of power electronics and is widely used in fields such as electric vehicles, power transmission, portable devices, and renewable energy systems. In these applications, the control accuracy of the DC-DC converter directly affects the stability and efficiency of the system. Especially in high-frequency switching modes (such as resonant converters or synchronous rectifier DC-DC converters), in relevant simulations, the sampling accuracy of the switching signal is crucial. In order to adapt to frequencies of these switching signals up to several hundred kHz or even higher, through design, a very high clock frequency is provided, which results in an increase in hardware complexity, an increase in system power consumption, an increase in design difficulty, and an increase in cost.

[0026] Based on this, in the embodiments of the present application, a simulation method, system, device, and storage medium are provided. Before the central processing unit in the system receives the pulse signal to be measured and conducts simulation, a Field Programmable Gate Array (FPGA) is introduced to process the pulse signal to be measured, so that the pulse signal to be measured processed by the field programmable gate array is converted into characteristic data with a lower frequency. Thus, the central processing unit no longer needs to be applicable to the calculation and processing of high-frequency data, reducing the requirements for the hardware capabilities of the central processing unit in the high-frequency pulse signal simulation scenario, and ultimately achieving the purpose of reducing the hardware complexity, system design difficulty, system power consumption, and system cost of the simulation system based on the central processing unit.

[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the following will elaborate on each embodiment of the present application with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in each embodiment of the present application, many technical details are proposed for the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0028] The division of the following various embodiments is for convenience of description and should not constitute any limitation to the specific implementation manner of the present application. The various embodiments can be combined and cross-referenced with each other on the premise of not being contradictory.

[0029] In the first aspect of the embodiments of the present application, a simulation method is provided, which is applied to a field programmable gate array. The following will be combined with Figures 1 to 3The method flow shown below describes the simulation method provided by this application for field programmable gate arrays.

[0030] In some embodiments, as Figure 1 shown, the simulation method applied to field programmable gate arrays at least includes the following steps:

[0031] Step 101: Based on at least two clock signals, sample the pulse signal to be measured separately to obtain at least two sets of sampled data.

[0032] Step 102: Extract the characteristic data of the pulse signal to be measured according to at least two sets of sampled data, where the characteristic data is used to characterize the pulse signal to be measured.

[0033] Step 103: Send the characteristic data to the central processing unit for the central processing unit to perform simulation calculations based on the characteristic data.

[0034] In this way, through sampling with at least two clock signals, on the premise of ensuring accurate sampling of the pulse signal to be measured, the pulse signal to be measured can be sampled at a lower frequency, so as to obtain low-frequency sampled data. At the same time, through feature extraction of the sampled data, the frequency of the data is further reduced. In this way, the data frequency input to the central processing unit is relatively low, and the central processing unit can perform calculation processing at a relatively low frequency during simulation, reducing the hardware capability requirements of the central processing unit for simulating high-frequency pulse signals, and thus reducing the hardware complexity, system design difficulty, system power consumption and system cost of the simulation system based on the central processing unit.

[0035] To facilitate better understanding by those skilled in the art Figure 1 of the embodiments shown below, the steps thereof will be explained as follows.

[0036] In step 101, based on at least two clock signals, sample the pulse signal to be measured separately to obtain at least two sets of sampled data. Among them, the number of clock signals used to sample the pulse signal to be measured in the embodiments of this application is not limited. It can be understood that according to the hardware capabilities of the central processing unit for simulation, the configuration of the field programmable gate array, the frequency of the pulse signal to be measured, the frequency of the clock signal, etc., the number of clock signals for sampling the pulse signal to be measured can be flexibly adjusted.

[0037] It should be noted that one clock signal in the embodiments of this application is a type of clock signal, and the frequencies and initial phases of different clock signals are not exactly the same. That is to say, in some embodiments, at least two clock signals may include: clock signals with the same frequency but different initial phases, and / or clock signals with different frequencies.

[0038] In some embodiments, at least two signals may include clock signals with the same frequency but different initial phases. In this way, by adjusting the initial phases of the same clock signal, the clock signals required by the field programmable gate array can be provided. Therefore, the number of clock signals required by the field programmable gate array can be minimized to the greatest extent, which is beneficial to reducing the hardware requirements for the field programmable gate array. At the same time, since at least two signals only have different initial phases, the uniform sampling of the pulse signal to be measured can be realized, making the timing of the sampled data more stable and more conducive to the subsequent data processing by the central processing unit. Of course,

[0039] In one example, the field programmable gate array can provide five clock signals: a clock signal with a frequency of 400 MHz and an initial phase of 0°, a clock signal with a frequency of 400 MHz and an initial phase of 45°, a clock signal with a frequency of 400 MHz and an initial phase of 90°, a clock signal with a frequency of 400 MHz and an initial phase of 135°, and a clock signal with a frequency of 200 MHz and an initial phase of 0°.

[0040] In one example, at least two signals may include clock signals with initial phases of 0°, 90°, 180°, and 270° respectively.

[0041] It should also be noted that in some embodiments, double-edge sampling can be further combined during the sampling process to further improve the resolution of the sampled data, obtain more complete information of the pulse signal to be measured, and thus be more conducive to supporting subsequent feature data extraction and simulation calculations.

[0042] In step 102, according to at least two sets of sampled data, the feature data of the pulse signal to be measured is extracted. Among them, the data content of the feature data is not limited in the embodiments of the present application. It can be any one or some data that can characterize the pulse signal to be measured, and the content of the pulse signal to be measured described by it is determined by the way the subsequent central processing unit is affected by the pulse signal to be measured during the simulation process: for example, when the central processing unit simulation is affected by the frequency of the pulse signal to be measured, the feature data needs to characterize the frequency of the pulse signal to be measured. At this time, the feature data may include the frequency of the pulse signal to be measured; also, when the central processing unit simulation is affected by the edge of the pulse signal to be measured, the feature data needs to characterize the time stamps of the rising edge and / or falling edge of the pulse signal to be measured, etc.

[0043] In some embodiments, the characteristic data includes at least one of the following: the timestamp of the rising edge of the pulse signal to be measured, the timestamp of the falling edge of the pulse signal to be measured, the high-level and low-level durations of the pulse signal to be measured, and the frequency of the pulse signal to be measured. Among them, the timestamps of the rising edge and the falling edge record the time of the level change of the pulse signal to be measured, which can be used to calculate the period, frequency, etc.; the high-level and low-level durations can be used to calculate the duty cycle; the duty cycle and the frequency: calculating the duty cycle and the frequency based on the signal period can help the control system optimize the operating state. Of course, the above is only an example description of the characteristic data. In some embodiments, the characteristic data may also include other contents, which will not be listed one by one here.

[0044] In step 103, the characteristic data is sent to the central processing unit for the central processing unit to perform simulation calculations based on the characteristic data. Among them, the embodiments of the present application do not limit the communication method between the field programmable gate array and the central processing unit.

[0045] It can be understood that since at least two channels of sampling data are obtained by sampling a pulse signal to be measured based on at least two channels of clock signals respectively, the data in at least two channels of sampling data are interleaved in time sequence. Based on this, in order to better extract features, in some embodiments, as Figure 2 shown, the simulation method applied to the field programmable gate array may further include at least the following steps:

[0046] Step 201: Based on at least two channels of clock signals, sample the pulse signal to be measured respectively to obtain at least two channels of sampling data.

[0047] Step 202: Combine and rearrange the data in at least two channels of sampling data according to the time sequence.

[0048] Step 203: Extract the characteristic data of at least two channels of sampling data according to the result of the combination and rearrangement, where the characteristic data is used to characterize the pulse signal to be measured.

[0049] Step 204: Send the characteristic data to the central processing unit for the central processing unit to perform simulation calculations based on the characteristic data.

[0050] In this way, on the basis of the embodiments shown in Figure 1 by combining and rearranging the data in at least two channels of sampling data according to the time sequence, it is possible to obtain the sampling data of the complete pulse signal to be measured that conforms to the time sequence, which can more intuitively and accurately represent the sampling result, making the subsequent feature extraction more efficient and accurate, thereby improving the real-time performance and accuracy of the simulation.

[0051] It is not difficult to find that Figure 2 the embodiments shown are namely in Figure 1Based on the illustrated embodiment, step 102 is further refined into step 202 and step 203, where Figure 1 Steps 101 and 103 in the illustrated embodiment are substantially the same as steps 201 and 204 above, and will not be elaborated here one by one. To facilitate better understanding by those skilled in the art Figure 2 of the illustrated embodiment, steps 202 and 203 will be explained below.

[0052] In step 202, according to the time sequence, the data in at least two channels of sampled data are combined and rearranged. It can be understood that each data in at least two channels of sampled data corresponds to a sampling timestamp, and the sampling timestamp represents the corresponding time sequence. Therefore, step 202 arranges all the data in at least two channels of sampled data according to the sampling timestamp.

[0053] It should be noted that in the above processing, signal preprocessing such as denoising and filtering can also be adopted to ensure the accuracy and integrity of the data.

[0054] In step 203, according to the result of the combined rearrangement, the characteristic data of at least two channels of sampled data are extracted. As mentioned before, the data content included in the characteristic data may be different, so the extraction method is also different. The content of the characteristic data and its extraction method have been described before, and will not be elaborated here one by one.

[0055] It can also be understood that there may be certain requirements for the simulation, such as real-time requirements. Therefore, in scenarios with specific requirements, corresponding requirements can be met through relevant configurations. For example, in some embodiments, as Figure 3 shown, the simulation method applied to a field programmable gate array may further include at least the following steps:

[0056] Step 301, based on at least two clock signals, sample the pulse signal to be measured respectively to obtain at least two channels of sampled data.

[0057] Step 302, according to at least two channels of sampled data, extract the characteristic data of the pulse signal to be measured, where the characteristic data is used to characterize the pulse signal to be measured.

[0058] Step 303, encapsulate the characteristic data according to a preset format.

[0059] Step 304, through a high-speed data bus, send the encapsulated result to the central processing unit for the central processing unit to perform simulation calculations according to the characteristic data included in the encapsulated result.

[0060] In this way, in Figure 1Based on the illustrated embodiment, by encapsulating the feature data and the high-speed data bus in a preset format, the feature data can be accurately, securely, reliably, and in real time transmitted to the central processor for simulation, thereby improving the real-time performance and accuracy of the simulation.

[0061] It is not difficult to find that Figure 3 The illustrated embodiment is based on Figure 1 the illustrated embodiment, and step 103 is further refined into step 303 and step 304, where Figure 1 Steps 101 and 102 in the illustrated embodiment are substantially the same as steps 301 and 302 above, and will not be elaborated here one by one. For better understanding by those skilled in the art Figure 3 of the illustrated embodiment, steps 303 and 304 will be explained below.

[0062] In step 303, the feature data is encapsulated in a preset format. Herein, the preset format in the embodiments of the present application is not limited and can be set according to requirements: for example, the preset format can specify the maximum data volume of the feature data that can be encapsulated at one time; also, the preset format can specify the time stamp span range corresponding to the feature data that can be encapsulated at one time; furthermore, the preset format can specify the order of different types of data in the feature data that can be encapsulated at one time, etc., and will not be listed one by one here.

[0063] In step 304, the encapsulated result is sent to the central processor through the high-speed data bus for the central processor to perform simulation calculations based on the feature data included in the encapsulated result. Herein, the high-speed data bus in the embodiments of the present application is not limited, and it can be a Serial Peripheral Interface (SPI), Low Voltage Differential Signaling (LVDS), Inter-Integrated Circuit (I2C) bus, Ethernet field bus, Mobile Industry Processor Interface (MIPI), USB3.0, Peripheral Component Interconnect Express (PCIE), etc., and will not be listed one by one here.

[0064] It should be noted that the embodiments of the present application do not limit the manner of connecting the field programmable gate array and the central processing unit based on a high-speed data bus. For example, the field programmable gate array and the central processing unit are directly connected through a high-speed data bus, or the connection between the field programmable gate array and the central processing unit also passes through some other devices, modules, units, etc. The connection from the field programmable gate array, other objects to the central processing unit is at least partially a high-speed data bus, etc., and will not be listed one by one here.

[0065] It should also be noted that the high-speed data bus is only an example. In some embodiments, the connection between the field programmable gate array and the central processing unit can also be connected through other buses for other requirements, and will not be listed one by one here.

[0066] Of course, Figure 3 The shown embodiments are only provided on the basis of Figure 1 the shown embodiments. In some cases, Figure 3 the shown embodiments can be combined with Figure 2 the shown embodiments. For example, step 302 shown in Figure 3 is replaced with step 202 and step 203 in Figure 2 the shown embodiments, etc., and will not be elaborated one by one here.

[0067] The second aspect of the embodiments of the present application provides a simulation method, which is applied to a central processing unit. The following will describe the simulation method applied to the central processing unit provided by the present application in combination with Figures 4 to 5 the shown method flow.

[0068] In some embodiments, as Figure 4 shown, the simulation method applied to the central processing unit at least includes the following steps:

[0069] Step 401: Receive the feature data sent by the field programmable gate array, where the feature data is obtained by the field programmable gate array based on at least two sampling data obtained from the pulse to be measured based on at least two clock signals, and the feature data is used to characterize the pulse signal to be measured.

[0070] Step 402: Perform simulation calculations according to the feature data.

[0071] In this way, through the sampling of at least two clock signals, on the premise of ensuring the accurate sampling of the pulse signal to be measured, the pulse signal to be measured can be sampled at a lower frequency, so as to obtain low-frequency sampling data. At the same time, through the feature extraction of the sampling data, the frequency of the data is further reduced. In this way, the data frequency input to the central processing unit is relatively low, and the central processing unit can perform simulation calculations at a relatively low frequency when performing simulation, reducing the hardware capability requirements of the central processing unit for simulating high-frequency pulse signals, thereby reducing the hardware complexity, system design difficulty, system power consumption and system cost of the simulation system based on the central processing unit.

[0072] It is not difficult to find that this embodiment is a method embodiment corresponding to the embodiment shown in the first aspect, and this embodiment can be implemented in cooperation with the embodiment shown in the first aspect. The relevant technical details mentioned in the embodiment shown in the first aspect are still valid in this embodiment. To avoid repetition, they will not be elaborated here. Correspondingly, the relevant technical details mentioned in this embodiment can also be applied to the embodiment shown in the first aspect.

[0073] It can be understood that in some scenarios, the pulse signal to be measured is a signal that is continuously adjusted until it meets the requirements. Therefore, the simulation based on the pulse signal to be measured may also involve feedback control to provide a more complete simulation result. Based on this, in some embodiments, as Figure 5 shown, the simulation method applied to the central processing unit may further include at least the following steps:

[0074] Step 501: Receive the feature data sent by the field programmable gate array, where the feature data is obtained by the field programmable gate array based on at least two sampling data obtained from the pulse signal to be measured based on at least two clock signals, and the feature data is used to characterize the pulse signal to be measured.

[0075] Step 502: Perform simulation calculations according to the feature data.

[0076] Step 503: Generate and output a control signal according to the current simulation result, so that after the pulse signal to be measured is adjusted according to the control signal, continue to perform simulation calculations according to the feature data corresponding to the adjusted pulse signal to be measured received.

[0077] In this way, on the basis of the embodiment shown in Figure 4 by controlling and adjusting the pulse signal to be measured according to the current simulation result to perform simulation, a complete and comprehensive simulation result of the pulse signal to be measured can be obtained.

[0078] It is not difficult to find that Figure 5 the embodiment shown is based on the embodiment shown in Figure 4 and a new step 503 is introduced, where Figure 4Steps 401 and 402 in the illustrated embodiment are substantially the same as steps 501 and 502 above, and will not be elaborated here one by one. For better understanding by those skilled in the art Figure 5 the illustrated embodiment, step 503 will be explained below.

[0079] In step 503, according to the current simulation result, a control signal is generated and output, so that after the pulse signal to be measured is adjusted according to the control signal, according to the characteristic data corresponding to the adjusted pulse signal to be measured received, the simulation calculation is continued. Among them, the present application embodiment does not limit the generation of the control signal. It can be understood that according to different application scenarios, different simulation requirements, etc., the generation of the control signal will have different ways.

[0080] For ease of understanding below, examples will be provided for the above embodiment, but this does not mean that only the solutions of the following examples can be used for implementation.

[0081] In some embodiments, the data received by the central processing unit is encapsulated data. Assuming the format is a data frame, then the central processing module first parses the encapsulated data frame to obtain characteristic data, such as timestamps that may include rising edges and / or falling edges, duty cycles, frequencies, etc. data. Then the central processing unit performs simulation calculations according to the characteristic data to obtain response data corresponding to the pulse signal to be measured, and then uses this response data as the result of the simulation to further calculate the control parameters that the pulse signal to be measured needs to be adjusted to generate a control signal, or predicts the future state according to the characteristic data and the simulation model, so as to dynamically optimize the control parameters to ensure the efficient operation of the system under different load conditions, such as calculating new duty cycles, frequencies, etc. according to the information such as duty cycles and frequencies sampled in real time. Then the control signal is output to the field programmable gate array or the power electronic controller (the power electronic controller is used to control the devices, components or equipment that generate the pulse signal to be measured), so as to optimize the power conversion efficiency and response speed and other performances of the power electronic equipment (such as DC-DC converters, inverters, etc.).

[0082] The step division of the above various methods is only for clear description. When implemented, they can be combined into one step or some steps can be split into multiple steps. As long as the same logical relationship is included, it is within the protection scope of this patent; adding insignificant modifications to the algorithm or process or introducing insignificant designs, but not changing the core design of its algorithm and process are all within the protection scope of this patent.

[0083] The third aspect of the embodiment of the present application also provides a simulation system, as Figure 6 shown, including: a field programmable gate array 601 and a central processing unit 602.

[0084] Among them, the field programmable gate array 601 is used to implement the simulation method according to any one of the first aspects, and the central processing unit is used to implement the simulation method according to any one of the second aspects.

[0085] In some embodiments, the field programmable gate array 601 and the central processing unit 602 are at least connected through a high-speed data bus.

[0086] Among them, the connection between the field programmable gate array 601 and the central processing unit 602 may also include connections implemented by other buses. These buses may include any number of interconnected buses and bridges, or may also connect various other circuits such as peripheral devices, voltage regulators, and power management circuits together. These are well known in the art, so they will not be further described herein.

[0087] It is not difficult to find that this embodiment is a system embodiment corresponding to the method embodiment, and this embodiment can be implemented in cooperation with the method embodiment. The relevant technical details mentioned in the method embodiment are still valid in this embodiment. To avoid repetition, they will not be elaborated here. Correspondingly, the relevant technical details mentioned in this embodiment can also be applied to the method embodiment.

[0088] In addition, to highlight the innovative part of this application, units that are not closely related to solving the technical problems proposed in this application are not introduced in this embodiment, but this does not mean that there are no other units in this embodiment.

[0089] The fourth aspect of the embodiments of this application further provides a device, including: a device body; and a simulation system as described in the third aspect disposed on the device body; among them, the simulation system is used to receive an externally input pulse signal to be measured and perform simulation to output a simulation result.

[0090] It is not difficult to find that this embodiment is a device embodiment corresponding to the system embodiment, and this embodiment can be implemented in cooperation with the device embodiment. The relevant technical details mentioned in the system embodiment are still valid in this embodiment. To avoid repetition, they will not be elaborated here. Correspondingly, the relevant technical details mentioned in this embodiment can also be applied to the system embodiment.

[0091] The fifth aspect of the embodiments of this application further provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, the above method embodiments are implemented.

[0092] That is, those skilled in the art can understand that all or part of the steps in implementing the methods of the above embodiments can be completed by instructing relevant hardware through a program. The program is stored in a storage medium, including several instructions to enable a device (which can be a single-chip microcomputer, a chip, etc.) or a processor to execute all or part of the steps of the methods described in various embodiments of the present application. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs.

[0093] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present application. In actual applications, various changes can be made to them in form and details without departing from the spirit and scope of the present application.

Claims

1. A simulation method, characterized in that: Applied to a field programmable logic gate array, the method comprises: Based on at least two clock signals, the pulse signal to be measured is sampled respectively to obtain at least two sampling data; Extracting characteristic data of the pulse signal to be measured according to the at least two channels of sampling data, wherein the characteristic data is used to characterize the pulse signal to be measured; The characteristic data is sent to a central processing unit so that the central processing unit performs simulation calculations according to the characteristic data.

2. The simulation method according to claim 1, characterized in that: The step of extracting characteristic data of the pulse signal to be measured according to the at least two channels of sampling data comprises: Combining and rearranging the data in the at least two channels of sampled data according to a time sequence; According to the result of merging and rearranging, the feature data of the at least two paths of sampling data are extracted.

3. The simulation method according to claim 1, characterized in that: The characteristic data includes at least one of the following: a timestamp of a rising edge of the pulse signal to be measured, a timestamp of a falling edge of the pulse signal to be measured, a high level and a low level duration of the pulse signal to be measured, and a frequency of the pulse signal to be measured.

4. The simulation method according to claim 1, characterized in that: The at least two clock signals include: clock signals with the same frequency but different initial phases, and / or clock signals with different frequencies.

5. The simulation method according to any one of claims 1 to 4, characterized in that: The step of sending the characteristic data to a central processor comprises: Encapsulating the characteristic data according to a preset format; The packaged results are sent to the central processor via a high-speed data bus.

6. A simulation method, characterized in that: Applied to a central processing unit, the method comprises: Receiving characteristic data sent by a field programmable logic gate array, wherein the characteristic data is sent by the field programmable logic gate array to the central processing unit according to the simulation method according to any one of claims 1 to 5; A simulation calculation is performed according to the characteristic data.

7. The simulation method according to claim 6, characterized in that: The method further comprises: According to the current simulation result, a control signal is generated and outputted, so that after the pulse signal to be measured is adjusted according to the control signal, the simulation calculation is continued according to the received characteristic data corresponding to the adjusted pulse signal to be measured.

8. A simulation system, characterized in that: Includes: Field Programmable Gate Array and Central Processing Unit; Wherein, the field programmable logic gate array and the central processing unit are connected via at least a high-speed data bus, the field programmable logic gate array is used to implement the simulation method as described in any one of claims 1 to 5, and the central processing unit is used to implement the simulation method as described in claim 6 or 7.

9. A device, characterized in that: include: Equipment body; and a simulation system as claimed in claim 8 disposed on the device body; The simulation system is used to receive an externally input pulse signal to be tested and perform simulation to output a simulation result.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the computer program implements the simulation method according to any one of claims 1 to 5, or executes the simulation method according to claim 6 or 7.

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