Logic comprehensive optimization method and device of circuit

Abstract

The invention provides a logic comprehensive optimization method and device for a circuit, and the method comprises the steps: obtaining N sub-graphs corresponding to the circuit, the sub-graphs being a part of a graph representation corresponding to the circuit, and N being an integer greater than or equal to 1; m pre-estimated effective sub-graphs are determined according to a comprehensive optimization prediction model and the N sub-graphs, the comprehensive optimization prediction model is used for predicting whether the sub-graphs can be optimized or not, the pre-estimated effective sub-graphs are sub-graphs which can be predicted to be optimized, and M is smaller than or equal to N; and logic comprehensive optimization is carried out on P pre-estimated effective sub-graphs, the P pre-estimated effective sub-graphs belong to the M pre-estimated effective sub-graphs, and P is smaller than or equal to M. According to the method provided by the invention, the logic comprehensive optimization efficiency can be improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and particularly to a method and device for logic synthesis optimization of a circuit. Background Art

[0002] Circuit power consumption, performance, and area (PPA) are core metrics that concern developers and users of electronic design automation (EDA) tools. However, according to Moore's Law, as the chip scale increases year by year, EDA tools need to process circuits of larger scale. In addition to PPA, the running time of EDA tools is also a key factor in improving the work efficiency of EDA users, which is related to chip engineers obtaining feedback on the tool running results in a timely manner and the chip market launch time. Moreover, the efficiency optimization of EDA tools themselves can also indirectly improve PPA.

[0003] Logic synthesis, which is located at the front end of the EDA tool chain, is used to synthesize the high-level description of a circuit into a low-level gate-level netlist, and it is one of the time-consuming bottlenecks of the tool chain. The logic synthesis tool needs to iteratively call multiple synthesis operators to optimize the PPA of the netlist. However, the overall netlist benefit of most synthesis operators is only 1-10%, which also means that there is 90-99% redundant calculation and ineffective calls to the time-consuming synthesis engine when traversing all subgraphs in the circuit. Therefore, there is an urgent need for a method to improve the efficiency of logic synthesis optimization. Summary of the Invention

[0004] This application provides a method and device for logic synthesis optimization of a circuit, which can improve the efficiency of logic synthesis optimization.

[0005] In a first aspect, a method for logic synthesis optimization of a circuit is provided. The method includes: obtaining N subgraphs corresponding to the circuit, where the subgraph is a part of the graph representation corresponding to the circuit, and N is an integer greater than or equal to 1; determining M estimated effective subgraphs according to a synthesis optimization prediction model and the N subgraphs, where the synthesis optimization prediction model is used to predict whether the subgraph can be optimized, and the estimated effective subgraph is a subgraph predicted to be optimizable, and M ≤ N; performing logic synthesis optimization on P estimated effective subgraphs, where the P estimated effective subgraphs belong to the M estimated effective subgraphs, and P ≤ M.

[0006] This application provides a method for logic synthesis optimization of a circuit, which can estimate whether a subgraph can be optimized before calling the synthesis engine for logic synthesis optimization, and prune the estimated ineffective subgraphs in advance to reduce redundant calls to the synthesis engine and improve the efficiency of logic synthesis optimization.

[0007] It should be understood that a circuit can be represented by a graph, and a sub-graph is a part cut out from the circuit diagram representation. If a sub-graph is predicted to be optimizable, then the sub-graph is a predicted effective sub-graph. If a sub-graph is predicted not to be optimizable, then the sub-graph is a predicted ineffective sub-graph.

[0008] The comprehensive optimization prediction model can adopt a linear model, a decision tree model, a neural network model, etc. N, M, and P are integers greater than or equal to 1.

[0009] Logic synthesis optimization includes replacing an atomic graph with a corresponding candidate sub-graph with higher benefits. The atomic graph and the corresponding candidate sub-graph have different structures but are functionally equivalent.

[0010] Combined with the first aspect, in some implementation manners of the first aspect, the determining M predicted effective sub-graphs according to the comprehensive optimization prediction model and the N sub-graphs includes: obtaining the optimization prediction features corresponding to the first sub-graph, where the optimization prediction features include any one or more of an evaluation benefit feature, a structural feature, a benefit feature of a historical logic synthesis operator, and a circuit high-level description feature. The first sub-graph is any one of the N sub-graphs. The evaluation benefit feature includes the optimization effect brought by a sub-graph of the same type as the first sub-graph in historical optimization to the circuit. The benefit of the historical logic synthesis operator includes the optimization effect brought by the logic synthesis operator that historically optimized the circuit to the circuit. Determining that the first sub-graph is the predicted effective sub-graph according to the optimization prediction features and the comprehensive optimization prediction model.

[0011] It should be understood that there are very many types of sub-graph structures and functions in a circuit, depending on the input, output, and internal structure of the circuit corresponding to the sub-graph. Usually, multiple sub-graphs of a circuit can be classified into a few types of sub-graphs.

[0012] The evaluation benefit feature includes the optimization effect brought by a sub-graph of the same type as the first sub-graph in historical optimization to the circuit. The evaluation benefit feature can be a two-dimensional time series of the evaluation benefits of historical sub-graphs or a one-dimensional total evaluation benefit sum. In the case where the evaluation benefit feature is a two-dimensional time series of evaluation benefits, since historical sub-graphs are accessed and synthesized one by one, the historical access can be segmented into a time series, and the evaluation benefit feature can be represented by a two-dimensional matrix Z F*T which means that Z represents the elements in the two-dimensional matrix are integers, F is the number of rows of the two-dimensional matrix, T is the number of columns of the two-dimensional matrix. At the same time, F is the number of evaluation benefit features, and T is the number of segmented time windows. In the case where the evaluation benefit feature is a one-dimensional total evaluation benefit sum of evaluation benefits, the evaluation benefit feature of the graph evaluation benefit database can be the sum of each row in the two-dimensional matrix Z F*T to obtain the total feature Z F .

[0013] The structural feature can be obtained by online extraction of the first sub-graph, or can be a structural feature obtained by estimating the number of nodes, the estimated number of reused nodes, the estimated maximum fanout free cone (MFFC), etc. of the first sub-graph, and this feature can be used to model the performance of the current circuit.

[0014] The benefits of historical logic synthesis operators include the optimization effects brought by the logic synthesis operators of the historical optimized circuit to the circuit. It should be understood that logic synthesis tools mostly execute a sequence of synthesis operators alternately. Before the execution of the current synthesis operator, there may have been many synthesis operators used to optimize the current circuit, and their benefit performances implicitly include some circuit features. Therefore, this feature can also be extracted and used to model the overall circuit to improve the prediction effect.

[0015] Circuits have different representations, such as Verilog, abstract syntax tree (AST), intermediate representation (IR), and and inverted graph (AIG) that only contains 2-input and gates and negation operators, etc. Their abstraction levels decrease while their scales increase. Therefore, the circuit representation with a high abstraction granularity has a lower modeling complexity and a higher degree of integration, and the high-level circuit description features can be used to guide the optimization of the underlying circuit.

[0016] This application provides a method for logic synthesis optimization of a circuit, which can input the obtained optimization prediction features into a synthesis optimization prediction model to obtain an estimated result of whether a sub-graph can be optimized, and prune the estimated invalid sub-graphs in advance to reduce redundant calls of the synthesis engine and improve the efficiency of logic synthesis optimization.

[0017] Combined with the first aspect, in some implementation manners of the first aspect, the optimization prediction feature includes the evaluation benefit feature, and the obtaining of the optimization prediction feature corresponding to the first sub-graph includes: determining the key value of the first sub-graph; matching in the graph evaluation benefit database according to the key value to obtain the evaluation benefit feature corresponding to the first sub-graph, and the graph evaluation benefit database includes the key values of at least one type of graph and the corresponding evaluation benefit features.

[0018] The methods for determining the key value of the first sub-graph include but are not limited to truth tables, negation-permutation-negation (NPN) equivalence class matching, etc.

[0019] The graph evaluation revenue database stores the evaluation revenue data when historical subgraphs are synthesized, that is, the data pair of (subgraph key value, comprehensive evaluation revenue). Among them, the comprehensive evaluation revenue includes the evaluation revenue feature G and / or GL, where G represents the global comprehensive revenue and GL represents the local comprehensive revenue. The global comprehensive revenue refers to the comprehensive revenue corresponding to the optimal candidate subgraph after the iteration of candidate subgraphs is completed. The local comprehensive revenue refers to the revenue of each candidate subgraph when iteratively selecting the optimal candidate subgraph, which can be positive or negative.

[0020] This application provides a method for logical synthesis optimization of a circuit. It can match the evaluation revenue feature corresponding to the first subgraph through the graph evaluation revenue database, and then obtain a predicted result on whether the subgraph can be optimized, improving the accuracy and efficiency of the prediction of the comprehensive optimization prediction model.

[0021] Combined with the first aspect, in some implementation manners of the first aspect, the method further includes: updating the graph evaluation revenue database according to the matching result of the first subgraph in the graph evaluation revenue database or the logical synthesis optimization result of the first subgraph.

[0022] Exemplarily, the comprehensive evaluation revenue of the graph evaluation revenue database includes any one or more of the parameters E, W, G, and GL, corresponding to each type of subgraph key value. Among them, E represents the number of times a certain type of subgraph is evaluated, W is the number of times a certain type of subgraph is selected as the optimal subgraph, G represents the global comprehensive revenue, and GL represents the local comprehensive revenue.

[0023] Exemplarily, after the first subgraph passes graph matching, the E corresponding to the key value of the first subgraph can be incremented by 1. After the first subgraph undergoes logical synthesis optimization, the parameters W, G, and GL corresponding to the key value of the first subgraph can be updated according to the logical synthesis optimization result.

[0024] This application provides a method for logical synthesis optimization of a circuit, which can continuously update the graph evaluation revenue database, improving the accuracy and efficiency of the prediction of the comprehensive optimization prediction model.

[0025] Combined with the first aspect, in some implementation manners of the first aspect, before performing logical synthesis optimization on P estimated effective subgraphs, the method further includes: sorting the M estimated effective subgraphs from high to low according to the comprehensive revenue of the M estimated effective subgraphs or the confidence level of the comprehensive revenue, where the P estimated effective subgraphs are the top P estimated effective subgraphs after sorting the M estimated effective subgraphs, and the comprehensive revenue includes the optimization effect brought by the optimized subgraph to the circuit.

[0026] It should be understood that if the estimated effective sub - graph at the m - th sorting position cannot bring comprehensive benefits, it is considered that the estimated effective sub - graphs with sorting orders after the m - th position cannot be optimized either, and the logical synthesis optimization process of the current circuit can be terminated in advance, where 1 ≤ m < M.

[0027] This application provides a method for logical synthesis optimization of a circuit, which can sort the estimated effective sub - graphs according to the comprehensive benefits or the confidence level of the comprehensive benefits, and terminate the logical synthesis optimization process of the current circuit in advance according to the actual comprehensive benefits, improving the efficiency of logical synthesis optimization.

[0028] In combination with the first aspect, in some implementation manners of the first aspect, the comprehensive optimization prediction model includes a comprehensive benefit estimation model and a pruning model. The comprehensive benefit estimation model is used to predict the comprehensive benefits or the confidence level of the comprehensive benefits. The comprehensive benefits include the optimization effect brought to the circuit by replacing the sub - graph with a candidate sub - graph in the circuit. The candidate sub - graph has a different structure from the sub - graph but the same function. The pruning model is used to judge whether the sub - graph is an estimated effective sub - graph according to the comprehensive benefits or the confidence level of the comprehensive benefits.

[0029] The input of the comprehensive benefit estimation model is the optimization prediction feature of the sub - graph, and the output is the comprehensive benefits of the sub - graph or the confidence level of the comprehensive benefits. The optimization prediction features include any one or more of the evaluation benefit feature, the structure feature, the benefit feature of the historical logical synthesis operator, and the high - level circuit description feature. The comprehensive benefit estimation model can be obtained through the optimization prediction features of multiple sub - graphs and the corresponding comprehensive benefits / confidence levels of the comprehensive benefits. Optionally, these multiple sub - graphs can be a part of the current circuit to be synthesized, or can belong to at least one typical circuit, or some of these multiple sub - graphs belong to at least one typical circuit and the other part belongs to the current circuit to be synthesized.

[0030] The input of the pruning model is the comprehensive benefits of the sub - graph or the confidence level of the comprehensive benefits, and the output is the optimization estimation result of the sub - graph. The optimization estimation result is used to indicate whether the sub - graph is an estimated effective sub - graph or an estimated ineffective sub - graph. The comprehensive benefit estimation model can be obtained through the comprehensive benefits of multiple sub - graphs or the confidence levels of the comprehensive benefits and the corresponding optimization estimation results. Optionally, these multiple sub - graphs can be a part of the current circuit to be synthesized, or can belong to at least one typical circuit, or some of these multiple sub - graphs belong to at least one typical circuit and the other part belongs to the current circuit to be synthesized.

[0031] This application provides a method for logical synthesis optimization of a circuit, which can use the comprehensive benefit estimation model to estimate the comprehensive benefits or the confidence level of the comprehensive benefits of the sub - graph, and use the pruning model to prune the estimated ineffective sub - graphs in advance to reduce the redundant calls of the synthesis engine, improving the efficiency of logical synthesis optimization.

[0032] In combination with the first aspect, in some implementations of the first aspect, the logical synthesis optimization of the P estimated effective subgraphs includes: replacing a second subgraph with a first candidate subgraph in the circuit, where the second subgraph is any one of the P estimated effective subgraphs, the first candidate subgraph has a different structure but the same function as the second subgraph, and the synthesis benefit of the candidate subgraph is greater than or equal to the synthesis benefit of the second subgraph.

[0033] In some possible implementations, the first candidate subgraph is an adjacent subgraph of the second subgraph, that is, the first candidate subgraph is adjacent to the second subgraph in the circuit diagram representation.

[0034] The present application provides a method for logical synthesis optimization of a circuit, which can estimate whether a subgraph can be optimized before calling a synthesis engine for logical synthesis optimization, and prune the estimated invalid subgraphs in advance to reduce redundant calls of the synthesis engine and improve the efficiency of logical synthesis optimization.

[0035] In combination with the first aspect, in some implementations of the first aspect, the replacing the second subgraph with the first candidate subgraph in the circuit includes: deleting the MFFC of the second subgraph in the circuit; adding the first candidate subgraph in the circuit.

[0036] The node set corresponding to the MFFC is the nodes that can be deleted in the second subgraph.

[0037] The present application provides a method for logical synthesis optimization of a circuit, which can estimate whether a subgraph can be optimized before calling a synthesis engine for logical synthesis optimization, and prune the estimated invalid subgraphs in advance to reduce redundant calls of the synthesis engine and improve the efficiency of logical synthesis optimization.

[0038] In combination with the first aspect, in some implementations of the first aspect, the synthesis optimization prediction model is trained through the optimization prediction features of multiple subgraphs and the corresponding optimization estimation results, and the optimization prediction features include any one or more of the evaluation benefit feature, the structure feature, the benefit feature of the historical logical synthesis operator, and the circuit high-level description feature.

[0039] Optionally, the multiple subgraphs can be a part of the currently to-be-synthesized circuit, or can belong to at least one typical circuit, or some of the multiple subgraphs belong to at least one typical circuit and the other part belongs to the currently to-be-synthesized circuit.

[0040] The present application provides a method for optimizing the logic synthesis of a circuit. The method can train a comprehensive optimization prediction model through the optimization prediction features and corresponding optimization prediction results of multiple subgraphs. Before calling the comprehensive engine for logic synthesis optimization, the comprehensive optimization prediction model is used to estimate whether a subgraph can be optimized, and the subgraphs with ineffective estimates are pruned in advance to reduce redundant calls of the comprehensive engine and improve the efficiency of logic synthesis optimization.

[0041] In a second aspect, a computer device is provided. The device includes: an acquisition module configured to acquire N subgraphs corresponding to a circuit, where the subgraphs are a part of the graph representation corresponding to the circuit, and N is an integer greater than or equal to 1; a processing module configured to determine M effectively estimated subgraphs according to the comprehensive optimization prediction model and the N subgraphs, where the comprehensive optimization prediction model is used to predict whether the subgraphs can be optimized, and the effectively estimated subgraphs are the subgraphs predicted to be optimizable, and M ≤ N; and perform logic synthesis optimization on P effectively estimated subgraphs, where the P effectively estimated subgraphs belong to the M effectively estimated subgraphs, and P ≤ M.

[0042] In combination with the second aspect, in some implementation manners of the second aspect, the processing module is specifically configured to: acquire the optimization prediction features corresponding to a first subgraph, where the optimization prediction features include any one or more of an evaluation benefit feature, a structural feature, a benefit feature of a historical logic synthesis operator, and a high-level description feature of the circuit, the first subgraph is any one of the N subgraphs, the evaluation benefit feature includes the optimization effect brought by the circuit by historically optimizing subgraphs of the same type as the first subgraph, and the benefit of the historical logic synthesis operator includes the optimization effect brought by the historical logic synthesis operator for optimizing the circuit; and determine that the first subgraph is the effectively estimated subgraph according to the optimization prediction features and the comprehensive optimization prediction model.

[0043] In combination with the second aspect, in some implementation manners of the second aspect, the optimization prediction features include the evaluation benefit feature, and the processing module is specifically configured to: determine the key value of the first subgraph; and match the evaluation benefit feature corresponding to the first subgraph in a graph evaluation benefit database according to the key value, where the graph evaluation benefit database includes key values of at least one type of graph and corresponding evaluation benefit features.

[0044] In combination with the second aspect, in some implementation manners of the second aspect, the processing module is further configured to update the graph evaluation benefit database according to the matching result of the first subgraph in the graph evaluation benefit database or the logic synthesis optimization result of the first subgraph.

[0045] In combination with the second aspect, in certain implementations of the second aspect, the processing module is further configured to sort the M predicted effective subgraphs from high to low according to the comprehensive benefits of the M predicted effective subgraphs or the confidence level of the comprehensive benefits, where the P predicted effective subgraphs are the top P predicted effective subgraphs after sorting the M predicted effective subgraphs, and the comprehensive benefits include the optimization effect brought by the optimized subgraph to the circuit.

[0046] In combination with the second aspect, in certain implementations of the second aspect, the comprehensive optimization prediction model includes a comprehensive benefit prediction model and a pruning model. The comprehensive benefit prediction model is used to predict the comprehensive benefits or the confidence level of the comprehensive benefits. The comprehensive benefits include the optimization effect brought by using a candidate subgraph to replace the subgraph in the circuit. The candidate subgraph has a different structure but the same function as the subgraph. The pruning model is used to determine whether the subgraph is a predicted effective subgraph according to the comprehensive benefits or the confidence level of the comprehensive benefits.

[0047] In combination with the second aspect, in certain implementations of the second aspect, the processing module is specifically configured to: use a first candidate subgraph to replace a second subgraph in the circuit, where the second subgraph is any one of the P predicted effective subgraphs, the first candidate subgraph has a different structure but the same function as the second subgraph, and the comprehensive benefits of the candidate subgraph are greater than or equal to the comprehensive benefits of the second subgraph.

[0048] In combination with the second aspect, in certain implementations of the second aspect, the processing module is specifically configured to: delete the MFFC of the second subgraph in the circuit; add the first candidate subgraph in the circuit.

[0049] In combination with the second aspect, in certain implementations of the second aspect, the comprehensive optimization prediction model is trained by using the optimization prediction features of multiple subgraphs and the corresponding optimization prediction results. The optimization prediction features include any one or more of the evaluation benefit features, structure features, benefit features of historical logic synthesis operators, and circuit high-level description features.

[0050] The beneficial effects of the second aspect and any possible implementation of the second aspect correspond to those of the first aspect and any possible implementation of the first aspect, and thus will not be elaborated herein.

[0051] In a third aspect, an embodiment of the present application provides a computer device, which includes a processor. The processor is used to be coupled with a memory, read and execute instructions and / or program codes in the memory to execute the first aspect or any possible implementation of the first aspect.

[0052] Fourthly, an embodiment of the present application provides a computer-readable storage medium, which stores program codes. When the computer-readable storage medium runs on a computer, the computer is caused to execute the implementation manner as described in the first aspect or any possible implementation manner of the first aspect.

[0053] Fifthly, an embodiment of the present application provides a computer program product, which includes computer program codes. When the computer program codes run on a computer, the computer is caused to execute the implementation manner as described in the first aspect or any possible implementation manner of the first aspect. Description of the Drawings

[0054] Figure 1 It is an exemplary flowchart of logic synthesis optimization.

[0055] Figure 2 It is an exemplary flowchart of another logic synthesis optimization method.

[0056] Figure 3 It is an exemplary flowchart of a logic synthesis optimization method provided by an embodiment of the present application.

[0057] Figure 4 It is a schematic flowchart of model training provided by an embodiment of the present application.

[0058] Figure 5 It is an exemplary flowchart of another logic synthesis optimization method provided by an embodiment of the present application.

[0059] Figure 6 It is an exemplary flowchart of another logic synthesis optimization method provided by an embodiment of the present application.

[0060] Figure 7 It is an exemplary flowchart of model selection provided by an embodiment of the present application.

[0061] Figure 8 It is a structural example diagram of a computer device provided by an embodiment of the present application.

[0062] Figure 9 It is a structural example diagram of another computer device provided by an embodiment of the present application.

[0063] Figure 10 It is an example diagram of a computer program product provided by an embodiment of the present application. Detailed Embodiments

[0064] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present application, rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the protection scope of the present application.

[0065] In the embodiments of the present application, words such as "exemplary" and "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design solution described as "exemplary" in the present application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Rather, the use of the word "exemplary" is intended to present concepts in a specific manner.

[0066] The business scenarios described in the embodiments of the present application are for more clearly illustrating the technical solutions in the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those of ordinary skill in the art can know that with the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are equally applicable to similar technical problems.

[0067] In this specification, references to "one embodiment" or "some embodiments" etc. mean that a specific feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, statements such as "in one embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments" etc. that appear in different places in this specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in another way. The terms "comprising", "including", "having" and their variants all mean "including but not limited to", unless otherwise specifically emphasized in another way.

[0068] In the present application, "at least one" means one or more, and "a plurality" means two or more. "And / or" describes the association relationship of associated objects and indicates that three relationships can exist. For example, A and / or B can represent: including the case where A exists alone, where A and B exist simultaneously, and where B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after. "At least one (item)" or similar expressions thereof refer to any combination of these items, including any combination of single item (s) or plural item (s). For example, at least one (item) of a, b, or c can represent: a, b, c, a - b, a - c, b - c, or a - b - c, where a, b, c can be single or multiple.

[0069] To facilitate the understanding of the embodiments of the present application, some definitions involved in the present application will be briefly described first.

[0070] 1. Electronic Design Automation (EDA): It refers to a design method that uses computer-aided design software to complete the design processes of very large-scale integrated circuit chips, such as functional design, synthesis, verification, and physical design (including layout, routing, layout, design rule checking, etc.).

[0071] 2. Logic Synthesis: It is a key step in the chip design process, which converts high-level logical descriptions into low-level gate-level netlists or Boolean function representations.

[0072] 3. Logic Optimization: The logical optimization and simplification of Boolean circuits, such as the optimization of an and inverted graph (AIG) that only contains 2-input and gates and inversion operators, the optimization of multiple-input gates (MIG), etc.

[0073] 4. Netlist Optimization: The optimization and simplification of gate-level circuits, such as the optimization of look-up-table (LUT) netlists, the optimization of application-specific integrated circuit (ASIC) netlists, etc.

[0074] 5. Operator: The specific optimization methods and parameters used in each stage. For example, in logic optimization, the rewrite operator that performs equivalent replacement on local logic networks, etc.

[0075] 6. Cut: A set of nodes that can completely represent the function of the root node extracted from the original circuit diagram representation.

[0076] 7. Subgraph: A local subgraph cut out from the circuit diagram representation, usually including the set of nodes where the cut is located, the root node, and all node sets connecting the root node and the set of nodes where the cut is located.

[0077] 8. Gain: The optimization effect of key indicators after executing a certain operator, such as a decrease in area or a decrease in hierarchy.

[0078] 9. Boolean satisfiability (SAT): It is used to solve whether there exists a set of variable assignments in a given truth equation to make the problem satisfiable. If such an assignment exists, this formula is satisfiable; otherwise, it is unsatisfiable. The Boolean satisfiability problem belongs to the decision problem and is also the first problem proven to be non-deterministic polynomial (NP) complete in polynomial complexity.

[0079] 10. Maximum fanout free cone (MFFC): In the process of logic synthesis and optimization, MFFC refers to the largest set of nodes independently used by the root node. The nodes in the MFFC have no output edges pointing to other parts except inside the current subgraph. When the root node is deleted, the nodes inside the MFFC can be deleted together without affecting the overall circuit function. MFFC is the maximum possible benefit for optimizing a subgraph.

[0080] Circuit power, performance, and area (PPA) are the core metrics that electronic design automation (EDA) tool developers and users are concerned about. However, according to Moore's Law, as the chip scale increases year by year, EDA tools need to process circuits of larger scales. In addition to PPA, the running time of EDA tools is also a key factor in improving the work efficiency of EDA users, which is related to chip engineers obtaining the feedback of tool running results in a timely manner and the chip's time to market. Moreover, the efficiency optimization of EDA tools themselves can also indirectly improve PPA.

[0081] Logic synthesis, which is located at the front end of the EDA tool chain, is used to synthesize the high-level description of the circuit abstraction into the low-level gate-level netlist and is one of the time-consuming bottlenecks in the tool chain. The logic synthesis tool needs to iteratively call various synthesis operators to optimize the PPA of the netlist. Therefore, the efficiency of each operator is the cornerstone of improving the synthesis efficiency. Since netlist optimization is mostly an NP-hard problem, synthesis operators are mostly heuristic algorithms and need to traverse all nodes, cuts, and subgraphs (collectively referred to as subgraphs) and call the core synthesis engine to attempt to optimize the netlist.

[0082] Figure 1 It is an exemplary flowchart of logic synthesis optimization.

[0083] 110. Traverse all subgraphs.

[0084] The circuit can be represented by a graph, and a subgraph is a part cut out from the circuit diagram representation. For each subgraph in the circuit diagram representation, the method shown in Figure 1 can be executed.

[0085] 120, Call the core synthesis engine to attempt to optimize the subgraph.

[0086] The core synthesis engine is used to optimize the subgraph. For example, an atomic graph can be replaced with a candidate subgraph with higher benefits. The candidate subgraph has a different structure from the atomic graph but is functionally equivalent.

[0087] 130, Confirm whether the subgraph can be optimized.

[0088] If the subgraph can be optimized, for example, a candidate subgraph with higher benefits can be found to replace the subgraph, then step 140 is executed. Otherwise, continue to attempt to optimize the next subgraph.

[0089] 140, Replace the atomic graph.

[0090] Replace the subgraph with the candidate subgraph.

[0091] Figure 2 It is an exemplary flowchart of another logic synthesis optimization method. Figure 2 The method shown corresponds to Figure 1 step 120.

[0092] 210, Traverse the nodes in the atomic graph 201.

[0093] The atomic graph 201 is any subgraph in the circuit diagram representation. By traversing the nodes in the atomic graph 201, the corresponding MFFC 203 of the atomic graph 201 can be found.

[0094] Exemplarily, the nodes in the root node or the set of root nodes of the atomic graph 201 can be used as the starting point for traversal, and the depth - first search or breadth - first search algorithm can be used to traverse the atomic graph 201. During the traversal, the visited nodes are marked to avoid repeated visits and infinite loops. During the traversal, each traversed node is judged. If a node has an output connection pointing to a node outside the current subgraph (i.e., other nodes also depend on the currently traversed node), then this node will not continue to traverse downwards, but terminate the traversal of this path, and continue to use the depth - first search or breadth - first search algorithm to traverse other paths until all possible paths are traversed. After the traversal is completed, return the size of the recorded MFFC203 and the corresponding node set.

[0095] 220, Generate candidate subgraphs.

[0096] The candidate sub-graph 205 is a sub-graph that has a different structure from the atomic graph 201 but is functionally equivalent. In some possible circuit optimization methods, using the candidate sub-graph 205 to replace the atomic graph 201 can obtain a relatively high overall synthesis benefit. It should be understood that using the candidate sub-graph 205 to replace the atomic graph 201 means deleting the corresponding MFFC 203 of the atomic graph 201 in the original circuit and adding the candidate sub-graph 205.

[0097] Exemplarily, one or more candidate sub-graphs 205 corresponding to the atomic graph 201 can be generated according to a functional truth table, an input-negation-permutation-output-negation (NPN) equivalence class matching database, a disjoint support decomposition (DSD), or SAT solving.

[0098] 230, logical sharing.

[0099] In a circuit diagram representation, a sub-graph adjacent to the atomic graph 201 is a neighboring sub-graph 207 of the atomic graph 201. Adjacency means that there are shared or dependent nodes between sub-graphs. If the structure of a certain neighboring sub-graph 207 of the atomic graph 201 is different from that of the atomic graph 201 but is functionally equivalent, it means that this neighboring sub-graph 207 can be used as a candidate sub-graph of the atomic graph 201 and is preferentially used to attempt to replace the atomic graph 201.

[0100] 240, determining the benefit.

[0101] The set of nodes corresponding to the MFFC 203 are the nodes that can be deleted in the atomic graph 201. Determine the benefit of using the candidate sub-graph 205 to replace the atomic graph 201, that is, determine the optimization effect of deleting the MFFC 203 and adding the candidate sub-graph 205 in the circuit diagram representation. If the benefit meets the requirements, then delete the MFFC 203 and add the candidate sub-graph 205 in the circuit diagram representation.

[0102] It should be understood that even though core synthesis engines such as SAT and DSD have been continuously optimized, their time consumption cannot be ignored. The complexity of the above brute-force traversal algorithm is O(QC), O(QCS), or O(QC 2 ), where Q is the number of nodes in the graph, C is the number of cuts on the nodes, and S is the number of equivalent sub-graphs of the cuts. At the same time, the overall netlist benefit of most synthesis operators is only 1 - 10%, which also means that there is 90 - 99% redundant calculation and ineffective calls to the time-consuming synthesis engine when traversing all possible sub-graphs.

[0103] The logic synthesis method provided by this application can estimate valid sub-graphs and invalid sub-graphs, and prune the estimated invalid sub-graphs in advance to reduce redundant calls to the synthesis engine.

[0104] The logic synthesis method provided by this application is a unified logic synthesis acceleration framework that does not depend on the underlying synthesis algorithms and representations and can be used in various EDA logic synthesis scenarios to accelerate logic synthesis operators at various levels and stages, including but not limited to word-level, gate-level, and bit-level synthesis. In addition, it can also be used for general software synthesis or IR optimization of compilers, etc.

[0105] Figure 3 It is an exemplary flowchart of a logic synthesis optimization method provided by an embodiment of this application.

[0106] 310. Obtain N subgraphs corresponding to the circuit.

[0107] It should be understood that the circuit can be represented by a graph, a subgraph is a part cut out from the circuit diagram representation, and N is an integer greater than or equal to 1.

[0108] 320. Determine M estimated effective subgraphs.

[0109] According to the synthesis optimization prediction model and the N subgraphs, determine M estimated effective subgraphs. The synthesis optimization prediction model is used to predict whether a subgraph can be optimized, and the synthesis optimization prediction model can adopt a linear model, a decision tree model, a neural network model, etc.

[0110] If a subgraph is predicted to be optimizable, then the subgraph is an estimated effective subgraph. If a subgraph is predicted not to be optimizable, then the subgraph is an estimated ineffective subgraph, M ≤ N, and M is an integer greater than or equal to 1.

[0111] 330. Perform logic synthesis optimization on P estimated effective subgraphs.

[0112] The P estimated effective subgraphs belong to the M estimated effective subgraphs, P ≤ M. The logic synthesis optimization includes replacing the original graph with a corresponding candidate graph with higher benefits. The original graph and the corresponding candidate graph have different structures but are functionally equivalent. P is an integer greater than or equal to 1.

[0113] Figure 4 It is a schematic flowchart of a model training provided by an embodiment of this application.

[0114] 410. Offline train the comprehensive benefit estimation model and the pruning model.

[0115] The training set circuit 401 can be at least one typical circuit selected according to the general circuit characteristics of the user. Optionally, it can also be one or more typical circuits selected by the user according to the characteristics of their own project, which is used to improve the logic synthesis acceleration effect on this project and reduce the impact of synthesis PPA. It should be understood that if the training set circuit 401 and the new circuit to be synthesized and optimized belong to the same circuit distribution, or have similar structures, functions, etc., then the model that performs well on the training set circuit 401 will also perform well on the new circuit.

[0116] Exemplarily, normal logic synthesis optimization without pruning can be performed on the training set circuit 401, and a large number of data pairs of subgraph features and synthesis benefits are collected for training the synthesis benefit prediction model and the pruning model. It should be understood that pruning a subgraph means not performing logic synthesis optimization on this subgraph, that is, not calling the synthesis engine to optimize this subgraph during the logic synthesis optimization process.

[0117] In a possible implementation manner, the logic synthesis optimization method proposed in this application can be used on multiple training set circuits 401, and then the model parameters are trained with the subgraph pruning number, synthesis time, PPA, etc. as the optimization objectives to achieve the balance of synthesis efficiency and synthesis effect. The model training algorithm can adopt algorithms based on gradient backpropagation, reinforcement learning, black box algorithms such as genetic algorithms, Bayesian optimization, etc.

[0118] In a possible implementation manner, the synthesis benefit prediction model and the pruning model can also be combined into a synthesis optimization prediction model, and the training set circuit 401 can be used to perform offline training on this synthesis optimization prediction model.

[0119] 420, online fine-tuning of the synthesis benefit prediction model and the pruning model.

[0120] It should be understood that in some possible implementation scenarios, the new circuit to be synthesized and optimized may be quite different from the training set circuit 401. Although the model trained in step 410 performs well overall on the training set circuit 401, there may also be problems with inaccurate benefit prediction on the new circuit, resulting in the deterioration of PPA or no acceleration effect.

[0121] To alleviate the generalization problem of the synthesis benefit prediction model and the pruning model on the new circuit, the online fine-tuning of the synthesis benefit prediction model and the pruning model can be performed according to some nodes or subgraphs 403 that have been synthesized or sampled from the current circuit to obtain a new model that performs better on this new circuit. Some nodes or subgraphs 403 that have been synthesized or sampled from the current circuit are a small part of nodes or subcircuits sampled from the new circuit. The sampling methods include random sampling, subcircuit classification and sampling, sampling according to the circuit structure such as sampling in topological order, sampling by layer, etc.

[0122] In some possible application scenarios, for a specific circuit, a customized model that is more friendly to the circuit is required. In this case, part of the specific circuit can be selected to perform online fine-tuning on the comprehensive revenue estimation model and the pruning model. It should be understood that when performing online fine-tuning on the model, only using a part of the circuit for fine-tuning, or having fewer fine-tuning iterations, can reduce the additional overhead.

[0123] In one possible implementation, the comprehensive revenue estimation model and the pruning model can also be combined into a comprehensive optimization prediction model. Part of the nodes or subgraphs 403 that have been synthesized or sampled from the current circuit can be used to perform online fine-tuning on the comprehensive optimization prediction model.

[0124] 430, online inference of the comprehensive revenue estimation model and the pruning model.

[0125] The un-synthesized nodes or subgraphs 405 of the current circuit refer to the nodes or subgraphs in the current circuit that have not been comprehensively optimized yet. If there is no need to fine-tune the model, the un-synthesized nodes or subgraphs 405 of the current circuit include all the nodes or subgraphs in the circuit, and are comprehensively optimized one by one in a certain access order. It should be understood that a part of the circuit that initially executes the logic synthesis method provided in this application will not be pruned, and is only used to collect historical comprehensive revenue information for cold-starting the comprehensive revenue estimation model and the pruning model. If it is necessary to fine-tune the model, the un-synthesized nodes or subgraphs 405 of the current circuit can include all the nodes or subgraphs, or only the nodes or subgraphs that have not been fine-tuned.

[0126] Optionally, the comprehensive revenue estimation model trained in step 410, or the comprehensive revenue estimation model fine-tuned in step 420 can be used to online predict the comprehensive revenue or the confidence of the comprehensive revenue of the un-synthesized nodes or subgraphs 405 of the current circuit, and according to the pruning model trained in step 410, or the pruning model fine-tuned in step 420, to determine whether it is necessary to prune the node or subgraph.

[0127] In one possible implementation, the comprehensive revenue estimation model and the pruning model can also be combined into a comprehensive optimization prediction model. The comprehensive optimization prediction model can be used to perform online inference on the un-synthesized nodes or subgraphs 405 of the current circuit.

[0128] Figure 5 It is an exemplary flowchart of another logic synthesis optimization method provided by the embodiments of this application.

[0129] 510, traverse all subgraphs.

[0130] Traverse all subgraphs of the circuit. In the logic synthesis optimization method provided by this application, before calling the time-consuming logic synthesis optimization, that is, before executing step 560, first estimate the synthesis benefit or the confidence level of the synthesis benefit of the subgraph and prune some subgraphs that are likely to be unoptimizable to reduce the number of calls to the synthesis engine.

[0131] 520, Extract subgraph circuit features.

[0132] Extract the features related to the synthesis benefit in the subgraph. In a possible implementation, the current subgraph can be matched in the graph evaluation benefit database to obtain the evaluation benefit features corresponding to the subgraph. The graph evaluation benefit database stores the evaluation benefit data when historical subgraphs are synthesized.

[0133] In a possible implementation, the structural features of the subgraph can also be calculated or estimated. For example, the number of nodes, the number of reused nodes, MFFC and other structural features of the subgraph can be extracted or estimated, and these features can model the circuit performance corresponding to the current subgraph.

[0134] 530, Estimate the synthesis benefit.

[0135] According to the features extracted in 520, use the synthesis benefit estimation model to estimate the synthesis benefit or the confidence level of the synthesis benefit. The synthesis benefit estimation model can adopt a linear model, a decision tree model, a neural network model, etc. The specific type of the synthesis benefit estimation model should not be construed as a limitation of this application.

[0136] 540, Determine whether the subgraph is a pre-estimated invalid subgraph.

[0137] According to the prediction result of the synthesis benefit estimation model and the pruning model, determine whether the current subgraph is a pre-estimated invalid subgraph. A pre-estimated invalid subgraph refers to a subgraph that is predicted to be unlikely to be optimized. Exemplarily, taking the predicted synthesis benefit or the confidence level of the synthesis benefit as the input of the pruning model, the optimization prediction result of the current subgraph can be output. The pruning model can adopt a linear model, a decision tree model, a neural network model, etc. The specific type of the pruning model should not be construed as a limitation of this application.

[0138] If the optimization prediction result of the current subgraph is a pre-estimated invalid subgraph, perform the pruning operation in step 550. Otherwise, the current subgraph is a valid subgraph, and step 560 is executed.

[0139] 550, Pruning.

[0140] Pruning the current subgraph means skipping the current subgraph without executing step 560 and continuing to traverse the next subgraph.

[0141] 560, Call the core synthesis engine for synthesis optimization.

[0142] Invoke the core synthesis engine to execute on the estimated valid subgraphs Figure 2 The logic synthesis optimization method shown. The core synthesis engine includes various algorithms for optimizing subgraphs, such as NPN equivalence class matching, DSD, SAT, etc. Invoking the core synthesis engine to perform logic synthesis optimization on subgraphs is the bottleneck of the logic synthesis time-consuming. Since the method provided by this application can prune the estimated invalid subgraphs and only perform logic synthesis optimization on the estimated valid subgraphs, it can accelerate the process of logic synthesis optimization and improve the efficiency of logic synthesis optimization.

[0143] 570, Determine whether the subgraph can be optimized.

[0144] Optimization means that the candidate subgraph for replacing the atomic graph can improve the PPA of the chip compared to the atomic graph. If the candidate subgraph can improve the PPA of the chip compared to the atomic graph, it means that the subgraph can be optimized, and step 580 is executed. Otherwise, it means that the subgraph cannot be optimized, and step 590 is executed.

[0145] 580, Replace the atomic graph.

[0146] Delete the MFFC of the atomic graph on the circuit and add a candidate subgraph that has a different structure but is functionally equivalent to the atomic graph.

[0147] 590, Determine whether to choose to prune the invalid subgraphs according to the true benefit sequence.

[0148] In some possible implementation manners, before executing step 560, the comprehensive benefit estimation model can be used to perform comprehensive benefit estimation on all subgraphs in the circuit, prune the estimated invalid subgraphs in the circuit, and only retain the estimated valid subgraphs. Then, these estimated valid subgraphs are sorted in descending order according to the estimated comprehensive benefit or the confidence level of the comprehensive benefit, and steps 560 to 590 are sequentially executed according to this sorting order.

[0149] If the estimated valid subgraph at the m-th sorting position cannot bring comprehensive benefits, it is considered that the estimated valid subgraphs after the m-th sorting position cannot be optimized either, and the current iteration process can be terminated in advance.

[0150] Figure 6 It is an exemplary flowchart of another logic synthesis optimization method provided by an embodiment of this application.

[0151] 610, Graph matching.

[0152] The graph evaluation revenue database 603 stores the evaluation revenue data when historical subgraphs are integrated, that is, the data pairs of (subgraph key value, comprehensive evaluation revenue). It should be understood that there are a very large number of subgraph structures and functions in the circuit, depending on the input and output and internal structure of the circuit corresponding to the subgraph. Multiple subgraphs of the circuit can be classified into a few categories of subgraphs, and each category of subgraphs can share features to reduce the amount of data stored in the graph evaluation revenue database 603. The subgraph key value is an identifier or index used to uniquely determine a certain category of subgraphs in the graph evaluation revenue database 603. The comprehensive evaluation revenue includes any one or more of the parameters E, W, G, and GL, corresponding to each type of subgraph key value. Among them, E represents the number of times a certain category of subgraphs is evaluated, W is the number of times a certain category of subgraphs is selected as the optimal subgraph, G represents the global comprehensive revenue, and GL represents the local comprehensive revenue. The global comprehensive revenue refers to the comprehensive revenue corresponding to the optimal candidate subgraph after the iteration of candidate subgraphs is completed. The local comprehensive revenue refers to the revenue of each candidate subgraph when iteratively selecting the optimal candidate subgraph, which can be positive or negative.

[0153] In some possible implementation manners, logical synthesis optimization as shown in Figure 2 can be performed on one or more typical circuits to generate the graph evaluation revenue database 603. Optionally, logical synthesis optimization as shown in Figure 2 can also be performed on some sub-circuits in the circuit where the current subgraph 601 is located to generate the graph evaluation revenue database 603. In some possible implementation manners, logical synthesis optimization as shown in Figure 2 can also be performed on one or more typical circuits and some sub-circuits in the circuit where the current subgraph 601 is located to generate the graph evaluation revenue database 603. The embodiments of the present application do not limit the generation manner of the graph evaluation revenue database 603.

[0154] Exemplarily, G and GL of the comprehensive evaluation revenue can be referred to as evaluation revenue features. The evaluation revenue features can be a two-dimensional time series of the evaluation revenue of historical subgraphs or a one-dimensional total evaluation revenue. In the case where the evaluation revenue feature is a two-dimensional time series of the evaluation revenue, since historical subgraphs are accessed and integrated one by one, the historical access can be segmented into a time series, and the evaluation revenue feature of the graph evaluation revenue database 603 can be represented by a two-dimensional matrix Z F*T where Z represents that the elements in the two-dimensional matrix are integers, F is the number of rows of the two-dimensional matrix, T is the number of columns of the two-dimensional matrix. At the same time, F is the number of evaluation revenue features, and T is the number of segmented time windows. In the case where the evaluation revenue feature is a one-dimensional total evaluation revenue, the evaluation revenue feature of the graph evaluation revenue database 603 can be the total feature Z F*T obtained by summing each row in Z F .

[0155] The visited sub - graph 602 is used to construct the graph evaluation revenue database 603, which can be divided into cold - start or hot - start modes. In cold - start, the visited sub - graph 602 on the new circuit is empty, and the graph evaluation revenue database 603 needs to be updated from scratch. In hot - start, historical sub - graph revenue data of other optimized circuits are already saved in the graph evaluation revenue database 603 on the new circuit.

[0156] Graph matching methods include but are not limited to truth tables, NPN equivalent class matching, etc. If the structure or function of the current sub - graph 601 can match the corresponding sub - graph key value in the graph evaluation revenue database 603, the evaluation revenue feature 604 corresponding to the sub - graph key value is extracted and the graph evaluation revenue database 603 is updated. Otherwise, the logic synthesis optimization method shown in Figure 2 is executed on the current sub - graph 601, and the graph evaluation revenue database 603 and the visited sub - graph 602 are updated. The evaluation revenue feature 604 can be a two - dimensional time series or a one - dimensional total evaluation revenue, and this feature is used to model the performance of historical similar circuits.

[0157] Exemplarily, if the current sub - graph 601 matches the corresponding sub - graph key value after graph matching, the E corresponding to the sub - graph key value can be incremented by 1. If the current sub - graph 601 does not match the corresponding sub - graph key value after graph matching, the logic synthesis optimization method shown in Figure 2 is executed on the current sub - graph 601, and the parameters E, W, G, GL in the graph evaluation revenue database 603 are updated according to the logic synthesis optimization result. At the same time, the current sub - graph 601 is added to the visited sub - graph 602.

[0158] 620, Comprehensive revenue estimation.

[0159] The structure feature 605 can be obtained by online extraction of the current sub - graph 601, or can be the structure feature obtained by estimating the number of nodes, the number of reusable nodes, the estimated MFFC, etc. of the current sub - graph 601. This feature can be used to model the performance of the current circuit.

[0160] Logic synthesis tools mostly execute a sequence of synthesis operators alternately. Before the current synthesis operator is executed, there may already be many synthesis operators used to optimize the current circuit, and their revenue performance implicitly contains a part of the circuit features, which can be called the revenue feature 606 of historical logic synthesis operators. Therefore, the revenue feature 606 of historical logic synthesis operators can also be used to model the overall circuit to improve revenue prediction and pruning effects.

[0161] Circuits have different representations, such as Verilog, abstract syntax tree (AST), intermediate representation (IR), and and-inverted graph (AIG) that only contains 2-input and gates and negation operators. Their abstraction levels decrease while their scales increase. Therefore, circuit representations with high abstraction granularity have lower modeling complexity and higher integrity. Embodiments of this application can use high-level circuit description feature 607 to guide low-level circuit optimization. High-level circuit description feature 607 can be understood as a higher-level overall circuit representation.

[0162] The estimated benefit of the current subgraph 601 can be predicted through a comprehensive benefit estimation model, taking any one or more of the evaluation benefit feature 604, structural feature 605, benefit feature 606 of historical logic synthesis operators, and high-level circuit description feature 607 as inputs to obtain the comprehensive benefit of the current subgraph 601 or the benefit confidence of the comprehensive benefit. The implementation of the comprehensive benefit estimation model depends on operator characteristics such as the original time consumption situation, representation, etc. For lightweight operators, only the benefit feature 606 of lightweight historical logic synthesis operators can be selected as the input, and a linear or multilayer perceptron (MLP) prediction model can be used as the comprehensive benefit estimation model. For time-consuming operators, all features can be selected as inputs, and complex neural network models, such as graph neural networks (GNNs), Transformers, etc., can be used as the modeling and prediction models for the comprehensive benefit estimation model.

[0163] 630, pruning.

[0164] Taking the comprehensive benefit or the confidence of the comprehensive benefit obtained at 620 as the input, output the optimization prediction result of whether the current subgraph 601 can be optimized. The pruning model can use a linear model, a decision tree model, a neural network classification model, etc.

[0165] Exemplarily, if the current subgraph 601 is predicted as a subgraph with ineffective estimation, then prune the current subgraph 601, that is, do not perform the Figure 2 shown logic synthesis optimization method, and update features such as E and GL in the graph evaluation benefit database 603. For example, add 1 to E corresponding to the key value of the current subgraph 601, and set GL to -1 as a penalty term. If the current subgraph 601 is predicted as a subgraph with effective estimation, then perform the Figure 2The logic synthesis optimization method shown, and according to the real synthesis result, update the parameters corresponding to the key value of the current sub-graph 601 in the graph evaluation benefit database 603, such as E, W, G, and GL. For example, increment the E corresponding to the current sub-graph 601 by 1, and set W, G, and GL corresponding to the current sub-graph 601 according to the real synthesis result.

[0166] It should be understood that the synthesis benefit prediction model and the pruning model can also be combined into one model. Exemplarily, the combined model is a synthesis optimization prediction model, which can take any one or more of the evaluation benefit feature 604, structure feature 605, benefit feature 606 of historical logic synthesis operators, and circuit high-level description feature 607 as inputs, and output an optimization prediction result indicating whether the current sub-graph 601 can be optimized. In the subsequent synthesis process, only the sub-graphs predicted to be optimizable are executed with the method shown in Figure 2 to reduce redundant calls to the synthesis engine.

[0167] Figure 7 is an exemplary flowchart of model selection provided by an embodiment of the present application.

[0168] In addition to Figure 4 online fine-tuning the synthesis benefit prediction model and the pruning model on the new circuit shown, multiple models for different circuit types can also be pre-trained in advance, such as model 1, model 2,..., model n. Then, when inferring on the new circuit, online identify the circuit type and select a model for this circuit type, such as model 2.

[0169] 710, extract features related to the circuit type.

[0170] Extract features related to the circuit type on the current new circuit, such as the benefit distribution of visited sub-graphs, circuit functions, high-level circuit representations, etc.

[0171] 720, determine the circuit type.

[0172] Input the features related to the circuit type obtained in step 710 into the circuit type identifier to determine which type the current new circuit belongs to. The circuit type identifier can adopt a linear model, a decision tree model, a neural network model, etc.

[0173] 730, select a suitable model.

[0174] According to the circuit type identification result in step 720, select a suitable model from the n pre-trained models, such as model 2. The n models can be a synthesis benefit prediction model or a pruning model, or can also be a synthesis optimization prediction model obtained by combining the synthesis benefit prediction model and the pruning model.

[0175] The above describes the logic synthesis optimization method according to the embodiments of the present application. Below, we will separately combineFigure 8 and Figure 9 Describe apparatuses and devices according to embodiments of the present application.

[0176] Embodiments of the present application also provide a computer storage medium, in which program instructions are stored, and when the program is executed, it may include some or all of the steps of the logic synthesis optimization method in the Figures 2 - 7 corresponding embodiment.

[0177] Figure 8 FIG. 1100 is a structural example diagram of a computer apparatus provided by an embodiment of the present application. The computer apparatus 1100 includes an acquisition module 1110 and a processing module 1120. The acquisition module 1110 and the processing module 1120 may be implemented by software, hardware, or a combination of both. The computer apparatus 1100 may be an EDA logic synthesis tool or a related module, device, etc. installed with the tool. After the apparatus of the present application is integrated into the logic synthesis software, multiple switches and interfaces can be added, such as a switch for turning on high-efficiency synthesis, a switch for turning on evaluation of benefits and local sub-graph feature extraction, an efficiency-effect optimization balance interface for configuring multi-objective weights, and an online model parameter tuning switch to improve the generalization of the model.

[0178] Among them, the acquisition module 1110 is used to acquire N sub-graphs corresponding to a circuit to execute Figure 3 310 in the Figure 5 and 510 in the

[0179] The processing module 1120 is used to determine M estimated effective sub-graphs according to the synthesis optimization prediction model and the N sub-graphs, and perform logic synthesis optimization on P of the M estimated effective sub-graphs, and execute Figures 2 - 7 some or all of the steps in the

[0180] Figure 9 FIG. 1200 is a structural example diagram of another computer apparatus provided by an embodiment of the present application. The computer apparatus 1200 includes a processor 1202, a communication interface 1203, and a memory 1204. An example of the computer apparatus 1200 is a computing device, such as a server for performing EDA simulation.

[0181] The method disclosed in the embodiments of the present application can be applied to or implemented by the processor 1202. The processor 1202 can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor, etc. In the implementation process, the steps of the above method can be completed by the integrated logic circuit in the hardware of the processor 1202 or the instructions in the form of software. The various methods, steps, and logic block diagrams disclosed in the embodiments of the present application can be implemented or executed. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as being executed and completed by the hardware decoding processor, or executed and completed by the combination of the hardware and software modules in the decoding processor.

[0182] The memory 1204 can be a volatile memory, a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), and direct rambus RAM (DRRAM). It should be noted that the memory of the methods described herein is intended to include but not be limited to these and any other suitable types of memories.

[0183] Communication can occur between the processor 1202, the memory 1204, and the communication interface 1203 via a bus. Executable code is stored in the memory 1204, and the processor 1202 reads the executable code in the memory 1204 to execute the corresponding method. The memory 1204 may also include software modules required for other running processes, such as an operating system. The operating system can be LINUX TM , UNIX TM , WINDOWS TM and so on.

[0184] For example, the executable code in the memory 1204 is used to implement the Figures 2 - 7 method shown, and the processor 1202 reads the executable code in the memory 1204 to execute the Figures 2 - 7 method shown.

[0185] In some embodiments of the present application, the disclosed method can be implemented as computer program instructions encoded in a machine-readable format on a computer-readable storage medium or encoded on other non-transitory media or articles. Figure 10A conceptual partial view of an example computer program product arranged in accordance with at least some of the embodiments presented herein is schematically shown. The example computer program product includes a computer program for executing a computer process on a computing device. In one embodiment, the example computer program product 1300 is provided using a signal bearing medium 1301. The signal bearing medium 1301 may include one or more program instructions 1302 which, when run by one or more processors, may provide the functions or portions of functions described above for Figures 2 - 7 the methods shown. Thus, for example, referring to the embodiments shown in Figures 2 - 7 , one or more of the features therein may be carried out by one or more instructions associated with the signal bearing medium 1301.

[0186] In some examples, the signal bearing medium 1301 may comprise a computer readable medium 1303 such as, but not limited to, a hard disk drive, a compact disk (CD), a digital video disk (DVD), a digital tape, a memory, a read-only memory (ROM), or a random access memory (RAM), etc. In some implementations, the signal bearing medium 1301 may comprise a computer recordable medium 1304 such as, but not limited to, a memory, a read / write (R / W) CD, a R / W DVD, etc. In some implementations, the signal bearing medium 1301 may comprise a communication medium 1305 such as, but not limited to, digital and / or analog communication media (e.g., fiber optic cable, waveguide, wired communication link, wireless communication link, etc.). Thus, for example, the signal bearing medium 1301 may be conveyed by a wireless form of the communication medium 1305 (e.g., a wireless communication medium compliant with the IEEE802.11 standard or other transmission protocol). The one or more program instructions 1302 may be, for example, computer executable instructions or logic implementing instructions. In some examples, the aforementioned computing device may be configured to provide various operations, functions, or actions in response to program instructions 1302 communicated to the computing device via one or more of the computer readable medium 1303, the computer recordable medium 1304, and / or the communication medium 1305. It should be understood that the arrangements described herein are for purposes of example only. Thus, those skilled in the art will understand that other arrangements and other elements (e.g., machines, interfaces, functions, orders, and groups of functions, etc.) can be used instead, and some elements may be omitted altogether depending on the desired results. Additionally, many of the elements described can be implemented as discrete or distributed components, or as functional entities combined with other components in any suitable combination and location.

[0187] Those of ordinary skill in the art can realize that the units and method steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0188] Those skilled in the art can clearly understand that for the convenience and conciseness of description, the specific working processes of the above-described devices and units can refer to the corresponding processes in the foregoing method embodiments and will not be described herein again.

[0189] In several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there can be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection to each other can be through some interfaces. The indirect coupling or communication connection of the devices or units can be in an electrical, mechanical or other form.

[0190] The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0191] In addition, the functional units in each embodiment of this application can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit.

[0192] When the above-mentioned functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art or a part of this technical solution can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of this application. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM), random access memories (RAM), magnetic disks, or optical discs that can store program codes.

[0193] As described above, the above is only the specific implementation manner of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art within the technical scope disclosed by this application can easily think of changes or substitutions, which should all be covered within the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

1. A method for optimizing the logic synthesis of a circuit, characterized in that, Including: Obtaining N sub - graphs corresponding to the circuit, where the sub - graph is a part of the graph representation corresponding to the circuit, and N is an integer greater than or equal to 1; Determining M estimated effective sub - graphs according to the comprehensive optimization prediction model and the N sub - graphs, where the comprehensive optimization prediction model is used to predict whether the sub - graph can be optimized, and the estimated effective sub - graph is a sub - graph predicted to be able to be optimized, and M ≤ N; Performing logic synthesis optimization on P estimated effective sub - graphs, where the P estimated effective sub - graphs belong to the M estimated effective sub - graphs, and P ≤ M.

2. The method according to claim 1, characterized in that, The step of determining M estimated effective sub - graphs according to the comprehensive optimization prediction model and the N sub - graphs includes: Obtaining the optimization prediction features corresponding to the first sub - graph, where the optimization prediction features include any one or more of the evaluation benefit feature, the structure feature, the benefit feature of the historical logic synthesis operator, and the high - level circuit description feature. The first sub - graph is any one of the N sub - graphs. The evaluation benefit feature includes the optimization effect brought by the historical optimization of the sub - graph of the same type as the first sub - graph to the circuit, and the benefit of the historical logic synthesis operator includes the optimization effect brought by the historical logic synthesis operator for optimizing the circuit to the circuit; Determining that the first sub - graph is the estimated effective sub - graph according to the optimization prediction features and the comprehensive optimization prediction model.

3. The method according to claim 2, characterized in that, The optimization prediction features include the evaluation benefit feature, and the step of obtaining the optimization prediction features corresponding to the first sub - graph includes: Determining the key value of the first sub - graph; Matching the evaluation benefit feature corresponding to the first sub - graph in the graph evaluation benefit database according to the key value, where the graph evaluation benefit database includes the key values of at least one type of graph and the corresponding evaluation benefit features.

4. The method according to claim 3, characterized in that, The method further includes: Updating the graph evaluation benefit database according to the matching result of the first sub - graph in the graph evaluation benefit database or the logic synthesis optimization result of the first sub - graph.

5. The method according to any one of claims 1 to 4, characterized in that Before performing logic synthesis optimization on P estimated effective sub - graphs, the method further includes: Sorting the M estimated effective sub - graphs from high to low according to the comprehensive benefit of the M estimated effective sub - graphs or the confidence level of the comprehensive benefit. The P estimated effective sub - graphs are the top P estimated effective sub - graphs after sorting the M estimated effective sub - graphs, and the comprehensive benefit includes the optimization effect brought by the optimized sub - graph to the circuit.

6. The method according to any one of claims 1 to 5, characterized in that, The comprehensive optimization prediction model includes a comprehensive benefit estimation model and a pruning model. The comprehensive benefit estimation model is used to predict the comprehensive benefit or the confidence level of the comprehensive benefit. The comprehensive benefit includes the optimization effect brought by using a candidate sub - graph to replace the sub - graph in the circuit. The candidate sub - graph has a different structure from the sub - graph but the same function. The pruning model is used to judge whether the sub - graph is an estimated effective sub - graph according to the comprehensive benefit or the confidence level of the comprehensive benefit.

7. The method according to any one of claims 1 to 6, characterized in that, The step of performing logic synthesis optimization on P estimated effective sub - graphs includes: Replace a second subgraph with a first candidate subgraph in the circuit, where the second subgraph is any one of the P estimated effective subgraphs, the first candidate subgraph has a different structure but the same function as the second subgraph, and the comprehensive benefit of the candidate subgraph is greater than or equal to the comprehensive benefit of the second subgraph.

8. The method according to claim 7, wherein The replacing of the second subgraph with the first candidate subgraph in the circuit includes: Deleting the maximum fanout-free cone (MFFC) of the second subgraph in the circuit; Adding the first candidate subgraph in the circuit.

9. The method according to any one of claims 1 to 8, characterized in that The comprehensive optimization prediction model is trained by the optimization prediction features of multiple subgraphs and the corresponding optimization estimation results. The optimization prediction features include any one or more of the evaluation benefit feature, the structure feature, the benefit feature of the historical logic synthesis operator, and the circuit high-level description feature.

10. A computer device, characterized in that, It includes: An acquisition module for acquiring N subgraphs corresponding to the circuit, where the subgraph is a part of the graph representation corresponding to the circuit, and N is an integer greater than or equal to 1; A processing module for determining M estimated effective subgraphs according to the comprehensive optimization prediction model and the N subgraphs. The comprehensive optimization prediction model is used to predict whether the subgraph can be optimized, and the estimated effective subgraph is a subgraph predicted to be optimizable, where M ≤ N; Performing logic synthesis optimization on P estimated effective subgraphs, where the P estimated effective subgraphs belong to the M estimated effective subgraphs and P ≤ M.

11. The device according to claim 10, characterized in that, The processing module is specifically used for: Acquiring the optimization prediction features corresponding to the first subgraph, where the optimization prediction features include any one or more of the evaluation benefit feature, the structure feature, the benefit feature of the historical logic synthesis operator, and the circuit high-level description feature. The first subgraph is any one of the N subgraphs. The evaluation benefit feature includes the optimization effect brought by the historical optimization of subgraphs of the same type as the first subgraph to the circuit, and the benefit of the historical logic synthesis operator includes the optimization effect brought by the historical logic synthesis operator for optimizing the circuit to the circuit; Determining that the first subgraph is the estimated effective subgraph according to the optimization prediction features and the comprehensive optimization prediction model.

12. The device according to claim 11, characterized in that, The optimization prediction features include the evaluation benefit feature. The processing module is specifically used for: Determining the key value of the first subgraph; Matching the evaluation benefit feature corresponding to the first subgraph in the graph evaluation benefit database according to the key value. The graph evaluation benefit database includes the key values of at least one type of graph and the corresponding evaluation benefit features.

13. The device according to claim 12, characterized in that, The processing module is further used to update the graph evaluation benefit database according to the matching result of the first subgraph in the graph evaluation benefit database or the logic synthesis optimization result of the first subgraph.

14. The device according to any one of claims 10 to 13, characterized in that, The processing module is further used to sort the M estimated effective subgraphs from high to low according to the comprehensive benefit of the M estimated effective subgraphs or the confidence level of the comprehensive benefit. The P estimated effective subgraphs are the first P estimated effective subgraphs after sorting the M estimated effective subgraphs. The comprehensive benefit includes the optimization effect brought by the optimized subgraph to the circuit.

15. The device according to any one of claims 10 to 14, characterized in that, The comprehensive optimization prediction model includes a comprehensive revenue estimation model and a pruning model. The comprehensive revenue estimation model is used to predict the comprehensive revenue or the confidence level of the comprehensive revenue. The comprehensive revenue includes the optimization effect brought to the circuit by replacing the subgraph with a candidate subgraph in the circuit. The candidate subgraph has a different structure but the same function as the subgraph. The pruning model is used to determine whether the subgraph is a pre-estimated effective subgraph according to the comprehensive revenue or the confidence level of the comprehensive revenue.

16. The device according to any one of claims 10 to 15, characterized in that The processing module is specifically configured to: Replace a second subgraph with a first candidate subgraph in the circuit. The second subgraph is any one of the P pre-estimated effective subgraphs. The first candidate subgraph has a different structure but the same function as the second subgraph, and the comprehensive revenue of the candidate subgraph is greater than or equal to the comprehensive revenue of the second subgraph.

17. The device according to claim 16, wherein The processing module is specifically configured to: Delete the maximum fan-out free cone (MFFC) of the second subgraph in the circuit; Add the first candidate subgraph in the circuit.

18. The device according to any one of claims 10 to 17, characterized in that The comprehensive optimization prediction model is trained through the optimization prediction features of multiple subgraphs and the corresponding optimization prediction results. The optimization prediction features include any one or more of the evaluation revenue feature, the structure feature, the revenue feature of the historical logic synthesis operator, and the circuit high-level description feature.

19. A computer device, characterized in that, Comprising: A processor, which is used to be coupled with a memory, read and execute the instructions and / or program codes in the memory to execute the method according to any one of claims 1-9.

20. A computer-readable medium, characterized in that, The computer-readable medium stores computer program codes. When the computer program codes run on a computer, the computer is caused to execute the method according to any one of claims 1-9.

21. A computer program product, characterized in that, The computer program product includes computer program codes. When the computer program codes run on a computer, the computer is caused to execute the method according to any one of claims 1-9.

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