FPGA interconnection resource traversal test method

Abstract

The invention belongs to the technical field of FPGA testing, and particularly relates to an FPGA interconnection resource traversal testing method. According to the FPGA interconnection resource traversal testing method, firstly, modeling is conducted on FPGA interconnection resources, a wiring resource diagram and an interconnection TILE diagram are constructed, the wiring resource diagram is a directed graph model established for all actually existing interconnection resources in an FPGA, and the interconnection TILE diagram is a directed graph model established for abstract interconnection resources in a single interconnection TILE; then regular wiring is carried out, that is, sub-graphs meeting certain constraint conditions are selected from the interconnection TILE graph and mapped to a wiring resource graph; and eliminating wiring loops and wiring breakpoints, which do not conform to the wiring rule, in the wire network through auxiliary wiring to obtain a to-be-tested wire network meeting the wiring rule, thereby traversing FPGA interconnection resources. The method is high in universality and suitable for FPGAs of different architectures; the wiring result is regular and easy to understand and realize; and a higher fault coverage rate can be realized by using a small number of configurations.

Description

Technical Field

[0001] The present invention belongs to the technical field of FPGA testing, and particularly relates to a method for traversing and testing FPGA interconnection resources. Background Art

[0002] FPGA chips, that is, field programmable gate array chips, are widely used in fields such as communication systems, big data, and artificial intelligence. In modern FPGAs, interconnection resources generally account for more than half of the chip area. Therefore, interconnection resource testing is of great significance for ensuring the security and reliability of FPGAs.

[0003] Existing methods for traversing and testing FPGA interconnection resources traverse interconnection resources by running search algorithms on the routing resource graph, such as the maximum flow algorithm, depth-first algorithm, deep learning algorithm, etc. The disadvantage of these methods is that the routing results are random, which is not conducive to subsequent fault analysis. In addition, when the scale of the FPGA is very large, problems such as too long algorithm running time, too large algorithm memory overhead, and unsatisfactory search effect may occur. Other methods for traversing and testing FPGA interconnection resources attempt to traverse interconnection resources with regular routing, but generally have the problem of incomplete traversal of interconnection resource types, and lack processing methods for irregular factors such as array boundaries, array vacancies, and non-CLB modules. Summary of the Invention

[0004] The purpose of the present invention is to provide a method for traversing and testing FPGA interconnection resources with high coverage, low number of test configurations, regular routing, and independent of chip scale.

[0005] The method for traversing and testing FPGA interconnection resources provided by the present invention specifically includes the following steps:

[0006] Step 1, interconnection resource modeling;

[0007] Step 2, regular routing;

[0008] Step 3, auxiliary routing.

[0009] Step 1, interconnection resource modeling; that is, establishing a routing resource graph and an interconnection TILE graph; where:

[0010] The routing resource graph is a directed graph model established for all actual interconnection resources in the FPGA. Its nodes are the actual interconnecting wires in the FPGA, and its directed edges are the actual programmable interconnection points (interconnection switches) in the FPGA.

[0011] The actual interconnecting wire refers to a complete interconnecting wire formed by interconnecting wire segments in one or more TILEs.

[0012] The actual programmable interconnect points (interconnect switches) refer to unidirectional interconnect switches that connect two interconnect segments and whose switching states are controlled by bitstreams. For bidirectional interconnect switches, they are modeled as two unidirectional interconnect switches.

[0013] The interconnect TILE graph is a directed graph model established for the abstract interconnect resources in a single interconnect TILE. Its nodes are the abstract interconnect lines in a single interconnect TILE, and its directed edges are the abstract programmable interconnect points (interconnect switches) in a single interconnect TILE.

[0014] The abstract interconnect line is the complete interconnect line formed by connecting the interconnect segments in a single interconnect TILE after imagining gluing the left and right sides and the top and bottom sides of the single interconnect TILE.

[0015] The abstract programmable interconnect point (interconnect switch) refers to a unidirectional interconnect switch that connects two interconnect segments in a single interconnect TILE and whose switching state is controlled by a bitstream. For bidirectional interconnect switches, they are modeled as two unidirectional interconnect switches.

[0016] In one embodiment, the interconnect resource information of the FPGA is extracted through the Tcl Console of the Vivado Design Suite, including the relevant information of FPGA objects such as TILE, WIRE (interconnect segment), PIP (interconnect switch), NODE (interconnect line), SITE (functional module), PIN (functional module port), etc. Then, after processing the interconnect resource information through an automated program, a routing resource graph and an interconnect TILE graph are obtained.

[0017] In one embodiment, if there are bidirectional interconnect lines and bidirectional interconnect switches in the FPGA, then the starting and ending points of the bidirectional interconnect lines and the directions of the bidirectional interconnect switches are determined according to the parity of the horizontal and vertical coordinates of the interconnect TILE, thereby establishing a unidirectional routing resource graph. For example, for LH, LV, and LVB in Xilinx 7 series FPGAs, 8 different unidirectional routing resource graphs can be established, which are distinguished by 3-bit binary numbers (000 - 111). The specific meanings are as follows:

[0018] When the first bit of the 3-bit binary number is 0, it means that in the interconnect TILE with an even X coordinate, LH0 is the starting point and LH12 is the ending point; in the interconnect TILE with an odd X coordinate, LH12 is the starting point and LH0 is the ending point.

[0019] When the first bit of the 3-bit binary number is 1, it means that in the interconnect TILE with an even X coordinate, LH12 is the starting point and LH0 is the ending point; in the interconnect TILE with an odd X coordinate, LH0 is the starting point and LH12 is the ending point.

[0020] The second bit of the 3-bit binary being 0 means that: among the interconnected TILEs with an even Y coordinate, LV0 is the starting point and LV18 is the ending point; among the interconnected TILEs with an odd Y coordinate, LV18 is the starting point and LV0 is the ending point.

[0021] The second bit of the 3-bit binary being 1 means that: among the interconnected TILEs with an even Y coordinate, LV18 is the starting point and LV0 is the ending point; among the interconnected TILEs with an odd Y coordinate, LV0 is the starting point and LV18 is the ending point.

[0022] The third bit of the 3-bit binary being 0 means that: among the interconnected TILEs with an even Y coordinate, LVB0 is the starting point and LVB12 is the ending point; among the interconnected TILEs with an odd Y coordinate, LVB12 is the starting point and LVB0 is the ending point.

[0023] The third bit of the 3-bit binary being 1 means that: among the interconnected TILEs with an even Y coordinate, LVB12 is the starting point and LVB0 is the ending point; among the interconnected TILEs with an odd Y coordinate, LVB0 is the starting point and LVB12 is the ending point.

[0024] Step 2, regular routing; that is, select a subgraph that meets certain constraint conditions in the interconnected TILE graph and map it to the routing resource graph to achieve regular routing.

[0025] The subgraph selected in the interconnected TILE graph, the constraint conditions include:

[0026] Constraint condition 1: In the subgraph, the in-degree of each node is at most 1;

[0027] Constraint condition 2: In the subgraph, the node with an in-degree of 0 must be the interconnection line of the output port of the functional module;

[0028] Constraint condition 3: In the subgraph, the node with an out-degree of 0 must be the interconnection line of the input port of the functional module;

[0029] Constraint condition 4: In the subgraph, there is no loop with zero displacement.

[0030] The displacement of the loop in the subgraph is defined as the difference between the coordinates of the ending interconnected TILE and the starting interconnected TILE after walking around the loop in the subgraph. The loop having a zero displacement means that after walking around the loop in the subgraph, it will return to the original interconnected TILE. The loop having a non-zero displacement means that after walking around the loop in the subgraph, it will reach another interconnected TILE with different coordinates.

[0031] Under constraint conditions 1 - 4, the connected components of the subgraph are divided into the following three cases:

[0032] Case 1: The connected component of the sub-graph is a loop, and the displacement of the loop is non-zero, that is, Constraint 4; the mapping result of this connected component is a set of parallel paths formed by cascading the interconnecting wires and interconnecting switches; the mapping result of this connected component is called a cascaded netlist.

[0033] Case 2: The connected component of the sub-graph is a single-loop graph with branches, and the displacement of the loop is non-zero, that is, Constraint 4. The leaf nodes with an out-degree of 0 in the branches are the interconnecting wires of the input ports of the functional modules, that is, Constraint 3; the mapping result of this connected component is a branch extending from the main trunk formed by parallel paths and terminating at the interconnecting wires of the input ports of the functional modules; the mapping result of this connected component is called a branched netlist.

[0034] Case 3: The connected component of the sub-graph is a tree. The nodes with an out-degree of 0, that is, the leaf nodes of the tree, are the interconnecting wires of the input ports of the functional modules, that is, Constraint 3. The nodes with an in-degree of 0, that is, the root nodes of the tree, are the interconnecting wires of the output ports of the functional modules, that is, Constraint 2; the mapping result of this connected component is many identical trees, starting from the interconnecting wires of the output ports of the functional modules and terminating at the interconnecting wires of the input ports of the functional modules; the mapping result of this connected component is called a fragmented netlist.

[0035] Mapping the sub-graph to the routing resource graph to achieve regular routing is to turn on the actual interconnecting switches corresponding to the edges (abstract interconnecting switches) included in the instruction sub-graph and turn off other actual interconnecting switches.

[0036] By selecting several sub-graphs that meet the constraint conditions and enabling them to completely traverse the interconnecting TILE graph, the corresponding actual interconnecting resources on the routing resource graph can be traversed.

[0037] In one implementation, first, the interconnecting wires of the same type are merged to obtain a merged interconnecting TILE graph, then the sub-graphs of the merged interconnecting TILE graph are selected, and then the sub-graphs of the merged interconnecting TILE graph are decomposed to obtain the sub-graphs of the interconnecting TILE graph, and mapped to the routing resource graph to achieve regular routing.

[0038] In one implementation, if there is a loopback connection in the FPGA, an additional constraint condition 5 for selecting sub-graphs can be added. Among them, the loopback connection refers to an interconnecting wire or an interconnecting switch that connects two interconnecting line segments with opposite directions at the boundary of the FPGA array (or the vacancy in the array).

[0039] Constraint 5: In a sub - graph, if there is a loop - back connection at the array boundary (or array vacancy) such that an upstream interconnect segment that should originally be connected to a downstream interconnect segment A is instead connected to a downstream interconnect segment B at the array boundary (or array vacancy), then when selecting interconnect segment B, interconnect segment A must also be selected. In particular, if both interconnect segment A and interconnect segment B are the endpoints of the interconnect lines, when selecting an interconnect switch driven by a certain interconnect segment B in the sub - graph, an interconnect switch driven by a certain interconnect segment A must also be selected. For example, in Xilinx 7 - series FPGAs, WL1END3 should have been connected to WL1END_N1_3, but it is connected to WR1END_S1_0 at the upper boundary of the array. Therefore, when selecting an interconnect switch driven by a certain WR1END_S1_0 in the sub - graph, an interconnect switch driven by a certain WL1END_N1_3 must also be selected.

[0040] Step 3, auxiliary routing; that is, eliminating the routing loops and routing breakpoints in the netlist to obtain a netlist to be tested that meets the routing rules.

[0041] In an actual FPGA, there are irregular factors such as local interconnect resources outside the CLB module, array boundaries, and array vacancies. Therefore, routing loops and routing breakpoints that do not conform to the routing rules may still appear in the netlist obtained through regular routing.

[0042] The so - called routing loop refers to an interconnect path that connects end - to - end in the netlist. The main reason for the appearance of a routing loop is that there is a loop - back connection at the FPGA array boundary (or array vacancy) that connects two interconnect segments with opposite directions, causing the interconnect path to connect end - to - end after passing through the loop - back connection multiple times.

[0043] The so - called routing breakpoint refers to a point in the netlist that is neither the starting point of the interconnect line of the output port nor the ending point of the interconnect line of the input port. The former is called the starting breakpoint, and the latter is called the ending breakpoint. The main reasons for the appearance of routing breakpoints are that the local interconnect resources outside the CLB module are not the interconnect resources to be tested and are regarded as interrupted during the generation of the netlist to be tested, and some interconnect resources may be interrupted at the array boundary (or array vacancy).

[0044] Therefore, it is necessary to eliminate the routing loops and routing breakpoints in the netlist through auxiliary routing to obtain the netlist to be tested.

[0045] In one implementation, the way to eliminate the routing loop is to disconnect a part of the interconnect switches to break the routing loop.

[0046] In one implementation, the way to eliminate the routing loop is to divide the interconnect path in the routing loop into two groups, select one group to remain unchanged in two test configurations respectively, and replace the other group with a simpler interconnect path. Then, disconnect a part of the interconnect switches in the replaced interconnect path to break the routing loop.

[0047] In one implementation, the way to eliminate the wiring breakpoints is to connect the terminating breakpoints to the input terminals of the CLBs and connect the starting breakpoints to the output terminals of the CLBs.

[0048] In one implementation, the way to eliminate the wiring breakpoints is to merge a part of the nets, and then connect the remaining terminating breakpoints to the input terminals of the CLBs and connect the remaining starting breakpoints to the output terminals of the CLBs.

[0049] In one implementation, the direct wiring of the interconnection resources is realized through the Fixed Routing Constraints in the xdc file of the Vivado design suite.

[0050] Compared with the prior art, the advantages of the present invention mainly include:

[0051] (1) Strong universality, applicable to FPGAs with different architectures;

[0052] (2) The wiring result is regular, easy to understand and implement, and is conducive to subsequent fault analysis;

[0053] (3) The coverage rate and the number of test configurations are independent of the scale of the FPGA chip;

[0054] (4) The types of interconnection resources are traversed comprehensively and completely. In particular, irregular factors such as array boundaries, array vacancies, and non-CLB modules can also be processed, and a higher fault coverage rate can be achieved with fewer configurations. Description of the Drawings

[0055] Figure 1 is the overall block diagram of the FPGA interconnection resource traversal method.

[0056] Figure 2 is the schematic diagram of the FPGA simplified model.

[0057] Figure 3 is the schematic diagram of the global interconnection switch and local interconnection switch of the FPGA simplified model.

[0058] Figure 4 is the interconnection TILE diagram of the FPGA simplified model.

[0059] Figure 5 is the merged interconnection TILE diagram of the FPGA simplified model.

[0060] Figure 6 is the sub-diagram of the merged interconnection TILE diagram of the FPGA simplified model.

[0061] Figure 7 is the sub-diagram of the interconnection TILE diagram of the FPGA simplified model.

[0062] Figure 8 It is the net to be tested in test configuration 00 - 03 of the FPGA simplified model.

[0063] Figure 9 It is the net to be tested in test configuration 04 - 07 of the FPGA simplified model.

[0064] Figure 10 It is the net to be tested in test configuration 08 - 11 of the FPGA simplified model.

[0065] Figure 11 It is the schematic diagram of the SINGLE - type interconnection line of Xilinx 7 - series FPGA.

[0066] Figure 12 It is the schematic diagram of the loop - back connection relationship of the SINGLE - type interconnection line of Xilinx 7 - series FPGA.

[0067] Figure 13 It is the schematic diagram of the SINGLE - SINGLE type interconnection switch of Xilinx 7 - series FPGA.

[0068] Figure 14 It is the schematic diagram of the sub - graph traversing the SINGLE - SINGLE type interconnection switch of Xilinx 7 - series FPGA.

[0069] Figure 15 It is the schematic diagram of the LONG - type interconnection line of Xilinx 7 - series FPGA.

[0070] Figure 16 It is the loop - back connection schematic diagram of the LONG - type interconnection line of Xilinx 7 - series FPGA.

[0071] Figure 17 It is the schematic diagram of the LH - LH / LV - LV / LVB - LVB type interconnection switch of Xilinx 7 - series FPGA.

[0072] Figure 18 It is the schematic diagram of the sub - graph traversing the LH - LH / LV - LV / LVB - LVB type interconnection switch of Xilinx 7 - series FPGA. Specific implementation mode

[0073] The following further introduces the present invention through embodiments in combination with the accompanying drawings.

[0074] The overall block diagram of the FPGA interconnection resource traversal test method is as Figure 1 shown, including three main steps: interconnection resource modeling, regular wiring, and auxiliary wiring. Finally, the wiring result of traversing the interconnection resources is obtained, where the dashed box is an optional step and can be skipped.

[0075] There are 3 embodiments, namely the interconnect resource traversal test method for the FPGA simplified model, the SINGLE-SINGLE type interconnect switch traversal test method for Xilinx 7 series FPGAs, and the LH-LH / LV-LV / LVB-LVB type interconnect switch traversal test method for Xilinx 7 series FPGAs.

[0076] Embodiment 1: Interconnect resource traversal test for the FPGA simplified model.

[0077] The FPGA simplified model is as Figure 2 shown, with an array scale of 3×3. There is an array vacancy at the coordinate position (1, 1), and there are two non-CLB modules at the coordinate positions (1, 0) and (1, 2), and the remaining coordinate positions are CLB modules. At the array boundary, there are loopback connections. At the array vacancy, there are loopback connections in the vertical direction and direct connections in the horizontal direction. Each CLB module includes two SLICE modules, called A(SLICE) and B(SLICE) respectively. Each interconnect TILE has global interconnect lines in four directions of E / W / S / N, and interconnect lines for two input ports of IA / IB and two output ports of OA / OB.

[0078] The global interconnect switch and the local interconnect switch are as Figure 3 shown. The switch with both ends connected to the global interconnect lines is called the global interconnect switch. There are 12 global interconnect switches in each interconnect TILE, including E->E, N->N, S->S, W->W, E->N, E->S, N->E, N->W, S->E, S->W, W->N, W->S. The global interconnect lines and the global interconnect switches are collectively called global interconnect resources, which constitute the global interconnect network throughout the FPGA. The remaining interconnect switches are called local interconnect switches. There are 16 local interconnect switches in each interconnect TILE, including OA->E, OA->N, OA->S, OA->W, OB->E, OB->N, OB->S, OB->W, E->IA, N->IA, S->IA, W->IA, E->IB, N->IB, S->IB, W->IB. The local interconnect lines and the local interconnect switches are collectively called local interconnect resources, which connect the global interconnect network with the functional modules.

[0079] Step 1, interconnect resource modeling, that is, establishing a wiring resource graph and an interconnect TILE graph.

[0080] The routing resource graph contains 64 nodes (4×8 = 32 global interconnect lines and 4×8 = 32 local interconnect lines), and 224 edges (12×8 = 96 global interconnect switches and 16×8 = 128 local interconnect switches). Among them, the local interconnect resources of non-CLB modules are not the interconnect resources to be measured. Therefore, the interconnect resources to be measured contain 56 nodes (4×8 = 32 global interconnect lines and 4×6 = 24 local interconnect lines), and 192 edges (12×8 = 96 global interconnect switches and 16×6 = 96 local interconnect switches).

[0081] The interconnect TILE graph is as shown in Figure 4 The interconnect TILE graph contains 8 nodes (4 global interconnect lines and 4 local interconnect lines), and 28 edges (12 global interconnect switches and 16 local interconnect switches).

[0082] Step 2: Regular routing, that is, select a subgraph that meets certain constraint conditions in the interconnect TILE graph and map it onto the routing resource graph to achieve regular routing.

[0083] In this embodiment, after merging the same type of interconnect lines, a merged interconnect TILE graph is obtained. The merged interconnect TILE graph is as shown in Figure 5 E and W are merged into HGLOBAL, N and S are merged into VGLOBAL, IA and IB are merged into INPUT, and OA and OB are merged into OUTPUT. The corresponding interconnect switches are also merged into VGLOBAL->VGLOBAL, HGLOBAL->HGLOBAL, VGLOBAL->HGLOBAL, HGLOBAL->VGLOBAL, OUTPUT->VGLOBAL, OUTPUT->HGLOBAL, VGLOBAL->INPUT, HGLOBAL->INPUT. The numbers represent the quantities of the corresponding types of interconnect lines (nodes) and interconnect switches (edges).

[0084] Select a subgraph of the merged interconnect TILE graph, as shown in Figure 6 It is divided into 5 subgraphs:

[0085] The first subgraph is composed of VGLOBAL->VGLOBAL;

[0086] The second subgraph is composed of HGLOBAL->HGLOBAL;

[0087] The third subgraph is composed of VGLOBAL->HGLOBAL and HGLOBAL->VGLOBAL;

[0088] The fourth subgraph is composed of OUTPUT->VGLOBAL and INPUT->VGLOBAL;

[0089] The 5th sub - figure consists of OUTPUT -> HGLOBAL and INPUT -> HGLOBAL.

[0090] These 5 sub - figures of the merged - type interconnected TILE graph can completely cover the merged - type interconnected TILE graph.

[0091] Decompose the sub - figure of the merged - type interconnected TILE graph to obtain the sub - figure of the interconnected TILE graph. As Figure 7 shown, it is divided into 8 sub - figures:

[0092] The 1st sub - figure consists of N -> N and S -> S;

[0093] The 2nd sub - figure consists of E -> E and W -> W;

[0094] The 3rd sub - figure consists of N -> E, E -> N, S -> W, and W -> S;

[0095] The 4th sub - figure consists of S -> E, E -> S, N -> W, and W -> N;

[0096] The 5th sub - figure consists of OA -> N, N -> IA, OB -> S, and S -> IB;

[0097] The 6th sub - figure consists of OA -> S, S -> IA, OB -> N, and N -> IB;

[0098] The 7th sub - figure consists of OA -> W, W -> IA, OB -> E, and E -> IB;

[0099] The 8th sub - figure consists of OA -> E, E -> IA, OB -> W, and W -> IB.

[0100] These 8 sub - figures of the interconnected TILE graph can completely cover the interconnected TILE graph.

[0101] It can be verified that Figure 7 the 8 sub - figures of the interconnected TILE graph in

[0102] all satisfy the necessary constraint conditions 1 - 4 and the optional constraint condition 5. The 4 sub - figures on the left belong to the cascaded type of nets, and the 4 sub - figures on the right belong to the fragmented type of nets.

[0103] Step 3: Auxiliary wiring, eliminate the wiring loops and wiring breakpoints in the net to obtain the net to be measured that meets the wiring rules.

[0104] In this embodiment, a total of 12 test configurations are finally obtained. Figure 8 It is a schematic diagram of the wire network to be tested for configurations 00, 01, 02, and 03. Figure 9 It is a schematic diagram of the wire network to be tested for configurations 04, 05, 06, and 07. Figure 10 It is a schematic diagram of the wire network to be tested for configurations 08, 09, 10, and 11. The corresponding generation process is as follows:

[0105] The generation process of configuration 00 is as follows: Select the subgraph composed of N->N and S->S; keep N->N unchanged, disconnect a part of the interconnection switches on S->S; connect the termination breakpoint to the input end of the CLB, and connect the starting breakpoint to the output end of the CLB.

[0106] The generation process of configuration 01 is as follows: Select the subgraph composed of N->N and S->S; keep S->S unchanged, disconnect a part of the interconnection switches on N->N; connect the termination breakpoint to the input end of the CLB, and connect the starting breakpoint to the output end of the CLB.

[0107] The generation process of configuration 02 is as follows: Select the subgraph composed of E->E and W->W; keep E->E unchanged, disconnect a part of the interconnection switches on W->W; connect the termination breakpoint to the input end of the CLB, and connect the starting breakpoint to the output end of the CLB.

[0108] The generation process of configuration 03 is as follows: Select the subgraph composed of E->E and W->W; keep W->W unchanged, disconnect a part of the interconnection switches on E->E; connect the termination breakpoint to the input end of the CLB, and connect the starting breakpoint to the output end of the CLB.

[0109] The generation process of configuration 04 is as follows: Select the subgraph composed of N->E, E->N, S->W, and W->S; keep N->E and E->N unchanged, replace S->W and W->S with S->S and W->W, and disconnect a part of the interconnection switches on S->S and W->W; connect the termination breakpoint to the input end of the CLB, and connect the starting breakpoint to the output end of the CLB.

[0110] The generation process of configuration 05 is as follows: Select the subgraph composed of N->E, E->N, S->W, and W->S; keep S->W and W->S unchanged, replace N->E and E->N with N->N and E->E, and disconnect a part of the interconnection switches on N->N and E->E; connect the termination breakpoint to the input end of the CLB, and connect the starting breakpoint to the output end of the CLB.

[0111] The generation process of Configuration 06 is as follows: Select the sub-graph composed of S->E, E->S, N->W, and W->N; Keep S->E and E->S unchanged, replace N->W and W->N with N->N and W->W, and disconnect a part of the interconnection switches on N->N and W->W; Connect the termination breakpoints to the input terminals of the CLBs, and connect the starting breakpoints to the output terminals of the CLBs.

[0112] The generation process of Configuration 07 is as follows: Select the sub-graph composed of S->E, E->S, N->W, and W->N; Keep N->W and W->N unchanged, replace S->E and E->S with S->S and E->E, and disconnect a part of the interconnection switches on S->S and E->E; Connect the termination breakpoints to the input terminals of the CLBs, and connect the starting breakpoints to the output terminals of the CLBs.

[0113] The generation process of Configuration 08 is as follows: Select the sub-graph composed of OA->N, N->IA, OB->S, and S->IB; Ignore the local interconnection resources of the non-CLB modules in the middle column.

[0114] The generation process of Configuration 09 is as follows: Select the sub-graph composed of OA->S, S->IA, OB->N, and N->IB; Ignore the local interconnection resources of the non-CLB modules in the middle column.

[0115] The generation process of Configuration 10 is as follows: Select the sub-graph composed of OA->W, W->IA, OB->E, and E->IB; Ignore the local interconnection resources of the non-CLB modules in the middle column; Connect the termination breakpoints and the starting breakpoints with E->E and W->W in the middle column to merge the nets.

[0116] The generation process of Configuration 11 is as follows: Select the sub-graph composed of OA->E, E->IA, OB->W, and W->IB; Ignore the local interconnection resources of the non-CLB modules in the middle column; Connect the termination breakpoints and the starting breakpoints with E->E and W->W in the middle column to merge the nets.

[0117] These 12 test configurations can fully cover the interconnection resources to be tested in the FPGA simplified model, and the coverage rates of the global interconnection lines to be tested, local interconnection lines to be tested, global interconnection switches to be tested, and local interconnection switches to be tested are all 100%.

[0118] Example 2: Traversal test of SINGLE-SINGLE type interconnection switches in Xilinx 7 series FPGAs.

[0119] Step 1, model the interconnection resources, that is, establish a wiring resource graph and an interconnection TILE graph.

[0120] In this embodiment, the interconnection resource information of the FPGA is extracted through the Tcl Console of the Vivado design suite, including the relevant information of FPGA objects such as TILE, WIRE (interconnection segment), PIP (interconnection switch), NODE (interconnection line), SITE (functional module), PIN (functional module port), etc. Then, after processing the interconnection resource information through an automated program, a routing resource map and an interconnection TILE map are obtained.

[0121] The SINGLE-type interconnection lines are as Figure 11 shown and are divided into a total of 8 types: EL1, ER1, NL1, NR1, SL1, SR1, WL1, and WR1. In each interconnection TILE, each type contains 4 interconnection lines. Among these 6 types of EL1, ER1, NL1, SR1, WL1, and WR1, 1 interconnection line in each type extends from the original end point to a second end point. In Figure 11 it is represented by a dashed line. These second end points are respectively called EL1END_S3_0, ER1END_N3_3, NL1END_S3_0, SR1END_N3_3, WL1END_N1_3, and WR1END_S1_0.

[0122] The loopback connection relationship of the SINGLE-type interconnection lines is as Figure 12 shown. In the horizontal direction (left and right boundaries), a certain upstream interconnection segment that was originally supposed to be connected to EL1 / ER1 / WL1 / WR1 will be connected to the downstream interconnection segment WL1 / WR1 / EL1 / ER1. In the vertical direction (upper and lower boundaries), a certain upstream interconnection segment that was originally supposed to be connected to NL1 / NR1 / SL1 / SR1 / EL1 / ER1 / WL1 / WR1 will be connected to the downstream interconnection segment SR1 / SL1 / NR1 / NL1 / ER1 / EL1 / WR1 / WL1. For the second end points, in the vertical direction (upper and lower boundaries), a certain upstream interconnection segment that was originally supposed to be connected to EL1END_S3_0 / ER1END_N3_3 / WL1END_N1_3 / WR1END_S1_0 will be connected to the downstream interconnection segment ER1END_N3_3 / EL1END_S3_0 / WR1END_S1_0 / WL1END_N1_3. The arrow A->B represents that a certain upstream interconnection segment was originally supposed to be connected to the downstream interconnection segment A, but is connected to the downstream interconnection segment B at the array boundary (or array vacancy). The dashed arrow A->B represents the loopback connection relationship between the second end points. The marked letter H represents the loopback connection relationship in the horizontal direction, and the marked letter V represents the loopback connection relationship in the vertical direction.

[0123] The SINGLE-SINGLE type interconnection switches are as Figure 13 shown and include 32 types:

[0124] EL1->EL1, ER1->ER1, NL1->NL1, NR1->NR1, WL1->WL1, WR1->WR1, SL1->SL1, SR1->SR1, EL1->ER1, ER1->EL1, NL1->NR1, NR1->NL1, WL1->WR1, WR1->WL1, SL1->SR1, SR1->SL1, EL1->NR1, NR1->WR1, WR1->NL1, NL1->EL1, WL1->SR1, SR1->ER1, ER1->SL1, SL1->WL1, EL1->SL1, SL1->ER1, ER1->NR1, NR1->EL1, WL1->NL1, NL1->WR1, WR1->SR1, SR1->WL1.

[0125] In each interconnected TILE, each type contains 4 PIPs, for a total of 128 SINGLE-SINGLE type PIPs.

[0126] Figure 13 The dashed arrow in the middle represents that one of the 4 PIPs is driven by the second end point.

[0127] Step 2, regular routing. Select a subgraph that meets certain constraint conditions in the interconnected TILE graph and map it to the routing resource graph to achieve regular routing.

[0128] Traverse the subgraph of the SINGLE-SINGLE type interconnect switch of Xilinx 7 series FPGAs as Figure 14 shown, which is divided into 4 subgraphs:

[0129] The upper left subgraph is composed of EL1->EL1, ER1->ER1, NL1->NL1, NR1->NR1, WL1->WL1, WR1->WR1, SL1->SL1, SR1->SR1;

[0130] The upper right subgraph is composed of EL1->ER1, ER1->EL1, NL1->NR1, NR1->NL1, WL1->WR1, WR1->WL1, SL1->SR1, SR1->SL1;

[0131] The lower left subgraph is composed of EL1->NR1, NR1->WR1, WR1->NL1, NL1->EL1, WL1->SR1, SR1->ER1, ER1->SL1, SL1->WL1;

[0132] The sub - graph in the lower right is composed of EL1->SL1, SL1->ER1, ER1->NR1, NR1->EL1, WL1->NL1, NL1->WR1, WR1->SR1, SR1->WL1.

[0133] It can be verified that these 4 sub - graphs all satisfy the necessary constraint conditions 1 - 4 and the optional constraint condition 5, and all belong to the cascade - type netlist. These 4 sub - graphs can completely cover the SINGLE - SINGLE type interconnection switch.

[0134] In this embodiment, the constraint condition 5 means that NL1 and SR1 must be selected simultaneously, NR1 and SL1 must be selected simultaneously, EL1, ER1, WL1, WR1 must be selected simultaneously, and when the outgoing edge of WL1 / WR1 is a dotted arrow, the outgoing edge of WR1 / WL1 must also be a dotted arrow.

[0135] Step 3: Auxiliary routing, eliminating the routing loops and routing breakpoints in the netlist to obtain the netlist to be tested that meets the routing rules.

[0136] In this embodiment, finally 8 test configurations are obtained.

[0137] The generation process of configuration 00 is as follows: Select Figure 14 The upper - left sub - graph; keep EL1->EL1, ER1->ER1, NL1->NL1, NR1->NR1 unchanged; disconnect a part of the interconnection switches in the other group of interconnection paths (WL1->WL1, WR1->WR1, SL1->SL1, SR1->SR1); connect the termination breakpoint to the input end of the CLB, and connect the starting breakpoint to the output end of the CLB.

[0138] The generation process of configuration 01 is as follows: Select Figure 14 The upper - left sub - graph; keep WL1->WL1, WR1->WR1, SL1->SL1, SR1->SR1 unchanged; disconnect a part of the interconnection switches in the other group of interconnection paths (keep EL1->EL1, ER1->ER1, NL1->NL1, NR1->NR1); connect the termination breakpoint to the input end of the CLB, and connect the starting breakpoint to the output end of the CLB.

[0139] The generation process of configuration 02 is as follows: Select Figure 14The upper-right sub-diagram; keep EL1->ER1, ER1->EL1, NL1->NR1, NR1->NL1 unchanged; replace the other group with simpler interconnection paths (WL1->WL1, WR1->WR1, SL1->SL1, SR1->SR1), disconnect a part of the interconnection switches in the replaced interconnection paths; connect the termination breakpoints to the input terminals of the CLB and the starting breakpoints to the output terminals of the CLB.

[0140] The generation process of Configuration 03 is as follows: Select Figure 14 The upper-right sub-diagram; keep WL1->WR1, WR1->WL1, SL1->SR1, SR1->SL1 unchanged; replace the other group with simpler interconnection paths (EL1->EL1, ER1->ER1, NL1->NL1, NR1->NR1), disconnect a part of the interconnection switches in the replaced interconnection paths; connect the termination breakpoints to the input terminals of the CLB and the starting breakpoints to the output terminals of the CLB.

[0141] The generation process of Configuration 04 is as follows: Select Figure 14 The lower-left sub-diagram; keep EL1->NR1, NR1->WR1, WR1->NL1, NL1->EL1 unchanged; replace the other group with simpler interconnection paths (WL1->WL1, SR1->SR1, ER1->ER1, SL1->SL1), disconnect a part of the interconnection switches in the replaced interconnection paths; connect the termination breakpoints to the input terminals of the CLB and the starting breakpoints to the output terminals of the CLB.

[0142] The generation process of Configuration 05 is as follows: Select Figure 14 The lower-left sub-diagram; keep WL1->SR1, SR1->ER1, ER1->SL1, SL1->WL1 unchanged; replace the other group with simpler interconnection paths (EL1->EL1, NR1->NR1, WR1->WR1, NL1->NL1), disconnect a part of the interconnection switches in the replaced interconnection paths; connect the termination breakpoints to the input terminals of the CLB and the starting breakpoints to the output terminals of the CLB.

[0143] The generation process of Configuration 06 is as follows: Select Figure 14 The lower-right sub-diagram; keep EL1->SL1, SL1->ER1, ER1->NR1, NR1->EL1 unchanged; replace the other group with simpler interconnection paths (WL1->WL1, NL1->NL1, WR1->WR1, SR1->SR1), disconnect a part of the interconnection switches in the replaced interconnection paths; connect the termination breakpoints to the input terminals of the CLB and the starting breakpoints to the output terminals of the CLB.

[0144] The generation process of Configuration 07 is as follows: Select Figure 14 the sub-diagram in the lower right; keep WL1->NL1, NL1->WR1, WR1->SR1, SR1->WL1 unchanged; replace the other group with simpler interconnection paths (EL1->EL1, SL1->SL1, ER1->ER1, NR1->NR1, disconnect a part of the interconnection switches in the replaced interconnection paths; connect the termination breakpoints to the input terminals of the CLB and connect the starting breakpoints to the output terminals of the CLB.

[0145] These 8 test configurations can fully cover the SINGLE-SINGLE type interconnection switches of Xilinx 7 series FPGAs, with a coverage rate of 100%.

[0146] In this embodiment, the direct routing of interconnection resources is achieved through the fixed routing constraints of the xdc file in the Vivado design suite.

[0147] Embodiment 3: Traversal test of LH-LH / LV-LV / LVB-LVB type interconnection switches of Xilinx 7 series FPGAs.

[0148] Step 1, interconnection resource modeling, establish a routing resource graph and an interconnection TILE graph.

[0149] In this embodiment, the interconnection resource information of the FPGA is extracted through the Tcl Console of the Vivado design suite, including the relevant information of FPGA objects such as TILE, WIRE (interconnection line segment), PIP (interconnection switch), NODE (interconnection line), SITE (functional module), PIN (functional module port), etc. Then, after processing the interconnection resource information through an automated program, a routing resource graph and an interconnection TILE graph are obtained.

[0150] The LONG type interconnection lines are as Figure 15 shown, and are divided into 3 types in total: LH, LV, and LVB. In each interconnection TILE, each type contains 1 interconnection line. The horizontal length of LH is 12, and the left and right end points are LH12 and LH0 respectively, with an intermediate end point LH6. The vertical length of LV is 18, and the upper and lower end points are LV18 and LV0 respectively, with an intermediate end point LV9. The vertical length of LVB is 12, and the upper and lower break points are LVB12 and LVB0 respectively, without an intermediate end point.

[0151] The loopback connection relationship of the LONG type interconnection lines is as Figure 16As shown. In the horizontal direction (left and right boundaries), a certain upstream interconnect line segment that should originally be connected to LH is connected to the downstream interconnect line segment LH. In the vertical direction (upper and lower boundaries), a certain upstream interconnect line segment that should originally be connected to LV / LVB is connected to the downstream interconnect line segment LV / LVB. The arrow A->B represents that a certain upstream interconnect line segment that should originally be connected to the downstream interconnect line segment A is connected to the downstream interconnect line segment B at the array boundary (or array vacancy). The marked letter H represents the loop-back connection relationship in the horizontal direction, and the marked letter V represents the loop-back connection relationship in the vertical direction.

[0152] In this embodiment, the starting and ending points of the bidirectional interconnect line and the direction of the bidirectional interconnect switch are determined according to the parity of the horizontal and vertical coordinates of the interconnect TILE. The bidirectional interconnect lines in Xilinx 7 series FPGAs are LH, LV, and LVB. Therefore, 8 different unidirectional routing resource graphs can be established and distinguished by 3-bit binary numbers (000 - 111). The specific meanings are as follows:

[0153] When the first bit of the 3-bit binary number is 0, it means that in the interconnect TILE with an even X coordinate, LH0 is the starting point and LH12 is the ending point; in the interconnect TILE with an odd X coordinate, LH12 is the starting point and LH0 is the ending point.

[0154] When the first bit of the 3-bit binary number is 1, it means that in the interconnect TILE with an even X coordinate, LH12 is the starting point and LH0 is the ending point; in the interconnect TILE with an odd X coordinate, LH0 is the starting point and LH12 is the ending point.

[0155] When the second bit of the 3-bit binary number is 0, it means that in the interconnect TILE with an even Y coordinate, LV0 is the starting point and LV18 is the ending point; in the interconnect TILE with an odd Y coordinate, LV18 is the starting point and LV0 is the ending point.

[0156] When the second bit of the 3-bit binary number is 1, it means that in the interconnect TILE with an even Y coordinate, LV18 is the starting point and LV0 is the ending point; in the interconnect TILE with an odd Y coordinate, LV0 is the starting point and LV18 is the ending point.

[0157] When the third bit of the 3-bit binary number is 0, it means that in the interconnect TILE with an even Y coordinate, LVB0 is the starting point and LVB12 is the ending point; in the interconnect TILE with an odd Y coordinate, LVB12 is the starting point and LVB0 is the ending point.

[0158] When the third bit of the 3-bit binary number is 1, it means that in the interconnect TILE with an even Y coordinate, LVB12 is the starting point and LVB0 is the ending point; in the interconnect TILE with an odd Y coordinate, LVB0 is the starting point and LVB12 is the ending point.

[0159] The LH-LH / LV-LV / LVB-LVB type interconnection switch is as follows Figure 17 as shown. The bidirectional interconnection switch is modeled as two unidirectional interconnection switches. Each interconnection TILE has a total of 6 LH-LH / LV-LV / LVB-LVB type interconnection switches. The 3-bit binary number marked on the arrow represents the corresponding unidirectional routing resource graph, and the symbol "*" represents that both 0 and 1 are acceptable. Each arrow can uniquely determine an interconnection switch in the interconnection TILE:

[0160] The LH->LH arrow marked with 0** represents LH12->LH0 in the interconnection TILE with an even X coordinate and LH0->LH12 in the interconnection TILE with an odd X coordinate;

[0161] The LH->LH arrow marked with 1** represents LH0->LH12 in the interconnection TILE with an even X coordinate and LH12->LH0 in the interconnection TILE with an odd X coordinate;

[0162] The LV->LV arrow marked with *0* represents LV18->LV0 in the interconnection TILE with an even Y coordinate and LV0->LV18 in the interconnection TILE with an odd Y coordinate;

[0163] The LV->LV arrow marked with *1* represents LV0->LV18 in the interconnection TILE with an even Y coordinate and LV18->LV0 in the interconnection TILE with an odd Y coordinate;

[0164] The LVB->LVB arrow marked with **0 represents LVB12->LVB0 in the interconnection TILE with an even Y coordinate and LVB0->LVB12 in the interconnection TILE with an odd Y coordinate;

[0165] The LVB->LVB arrow marked with **1 represents LVB0->LVB12 in the interconnection TILE with an even Y coordinate and LVB12->LVB0 in the interconnection TILE with an odd Y coordinate.

[0166] Step 2, regular routing. Select a subgraph that meets certain constraint conditions in the interconnection TILE graph and map it to the routing resource graph to achieve regular routing.

[0167] Traverse the subgraph of the LH-LH / LV-LV / LVB-LVB type interconnection switch of the Xilinx 7 series FPGA as Figure 18 shown, which is divided into 2 subgraphs:

[0168] The left sub - figure selects the unidirectional routing resource diagram 000, which is composed of the LH->LH arrow marked with 0**, the LV->LV arrow marked with *0*, and the LVB->LVB arrow marked with **0;

[0169] The right sub - figure selects the unidirectional routing resource diagram 111, which is composed of the LH->LH arrow marked with 1**, the LV->LV arrow marked with *1*, and the LVB->LVB arrow marked with **1.

[0170] It can be verified that both of these 2 sub - figures meet the necessary constraint conditions 1 - 4 and the optional constraint condition 5, and both belong to the cascaded netlist. These 2 sub - figures can completely cover the LH - LH / LV - LV / LVB - LVB type interconnection switches.

[0171] Step 3, auxiliary routing, eliminates the routing loops and routing breakpoints in the netlist to obtain the netlist to be tested that meets the routing rules.

[0172] In this embodiment, 4 test configurations are finally obtained.

[0173] Configurations 00 and 01 select the left sub - figure of the unidirectional routing resource diagram 000( Figure 18 ), disconnect a part of the interconnection switches, and ensure that the disconnected interconnection switches in the two configurations are different; connect the termination breakpoint to the input end of the CLB, and connect the starting breakpoint to the output end of the CLB.

[0174] Configurations 02 and 03 select the right sub - figure of the unidirectional routing resource diagram 111( Figure 18 ), disconnect a part of the interconnection switches, and ensure that the disconnected interconnection switches in the two configurations are different; connect the termination breakpoint to the input end of the CLB, and connect the starting breakpoint to the output end of the CLB.

[0175] These 4 test configurations can completely cover the LH - LH / LV - LV / LVB - LVB type interconnection switches of Xilinx 7 - series FPGAs, and the coverage rate is 100%.

[0176] In this embodiment, the direct routing of the interconnection resources is realized through the fixed routing constraints (Fixed Routing Constraints) of the xdc file in the Vivado design suite.

[0177] As described above, it is only a preferred embodiment of the present invention and does not impose any form of limitation on the present invention. Any person skilled in the art, without departing from the scope and concept of the present invention, makes simple modifications and changes to the above - mentioned embodiments based on the technical essence of the present invention, which all fall within the scope of protection of the technical solution of the present invention.

Claims

1. A FPGA interconnection resource traversal test method, characterized in that: The specific steps are: Step 1: interconnection resource modeling, that is, establishing a wiring resource diagram and an interconnection TILE diagram; wherein: The wiring resource graph is a directed graph model established for all actually existing interconnection resources in the FPGA, wherein the nodes are actually existing interconnection lines in the FPGA, and the directed edges are actually existing programmable interconnection points in the FPGA, i.e., interconnection switches; The actually existing interconnection line refers to a complete interconnection line formed by connecting interconnection line segments in one or more TILEs; The actual programmable interconnection point refers to a unidirectional interconnection switch connecting two interconnection line segments, the switch state of which is controlled by a bit stream; for a bidirectional interconnection switch, it is modeled as two unidirectional interconnection switches; The interconnection TILE graph is a directed graph model for abstract interconnection resources in a single interconnection TILE, wherein the nodes are abstract interconnection lines in a single interconnection TILE, and the directed edges are abstract programmable interconnection points, i.e., interconnection switches, in a single interconnection TILE. The abstract interconnection line is a complete interconnection line formed by imagining that the left and right sides of a single interconnection TILE are bonded together, and the upper and lower sides are bonded together, and then the interconnection line segments in the single interconnection TILE are connected; The abstract programmable interconnection point refers to a unidirectional interconnection switch connecting two interconnection line segments in a single interconnection TILE, whose switch state is controlled by a bit stream; a bidirectional interconnection switch is modeled as two unidirectional interconnection switches; Step 2, regular wiring, that is, selecting a subgraph that meets certain constraints in the interconnected TILE graph and mapping it to the wiring resource graph to achieve regular wiring; The constraints include: Constraint 1: In the subgraph, the in-degree of each node is at most 1; Constraint 2: In the subgraph, the node with in-degree 0 must be the interconnection line of the output port of the functional module; Constraint 3: In the subgraph, the node with out-degree 0 must be the interconnection line of the input port of the functional module; Constraint 4: There is no zero-displacement ring in the subgraph; The displacement of a loop in a subgraph is defined as the difference between the interconnected Tile coordinates of the end point and the interconnected Tile coordinates of the starting point after walking along the loop in the subgraph. If the displacement of a loop is zero, it means that after walking along the loop in the subgraph, the original interconnected Tile is returned. If the displacement of a loop is not zero, it means that after walking along the loop in the subgraph, another interconnected Tile with different coordinates is reached. Under constraints 1-4, the connected components of the subgraph are divided into the following three cases: Case 1: The connected component of the subgraph is a ring, and the displacement of the ring is non-zero, that is, constraint condition 4; the mapping result of this connected component is a set of parallel paths formed by the cascade of interconnection lines and interconnection switches; the mapping result of this connected component is called a cascade type line network; Case 2: The connected component of the subgraph is a branched single-loop graph, the displacement of the loop is non-zero, that is, constraint condition 4, and the leaf node with out-degree 0 in the branch is the interconnection line of the functional module input port, that is, constraint condition 3; the mapping result of this connected component is that the trunk formed by parallel paths extends to the branches terminating at the interconnection line of the functional module input port; the mapping result of this connected component is called a branch-type line network; Case 3: The connected component of the subgraph is a tree, the nodes with out-degree 0, i.e., the leaf nodes of the tree, are the interconnections of the functional module input ports, i.e., constraint 3, and the nodes with in-degree 0, i.e., the root nodes of the tree, are the interconnections of the functional module output ports, i.e., constraint 2; the mapping result of this connected component is many identical trees, starting from the interconnections of the functional module output ports and ending at the interconnections of the functional module input ports; the mapping result of this connected component is called a fragmented line network; Mapping the subgraph onto the wiring resource graph to realize regular wiring is to instruct the actual interconnection switches corresponding to the edges, i.e., the abstract interconnection switches, contained in the subgraph to be turned on, and other actual interconnection switches to be turned off; By selecting several subgraphs that meet the constraints and making them fully traverse the interconnection TILE graph, it is possible to traverse the corresponding actual interconnection resources on the wiring resource graph; Step 3, auxiliary wiring, that is, eliminating wiring loops and wiring breakpoints in the wire network to obtain a wire network to be tested that meets the wiring rules; The wiring loop refers to an interconnection path that is connected end to end in the wire network; the main reason for the wiring loop is that there is a loopback connection connecting two interconnection line segments in opposite directions at the boundary of the FPGA array or at the array gap, so that the interconnection path is connected end to end after passing through the loopback connection multiple times; The wiring breakpoint refers to a point in the network that is not the starting point of the output port interconnection line, or is not the end point of the input port interconnection line. The former is called a start breakpoint, and the latter is called an end breakpoint. The main reason for the wiring breakpoint is that the local interconnection resources of the non-CLB module are not the interconnection resources to be tested, and are regarded as interrupted in the process of generating the network to be tested, and some interconnection resources may be interrupted at the array boundary or array gap.

2. The FPGA interconnection resource traversal test method according to claim 1, characterized in that: In step 1, the wiring resource diagram and the interconnection TILE diagram extract the interconnection resource information of the FPGA through the TclConsole of the Vivado design suite, including the relevant information of TILE, interconnection line segment (WIRE), interconnection switch (PIP), interconnection line (NODE), functional module (SITE), and functional module port (PIN) FPGA objects, and then obtain the interconnection resource information after processing it through an automated program.

3. The FPGA interconnection resource traversal test method according to claim 1, characterized in that: In step 1, if there are bidirectional interconnection lines and bidirectional interconnection switches in the FPGA, the starting point and end point of the bidirectional interconnection line and the direction of the bidirectional interconnection switch are determined according to the parity of the horizontal and vertical coordinates of the interconnection TILE, thereby establishing a unidirectional wiring resource map.

4. The FPGA interconnection resource traversal test method according to claim 3, characterized in that: In step 1, a unidirectional wiring resource diagram is established. Specifically: For LH, LV, and LVB in Xilinx 7 series FPGA, 8 different unidirectional routing resource diagrams are established, distinguished by 3-bit binary numbers (000-111). The specific meanings are as follows: The first bit of the 3-bit binary is 0, which means: in the interconnected TILE with an even X coordinate, LH0 is the starting point and LH12 is the end point; in the interconnected TILE with an odd X coordinate, LH12 is the starting point and LH0 is the end point; The first bit of the 3-bit binary is 1, which means: in the interconnected TILE with an even X coordinate, LH12 is the starting point and LH0 is the end point; in the interconnected TILE with an odd X coordinate, LH0 is the starting point and LH12 is the end point; The second bit of the 3-bit binary is 0, which means: in the interconnected TILE with an even Y coordinate, LV0 is the starting point and LV18 is the end point; in the interconnected TILE with an odd Y coordinate, LV18 is the starting point and LV0 is the end point; The second bit of the 3-bit binary is 1, which means: in the interconnected TILE with an even Y coordinate, LV18 is the starting point and LV0 is the end point; in the interconnected TILE with an odd Y coordinate, LV0 is the starting point and LV18 is the end point; The third bit of the 3-bit binary is 0, which means: in the interconnected TILE with an even Y coordinate, LVB0 is the starting point and LVB12 is the end point; in the interconnected TILE with an odd Y coordinate, LVB12 is the starting point and LVB0 is the end point; The third bit of the 3-bit binary is 1, which means: in the interconnected TILE with an even Y coordinate, LVB12 is the starting point and LVB0 is the end point; in the interconnected TILE with an odd Y coordinate, LVB0 is the starting point and LVB12 is the end point.

5. The FPGA interconnection resource traversal test method according to claim 1, characterized in that: In step 2, interconnect lines of the same type are first merged to obtain a merged interconnect TILE graph, and then a subgraph of the merged interconnect TILE graph is selected, and then the subgraph of the merged interconnect TILE graph is decomposed to obtain a subgraph of the interconnect TILE graph, which is mapped to the wiring resource graph to achieve regular wiring.

6. The FPGA interconnection resource traversal test method according to claim 1, characterized in that: In step 2, if there is a loopback connection in the FPGA, an additional constraint condition 5 for selecting a subgraph is added; wherein the loopback connection refers to the presence of an interconnection line or an interconnection switch connecting two interconnection line segments in opposite directions at the boundary of the FPGA array or at a gap in the array; Constraint 5 is: in the subgraph, if there is a loop connection at the array boundary or array gap, so that a certain upstream interconnection line segment should be connected to the downstream interconnection line segment A, but is connected to the downstream interconnection line segment B at the array boundary or array gap, then when interconnection line segment B is selected, interconnection line segment A must be selected at the same time; in particular, if interconnection line segment A and interconnection line segment B are both interconnection line end points, when an interconnection switch driven by an interconnection line segment B is selected in the subgraph, an interconnection switch driven by an interconnection line segment A must be selected at the same time.

7. The FPGA interconnection resource traversal test method according to claim 1, characterized in that: In step 3, the method of eliminating the wiring loop is: Disconnect some of the interconnection switches to break the wiring loop; or, The interconnection paths in the wiring loop are divided into two groups. One of the groups is selected in two test configurations to remain unchanged, and the other group is replaced with a simpler interconnection path. A part of the interconnection switches in the replaced interconnection path is disconnected to interrupt the wiring loop.

8. The FPGA interconnection resource traversal test method according to claim 1, characterized in that: In step 3, the method of eliminating wiring breakpoints is: Connect the end breakpoint to the input of the CLB and the start breakpoint to the output of the CLB; or, Merge some of the nets, then connect the remaining end breakpoints to the input of the CLB and the remaining start breakpoints to the output of the CLB.

9. The FPGA interconnection resource traversal test method according to claim 8, characterized in that: In step 3, direct routing of interconnect resources is achieved through fixed routing constraints in the xdc file in the Vivado Design Suite.

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