Dynamic logic simulation method and system based on superconducting integrated circuit, terminal and medium

Abstract

The invention provides a dynamic logic simulation method and system based on a superconducting integrated circuit, a terminal and a medium, and the method comprises the steps: S100, building a simulation queue based on layout information or a gate-level netlist file of the superconducting integrated circuit; step S200, acquiring an input port of the logic gate unit corresponding to the earliest signal arrival time and a corresponding excitation signal from the simulation queue; s300, determining the state change of the logic gate unit based on the input port of the logic gate unit and the corresponding excitation signal thereof and the state machine description defined in the unit library of the superconducting integrated circuit; step S400, updating the simulation queue based on the state change of the logic gate unit; and step S500, repeating the steps S200 to S400 until the simulation queue is empty or the preset maximum simulation time is reached, and ending the simulation process. According to the invention, the logic operation in the superconducting integrated circuit is simplified, the total time length of the whole waveform simulation is shortened, and the dynamic logic simulation efficiency is remarkably improved.

Description

Technical Field

[0001] This application belongs to the technical field of superconducting integrated circuits, and relates to a dynamic logic simulation method, system, terminal and medium based on superconducting integrated circuits. Background Art

[0002] A superconducting integrated circuit refers to an integrated circuit based on Josephson junctions and superconducting materials, including a single-flux-quantum (SFQ) circuit. The SFQ circuit is mainly composed of Josephson junctions, and represents digital logic "0" and "1" by the presence or absence of the magnetic flux quantum Ф0 in a superconducting loop. Compared with traditional semiconductor CMOS (Complementary Metal Oxide Semiconductor) circuits, the tiny and quantized nature of the magnetic flux quantum significantly reduces the influence of crosstalk and power consumption, and the narrow voltage pulses generated in the junction when the magnetic flux quantum enters and exits the loop also enable it to obtain an extremely high frequency. This advantage of both ultra-high operating speed and extremely low power consumption makes this circuit have significant prospects in applications such as ultra-wideband analog-to-digital converters (ADCs) and superconducting computers.

[0003] With the continuous development of superconducting integrated circuits and the increasingly diverse application requirements, the functional verification thereof faces many challenges. According to different time and accuracy requirements, different verification schemes need to be selected, such as device-level analog simulation and gate-level dynamic logic simulation.

[0004] In terms of dynamic logic simulation, currently, superconducting integrated circuits generally adopt a scheme of superconducting logic gate Verilog modeling to achieve a scheme compatible with commercial simulation tools. Although this method can meet some simulation requirements to a certain extent, it requires a large amount of complex Verilog modeling and logical operation work, which results in a large time overhead for the entire simulation process. Especially when facing some requirements for fast dynamic logic simulation, the existing methods are rather ineffective and difficult to meet the requirements of practical applications. Summary of the Invention

[0005] The purpose of this application is to provide a dynamic logic simulation method, system, terminal and medium based on superconducting integrated circuits, which is used to improve the efficiency of dynamic logic simulation.

[0006] In a first aspect, the present application provides a dynamic logic simulation method based on a superconducting integrated circuit, including: Step S100, constructing a simulation queue based on the layout information or gate-level netlist file of the superconducting integrated circuit; the simulation queue includes a series of input ports of logic gate units sorted according to the signal arrival time and their corresponding excitation signals; Step S200, obtaining from the simulation queue the input port of the logic gate unit corresponding to the earliest signal arrival time and its corresponding excitation signal; Step S300, determining the state change of the logic gate unit based on the input port of the logic gate unit and its corresponding excitation signal, and the state machine description defined in the cell library of the superconducting integrated circuit; Step S400, updating the simulation queue based on the state change of the logic gate unit; Step S500, repeating Step S200 to Step S400 until the simulation queue is empty or a preset maximum simulation time is reached, and ending the simulation process.

[0007] In an implementation manner of the first aspect, constructing a simulation queue based on the layout information or gate-level netlist file of the superconducting integrated circuit includes: converting the layout information or gate-level netlist file of the superconducting integrated circuit into a netlist data structure; the netlist data structure is used to describe the information of different logic gate units in the superconducting integrated circuit in the form of a data structure; performing static timing analysis on the netlist data structure to obtain the time when the input port of each logic gate unit receives the corresponding excitation signal, and defining the time as the signal arrival time; adding the input ports of all logic gate units and their corresponding excitation signals to a preset list in the order of the signal arrival time, to form the simulation queue.

[0008] In an implementation manner of the first aspect, performing static timing analysis on the netlist data structure includes: traversing all the logic gate units described in the netlist data structure based on the breadth-first search algorithm, and taking the selected logic gate unit as the current-level logic gate unit; obtaining the signal transmission time of the output port of the previous-level logic gate unit; obtaining the delay information of the interconnect unit between the current-level logic gate unit and the previous-level logic gate unit from the cell library of the superconducting integrated circuit; the delay information is used to reflect the time when the signal is transmitted from the output port of the previous-level logic gate unit through the interconnect unit to the input port of the current-level logic gate unit; calculating the time when the input port of the current-level logic gate unit receives the corresponding excitation signal based on the signal transmission time and the delay information, and taking it as the signal arrival time.

[0009] In an implementation of the first aspect, it further includes: optimizing the netlist data structure before performing static timing analysis on the netlist data structure; wherein the step of optimizing the netlist data structure includes: parsing the netlist data structure to obtain information about different logic gate units in the superconducting integrated circuit; based on the information of the logic gate units, finding all logic gate units of the interconnect type from the cell library of the superconducting integrated circuit; reconnecting each of the logic gate units of the interconnect type; removing all the interconnect units, and retaining the mapping relationship between the input ports and output ports corresponding to the interconnect units and the delay information of the interconnect units.

[0010] In an implementation of the first aspect, based on the input ports of the logic gate unit and their corresponding excitation signals, and the state machine description defined in the cell library of the superconducting integrated circuit, determining the state change of the logic gate unit includes: if the current state of the logic gate unit is low level, when the excitation signal arrives at the corresponding input port, the next state of the logic gate unit will change to high level; if the current state of the logic gate unit is low level, when the internal clock signal arrives at the corresponding input port, the next state of the logic gate unit will remain low level; if the current state of the logic gate unit is high level, when the excitation signal arrives at the corresponding input port, the next state of the logic gate unit will remain high level; if the current state of the logic gate unit is high level, when the internal clock signal arrives at the corresponding input port, the next state of the logic gate unit will change to low level, and at the same time, the output port of the logic gate unit outputs a signal.

[0011] In an implementation of the first aspect, based on the state change of the logic gate unit, updating the simulation queue includes: determining whether the output port of the logic gate unit has output a signal; if so, determining the input ports of the next-level logic gate unit according to the output port of the logic gate unit; determining the signal arrival time of the next-level logic gate unit; using the signal output by the output port of the logic gate unit as the excitation signal of the next-level logic gate unit; adding the input ports of the next-level logic gate unit and their corresponding excitation signals to the simulation queue according to the signal arrival time; otherwise, keeping the content of the simulation queue unchanged.

[0012] In an implementation of the first aspect, it further includes: selecting an input port or an output port of any one of the logic gate units as a measurement node; and drawing a corresponding simulation waveform diagram according to the time variation characteristic of the logic level value at the measurement node.

[0013] Second aspect, the present application provides a dynamic logic simulation system based on a superconducting integrated circuit, including: a queue construction module, configured to construct a simulation queue based on the layout information or gate-level netlist file of the superconducting integrated circuit; the simulation queue includes a series of input ports of logic gate units sorted according to the signal arrival time and their corresponding excitation signals; an information acquisition module, configured to acquire, from the simulation queue, the input ports of the logic gate units corresponding to the earliest signal arrival time and their corresponding excitation signals; a state determination module, configured to determine the state change of the logic gate unit based on the input ports of the logic gate unit and their corresponding excitation signals, and the state machine description defined in the cell library of the superconducting integrated circuit; a queue update module, configured to update the simulation queue based on the state change of the logic gate unit; a simulation control module, configured to repeat the operation steps in the information acquisition module, the state determination module, and the queue update module until the simulation queue is empty or a preset maximum simulation time is reached, and end the simulation process.

[0014] Third aspect, the present application provides a terminal, including: a processor and a memory; the memory is used to store a computer program; the processor is used to execute the computer program stored in the memory so that the terminal executes the method described above.

[0015] Fourth aspect, the present application provides a computer-readable storage medium, on which a computer program is stored, and when the program is executed by a processor, the method described above is implemented.

[0016] As described above, the dynamic logic simulation method, system, terminal, and medium based on the superconducting integrated circuit of the present application simplify the logic operation in the superconducting integrated circuit by adopting a simple logic gate state machine description, avoid the complex behavior-level modeling process, effectively reduce the computational overhead of waveform simulation; by applying the optimization means of removing the interconnect unit, the computational overhead of the interconnect unit in the simulation process is effectively reduced, the total duration of the entire waveform simulation is shortened, and the dynamic logic simulation efficiency is significantly improved. Description of the Drawings

[0017] Figure 1 It shows a schematic structural diagram of the mobile terminal described in the present application in an embodiment.

[0018] Figure 2 It shows a flowchart of the dynamic logic simulation method based on the superconducting integrated circuit described in the present application in an embodiment.

[0019] Figure 3 It shows a schematic diagram of the structure before optimization of the netlist data structure described in the present application in an embodiment.

[0020] Figure 4Shown is a schematic diagram of the optimized structure of the netlist data structure described in this application in an embodiment.

[0021] Figure 5 Shown is a schematic diagram of the simulation queue described in this application in an embodiment.

[0022] Figure 6a Shown is a schematic diagram of the structure of the D flip-flop described in this application in an embodiment.

[0023] Figure 6b Shown is a schematic diagram of the state transition diagram of the D flip-flop described in this application in an embodiment.

[0024] Figure 7 Shown is a schematic diagram of the structure of the simulation waveform diagram described in this application in an embodiment.

[0025] Figure 8 Shown is a schematic diagram of the structure of the dynamic logic simulation system based on superconducting integrated circuits described in this application in an embodiment.

[0026] Figure 9 Shown is a schematic diagram of the structure of the terminal described in this application in an embodiment. Detailed implementation manners

[0027] The following uses specific specific examples to illustrate the implementation manners of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0028] It should be noted that the diagrams provided in the following embodiments only illustrate the basic concept of this application in a schematic manner. Therefore, only the components related to this application are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in its actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0029] In addition, in this application, descriptions such as "first" and "second" are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one such feature. Additionally, the technical solutions between various embodiments may be combined with each other, but it must be based on the ability of those of ordinary skill in the art to implement. When the combination of technical solutions results in contradictions or is unachievable, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0030] The following embodiments of this application provide a dynamic logic simulation method, system, terminal, and medium based on a superconducting integrated circuit. By using a simple logic gate state machine description, this application simplifies the logic operations in a superconducting integrated circuit, avoids a complex behavioral-level modeling process, and effectively reduces the computational overhead of waveform simulation. By applying an optimization method of removing interconnect units, it effectively reduces the computational overhead of interconnect units during the simulation process, shortens the total duration of the entire waveform simulation, and significantly improves the efficiency of dynamic logic simulation.

[0031] The dynamic logic simulation method based on a superconducting integrated circuit provided by the embodiments of this application can run on similar devices such as mobile terminals and computer terminals. Taking running on the mobile terminal as an example, Figure 1 is a hardware structure block diagram of the mobile terminal, as Figure 1 shown, the mobile terminal may include: a processor and a memory. The processor may be a central processing unit, and the memory is used to store data. Figure 1 The mobile terminal in [the figure] is only for illustration and does not limit the specific structure of the mobile terminal.

[0032] Optionally, the mobile terminal may further include: a communication transmission device and an input / output device.

[0033] Optionally, the memory may be used to store computer programs, such as software programs and modules of application software. The memory may include a high-speed random access memory and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memories. In some instances, the memory may further include a memory remotely disposed relative to the processor, and these remote memories may be connected to the mobile terminal through a network. Examples of the above networks include, but are not limited to, the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof.

[0034] Optionally, the communication transmission device can be used to receive or send data via a network, which can include a wireless network provided by the communication provider of the mobile terminal. The communication transmission device can include a NIC (Network Interface Controller), which can be connected to other network devices through a base station so as to communicate with the Internet.

[0035] Next, the technical solutions in the embodiments of the present application will be described in detail with reference to the accompanying drawings in the embodiments of the present application.

[0036] Please refer to Figure 2 , which shows a flowchart of the dynamic logic simulation method based on a superconducting integrated circuit according to the present application in an embodiment. As Figure 2 shown, this embodiment provides a dynamic logic simulation method based on a superconducting integrated circuit, including the following steps S100 to step S500.

[0037] In step S100, a simulation queue is constructed based on the layout information or gate-level netlist file of the superconducting integrated circuit.

[0038] Specifically, the layout information of the superconducting integrated circuit can be derived from a variety of different layout editing tools and transmitted and parsed through a dedicated interface program.

[0039] The gate-level netlist file uses netlist-level hardware description. This file can be written in any one of the hardware description languages. Common hardware description languages include Verilog and VHDL, etc. For example, Verilog has the characteristics of simplicity and flexibility and can conveniently describe various complex circuit logics. For a superconducting integrated circuit containing multiple logic gate units and complex combinational logics, using Verilog can clearly define the input ports and output ports of each logic gate unit and their logical relationships.

[0040] The simulation queue includes a series of input ports of logic gate units sorted according to the signal arrival time and their corresponding excitation signals.

[0041] In the embodiments of the present application, the signal arrival time is defined as the time node when the input port of the logic gate unit receives the excitation signal. In other embodiments, sorting can also be performed according to the trigger time. The trigger time is defined as the time node when the output port of the logic gate unit sends a signal.

[0042] During the simulation process, the excitation signal is a signal source acting on the input port of the logic gate unit. The logic gate unit performs corresponding logical operations based on the time-varying level signal provided by the excitation signal. Different excitation signals will cause the logic gate unit to produce different output results. By analyzing the output of the logic gate unit under a specific excitation signal, it can be determined whether the logic gate unit is operating according to the expected logical function, thereby achieving the goal of verifying the correctness of the logic design of the superconducting integrated circuit.

[0043] In an embodiment of the present application, based on the layout information or gate-level netlist file of the superconducting integrated circuit, constructing a simulation queue includes the following steps S101 to S103.

[0044] In step S101, convert the layout information or gate-level netlist file of the superconducting integrated circuit into a netlist data structure.

[0045] Specifically, the netlist data structure is used to describe the information of different logic gate units in the superconducting integrated circuit in the form of a data structure.

[0046] In step S102, perform static timing analysis on the netlist data structure to obtain the time when the input port of each logic gate unit receives the corresponding excitation signal, and define this time as the signal arrival time.

[0047] In an embodiment of the present application, performing static timing analysis on the netlist data structure includes: based on the breadth-first search algorithm, traverse all the logic gate units described in the netlist data structure, and use the selected logic gate unit as the current-level logic gate unit; obtain the signal transmission time of the output port of the previous-level logic gate unit; obtain the delay information of the interconnect unit between the current-level logic gate unit and the previous-level logic gate unit from the unit library of the superconducting integrated circuit; the delay information is used to reflect the time when the signal is transmitted from the output port of the previous-level logic gate unit to the input port of the current-level logic gate unit through the interconnect unit; based on the signal transmission time and the delay information, calculate the time when the input port of the current-level logic gate unit receives the corresponding excitation signal, and use it as the signal arrival time.

[0048] For example, the current-level logic gate unit is the first logic gate unit, and the first logic gate unit is connected to the second logic gate unit through an interconnect unit. At t = 5, the output port of the first logic gate unit sends a signal to the cascaded second logic gate unit. From the unit library of the superconducting integrated circuit, the delay information of the interconnect unit can be obtained as t = 2. Therefore, it can be deduced that the actual time when the signal arrives at the input port of the second logic gate is t = 7.

[0049] If the current - stage logic - gate unit is the first - stage logic - gate unit, that is, there is no previous - stage logic - gate unit, then the time when the input port of the current - stage logic - gate unit receives the initial input signal is regarded as the signal arrival time. For example, if the arrival time of the initial input signal is t = 0, then the signal arrival time of the current - stage logic - gate unit is t = 0.

[0050] In an embodiment of the present application, the dynamic logic simulation method based on a superconducting integrated circuit described in the embodiments of the present application further includes: optimizing the netlist data structure before performing static timing analysis on the netlist data structure.

[0051] In an embodiment of the present application, the steps of optimizing the netlist data structure include: parsing the netlist data structure to obtain information about different logic - gate units in the superconducting integrated circuit; based on the information of the logic - gate units, finding all logic - gate units of the interconnection - line type from the unit library of the superconducting integrated circuit; reconnecting each of the logic - gate units of the interconnection - line type; removing all the interconnection - line units, and retaining the mapping relationship between the input port and the output port corresponding to the interconnection - line unit and the delay information of the interconnection - line unit.

[0052] Specifically, the logic - gate units of the interconnection - line type include a driving unit, a receiving unit, a passive transmission line, a Josephson - junction transmission line, and a shunt. Among them, the driving unit is the signal - generating port, which is used to generate and send the required initial input signal to subsequent components of the circuit. The receiving unit is located at the target node and is used to capture the electrical signal sent from the previous stage. The passive transmission line can guide the direction of electron flow without consuming additional energy, and at the same time has the characteristic of low loss, which can ensure the integrity of information without being damaged while reducing the influence of thermal - noise interference. The Josephson - junction transmission line is constructed by using a unique channel formed by a weak insulating layer between superconducting materials, allowing the carrier to pass through at an extremely high speed without hindrance. The shunt is used to achieve the purpose of optimizing the load - balancing configuration.

[0053] Please refer to Figure 3 , which shows the schematic diagram of the structure of the netlist data structure described in the present application before optimization in an embodiment. As Figure 3 shown, Logic Gate 1 and Logic Gate 2 are the logic - gate units of the interconnection - line type. There are multiple interconnection - line units distributed around Logic Gate 1 and Logic Gate 2.

[0054] Please refer to Figure 4 , which shows the schematic diagram of the structure of the netlist data structure described in the present application after optimization in an embodiment. As Figure 4As shown, only the logic gates 1, 2 and the logical connection between them are retained in the netlist data structure. The input ports of both logic gates 1 and 2 are marked as AI and B1, and the output ports are both marked as Out.

[0055] In an embodiment of the present application, the step of reconnecting each of the logic gate units of the interconnect type includes: modifying the connection relationship of the front and rear nodes of the logic gate units of the interconnect type based on the principle of the shortest signal transmission path and the minimum delay.

[0056] When analyzing the logic simulation results of a superconducting integrated circuit, the focus is mainly on the waveform changes of the logic gate units. Since the waveform of the interconnect unit remains constant throughout the simulation and does not participate in logical operations, removing the interconnect unit will not affect the logical function of the circuit. Retaining these interconnect units will instead cause the simulation process to needlessly calculate their logical changes, which, although non-existent, will significantly increase the time required for the simulation.

[0057] In this implementation, by applying the optimization measure of removing the interconnect units, the computational overhead of the interconnect units during the simulation is effectively reduced, the total duration of the entire waveform simulation is shortened, the simulation efficiency is significantly improved, and the logical analysis of the superconducting integrated circuit becomes more rapid and efficient.

[0058] In step S103, according to the order of arrival time of the signals, the input ports of all the logic gate units and their corresponding excitation signals are added to a preset list to form the simulation queue.

[0059] In an embodiment of the present application, the simulation queue is a data structure for storing the input ports of the logic gate units to be processed and their corresponding excitation signals.

[0060] Each time an excitation signal is added to the simulation queue, it is equivalent to adding a waveform event to be processed to the simulation queue. These waveform events are arranged in chronological order, and the system updates the state of the circuit by processing each waveform event in turn.

[0061] In step S200, from the simulation queue, the input ports of the logic gate units corresponding to the earliest signal arrival time and their corresponding excitation signals are obtained.

[0062] Specifically, the earliest signal arrival time is the minimum value among the timestamps corresponding to all elements in the simulation queue.

[0063] Please refer to Figure 5 , which shows a schematic diagram of the simulation queue according to the present application in an embodiment.

[0064] As Figure 5As shown, after the logic gate unit corresponding to the earliest signal arrival time and its corresponding excitation signal are extracted from the simulation queue, the logic gate unit and its corresponding excitation signal will be automatically removed from the simulation queue, and subsequent other elements will be advanced in sequence waiting to be processed.

[0065] In step S300, based on the input ports of the logic gate unit and its corresponding excitation signal, and the state machine description defined in the cell library of the superconducting integrated circuit, determine the state change of the logic gate unit.

[0066] In an embodiment of the present application, the state machine description is the state transition diagram and state transition table of the logic gate unit defined in the cell library of the superconducting integrated circuit.

[0067] Taking the logic gate unit as a D flip-flop as an example, please refer to Figure 6a and 6b , Figure 6a which shows the structural schematic diagram of the D flip-flop described in the present application in an embodiment, Figure 6b and which shows the schematic diagram of the state transition diagram of the D flip-flop described in the present application in an embodiment. Please refer to Table 1, which shows the state transition table of the D flip-flop described in the present application.

[0068] Table 1. State transition table of D flip-flop

[0069]

[0070] In an embodiment of the present application, based on the input ports of the logic gate unit and its corresponding excitation signal, and the state machine description defined in the cell library of the superconducting integrated circuit, determining the state change of the logic gate unit includes: if the current state of the logic gate unit is low level, when the excitation signal arrives at the corresponding input port, the next state of the logic gate unit will become high level; if the current state of the logic gate unit is low level, when the internal clock signal arrives at the corresponding input port, the next state of the logic gate unit will become low level; if the current state of the logic gate unit is high level, when the excitation signal arrives at the corresponding input port, the next state of the logic gate unit will become high level; if the current state of the logic gate unit is high level, when the internal clock signal arrives at the corresponding input port, the next state of the logic gate unit will become low level, and at the same time the output port of the logic gate unit outputs a signal.

[0071] It should be noted that the number of states of different logic gate units varies. For example, the D-type flip-flop mentioned above only has two states, high level and low level; while other types of logic gate units may have three, four or even more states. To save space, the specific state conditions of other logic gate units will not be described in detail in this application.

[0072] In this implementation, by using a simple logic gate state machine description, the logic operations in the superconducting integrated circuit are simplified, the complex behavior-level modeling process is avoided, and the computational overhead of waveform simulation is effectively reduced.

[0073] In step S400, based on the state change of the logic gate unit, the simulation queue is updated.

[0074] In an embodiment of the present application, updating the simulation queue based on the state change of the logic gate unit includes: determining whether a signal is output from the output port of the logic gate unit; if so, determining the input port of the next-level logic gate unit according to the output port of the logic gate unit; determining the signal arrival time of the next-level logic gate unit; using the signal output from the output port of the logic gate unit as the excitation signal of the next-level logic gate unit; adding the input port of the next-level logic gate unit and its corresponding excitation signal to the simulation queue according to the signal arrival time; otherwise, keeping the content of the simulation queue unchanged.

[0075] Specifically, after determining the output port of the logic gate unit, the input port of the next-level logic gate unit can be determined according to the mapping relationship between the corresponding input port and output port of the interconnection unit.

[0076] In addition, the signal arrival time of the next-level logic gate unit can be determined according to the method described in step S102 above. For specific embodiments, reference can be made to step S102, which will not be repeated here.

[0077] In step S500, steps S200 to S400 are repeated until the simulation queue is empty or a preset maximum simulation time is reached, and the simulation process ends.

[0078] Specifically, the simulation queue being empty includes the following two situations:

[0079] (1) The state transition of the logic gate unit is not triggered.

[0080] Specifically, during the simulation process, if the current logic gate unit does not undergo a state transition, no new elements will be added to the simulation queue. At this time, the simulation queue only continuously removes existing elements. Without new elements being added, the elements in the simulation queue will eventually be completely removed, resulting in the simulation queue becoming an empty queue, thereby triggering the end of the simulation process.

[0081] (2) The output signal of the logic gate unit is not triggered.

[0082] Specifically, when the output signal of the logic gate unit is not triggered, no new signal will be added to the simulation queue either. Subsequently, as the existing elements are continuously removed, the queue will gradually become empty, meeting the condition for ending the simulation.

[0083] In the embodiment of the present application, the maximum simulation time can be set by the user according to needs, such as 1000 ps (picoseconds). Each time an element is obtained from the simulation queue, its timestamp will be checked. If it is found that the timestamp exceeds the set maximum simulation time, then even if the simulation queue is not empty, the simulation process will be directly terminated.

[0084] In an embodiment of the present application, the dynamic logic simulation method based on a superconducting integrated circuit described in the embodiment of the present application further includes the following steps S600 and S700.

[0085] In step S600, select an input port or an output port of any one of the logic gate units as a measurement node.

[0086] In the embodiment of the present application, the user can select an input port or an output port of the logic gate unit as a measurement node according to needs. This means that the user can flexibly decide which points in the circuit to monitor.

[0087] In step S700, draw a corresponding simulation waveform diagram according to the time variation characteristics of the logic level value at the measurement node.

[0088] Please refer to Figure 7 , which shows a schematic structural diagram of the simulation waveform diagram described in the present application in an embodiment. As Figure 7 shown, the abscissa in the simulation waveform diagram represents the simulation time, and the ordinate represents the logic level value. Specifically, when there is a value on the ordinate, it represents a high level, and when there is no value, it represents a low level.

[0089] It should be noted that the protection scope of the dynamic logic simulation method based on a superconducting integrated circuit described in the embodiment of the present application is not limited to the execution order of the steps listed in this embodiment. Any solution achieved by adding or reducing steps of the prior art and replacing steps according to the principle of the present application is included in the protection scope of the present application.

[0090] Please refer to Figure 8 , which shows a schematic structural diagram of the dynamic logic simulation system based on a superconducting integrated circuit described in the present application in an embodiment. As Figure 8As shown in the figure, the present application provides a dynamic logic simulation system based on a superconducting integrated circuit, including a queue construction module, an information acquisition module, a state determination module, a queue update module, and a simulation control module.

[0091] The queue construction module is used to construct a simulation queue based on the layout information or gate-level netlist file of the superconducting integrated circuit; the simulation queue includes a series of input ports of logic gate units sorted according to the signal arrival time and their corresponding excitation signals.

[0092] The information acquisition module is used to acquire, from the simulation queue, the input port of the logic gate unit corresponding to the earliest signal arrival time and its corresponding excitation signal.

[0093] The state determination module is used to determine the state change of the logic gate unit based on the input port of the logic gate unit and its corresponding excitation signal, as well as the state machine description defined in the cell library of the superconducting integrated circuit.

[0094] The queue update module is used to update the simulation queue based on the state change of the logic gate unit.

[0095] The simulation control module is used to repeat the operation steps in the information acquisition module, the state determination module, and the queue update module until the simulation queue is empty or a preset maximum simulation time is reached, and then end the simulation process.

[0096] It should be noted that the structures and principles of the queue construction module, the information acquisition module, the state determination module, the queue update module, and the simulation control module described in the present application correspond one by one to the steps in the above-mentioned dynamic logic simulation method based on a superconducting integrated circuit, so they will not be elaborated here.

[0097] The dynamic logic simulation system based on a superconducting integrated circuit provided in the embodiments of the present application can implement the dynamic logic simulation method described in the present application. However, the implementation device of the dynamic logic simulation method described in the present application includes, but is not limited to, the structure of the dynamic logic simulation system based on a superconducting integrated circuit listed in this embodiment. Any structural deformation and replacement of the prior art made according to the principle of the present application are included in the protection scope of the present application.

[0098] Please refer to Figure 9 which shows the structural schematic diagram of the terminal in an embodiment of the present application. As Figure 9 shown, the present application provides a terminal, including: a processor and a memory.

[0099] The memory is used to store a computer program.

[0100] The processor is configured to execute the computer program stored in the memory, so that the terminal executes the method described above.

[0101] In an embodiment of the present application, the processor may be a general-purpose processor, including a central processing unit (CPU for short), a network processor (NP for short), etc.; it may also be a digital signal processor (DSP for short), an application-specific integrated circuit (ASIC for short), a field programmable gate array (FPGA for short), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The memory may be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, a magnetic disk, or an optical disk.

[0102] This embodiment further includes one or more of a multimedia component, an input / output (I / O) interface, and a communication component.

[0103] The multimedia component may include a screen and an audio component. The screen may be, for example, a touch screen, and the audio component is used to output and / or input audio signals. For example, the audio component may include a microphone for receiving external audio signals. The received audio signals may be further stored in the memory or transmitted through the communication component. The audio component also includes at least one speaker for outputting audio signals. The I / O interface provides an interface between the processor and other interface modules, and the other interface modules may be a keyboard, a mouse, buttons, etc. These buttons may be virtual buttons or physical buttons. The communication component may adopt wireless communication methods, such as Wi-Fi, Bluetooth, Near Field Communication (NFC), 2G, 3G, or 4G, or a combination of one or more of them. Accordingly, the communication component may include: a Wi-Fi module, a Bluetooth module, and an NFC module.

[0104] In several embodiments provided in this application, it should be understood that the disclosed system, device, or method may be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of modules / units is only a logical function division, and there may be other division methods in actual implementation. For example, multiple modules or units may be combined or integrated into another system, or some features may be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other may be through some interfaces, and the indirect couplings or communication connections of devices or modules or units may be in electrical, mechanical, or other forms.

[0105] The modules / units described as separate components may or may not be physically separated, and the components displayed as modules / units may or may not be physical modules, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules / units may be selected according to actual needs to achieve the purpose of the embodiments of this application. For example, in each embodiment of this application, the functional modules / units may be integrated in a processing module, or each module / unit may exist physically alone, or two or more modules / units may be integrated in one module / unit.

[0106] Those of ordinary skill in the art should also be further aware that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0107] The embodiments of the present application also provide a computer-readable storage medium, on which a computer program is stored, and when the program is executed by a processor, the above-described method is implemented. Those of ordinary skill in the art can understand that all or part of the steps in the method of implementing the above embodiments can be completed by instructing the processor through a program. The described program can be stored in a computer-readable storage medium. The storage medium is a non-transitory medium, such as random access memory, read-only memory, flash memory, hard disk, solid-state drive, magnetic tape, floppy disk, optical disc, and any combination thereof. The above storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more integrated available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., digital video disc (DVD)), or a semiconductor medium (e.g., solid state disk (SSD)), etc.

[0108] The embodiments of the present application can also provide a computer program product, which includes one or more computer instructions. When the computer instructions are loaded and executed on a computing device, the processes or functions described in the embodiments of the present application are fully or partially generated. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, or data center to another website, computer, or data center in a wired manner (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or a wireless manner (e.g., infrared, wireless, microwave, etc.).

[0109] When the computer program product is executed by a computer, the computer executes the method described in the foregoing method embodiments. The computer program product may be a software installation package. In the case where the foregoing method needs to be used, the computer program product can be downloaded and executed on the computer.

[0110] The descriptions of the processes or structures corresponding to the foregoing various drawings each have their own focuses. For parts not detailed in a certain process or structure, reference may be made to the relevant descriptions of other processes or structures.

[0111] The foregoing embodiments merely illustrate the principles and effects of the present application, rather than limiting the present application. Any person familiar with this technology can modify or change the foregoing embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed in the present application should still be covered by the claims of the present application.

Claims

1. A dynamic logic simulation method based on superconducting integrated circuits, characterized in that: include: Step S100, constructing a simulation queue based on the layout information or gate-level netlist file of the superconducting integrated circuit; the simulation queue includes a series of input ports of logic gate units sorted according to signal arrival time and their corresponding excitation signals; Step S200, obtaining the input port of the logic gate unit corresponding to the earliest signal arrival time and its corresponding excitation signal from the simulation queue; Step S300, determining a state change of the logic gate unit based on an input port of the logic gate unit and its corresponding excitation signal, and a state machine description defined in a cell library of a superconducting integrated circuit; Step S400, updating the simulation queue based on the state change of the logic gate unit; Step S500, repeating steps S200 to S400 until the simulation queue is empty or the preset maximum simulation time is reached, and then terminating the simulation process.

2. The method according to claim 1, characterized in that Based on the layout information or gate-level netlist file of the superconducting integrated circuit, the simulation queue is constructed including: Converting the layout information or gate-level netlist file of the superconducting integrated circuit into a netlist data structure; the netlist data structure is used to describe the information of different logic gate units in the superconducting integrated circuit in the form of a data structure; Performing static timing analysis on the netlist data structure to obtain the time when the input port of each logic gate unit receives the corresponding stimulus signal, and defining the time as the signal arrival time; According to the order of arrival time of the signals, the input ports of all the logic gate units and their corresponding excitation signals are added to a preset list to form the simulation queue.

3. The method according to claim 2, characterized in that Performing static timing analysis on the netlist data structure includes: Based on a breadth-first search algorithm, traverse all the logic gate units described in the netlist data structure, and use the selected logic gate unit as the current-level logic gate unit; Obtain the signal sending time of the output port of the previous level logic gate unit; Obtaining delay information of an interconnection line unit between the current-stage logic gate unit and the previous-stage logic gate unit from a unit library of the superconducting integrated circuit; the delay information is used to reflect the time taken for a signal to be transmitted from an output port of the previous-stage logic gate unit through the interconnection line unit to an input port of the current-stage logic gate unit; Based on the signal sending time and the delay information, the time when the input port of the current-stage logic gate unit receives the corresponding excitation signal is calculated and used as the signal arrival time.

4. The method according to claim 3, characterized in that: Also includes: Before performing static timing analysis on the netlist data structure, optimizing the netlist data structure; in The step of optimizing the netlist data structure includes: Parsing the netlist data structure to obtain information of different logic gate units in the superconducting integrated circuit; Based on the information of the logic gate unit, searching for logic gate units of all interconnection line types from a unit library of the superconducting integrated circuit; Reconnecting logic gate units of each interconnect line type; All the interconnection line units are removed, and the mapping relationship between the input port and the output port corresponding to the interconnection line unit and the delay information of the interconnection line unit are retained.

5. The method according to claim 1, characterized in that Based on the input port of the logic gate unit and its corresponding excitation signal, and the state machine description defined in the unit library of the superconducting integrated circuit, determining the state change of the logic gate unit includes: If the current state of the logic gate unit is a low level, when the excitation signal reaches the corresponding input port, the next state of the logic gate unit will become a high level; If the current state of the logic gate unit is a low level, when the internal clock signal reaches the corresponding input port, the next state of the logic gate unit will become a low level; If the current state of the logic gate unit is a high level, when the excitation signal reaches the corresponding input port, the next state of the logic gate unit will become a high level; If the current state of the logic gate unit is a high level, when the internal clock signal reaches the corresponding input port, the next state of the logic gate unit will become a low level, and the output port of the logic gate unit outputs a signal.

6. The method according to claim 4, characterized in that Based on the state change of the logic gate unit, updating the simulation queue includes: Determining whether the output port of the logic gate unit outputs a signal; If yes, determine the input port of the next-level logic gate unit according to the output port of the logic gate unit; determine the signal arrival time of the next-level logic gate unit; use the signal output by the output port of the logic gate unit as the excitation signal of the next-level logic gate unit; add the input port of the next-level logic gate unit and its corresponding excitation signal to the simulation queue according to the signal arrival time; Otherwise, the content of the simulation queue remains unchanged.

7. The method according to claim 1, characterized in that Also includes: Selecting an input port or an output port of any of the logic gate units as a measurement node; According to the time variation characteristics of the logic level value at the measurement node, a corresponding simulation waveform diagram is drawn.

8. A dynamic logic simulation system based on superconducting integrated circuits, characterized in that: include: A queue construction module is used to construct a simulation queue based on the layout information or gate-level netlist file of the superconducting integrated circuit; the simulation queue includes a series of input ports of logic gate units sorted according to signal arrival time and their corresponding excitation signals; An information acquisition module, used for acquiring the input port of the logic gate unit corresponding to the earliest signal arrival time and its corresponding excitation signal from the simulation queue; A state determination module, used to determine the state change of the logic gate unit based on the input port of the logic gate unit and its corresponding excitation signal, and the state machine description defined in the unit library of the superconducting integrated circuit; A queue updating module, used for updating the simulation queue based on the state change of the logic gate unit; The simulation control module is used to repeat the operation steps in the information acquisition module, the state determination module and the queue update module until the simulation queue is empty or the preset maximum simulation time is reached, thereby terminating the simulation process.

9. A terminal, characterized in that: include: Processor and memory; The memory is used to store computer programs; The processor is configured to execute the computer program stored in the memory, so that the terminal executes the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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