High-reliability clock network construction method based on distributed dynamic management
By dividing the clock generation plane and the control management plane in the integrated circuit, the distributed clock network is dynamically planned, which solves the problem that centralized clock network management is difficult to meet clock requirements under complex chip scale, and realizes the construction of clock networks with high reliability, low power consumption and high scalability.
Patent Information
- Application Number
- CN202510285007.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-11
- Publication Date
- 2025-06-27
AI Technical Summary
In existing integrated circuit designs, centralized clock network management is difficult to meet clock requirements under complex chip scale, and a single management solution has problems such as high power consumption, reliability and insufficient scalability.
A distributed and dynamically managed high-reliability clock network is proposed. By dividing the clock network inside the chip into a clock generation plane and a control management plane, the distributed clock network is dynamically planned, and dynamic management of clocks at all levels and centralized planning of enable signals is realized.
It realizes dynamic management of modules, high scalability, high reliability and low power consumption clock network construction, reduces dynamic power consumption and improves system reliability.
Smart Images
Figure CN120218002A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of integrated circuit design, and relates to a distributed management clock network technology inside a chip. This technology forms a distributed system by building clock generation modules in each module, and ensures the dynamic management of the clock network through the management of the distributed system. This system can effectively reduce dynamic power consumption and improve reliability. Background Art
[0002] In chip design, clock network management is crucial because the clock signal is the key to coordinating the operations of various modules inside the chip. Currently, the following technologies are mainly used for clock management.
[0003] Based on PLL (Phase Locked Loop) and DPLL (Digital Phase Locked Loop). It mainly generates stable clock signals through phase-locked loop technology, supports frequency multiplication, division, and phase adjustment. It can provide high-precision clock signals, support dynamic frequency adjustment, and adapt to the needs of different modules. However, the analog PLL design is complex, with high power consumption. The locking time is long, which may affect the system startup time.
[0004] Based on clock distribution network for management. The clock signal is distributed through a symmetric tree structure or a grid structure (Clock Mesh) to ensure that the delay of the clock reaching each module is consistent. This technology has extremely low clock skew and is suitable for ultra-high frequency design. However, its power consumption and wiring resource occupancy are higher.
[0005] Cross-Clock Domain Processing (CDC) technology. When transferring signals between different clock domains, it uses technologies such as synchronizers, handshake protocols, or FIFOs to solve clock domain interaction problems. This technology improves the reliability of cross-clock domain communication and avoids metastability problems. However, it increases the design and verification complexity and may introduce additional delays.
[0006] Gated clock technology. By adding gated logic on the clock path, the unnecessary clock signals are dynamically turned off to save power. This technology significantly reduces dynamic power consumption and is easy to implement modular clock control. However, it will introduce additional clock skew and increase the complexity of timing verification.
[0007] Today's chip design is becoming increasingly complex. While having high-precision requirements for the clock signal network, there are also higher requirements for power consumption and scalability. The single-source centralized management schemes based on phase-locked loops and clock distribution networks have the disadvantage of high power consumption. Cross-clock domain processing and gated clock technology cannot simultaneously balance the reliability and scalability of the clock signal network.
[0008] In existing integrated circuit designs, centralized clock network management is widely adopted. That is, after an external clock is input, it passes through a general clock generation module to generate various generated clocks for each module inside the chip, and the module manages the clocks of each module. With the continuous increase in chip scale, a single centralized clock network construction and management can no longer meet the complex clock requirements of chips. Summary of the Invention
[0009] The present invention proposes a construction of a distributed and dynamically manageable highly reliable clock network. This network has the characteristics of dynamic management of modules, high scalability, high reliability, and low power consumption.
[0010] To achieve the above object, the technical means adopted in the present invention is to divide the clock network inside the chip into a clock generation plane and a control and management plane. The division of the clock generation plane corresponds to the division of the functional modules inside the chip, and the clock generation modules are distributed in the functional modules at all levels; the control and management plane generates an enable signal for controlling the clocks at all levels in the clock generation plane according to the functional requirements inside the chip, and dynamically manages the clocks distributed inside the chip through the enable signal. Through this method, the clocks distributed at all levels inside the chip can be dynamically and centrally planned, effectively solving the complex clock generation and management problems inside large-scale integrated circuits.
[0011] The following technical solutions are adopted to implement:
[0012] The construction of a dynamically planned distributed clock network is divided into the construction of a clock generation plane and a control and management plane. The clock generation plane is based on the division of the internal functional modules of the chip, extracts the clocks of each level of functional modules and isolates the corresponding clock generation modules at all levels distributed in the sub-functional modules at all levels. The control and management plane is based on the functions inside the chip, summarizes the parts that can be centrally controlled and managed, extracts the control information in each level of functional modules, and centrally plans and manages the clock networks at all levels.
[0013] The construction method of the clock generation plane is to extract the clocks required by each level of functional modules inside the chip on the basis of clarifying the internal functional structure of the chip, construct the corresponding clock generation modules at all levels of functional modules, and the clock generation modules at all levels are distributed in the functional modules at all levels. In the construction of a three-level clock network, the first-level clock generation module inside the chip is based on the externally input clock to generate different frequency sub-source clocks required for all inside the chip. The second-level clock generation module uses the sub-source clock as the input to generate the subsystem generation clocks required by each third-level module in the second-level system for the third-level modules to use. The third-level clock generation module uses the second-level clock as the input to generate all the generated clocks required in the third-level modules.
[0014] The construction method of the control and management plane is to extract the enable signals for controlling the generated clocks at all levels based on the internal functions of the induction chip, centrally plan and dynamically manage these enable signals, which are used to manage the generated clocks at all levels according to the different functions of the chip. The control and management plane is mainly composed of a dynamic planning module, which generates the enable signals for clock management at all levels according to the chip functions. In particular, by managing the enable signals of different-level clocks, the dynamic power consumption of the chip can be reduced by turning off unnecessary clocks.
[0015] The construction and management method of the dynamic planning distributed clock network is as follows. Among them, S1x (x = 0, 1, 2) is the clock generation plane, and S2x (x = 0, 1) is the control and management plane.
[0016] S10: Establish a primary clock generation module to generate the sub-source clock signals required inside the circuit. The primary clock generation module divides or multiplies the externally input clock of the chip to generate all the frequency clocks required for each function inside the chip, and these clocks correspond to the primary sub-source clock signals.
[0017] S20: According to the function division of the chip, extract the control signals of each function of the chip. The dynamic planning module uses the control signals of each function as inputs to generate the clock control signals for controlling the clock generation modules at all levels.
[0018] S10.1: Establish a secondary clock generation module. Combine the sub-source clock generated in step S10 with the secondary subsystem control signal generated in step S20, and through the gating logic inside the module, generate the secondary subsystem generated clock for use by the secondary subsystem and the modules below the secondary subsystem.
[0019] S20.1: Divide the tertiary sub-modules according to the functions of the secondary subsystem, extract the clock enable signals of the tertiary sub-modules according to the function division of the tertiary sub-modules, and manage all the clocks inside the sub-modules through the clock enable signals of the tertiary sub-modules.
[0020] S10.2: Establish a tertiary clock generation module. In the tertiary clock generation module, combine the clock control signal generated in step S20 with the sub-module clock enable signal generated in step S21, and through the gating logic gate the secondary subsystem generated clock generated in step S11 to generate the tertiary sub-module generated clock.
[0021] In steps S20 and S20.1, the on-chip clock can be controlled according to different functional requirements within the dynamic programming module by controlling the clock control signals at all levels. In particular, not only can the generated clocks at all levels be widely controlled according to different functional requirements during the chip initialization phase, but also the clocks at all levels can be dynamically managed during the chip operation. The above method steps adopt the method of combining the clock generation plane and the control and management plane, realizing the construction and management of the dynamic programming distributed clock network.
[0022] The present invention has the following advantages:
[0023] 1. The clock generation plane separates the clocks at all levels from the complex chip functional logic, forms independent sub-clock generation modules at all levels and distributes them in the corresponding functional modules. The construction of the distributed clock network tree-izes and scales the complex clock network, realizing the refined construction and management of the complex clock logic in the chip and safely establishing a perfect clock network. In addition, combining the functional module with its corresponding clock module also facilitates the transplantation of the entire functional code, having very flexible usability.
[0024] 2. The clock management plane dynamically overall manages the distributed clock networks at all levels. By using the gating logic through the clock enable signals at all levels to generate the gated clocks at all levels, the dynamic power consumption generated by the clock flips of the non-working logic can be reduced. By dynamically programming and managing the distributed clocks, the low-power design is penetrated into the deep-level module design, reducing the system dynamic power consumption and enhancing the reliability of the system. Brief Description of the Drawings
[0025] Figure 1 It is the principle block diagram of the construction of the dynamic programming distributed three-level clock network according to the embodiment of the present invention;
[0026] Figure 2 It is the management method of the dynamic programming distributed clock network according to the embodiment of the present invention; Detailed Embodiment
[0027] The present invention will be further described in detail below with reference to the drawings and embodiments.
[0028] The present invention has been successfully applied to two PCIe switching circuits. Both of the two PCIe switching circuits adopt this method of constructing and managing the dynamic programming distributed clock network. One of the PCIe switching circuits is for two-level clock construction and management, and the other PCIe switching circuit is for three-level clock construction and management. Currently, both circuits have passed the user trial and can work correctly and stably, and can reduce the dynamic power consumption under specific modes and functions. Hereinafter, one of the PCIe switching circuits for three-level clock construction and management will be taken as an example for detailed introduction.
[0029] Figure 1It is a principle block diagram of constructing and managing a dynamic programming distributed clock network according to an embodiment of the present invention. A method for constructing and managing a dynamic programming distributed clock network in this embodiment uses a pair of PCIe differential clock pins REFCLK_p / n of a PCIe switching circuit as an external clock input, and generates sub-source clocks in a primary clock generation module for sharing by a secondary subsystem and a circuit sharing module; inside the secondary subsystem, using the sub-source clock as an input, a secondary subsystem generated clock is generated according to the enable signal output by the dynamic programming module for sharing by a tertiary sub-module and the secondary subsystem sharing module; inside the tertiary sub-module, using the secondary subsystem generated clock as an input, a corresponding tertiary sub-module generated clock is generated according to the enable signal output by the dynamic programming module and the enable signal of the PCIe controller IP (PCIe_IP) for sharing by the PCIe controller IP and other modules in the sub-module.
[0030] The construction of the dynamic programming distributed clock network according to the embodiment of the present invention includes a primary clock generation module, i.e., a total clock generation module (CGU_GLB), a dynamic programming module, a secondary subsystem clock generation module (CLK_SYS_x, x = 0 to 2), and a tertiary sub-module clock generation module (CGU_px, x = 0 to 6). The PCIe switching circuit uses the PCIe differential clock pins REFCLK_p / n as an external clock input. Through the total clock generation module, 3 sub-source clocks are generated. Inside each subsystem, using its corresponding 1 sub-source clock as an input, 1 secondary subsystem generated clock is generated in the subsystem clock generation module of the subsystem under the management of the dynamic programming module. A total of 3 secondary subsystem generated clocks are generated by 3 subsystems. Each sub-module inside the subsystem uses the corresponding secondary subsystem generated clock as an input, and 6 groups of 5 sub-module generated clocks in each group are generated in the sub-module clock generation module under the management of the dynamic programming management module and the PCIe controller IP. A total of 90 sub-module generated clocks in 18 groups are generated by 18 sub-modules of 3 subsystems.
[0031] (1) Total clock generation module
[0032] The total clock generation module in the PCIe switching circuit uses the differential clock pin input REFCLK_p / n of the PCIe switching circuit as an external clock input, and generates sub-source clocks with the required frequencies inside the PCIe switching circuit. The PCIe switching circuit has 12 PCIe ports, and the 12 PCIe ports are divided into 3 subsystems with every 4 ports as a group. The total clock generation module generates 3 sub-source clocks for use by the corresponding 3 subsystems. In particular, the circuit sharing module and subsystem 0 inside the circuit share one sub-source clock.
[0033] (2) 3 secondary subsystem clock generation modules
[0034] A subsystem clock generation module is integrated inside each of the three subsystems of the PCIe switch circuit. Inside each subsystem of the PCIe switch circuit, six sub-modules are divided for the four ports according to their different functions. The subsystem clock generation module inside the subsystem takes the sub-source clock of the subsystem as the input, and through the management of the dynamic programming module, six subsystem-generated clocks corresponding to each sub-module and their corresponding reset signals with asynchronous reset and synchronous cancellation are generated. Particularly, the subsystem shared module and sub-module 0 inside each subsystem share one subsystem-generated clock.
[0035] (3) 18 sub-module clock generation modules
[0036] The PCIe switch circuit is divided into three subsystems and six sub-modules according to 12 ports and their configuration functions. Each sub-module integrates one PCIe port controller IP, and a total of 18 PCIe port controller IPs are integrated. The 18 sub-clock generation modules correspond to the PCIe IPs of each port, generating the clocks and resets of the PCIe IPs of each port. Each port PCIe port controller IP uses five clocks according to different functions, and a total of 90 clocks are used for the 18 port PCIe IPs. Particularly, the clocks of other modules inside each sub-module are sourced from one of the clocks of sub-module 0.
[0037] (4) Dynamic programming module
[0038] The PCIe switch circuit with 12 PCIe ports can be combined into 16 port configuration modes. In a specific port mode, unused port clocks can be turned off to reduce the chip power consumption, and the dynamic programming module integrated inside the PCIe switch emerges as the times require. The dynamic programming module generates three subsystem enable signals and 18 sub-clock enable signals for the three subsystems and 18 sub-modules respectively. The subsystem enable signals manage the subsystem-generated clocks of the three subsystems, and the sub-clock enable signals manage the 18 sub-clock enable signals.
[0039] The management method of the dynamic programming distributed clock network in the embodiment of the present invention is to divide the clock network inside the PCIe switch circuit into a clock generation plane and a control and management plane according to functions. The enable signals generated by the control and management plane dynamically manage each clock inside the clock generation plane. Each clock generation module inside the clock generation plane uses gated clocks, and the gated clocks are strictly designed according to mature standard logic, avoiding clock glitches introduced by logic design defects and ensuring the reliability of the timing.
[0040] S10: Analyze the external input clock and each clock frequency required within the chip, establish a total clock generation module, and generate the sub-source clock signals required inside the circuit. The PCIe switching circuit uses a pair of PCIe differential clock pins REFCLK_p / n as the external clock input, and generates three sub-source clocks for corresponding three subsystems to use.
[0041] S20: Divide the subsystems according to the chip functions. The dynamic programming module generates corresponding subsystem clock control signals according to the subsystem functions, and generates corresponding sub-module clock control signals according to the sub-module functions. The PCIe switching circuit divides into three subsystems and 18 sub-modules. The dynamic programming module outputs three subsystem clock control signals to manage the subsystem-generated clocks within the three subsystems, and outputs 18 sub-module clock control signals to manage the sub-module-generated clocks within the 18 sub-modules.
[0042] S10.1: Generate the subsystem-generated clocks from the sub-source clocks according to the subsystem control signals. The three subsystems of the PCIe switching circuit correspond to three subsystem clock generation modules. The subsystem clock generation modules generate the subsystem-generated clocks through gating logic according to the sub-source clocks and the subsystem clock control signals output by the dynamic programming module. The dynamic programming module controls the enabling and disabling of the subsystem-generated clocks by managing the subsystem clock control signals generated according to whether the 18 sub-modules are enabled or disabled in 16 different configuration modes of 12 ports of the PCIe switching circuit. For example, when the PCIe switching circuit only uses the ports within subsystem 0, the subsystem 0-generated clock can be enabled by the subsystem 0 clock control signal output by the dynamic programming module. At this time, the subsystem 1-generated clock and the subsystem 2-generated clock are in the disabled state to achieve the purpose of reducing dynamic power consumption.
[0043] S20.1: Divide the sub-modules according to the subsystem functions. The PCIe controller IP generates corresponding sub-module clock enable signals according to the sub-module functions. The PCIe controller IPs inside the 18 sub-modules of the PCIe switching circuit generate the enable signals for the sub-module clock generation modules according to different function divisions, namely the core clock enable signal, the additional clock enable signal, the mixed clock enable signal, and the receive clock enable signal.
[0044] S10.2: Generate the sub-module-generated clocks from the subsystem-generated clocks according to the sub-module control and enable signals. The sub-module clock generation modules within the 18 sub-modules of the PCIe switching circuit correspond one-to-one with the PCIe controller IPs. The sub-module clock generation modules generate the sub-module-generated clocks required by the PCIe controller IP and other logics through gating logic according to the sub-module clock control signals output by the dynamic programming module and the sub-module clock enable signals output by the PCIe controller IP.
[0045] The PCIe switching circuit realizes the refined management of the complex internal clock network of the PCIe switching circuit by applying the above-mentioned dynamic programming distributed clock network construction and management method, reliably and securely establishes a perfect clock network, reduces the dynamic power consumption of the PCIe switching circuit, and improves the reliability of the system.
Claims
1. A method for constructing a high-reliability clock network based on distributed dynamic management, characterized in that: It is divided into the construction of clock generation plane and control management plane. The clock network inside the chip is divided into clock generation plane and control management plane. The division of clock generation plane corresponds to the division of functional modules inside the chip. The clock generation modules are distributed in functional modules at all levels. The control management plane generates and manages clock enable signals. The enable signals control the clocks distributed in various modules in the chip. Dynamic distributed clock management is achieved through centralized planning of enable signals.
2. The method for constructing a high-reliability clock network based on distributed dynamic management according to claim 1, characterized in that: The clock generation plane is based on the division of functional modules within the chip. It refines the clocks of functional modules at all levels and independently distributes the corresponding clock generation modules at all levels in sub-functional modules at all levels. The control and management plane is based on the functions within the chip, summarizes the parts that can be centrally controlled and managed, extracts the control information in functional modules at all levels, and centrally plans and manages clock networks at all levels.
3. The method for constructing a high-reliability clock network based on distributed dynamic management according to claim 1, characterized in that: The construction of the clock generation plane is to extract the clocks required by the functional modules at all levels inside the chip on the basis of clarifying the internal functional structure of the chip, and to construct clock generation modules at all levels corresponding to the functional modules at all levels. The clock generation modules at all levels are distributed in the functional modules at all levels. In the construction of the three-level clock network, the first-level clock generation module in the chip generates sub-source clocks of different frequencies for all the requirements inside the chip based on the external input clock. The second-level clock generation module uses the sub-source clock as input to generate the subsystem generated clocks required by each third-level module in the second-level system for use by the third-level modules. The third-level clock generation module uses the second-level clock as input to generate all the generated clocks required in the third-level modules.
4. The method for constructing a high-reliability clock network based on distributed dynamic management according to claim 1, characterized in that: The construction of the control management plane is to extract the enable signal for controlling the generated clock at each level in the functional modules at each level based on the summary of the internal functions of the chip, centrally plan and dynamically manage the enable signal. This enable signal is used to manage the generated clock at each level according to the different functions of the chip. The control management plane is composed of a dynamic planning module, which generates enable signals for clock management at each level according to the chip function. By managing the clock enable signals at different levels, non-essential clocks are turned off to reduce the dynamic power consumption of the chip.
5. The method for constructing a high-reliability clock network based on distributed dynamic management according to claim 1, characterized in that: Assuming there are three clock generation planes represented by S1x (x=0, 1, 2) and two control management planes represented by S2x (x=0, 1), the construction process is as follows: S10: Establishing a primary clock generation module to generate sub-source clock signals required inside the circuit. The primary clock generation module divides or multiplies the frequency of the chip's external input clock to generate all the frequency clocks required by various functions inside the chip. These clocks correspond to primary sub-source clock signals. S20: According to the functional division of the chip, the control signals of each function of the chip are extracted, and the dynamic planning module uses the control signals of each function as input to generate clock control signals for controlling clock generation modules at various levels.
6. The method for constructing a high-reliability clock network based on distributed dynamic management according to claim 5, characterized in that: In S10, a secondary clock generation module is established. The sub-source clock generated in step S10 is combined with the secondary subsystem control signal generated in step S20. Through the gating logic in the module, a secondary subsystem generated clock is generated for use by the secondary subsystem and modules below the secondary subsystem.
7. The method for constructing a high-reliability clock network based on distributed dynamic management according to claim 5 or 6, characterized in that: In S10, a three-level clock generation module is established. In the three-level clock generation module, the clock control signal generated in step S20 is combined with the sub-module clock enable signal generated in step S21, and the secondary subsystem generated clock generated in step S11 is gated by gating logic to generate a three-level sub-module generated clock.
8. The method for constructing a high-reliability clock network based on distributed dynamic management according to claim 5, characterized in that: In S20, a third-level sub-module is divided according to the function of the second-level subsystem, a clock enable signal of the third-level sub-module is extracted according to the functional division of the third-level sub-module, and all clocks inside the sub-module are managed through the clock enable signal of the third-level sub-module.
9. The method for constructing a high-reliability clock network based on distributed dynamic management according to claim 5 or 8, characterized in that: In the dynamic planning module, the on-chip clock is controlled by controlling the clock control signals at all levels according to different functional requirements. Not only can the generated clocks at all levels be controlled on a large scale according to different functional requirements during the chip initialization phase, but the clocks at all levels can also be dynamically managed during the chip operation process. The construction and management of the dynamically planned distributed clock network are realized by combining the clock generation plane and the control management plane.