A programmable delay circuit for anti-fuse FPGA embedded PLL_IP

Abstract

The present invention discloses a programmable delay circuit for use in an anti-fuse FPGA embedded PLL_IP, belonging to the field of anti-fuse FPGA logic design. The circuit comprises a decoding configuration circuit and two sets of programmable delay submodule circuits; the two sets of programmable delay submodule circuits have different configuration signals and are respectively designed at the reference clock input terminal and feedback clock input terminal of the anti-fuse FPGA embedded PLL_IP. By programming the decoding configuration circuit, the circuit can output a t-15 to +15 times delay. A The decoding configuration circuit includes a one-bit enable signal and a four-bit data input signal. When the antifuse FPGA is in test mode, the four-bit data input signal comes from the antifuse FPGA's internal register chain and can be configured based on the JTAG protocol. When the antifuse FPGA is in use mode, the programming input signal comes from the programmed antifuse switch, and its state is one-time programming. This invention can improve the operating flexibility of the antifuse FPGA's embedded PLL_IP and optimize the antifuse FPGA's clock network.

Description

Technical Field

[0001] The present invention relates to the technical field of anti-fuse type FPGA logic design, and in particular to a programmable delay circuit applied to an anti-fuse type FPGA embedded PLL_IP. Background Art

[0002] A Field Programmable Gate Array (FPGA) is a programmable semi-custom device characterized by flexible configuration, high speed, strong adaptability, and short development cycles. Based on their programming logic structure, FPGAs can be categorized as SRAM, antifuse, and FLASH. Antifuse FPGAs are one-time programmable FPGAs that use antifuses as their basic configurable unit. They offer non-volatility, high reliability, high security, and strong radiation resistance, leading to their dominant position in the military and aviation sectors.

[0003] The PLL (Phase Locked Loop) IP core (Intellectual Property core) is a clock management module embedded in FPGAs. FPGA designers can significantly reduce development time by invoking the PLL IP. Its typical structure includes five modules: a reference clock divider, a phase detector, a low-pass filter, a voltage-controlled oscillator, and a feedback clock divider. Users can use the programmable PLL IP to generate various clocks based on an external reference clock input.

[0004] Currently, commercial SRAM-based FPGAs have PLL_IP cores that can generate more flexible clock signals. For example, Xilinx's 7-series FPGAs can phase-shift clock signals, select PLL_IP input clocks or feedback clocks from multiple clock sources external or internal to the FPGA, and dynamically adjust PLL settings while the FPGA is operating. However, because the basic unit of antifuse-type FPGAs is an antifuse and their application scenarios are special, there is little research in China on the functional expansion of PLL_IP in antifuse-type FPGAs. It is usually necessary to call on the FPGA's internal logic resources to implement additional functions. Summary of the Invention

[0005] The object of the present invention is to provide a programmable delay circuit applied to an anti-fuse FPGA embedded PLL_IP to solve the problems in the background technology.

[0006] To solve the above technical problems, the present invention provides a programmable delay circuit for anti-fuse FPGA embedded PLL_IP, including a decoding configuration circuit and two sets of programmable delay sub-module circuits; wherein,

[0007] The two groups of programmable delay submodule circuits have the same circuit structure but different configuration signals; each group of programmable delay submodule circuits includes a first-stage programmable delay circuit and a second-stage programmable delay circuit, wherein:

[0008] The first-stage programmable delay circuit is used to adjust the signal delay with coarse precision, and is composed of a unit delay buffer A, three quadruple delay buffers B, and three multiplexers. The delay length of the unit delay buffer A is t A , the delay length of the quadruple delay buffer B is 4×t A The first-level programmable delay circuit can realize input 0, 4×t A ,8×t A , 12×t A Four different lengths of delay;

[0009] The second-stage programmable delay circuit is used to fine-tune the signal delay. It consists of four unit delay buffers A and three multiplexers. The delay length of the unit delay buffer A is t A The second-level programmable delay circuit can realize input 0, 1×t A , 2×t A , 3×t A Four different time delays;

[0010] Each group of programmable delay submodule circuits is composed of a first-stage programmable delay circuit and a second-stage programmable delay circuit in series. By programming the decoding configuration circuit, the output of a 4-bit control signal can control the output delay of the programmable delay submodule circuit to be 0 to 15 times t A Length of delay time.

[0011] In one embodiment, two sets of programmable delay submodule circuits are respectively designed at the reference clock input and feedback clock input of the anti-fuse FPGA embedded PLL_IP. By programming the decoding configuration circuit, the output of -15 to +15 times of t A The "-" and "+" are used to distinguish the position relationship of the reference clock signal with respect to the feedback clock signal. "+" is used to configure the reference clock input delay so that the reference clock signal leads the feedback clock signal; "-" is used to configure the feedback clock input delay so that the reference clock signal lags the feedback clock signal.

[0012] In one embodiment, the decoding configuration circuit includes a one-bit enable signal and a four-bit data input signal. When the anti-fuse FPGA is in test mode, the four-bit data input signal comes from the internal register chain of the anti-fuse FPGA, and its input signal state can be configured based on the JTAG protocol; when the anti-fuse FPGA is used in use mode, the four-bit data input signal comes from the programmed anti-fuse switch state, and its state is one-time burn.

[0013] In one embodiment, in the use mode, the embedded PLL_IP is called through the anti-fuse FPGA dedicated programmer. In the programmer interface, the configuration process of the programmable delay circuit applied to the anti-fuse FPGA embedded PLL_IP is as follows:

[0014] Determine the usage scenarios of the antifuse FPGA embedded PLL IP;

[0015] The programmer selects the programmable delay submodule circuit information;

[0016] Select the delay "±" state;

[0017] Select the delay length;

[0018] The programmer programs the anti-fuse FPGA;

[0019] Power on and use.

[0020] In one embodiment, in the usage mode, the configuration process of the programmable delay circuit applied to the anti-fuse FPGA embedded PLL_IP is as follows:

[0021] Based on the application scenario of the antifuse FPGA, the user determines whether to use the embedded PLL_IP. If the embedded PLL_IP is used, the user determines how to use it. Based on the programming software, the user obtains clock network information and the internal layout and routing information of the antifuse FPGA. The user then determines whether to use the programmable delay circuit for the antifuse FPGA embedded PLL_IP. If so, the user determines the delay time and delay method to be configured.

[0022] In the IP calling interface of the programmer, select PLL_IP; in the PLL_IP interface, select to use programmable delay and select the "±" state, that is, select to configure the programmable delay submodule circuit of the reference clock input end of the anti-fuse FPGA embedded PLL_IP or the programmable delay submodule circuit of the feedback clock input end of the embedded PLL_IP; select the delay time of the programmable delay submodule circuit, and select the discrete configuration mode to select the adjustable delay time accuracy as t A , adjustable range is 0~15×t A Delay time;

[0023] The configuration information of the programmable delay circuit used in the PLL_IP embedded in the anti-fuse FPGA is sent to the chip in the form of a data stream through the programming host computer. The internal circuit of the anti-fuse FPGA addresses the corresponding antifuse based on the data stream and performs programming to complete the configuration.

[0024] After programming is complete and power is applied, the input signal of the decoding configuration circuit is determined by the programming state of the corresponding antifuse. The delay state of the programmable delay circuit applied to the antifuse-type FPGA embedded PLL_IP is successfully configured and can be used by the user.

[0025] In one embodiment, in test mode, the configuration process of the programmable delay circuit applied to the anti-fuse FPGA embedded PLL_IP is as follows:

[0026] Determine the test items for antifuse FPGA;

[0027] Determine how the programmable delay submodule circuit is configured;

[0028] Send test data to antifuse FPGA;

[0029] Configure programmable delay submodule circuit;

[0030] The delay state of the programmable delay circuit applied to the anti-fuse FPGA embedded PLL_IP is successfully configured;

[0031] Test feedback and test again and again.

[0032] In one embodiment, in test mode, the configuration process of the programmable delay circuit applied to the anti-fuse FPGA embedded PLL_IP is as follows:

[0033] Determine the test method and content based on the antifuse FPGA's test items, including layout and routing, IP testing, and port testing. Based on the determined test method and test content, choose whether to use the programmable delay circuit applied to the antifuse FPGA's embedded PLL_IP. If so, determine the delay time configuration method for the programmable delay submodule circuit.

[0034] Based on the JTAG protocol, the test platform sends command and data streams to the anti-fuse FPGA under test, accessing the internal register chain of the anti-fuse FPGA under test. The internal register chain latches the data as the input signal of the decoding configuration circuit, configuring the delay state of the programmable delay submodule circuit.

[0035] After the test instructions and test data are sent, the delay state of the programmable delay circuit of the PLL_IP embedded in the anti-fuse FPGA is configured; the test feedback results are compared with the expected results, and repeated tests are performed based on the comparison results and the test item content.

[0036] In one embodiment, the configuration method of the programmable delay circuit applied to the PLL_IP embedded in the anti-fuse type FPGA is determined by the internal clock network layout and routing delay of the anti-fuse type FPGA and the frequency of the input clock and feedback clock of the PLL_IP embedded in the anti-fuse type FPGA; the output delay of the programmable delay circuit applied to the PLL_IP embedded in the anti-fuse type FPGA is a static delay, that is, after programming, the delay state is fixed during use.

[0037] In one embodiment, the input clock signal of the PLL_IP embedded in the anti-fuse FPGA, that is, the input signal corresponding to the first group of programmable delay sub-module circuits, comes from an external clock, and the output clock of the previous level PLL_IP comes from the input clock CLKxP of the differential I / O;

[0038] The feedback clock signal of the PLL_IP embedded in the anti-fuse FPGA, that is, the input signal source of the second group of programmable delay sub-module circuits is the output clock of PLL_IP, the clock from the clock network after wiring, and the input clock CLKxN from the differential I / O.

[0039] In one embodiment, the power signal of the programmable delay circuit applied to the anti-fuse FPGA embedded PLL_IP is the anti-fuse FPGA core power signal, and the ground signal is the ground signal of the anti-fuse FPGA embedded PLL_IP, and the power-on state is consistent therewith.

[0040] The present invention provides a programmable delay circuit for use in an anti-fuse FPGA embedded PLL_IP, which has the following beneficial effects:

[0041] (1) Ability to achieve coarse and fine precision delay adjustment of the relative delay between the input reference clock and the feedback clock of the PLL_IP embedded in the anti-fuse FPGA;

[0042] (2) When used together with PLL_IP, it will not occupy the internal resources of the chip;

[0043] (3) It can generate a coarse or fine precision delay of the feedback clock of the PLL_IP relative to the input reference clock, adapting to the different working states of the anti-fuse FPGA under high-frequency clock and low-frequency clock, and can improve the clock locking speed of the PLL_IP, especially for specific application scenarios, which can effectively improve the system performance;

[0044] (4) It can generate discrete delays to compensate for the distributed delay of the clock signal in the clock network, effectively reducing the impact of the delay caused by the load on the performance of the anti-fuse FPGA. This will be more obvious in large-scale systems.

[0045] (5) It has flexible programming and simple structure, which is suitable for the needs of different users. It does not require the design of a large number of delay lines and can reduce a certain chip design area. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 The diagram is a schematic diagram of the principle of a programmable delay circuit applied to an anti-fuse FPGA embedded PLL_IP provided by the present invention.

[0047] Figure 2 Schematic diagram of the structure of the programmable delay sub-module circuit.

[0048] Figure 3 This diagram shows the relationship between the delay time of the programmable delay circuit used in the anti-fuse FPGA embedded PLL_IP and the input and output signals of the decoding configuration circuit.

[0049] Figure 4 This is the user mode programming flowchart for the programmable delay circuit embedded in the PLL_IP of an anti-fuse FPGA.

[0050] Figure 5 The following is a test flow chart for the programmable delay circuit in test mode applied to the PLL_IP embedded in the anti-fuse FPGA. DETAILED DESCRIPTION

[0051] The following, combined with the accompanying drawings and specific embodiments, further details a programmable delay circuit for an antifuse FPGA embedded PLL_IP, as proposed by the present invention. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clarify the purpose of illustrating the embodiments of the present invention.

[0052] like Figure 1 As shown, the present invention provides a programmable delay circuit for use in an anti-fuse FPGA embedded PLL_IP. The structure includes a decoding configuration circuit and two sets of programmable delay sub-module circuits. The two sets of programmable delay sub-module circuits have different configuration signals and are respectively designed at the reference clock input terminal and feedback clock input terminal of the anti-fuse FPGA embedded PLL_IP. By programming the decoding configuration circuit, it can output -15 to +15 times the t A The length of the delay time, where t A is the delay length of the unit delay buffer; "-" and "+" are used to distinguish the position relationship of the reference clock signal relative to the feedback clock signal. "+" is used to configure the reference clock input delay size so that the reference clock signal leads the feedback clock signal; "-" is used to configure the feedback clock input delay size so that the reference clock signal lags the feedback clock signal.

[0053] The structures of the two groups of programmable delay submodule circuits are consistent, including a first-level programmable delay circuit and a second-level programmable delay circuit, respectively. Figure 2 As shown, the first-stage programmable delay circuit is used to coarsely adjust the signal delay, and consists of a unit delay buffer A (i.e., buffer A: XI1), three quadruple delay buffers B (i.e., buffer B: XI2, XI3, XI4) and three multiplexers (i.e., XM1, XM2 and XM3). The delay length of the unit delay buffer A is t A , the delay length of the quadruple delay buffer B is 4×t A The first-level programmable delay circuit can realize input 0, 4×t A ,8×t A , 12×t A Four different lengths of delay; the second-stage programmable delay circuit is used to fine-tune the signal delay, and consists of four unit delay buffers A (i.e., XI5, XI6, XI7, XI8) and three multiplexers (i.e., XM4, XM5, and XM6). The delay length of the unit delay buffer A is t A The second-level programmable delay circuit can realize input 0, 1×t A , 2×t A , 3×t A Four different time delays. Each set of programmable delay submodule circuits consists of a first-stage programmable delay circuit and a second-stage programmable delay circuit connected in series. By programming the decoding configuration circuit, the output of a 4-bit control signal can control the programmable delay submodule circuit to output a delay of 0 to 15 times t A Length of delay time.

[0054] The relationship between the output signal of the decoding configuration circuit and the delay result of the programmable delay circuit applied to the PLL_IP embedded in the anti-fuse FPGA is shown in Table 1. Among them, the EN signal of the decoding configuration circuit is used to configure the feedback clock of the anti-fuse PLL_IP to lag or advance relative to the input reference clock. When EN=1'b0, the feedback clock of the anti-fuse PLL_IP lags relative to the input reference clock; when EN=1'b0, the feedback clock of the anti-fuse PLL_IP advances relative to the input reference clock.

[0055] like Figure 3 As shown, the decoding configuration circuit includes a one-bit enable signal and a four-bit data input signal. The input signal source of the decoding configuration module mainly comes from: 1. JTAG-based test data in test mode, 2. Anti-fuse state after the anti-fuse is programmed based on the programmer configuration signal in use mode; the configuration information relationship is shown in Table 1 below:

[0056]

[0057]

[0058] Table 1 Relationship between delay time and input and output signals of decoding configuration circuit

[0059] like Figure 4 As shown, the configuration process in user mode of a programmable delay circuit embedded in an anti-fuse FPGA PLL_IP of the present invention is as follows:

[0060] Based on the antifuse FPGA application scenario, the user should determine whether to use the embedded PLL_IP. If so, determine how to use it. Based on the programming software, the user should obtain clock network information and the antifuse FPGA's internal layout and routing information to determine whether to use configurable delays. If so, the user should determine the delay time and delay method to be configured.

[0061] In the IP calling interface of the programmer, select PLL_IP; in the PLL_IP interface, select to use the programmable delay circuit applied to the anti-fuse FPGA embedded PLL_IP to delay the output state. Specifically, select the "±" state, that is, to configure the programmable delay submodule circuit at the reference clock input end of the anti-fuse FPGA embedded PLL_IP, or the programmable delay submodule circuit at the feedback clock input end of the embedded PLL_IP; select the delay length of the programmable delay submodule circuit. The configuration mode is discrete. Select the adjustable delay time accuracy as t A , adjustable range is 0~15×t A delay time.

[0062] The internal circuitry of an antifuse-based FPGA addresses the corresponding antifuse based on the data bit stream and programs it to complete configuration. After programming, the power is turned on. The input signal to the decoder configuration circuit is determined by the programmed state of the corresponding antifuse, successfully configuring the delay state of the programmable delay submodule circuit. After the user powers on the chip, they input a clock signal.

[0063] In normal use of the anti-fuse FPGA, the PLL_IP locks the clock normally.

[0064] like Figure 5 As shown, the present invention is a configuration process in test mode for a programmable delay circuit embedded with a PLL_IP in an anti-fuse FPGA, specifically:

[0065] Determine the test method and test content based on the anti-fuse FPGA's test items, including layout and routing, IP testing, and port testing. Based on the determined test method and test content, choose whether to use the programmable delay circuit applied to the anti-fuse FPGA's embedded PLL_IP. If used, determine the delay time configuration method of the programmable delay sub-module circuit.

[0066] Based on the JTAG protocol, through a test platform such as the ADVANTEST 93K test platform or a built-in test board, instructions and data code streams are sent to the anti-fuse FPGA to be tested, and the internal register chain of the anti-fuse FPGA to be tested is accessed; the internal register chain latches the data as the input signal of the decoding configuration circuit, and configures the delay state of the programmable delay sub-module circuit; specifically, based on the configuration code stream, the delay "±" state is programmed, that is, the programmable delay sub-module circuit at the reference clock input end of the PLL_IP embedded in the anti-fuse FPGA, or the programmable delay sub-module circuit at the feedback clock input end of the embedded PLL_IP is selected and configured; the delay length of the programmable delay sub-module circuit is programmed, and the configuration method is discrete selection with an adjustable delay time accuracy of t A , adjustable range is 0~15×t A delay time.

[0067] After the test instructions and test data are sent, the delay state of the programmable delay circuit of the PLL_IP embedded in the anti-fuse FPGA is configured; the test feedback results are compared with the expected results, and repeated tests are performed based on the comparison results and the test item content.

[0068] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A programmable delay circuit for an anti-fuse FPGA embedded PLL_IP, characterized in that: It includes a decoding configuration circuit and two sets of programmable delay submodule circuits; wherein, The two groups of programmable delay submodule circuits have the same circuit structure but different configuration signals; each group of programmable delay submodule circuits includes a first-stage programmable delay circuit and a second-stage programmable delay circuit, wherein: The first-stage programmable delay circuit is used to adjust the signal delay with coarse precision, and is composed of a unit delay buffer A, three quadruple delay buffers B, and three multiplexers. The delay length of the unit delay buffer A is t A , the delay length of the quadruple delay buffer B is 4×t A The first-level programmable delay circuit can realize input 0, 4×t A ,8×t A , 12×t A Four different lengths of delay; The second-stage programmable delay circuit is used to fine-tune the signal delay. It consists of four unit delay buffers A and three multiplexers. The delay length of the unit delay buffer A is t A The second-level programmable delay circuit can realize input 0, 1×t A , 2×t A , 3×t A Four different time delays; Each group of programmable delay submodule circuits is composed of a first-stage programmable delay circuit and a second-stage programmable delay circuit in series. By programming the decoding configuration circuit, the output of a 4-bit control signal can control the output delay of the programmable delay submodule circuit to be 0 to 15 times t A Length of delay time.

2. The programmable delay circuit for anti-fuse FPGA embedded PLL_IP according to claim 1, wherein: Two sets of programmable delay submodule circuits are designed at the reference clock input and feedback clock input of the anti-fuse FPGA embedded PLL_IP respectively. By programming the decoding configuration circuit, it can output -15 to +15 times of t A The "-" and "+" are used to distinguish the position relationship of the reference clock signal with respect to the feedback clock signal. "+" is used to configure the reference clock input delay so that the reference clock signal leads the feedback clock signal; "-" is used to configure the feedback clock input delay so that the reference clock signal lags the feedback clock signal.

3. The programmable delay circuit for anti-fuse FPGA embedded PLL_IP according to claim 2, wherein: The decoding configuration circuit includes a one-bit enable signal and a four-bit data input signal. When the anti-fuse FPGA is in test mode, the four-bit data input signal comes from the internal register chain of the anti-fuse FPGA, and its input signal state can be configured based on the JTAG protocol; when the anti-fuse FPGA is used in use mode, the four-bit data input signal comes from the programmed anti-fuse switch state, and its state is one-time burning.

4. The programmable delay circuit for anti-fuse FPGA embedded PLL_IP according to claim 3, wherein: In use mode, use the anti-fuse FPGA dedicated programmer to call the embedded PLL_IP. In the programmer interface, the configuration process for the programmable delay circuit applied to the anti-fuse FPGA embedded PLL_IP is as follows: Determine the usage scenarios of the antifuse FPGA embedded PLL IP; The programmer selects the programmable delay submodule circuit information; Select the delay "±" state; Select the delay length; The programmer programs the anti-fuse FPGA; Power on and use.

5. The programmable delay circuit for anti-fuse FPGA embedded PLL_IP according to claim 4, characterized in that: In use mode, the configuration process for the programmable delay circuit used in the anti-fuse FPGA embedded PLL_IP is as follows: Based on the application scenario of the antifuse FPGA, the user determines whether to use the embedded PLL_IP. If the embedded PLL_IP is used, the user determines how to use it. Based on the programming software, the user obtains clock network information and the internal layout and routing information of the antifuse FPGA. The user then determines whether to use the programmable delay circuit for the antifuse FPGA embedded PLL_IP. If so, the user determines the delay time and delay method to be configured. In the IP calling interface of the programmer, select PLL_IP; in the PLL_IP interface, select to use programmable delay and select the "±" state, that is, select to configure the programmable delay submodule circuit at the reference clock input end of the anti-fuse FPGA embedded PLL_IP or the programmable delay submodule circuit at the feedback clock input end of the embedded PLL_IP; select the delay length of the programmable delay submodule circuit, and select the discrete configuration mode with an adjustable delay time accuracy of t A , adjustable range is 0~15×t A Delay time; The configuration information of the programmable delay circuit used in the PLL_IP embedded in the anti-fuse FPGA is sent to the chip in the form of a data stream through the programming host computer. The internal circuit of the anti-fuse FPGA addresses the corresponding antifuse based on the data stream and performs programming to complete the configuration. After programming is complete and power is applied, the input signal of the decoding configuration circuit is determined by the programming state of the corresponding antifuse. The delay state of the programmable delay circuit applied to the antifuse-type FPGA embedded PLL_IP is successfully configured and can be used by the user.

6. The programmable delay circuit for anti-fuse FPGA embedded PLL_IP according to claim 5, characterized in that: In test mode, the configuration process for the programmable delay circuit used in the antifuse FPGA embedded PLL_IP is as follows: Determine the test items for antifuse FPGA; Determine how the programmable delay submodule circuit is configured; Send test data to antifuse FPGA; Configure programmable delay submodule circuit; The delay state of the programmable delay circuit applied to the anti-fuse FPGA embedded PLL_IP is successfully configured; Test feedback and test again and again.

7. The programmable delay circuit for anti-fuse FPGA embedded PLL_IP according to claim 6, wherein: In test mode, the configuration process for the programmable delay circuit used in the antifuse FPGA embedded PLL_IP is as follows: Determine the test method and content based on the antifuse FPGA's test items, including layout and routing, IP testing, and port testing. Based on the determined test method and test content, choose whether to use the programmable delay circuit applied to the antifuse FPGA's embedded PLL_IP. If so, determine the delay time configuration method for the programmable delay submodule circuit. Based on the JTAG protocol, the test platform sends command and data streams to the anti-fuse FPGA under test, accessing the internal register chain of the anti-fuse FPGA under test. The internal register chain latches the data as the input signal of the decoding configuration circuit, configuring the delay state of the programmable delay submodule circuit. After the test instructions and test data are sent, the delay state of the programmable delay circuit of the PLL_IP embedded in the anti-fuse FPGA is configured; the test feedback results are compared with the expected results, and repeated tests are performed based on the comparison results and the test item content.

8. The programmable delay circuit for anti-fuse FPGA embedded PLL_IP according to claim 7, wherein: The configuration method of the programmable delay circuit applied to the PLL_IP embedded in the anti-fuse type FPGA is determined by the internal clock network layout and routing delay of the anti-fuse type FPGA and the frequency of the input clock and feedback clock of the PLL_IP embedded in the anti-fuse type FPGA; the output delay of the programmable delay circuit applied to the PLL_IP embedded in the anti-fuse type FPGA is a static delay, that is, after programming, the delay state is fixed during use.

9. The programmable delay circuit for anti-fuse FPGA embedded PLL_IP according to claim 8, characterized in that: The input clock signal of the PLL_IP embedded in the anti-fuse FPGA, that is, the input signal of the first group of programmable delay sub-module circuits, comes from the external clock, and the output clock of the previous level PLL_IP comes from the input clock CLKxP of the differential I / O; The feedback clock signal of the PLL_IP embedded in the anti-fuse FPGA, that is, the input signal source of the second group of programmable delay sub-module circuits is the output clock of PLL_IP, the clock from the clock network after wiring, and the input clock CLKxN from the differential I / O.

10. The programmable delay circuit for anti-fuse FPGA embedded PLL_IP according to claim 9, characterized in that: The power signal of the programmable delay circuit applied to the anti-fuse FPGA embedded PLL_IP is the anti-fuse FPGA core power signal, and the ground signal is the ground signal of the anti-fuse FPGA embedded PLL_IP, and the power-on state is consistent with it.

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