A clock tree generation method, medium and electronic device

Abstract

The application belongs to the technical field of integrated circuits, and provides a clock tree generation method, a medium and an electronic device. The method comprises the following steps: obtaining a netlist file of a circuit; identifying a clock network according to a network identifier in the netlist file. Then, the type of a device is identified according to the identification information of the device in the netlist file, and the pin information of the device is determined. The clock link is determined according to the connection relationship of the device in the netlist file. Furthermore, the flow direction of the clock signal can be determined according to the clock link and the pin information of the device. Therefore, the electronic device can automatically draw a clock tree, and the circuit development efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a clock tree generation method, a medium and an electronic device. BACKGROUND

[0002] The circuit system of an electronic device usually includes a clock circuit that generates a clock signal, which can also be referred to as a clock network. The clock network outputs the clock signal to each clock demand device that needs the clock signal, so that the clock demand device can work in order according to the clock signal. In order to facilitate the analysis of the flow direction of the clock signal in the circuit system, the developer usually needs to draw a corresponding clock tree, and the architecture diagram of the clock tree includes information such as a clock source, a clock signal flow direction, and a clock signal frequency.

[0003] However, the scale of the circuit system is getting larger and larger, which leads to the increasing complexity of the design of the clock circuit. Moreover, the application scenario of the circuit system can change, which leads to changes in the clock demand of the circuit system, such as the need to add a clock source, modify a clock frequency, and the like, so that the clock tree architecture diagram also needs to be frequently modified. Due to the lack of an automatic way, the developer needs to spend a lot of time for drawing the clock tree architecture diagram, which reduces the development efficiency of the circuit system. SUMMARY

[0004] The present application provides a clock tree generation method, a medium and an electronic device, which can identify the types of each device and the flow direction of the clock signal according to a netlist file and the like, and then automatically draw a clock tree.

[0005] In a first aspect, a clock tree generation method is provided, applied to an electronic device, and the method includes: obtaining a network identifier of at least one network in a circuit system, and identification information of a device in the at least one network and a connection state between devices; determining a clock network in the at least one network according to the network identifier of the at least one network, the clock network being used to output at least one clock signal; determining the identification information of at least one device in the clock network and the connection relationship between the at least one device and other devices in the circuit system; determining the type of the at least one device according to the identification information of the at least one device; determining the flow direction of the at least one clock signal in the circuit system according to the connection relationship of the at least one device; and generating a corresponding clock tree of the circuit system according to the type of the at least one device and the flow direction of the at least one clock signal.

[0006] In the above scheme, the network identifier of the acquired circuit system, the identifier information of the devices, and the connection state between the devices can be acquired from a netlist file of the circuit system. By identifying the network identifiers of the multiple networks, the clock network can be identified. Then, according to the identifier information of the devices in the circuit system, the clock source device, the clock conversion device, and the clock demand device connected to the clock network in the clock network can be identified. Moreover, according to the pin connection relationship of the devices in the netlist file, the flow direction of the clock signal can be determined. Finally, according to the flow direction of each device and the clock signal, the clock tree can be drawn. In this way, the developer does not need to spend a lot of time to draw the clock tree, and the method can automatically draw the clock tree, thereby improving the development efficiency of the circuit system.

[0007] In combination with the first aspect, in some implementations, the method further includes: determining, according to the identifier information of the at least one device, a clock source device in the at least one device of the clock network, the clock source device being configured to generate a clock signal.

[0008] In the above scheme, the electronic device can identify the clock source device according to the identifier information such as the code, the bit number, and the keyword of the device. For example, the device name including “XTAL”, such as “XTAL10”, can be considered as a crystal oscillator. In this way, the electronic device can identify the type of the device in the circuit system, and the method can automatically draw the clock tree, thereby improving the development efficiency of the circuit system.

[0009] In combination with the first aspect, in some implementations, the method further includes: acquiring, according to the identifier information of the devices and the connection state between the devices in the at least one network of the circuit system, the identifier information of the devices connected to the clock network; and determining, according to the identifier information of the devices connected to the clock network, a clock demand device, the clock demand device being a device consuming the clock signal.

[0010] In the above scheme, if a device is connected to the clock source device and the device is not a small device or a small device that can be penetrated, the device can be considered as a device requiring the clock signal, i.e., the clock demand device. In this way, the electronic device can identify the type of the device in the circuit system, and the method can automatically draw the clock tree, thereby improving the development efficiency of the circuit system.

[0011] In combination with the first aspect, in some implementations, the method further includes: determining, according to the identifier information of the at least one device, a clock conversion device in the at least one device of the clock network, the clock conversion device being configured to change a parameter value of the clock signal.

[0012] In the above scheme, the electronic device can identify the clock conversion device according to the identification information such as the code, the bit number, and the keyword of the device. For example, if the device name includes "MUX", it can be considered that the device is a multiplexer. In this way, the electronic device can identify the type of the device in the circuit system, and the method can automatically draw the clock tree, without the developer spending a lot of time drawing the clock tree, thereby improving the development efficiency of the circuit system.

[0013] In combination with the first aspect, in some implementations, the method further includes: generating a clock tree corresponding to the circuit system according to the clock source device, the clock conversion device, the clock demand device, and the flow direction of the at least one clock signal, the clock tree including the parameter value of the at least one clock signal at the pin of the clock source device, the clock conversion device, and the clock demand device.

[0014] In the above scheme, the electronic device can obtain the specifications of each clock device according to the type of the identified clock device, and then calculate the parameter size of the clock signal at each pin and mark the parameters of the clock signal in the clock tree. The method can automatically draw the clock tree, without the developer spending a lot of time drawing the clock tree, thereby improving the development efficiency of the circuit system.

[0015] In combination with the first aspect, in some implementations, the method further includes: obtaining device identification configuration data, the device identification configuration data including a correspondence between the identification information and the type of at least one device; and determining the type of the at least one device according to the device identification configuration data and the identification information of the at least one device.

[0016] In the above scheme, the electronic device can identify the type of the device according to the device identification configuration data. The device identification configuration data can be pre-set by the user or obtained by the electronic device 100 from a device identification database including a large number of correspondences between device identification and device type. In this way, the electronic device can identify the type of the device in the circuit system, and the method can automatically draw the clock tree, without the developer spending a lot of time drawing the clock tree, thereby improving the development efficiency of the circuit system.

[0017] In combination with the first aspect, in some implementations, the device identification configuration data is from a device identification database connected to the electronic device.

[0018] In combination with the first aspect, in some implementations, the method further includes: obtaining network identification configuration data, the network identification configuration data including a correspondence between at least one network identification and a network type; and determining a clock network in the at least one network according to the network identification configuration data and the network identification of the at least one network.

[0019] In the above scheme, the electronic device identifies the type of the network, which can be identified according to network identification configuration data. The network identification configuration data can be preset by the user in advance, or obtained by the electronic device 100 from a network identification database, which includes a large number of network identification and network type correspondence. In this way, the electronic device can identify the network type in the circuit system, and the method can automatically draw the clock tree, without the developer spending a lot of time drawing the clock tree, thereby improving the development efficiency of the circuit system.

[0020] In combination with the first aspect, in some implementations, the network identification configuration data is from a network identification database connected to the electronic device.

[0021] In combination with the first aspect, in some implementations, the method further includes: determining a netlist file for describing the circuit system; and parsing the netlist file to obtain the network identification of at least one network in the circuit system, the identification information of devices in the at least one network, and the connection state between the devices.

[0022] In the above scheme, the electronic device can obtain the netlist file of the circuit system, and draw the clock tree according to the type of the device in the netlist file and the flow direction of the clock signal. In this way, the method can automatically draw the clock tree without the developer spending a lot of time drawing the clock tree, thereby improving the development efficiency of the circuit system.

[0023] In combination with the first aspect, in some implementations, the identification information of the at least one device includes one or more of the code, the bit number, and the keyword of the at least one device.

[0024] In combination with the first aspect, in some implementations, the circuit system further includes one or more of a power network and a bus network; the clock source device includes one or more of a crystal oscillator, a clock oscillator, a resonant tank circuit, a resistor-capacitor oscillator, a silicon oscillator, and an atomic clock; the clock conversion device includes one or more of a frequency synthesizer, a frequency divider, a phase-locked loop, a direct digital frequency synthesizer, and a clock driver; and the parameter value of the clock signal includes one or more of a frequency, a signal strength, and a phase.

[0025] Secondly, the present application provides an electronic device, which includes a processor and a memory. The memory is configured to store instructions, and the processor is configured to execute the instructions. When the processor executes the instructions, the method described in the first aspect is performed.

[0026] Thirdly, the present application provides a computer-readable storage medium, which stores instructions. When the instructions are executed on a computing device, the method described in the first aspect is performed.

[0027] In a fourth aspect, the present application provides a computer program product, characterized by comprising computer instructions, when executed by a computing device, the computing device executes the method as described in the first aspect.

[0028] To sum up, by the clock tree generation method, medium and electronic device provided by the present application, the electronic device can identify the types of each device and the flow direction of the clock signal according to the netlist file and the like, and then automatically draw the clock tree. The developer can view or adjust the clock architecture of the circuit system according to the clock tree. And the developer does not need to spend a lot of time drawing the clock tree, which improves the development efficiency of the circuit system. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiment description will be briefly introduced as follows.

[0030] Figure 1 is a clock tree structure schematic diagram provided by an embodiment of the present application;

[0031] Figure 2 is a flowchart of a clock tree generation method provided by an embodiment of the present application;

[0032] Figure 3 is a structure schematic diagram of a clock tree generation system provided by an embodiment of the present application;

[0033] Figure 4 is a flowchart of a clock tree generation method provided by an embodiment of the present application, which includes a network identification database and a device identification database in a database;

[0034] Figure 5 is an interface schematic diagram of obtaining a netlist file provided by an embodiment of the present application;

[0035] Figure 6 is a circuit structure schematic diagram of a circuit system provided by an embodiment of the present application;

[0036] Figure 7 is a netlist file schematic diagram of a circuit system provided by an embodiment of the present application;

[0037] Figure 8 is an interface data of modifying network identification configuration data provided by an embodiment of the present application;

[0038] Figure 9 is a flowchart of a clock device identification method provided by an embodiment of the present application;

[0039] Figure 10 is an interface schematic diagram of device pin information provided by an embodiment of the present application;

[0040] Figure 11 is an interface schematic diagram of clock link information provided by an embodiment of the present application;

[0041] Figure 12 is an interface schematic diagram of clock link information provided by an embodiment of the present application;

[0042] Figure 13 is an interface schematic diagram of clock link information provided by an embodiment of the present application;

[0043] Figure 14 is an interface schematic diagram of clock tree provided by an embodiment of the present application;

[0044] Figure 15 is a flow schematic diagram of a clock tree generation method provided by an embodiment of the present application, including a device identification database in a database;

[0045] Figure 16 is a flow schematic diagram of a clock tree generation method provided by an embodiment of the present application, including a network identification database in a database;

[0046] Figure 17 is a flow schematic diagram of a clock tree generation method provided by an embodiment of the present application, not including a database;

[0047] Figure 18 is a structure schematic diagram of a clock tree generation device provided by an embodiment of the present application;

[0048] Figure 19 is a structure schematic diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0049] The illustrative embodiments of the present application include, but are not limited to, a clock tree generation method, a medium and an electronic device.

[0050] Circuit system is composed of multiple circuit networks, such as power supply network, clock network, bus network, etc. Clock network usually connects clock demanding devices, and the clock network generates and processes clock signals, and then outputs the processed clock signals to the clock demanding devices.

[0051] The devices in the clock network can be specifically divided into clock source devices and clock conversion devices. Moreover, the clock network can include one or more clock source devices and clock conversion devices, that is, one or more clock signals can be included in the same circuit system.

[0052] Clock source devices are used to generate clock signals, such as crystal oscillators (crystals), clocks, resonant tank circuits, resistance-capacitance oscillators (RC oscillators), silicon oscillators, atomic clocks, and the like. Crystals can also be specifically divided into voltage-controlled crystals, oven-controlled crystals, and vehicle-mounted crystals, and the like. Atomic clocks can also be specifically divided into cesium atomic clocks, hydrogen atomic clocks, and rubidium atomic clocks, and the like. Clock source devices can exist independently in a circuit system, or can be integrated with other devices. For example, clock sources are included in clock-demanding devices such as field-programmable gate arrays (FPGAs) and clock management units (CMUs). Clock-demanding devices that integrate these clock sources can use the clock signals generated by these clock sources, and these clock signals can also be used by other clock-demanding devices.

[0053] Clock conversion devices are used to process clock signals, such as changing the frequency, phase, voltage, and the like of the clock signals. Clock conversion devices can include frequency synthesizers, frequency dividers, phase-locked loops (PLLs), direct digital synthesizers (DDSs), clock drivers, and the like.

[0054] Clock-demanding devices are logic devices that require clock signals, such as FPGAs, central processing units (CPUs), application specific integrated circuits (ASICs), digital signal processing (DSP) chips, and the like.

[0055] Exemplarily, Figure 1 A structural diagram of a clock tree is shown. As Figure 1 shown, the clock tree includes external input frequency A and input frequency B. The range of input frequency A is 0-1000 kilohertz (KHz), and 32768 Hz is taken as an example here. The range of input frequency B is 4-64 megahertz (MHz), and 8 MHz is taken as an example here. The clock sources included in the clock tree are: low speed external clock (LSE), low speed internal clock (LSI), high speed internal clock (HSI), and high speed external clock (HSE). Among them, the RC oscillator is used for LSI and HSI. Figure 1For example, the output of the LSI is 100 KHz, the output of the HSI is 8 KHz, and the LSE and the HSE use the external input frequency A and / or the input frequency B.

[0056] The signal output by the HSE is divided by 32 to obtain HSE_RTC, and the signals of the HSE_RTC, the LSE and the LSI are input into a multiplexer MUX1 to obtain a clock signal to RTC input into a run time clock (RTC), where the to RTC is 100 KHz. The signal output by the LSI can also be directly used as a clock signal to IWDG of an independent watchdog (IWDG), where the to IWDG is 100 KHz. The signal output by the HSI can also be output to a flash programming interface (FLI), where the to FLI is 100 KHz. The HSE is divided by one and input into a multiplexer MUX2, and then output to a PLL. The output of the PLL and the to IWDG and the to FLI are input into a multiplexer MUX3 to obtain a clock signal of a high performance bus clock (HCLK), a clock signal of a processor Cortex (CorCLK) and a free running clock (FCLK), where the HCLK, the CorCLK and the FCLK are 48 KHz.

[0057] As can be seen from the above, in order to facilitate the analysis of the clock design of the current circuit system, the developer can analyze the flow direction, frequency, voltage size and phase noise of each clock signal in the circuit system by using the clock tree. However, the clock tree needs to be drawn by the developer according to the circuit diagram, and when the clock requirement of the circuit system changes, the developer also needs to modify the clock tree. Therefore, the developer spends a lot of time on drawing the clock tree architecture diagram, which reduces the development efficiency of the circuit system.

[0058] In order to solve the problem that the manual drawing of the clock tree consumes a lot of time, the application provides a clock tree generation method applied to an electronic device 100. The electronic device 100 first acquires network identifiers of a plurality of networks in a circuit system and pin connection states of devices in the plurality of networks. For example, the electronic device 100 can acquire a netlist file of the circuit system, and the netlist file includes network identifiers of each network and pin connection relationships of each device.

[0059] The electronic device 100 identifies the network identification of the plurality of networks, and then identifies the clock network. According to the identification information of the devices in the circuit system, the clock source device, the clock conversion device and the clock demand device connected to the clock network in the clock network can be identified. According to the pin connection relationship of the devices in the netlist file, the flow direction of the clock signal in the clock source device, the clock conversion device and the clock demand device can be determined. Finally, the clock tree can be drawn according to the flow direction of the clock signal in the clock source device, the clock conversion device and the clock demand device.

[0060] Optionally, the electronic device 100 can also obtain device identification configuration data, and then the electronic device 100 can determine the type of each device according to the device identification configuration data. The device identification configuration includes the correspondence between the identification information of a plurality of devices and the type of the devices, for example, the device whose identification information contains the keyword "XTAL" is a crystal oscillator, and the device whose identification information contains the keyword "MUX" is a multiplexer.

[0061] Optionally, the electronic device 100 can also obtain network identification configuration data, and then the electronic device 100 can determine the type of each network according to the network identification configuration data. The network identification configuration data includes the correspondence between the identification of a plurality of networks and the type of the networks, for example, the network whose identification includes the keywords "clk" and "XTAL" is a clock network.

[0062] In this way, by using the clock tree generation method provided in the present application, the electronic device can identify the type of each device and the flow direction of the clock signal according to the netlist file, and then automatically draw the clock tree. The developer does not need to spend a lot of time to draw the clock tree, and the development efficiency of the circuit system is improved.

[0063] The electronic device 100 can be a terminal device such as a mobile phone, a tablet computer, a wearable device, a vehicle-mounted device, an augmented reality (AR) / virtual reality (VR) device, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, a personal digital assistant (PDA), or a dedicated camera (for example, a single-lens reflex camera, a card-type camera), and the like. The electronic device 100 can also be a physical server or a cloud device such as an X86 server, an ARM server, and the like, or a virtual machine (VM) implemented based on a general-purpose physical server in combination with a network function virtualization (NFV) technology. The VM refers to a complete computer system having a complete hardware system function, which is simulated by software, runs in a completely isolated environment, and is complete. The specific type of the electronic device 100 is not limited in the present application.

[0064] The clock tree generation method provided in the present application will be described in detail below. The clock tree generation method can be applied to the electronic device 100 described above, as shown in the following figure, and can include the following steps: Figure 2

[0065] S210: Obtain the network identifiers of a plurality of networks in the circuit system, the identification information of the devices, and the connection relationship.

[0066] The electronic device 100 can obtain the network identifiers of a plurality of networks in the circuit system, the identification information of the devices, and the connection relationship through a circuit diagram or a netlist file uploaded by a user. The netlist file can be in a telnet host file (TEL) format, a circuit description language (RPT) format, or a report (RPT) format, and the like.

[0067] The network identifier can include the name, keyword, and code of the network. The identification information of the device can include the code, pin number, name, and specification of the device. The connection relationship of the device includes the connection relationship of the pins between the devices, and the identification of the input / output signals at each pin.

[0068] S220: Identify the clock network in the circuit system according to the network identifier.

[0069] ​The electronic device 100 can identify the clock network in the circuit system according to the network identification of the obtained multiple networks. For example, the clock network can be identified according to whether the name of the network in the circuit system contains a clock network keyword. For example, the network name containing a clock keyword such as “CLK”, “XTAL”, etc. is the clock network.

[0070] In some embodiments, the electronic device 100 can also identify the clock network according to preset network identification configuration data. The network identification configuration data includes identification information of multiple clock networks, and can also include the correspondence between other network identification and network type. The network identification configuration data can be preset by the user in advance, or can be obtained by the electronic device 100 from a network identification database. The network identification database includes a large number of correspondence between network identification and network type. The present application does not make specific limitation.

[0071] In some embodiments, the electronic device 100 can also obtain network identification filtering data, which includes multiple network name keywords that need to be filtered. The electronic device 100 will also identify whether the network name contains the keywords in the network identification filtering data. If yes, even if the network name contains the clock network keyword, the network will not be determined as the clock network. That is, only the network name contains the clock network keyword, and the network name does not contain the keywords in the network identification filtering data, the network will be determined as the clock network.

[0072] For example, the network identification filtering data can include keywords such as “VCC”, “EN_IN”, etc. When the network name includes “CLK” and “VCC”, the electronic device 100 can determine that the network is not a clock network, and the network can be determined as a power supply network for the clock network. When the network name includes “CLK” and “EN_IN”, the electronic device 100 can also determine that the network is not a clock network, and the network can be determined as a network inputting an enable signal to the clock network.

[0073] S230: Determine the type and pin information of each device according to the identification information of the device.

[0074] The type of the device can be the functional type and specification information of the device, for example, the functional type includes resistance, capacitance, multiplexer, crystal oscillator, frequency divider, etc., and the specification information includes resistance value, capacitance value, etc. The electronic device will determine the type of the device according to the coding, bit number, name and keyword of the device.

[0075] For example, if the name of the device includes "R", such as "R5287", it can be considered that the device is a resistor, and if the name of the device includes "XTAL", such as "XTAL10", it can be considered that the device is a crystal oscillator. Alternatively, the electronic device 100 can also determine the type of the device through the device sub-class code, for example, the device with the sub-class code "1201" is a clock oscillator, the device with the sub-class code "1202" is a crystal oscillator, the device with the sub-class code "1203" is a general voltage-controlled crystal oscillator, the device with the sub-class code "1206" is a rubidium atomic clock, the device with the sub-class code "1208" is a constant-temperature crystal oscillator, the device with the sub-class code "1271" is a vehicle-mounted clock oscillator, and the device with the sub-class code "1272" is a vehicle-mounted clock oscillator.

[0076] The electronic device 100 can also determine the pin information corresponding to the device according to the type of the recognized device. The pin information can specifically include the pin sequence number, pin name, pin type, pin direction, and pin matching relationship of the device, wherein the pin direction includes whether the signal of the pin is an output signal (out) or an input signal (in). For example, the pin direction of the pin A1 of the device A is OUT, and the pin direction of the pin B1 of the device B is IN.

[0077] In some embodiments, the electronic device 100 can also identify the type of the device according to preset device identification configuration data, which includes the correspondence between the identification information of a plurality of devices and their types. Similarly, the device identification configuration data can be preset by the user in advance, or can be obtained by the electronic device 100 from a device identification database, which includes a large number of correspondence between device identification and type.

[0078] In some embodiments, the electronic device 100 can also identify the type of the device according to preset device identification configuration data, which includes the correspondence between the identification information of a plurality of devices and their types. Similarly, the device identification configuration data can be preset by the user in advance, or can be obtained by the electronic device 100 from a device identification database, which includes a large number of correspondence between device identification and type.

[0079] In some embodiments, the device identification configuration data can further include information about whether the device belongs to the type of penetrable device. The electronic device 100 can further determine whether the device is a penetrable device according to the device identification configuration data. For example, a device with a small resistance value, such as a resistor, an inductor, a magnetic bead, a copper sheet, a safety tube, a diode connected in forward direction, or a device with a small DC impedance can be identified as a penetrable device. Alternatively, in subsequent generation of the clock tree, the penetrable device will not be drawn in the clock tree.

[0080] S240: determining the clock link according to the connection relationship of the device, and determining the flow direction of the clock signal according to the pin information of the device.

[0081] The electronic device 100 determines the clock link according to the identified clock network and the connection relationship of each device. The clock link includes the connection relationship of each device in the clock network and the connection relationship of the devices connected to the clock network. The electronic device 100 further determines the flow direction of the clock signal in combination with the connection relationship of the clock link device and the pin direction. For example, the electronic device 100 first acquires the clock link according to the identified clock network. Then, the connection relationship of the clock link device is acquired, such as the pin A1 of the device A connected to the pin B1 of the device B. The type of the clock link device is further acquired, such as the device A belonging to the clock source device, the device B belonging to the clock conversion device, and the pin direction of the pin A1 of the device A being OUT, and the pin direction of the pin B1 of the device B being IN. Further, the electronic device 100 can determine that the clock signal flows from the pin A1 of the device A to the pin B1 of the device B.

[0082] S250: generating the clock tree according to the type of the device and the flow direction of the clock signal.

[0083] After the electronic device 100 acquires the flow direction of the clock signal, the electronic device 100 further determines the source end and the device mainly flowed through of the clock signal in combination with the type of the device, and further generates the clock tree. For example, the electronic device 100 can acquire the type of the device according to step S230, and can determine the clock source device, the clock conversion device, and the clock demand device, and the like, which are the clock link devices mainly flowed through by the clock signal, and can regard the penetrable device as a conductive path. Then, the clock tree is generated according to the clock link devices mainly flowed through by the clock signal and the flow direction of the clock signal.

[0084] In some embodiments, the electronic device 100 will also determine the parameter information of the clock signal by combining the types of the clock source device and the clock conversion device. For example, the identification information of the crystal oscillator may include the crystal oscillator's specification information. For example, if the crystal oscillator's specification is 50MHz, then it can be determined that the frequency of the clock signal at the pin of the output clock signal of the crystal oscillator is 50MHz. The electronic device 100 will also mark the parameter information of the clock signal at each pin in the clock tree. The parameter information may specifically include the frequency, signal strength, phase, etc. of the clock signal.

[0085] In some embodiments, the electronic device 100 will also acquire the user interface (UI) graphics corresponding to each device in the clock tree, and draw the connection relationships of each device in the clock tree and mark the flow of clock signals. The electronic device 100 will also display the drawn clock tree structure on the display interface. That is to say, the clock tree displayed by the electronic device 100 can be text data such as a netlist file, or it can be graphical data. This application does not impose specific limitations on this.

[0086] In summary, using the clock tree generation method provided in this application, the electronic device 100 can identify the types of various devices and the flow of clock signals based on netlist files, and thus automatically draw a clock tree. Developers can view or adjust the clock architecture of the circuit system based on the clock tree. Furthermore, developers do not need to spend a significant amount of time drawing the clock tree, thus improving the development efficiency of the circuit system.

[0087] Next, let's combine... Figure 3 This application introduces a clock tree generation system provided in an embodiment, which can run in an electronic device 100. For example... Figure 3 As shown, the clock tree generation system comprises an application layer, a business logic layer, and a data layer. The application layer includes a user interface display module 301; the business logic layer includes a netlist parsing module 302, a clock network analysis module 303, a clock link analysis module 304, a device symbol generation module 305, a clock source identification module 306, a clock tree generation module 307, and an application program interface (API) 308; and the data layer includes a database module 309.

[0088] The interface display module 301 can be used to display an interface for obtaining circuit system information and an interface for displaying the generated clock tree. The interface display module 301 is specifically a web page or a client, etc. A user can upload circuit diagram or netlist file information of a circuit system through the interface display module 301 to display an interface for obtaining circuit system information. The following is described by taking the circuit system information as a netlist file as an example. Then the interface display module 301 sends the netlist file to the business logic layer through the API 308, obtains the generated clock tree through the API 308 after the business logic layer generates the clock tree, and displays the clock tree on the interface.

[0089] In some embodiments, the interface display module 301 can also be used to display interfaces for clock link information, device pin information, etc. Specifically, refer to the following Figure 8 、 Figures 10 to 14 and related descriptions.

[0090] The netlist analysis module 302 is used to parse the identification information of each network, the identification information of the device, and the connection relationship of the device in the circuit system according to the netlist file obtained by the interface display module 301. Optionally, the netlist file obtained by the netlist analysis module 302 can also come from the task database in the database module 309. The netlist analysis module 302 is also used to send the parsed identification information of each network to the clock network analysis module 303, and send the parsed connection relationship of the device to the clock link analysis module 304, and send the parsed identification information of the device to the device symbol generation module 305 and the clock source identification module 306.

[0091] The clock network analysis module 303 is used to identify the clock network in the circuit system according to the identification information of each network parsed by the netlist analysis module 302. Optionally, the clock network analysis module 303 can also send the identification information of the clock network to the clock link analysis module 304 and / or the device symbol generation module 305.

[0092] In some embodiments, the clock network analysis module 303 can identify the clock network according to the preset network identification configuration data. The network identification configuration data can be preset by the user in advance, or can be obtained from the network identification database in the database module 309.

[0093] The clock link analysis module 304 is used to identify the clock link. The clock link analysis module 304 can first obtain the clock network identified by the clock network analysis module 303, and then identify the connection relationship of the device in the clock network and the connection relationship of the device connected to the clock network to obtain the clock link.

[0094] Alternatively, the clock link analysis module 304 can also obtain the connection relationship of the clock link device and the clock source device identified in the netlist file after the device symbol generation module 305 identifies the clock link device and the clock source identification module 306 identifies the clock source device, and then obtains the clock link.

[0095] The device symbol generation module 305 is configured to identify the type of the device according to the identification information of the device parsed by the netlist parsing module 302. The device symbol generation module 305 can identify the type of each device in the circuit system, including the pin direction of the device, according to the identification information of the device parsed by the netlist parsing module 302. Then the device type is sent to the clock link analysis module 304, and the clock link is identified by the clock link analysis module 304, and the flow direction of the clock signal is determined according to the pin direction of the device in the clock link.

[0096] Alternatively, the device symbol generation module 305 can also identify the type of each device in the clock link after the clock link analysis module 304 identifies the clock link, and the device symbol generation module 305 determines the flow direction of the clock signal according to the pin information of the device.

[0097] In some embodiments, the device symbol generation module 305 can identify the type of the device according to the preset device identification configuration data, which can be preset by the user in advance or obtained from the device identification database in the database module 309.

[0098] The clock source identification module 306 is configured to identify the clock source device according to the identification information of the device. The clock source identification module 306 can identify the clock source device in the circuit system first, and send the information of the clock source device to the clock link analysis module 304. Alternatively, the clock source identification module 306 can directly obtain the clock link identified by the clock link analysis module 304, and then identify the clock source device in the clock link. Optionally, the clock source identification module 306 and the device symbol generation module 305 can be combined into the same module, that is, the device symbol generation module 305 directly determines the clock source device according to the type of the device.

[0099] In some embodiments, the clock source identification module 306 can identify the type of the device according to the preset device identification configuration data, which can be preset by the user in advance or obtained from the device identification database in the database module 309.

[0100] The clock tree generation module 307 is configured to obtain the clock signal flow direction identified by the clock network analysis module 304, the device type identified by the device symbol generation module 305, and the clock source device identified by the clock source identification module 306. The clock tree generation module 307 is further configured to generate a clock tree according to the clock signal flow direction, the device type, and the identified clock source device. The clock tree includes the flow direction of the clock signal, and can further include parameter information of the clock signal, etc.

[0101] Optionally, after the clock tree generation module 307 generates the clock tree, the clock tree can be sent to the interface display module 301 through the API 308, so that the interface display module 301 can also display the clock tree on the interface. Alternatively, the clock tree generation module 307 can also send the generated clock tree to other service modules, and the other service modules use the clock tree to detect or simulate the circuit system, etc. For example, the other service modules can also use the clock tree to perform signal integrity (SI) simulation, clock detection, phase noise detection, and level matching detection, etc.

[0102] The API 308 is configured to obtain the circuit system information such as the netlist file obtained by the interface display module 301, and send the circuit system information to the netlist analysis module 302. The API 308 is further configured to obtain the clock tree generated by the clock tree generation module 307, and send the clock tree to the interface display module 301 for display, or send the clock tree to other service modules for detection or simulation of the circuit system, etc.

[0103] The database module 309 includes a task database, a network identification database, and a device identification database. The netlist analysis module 302 can obtain the netlist file and other information of the circuit system from the task database. The clock network analysis module 303 can obtain network identification configuration data from the network identification database. The device symbol generation module 305 and the clock source identification module 306 can obtain device identification configuration data from the device identification database.

[0104] In summary, the clock tree generation system provided in the present application can automatically draw a clock tree according to the netlist file and other information such as the identified device type and the clock signal flow direction. The developer can view or adjust the clock architecture of the circuit system according to the clock tree. The developer does not need to spend a lot of time to draw the clock tree, and the development efficiency of the circuit system is improved.

[0105] The clock tree generation system shown in FIG. 1 is taken as an example to introduce another clock tree generation method provided in the present application. In the method, the database module 309 includes a network identification database and a device identification database. Figure 3 The clock tree generation system shown in FIG. 1 is taken as an example to introduce another clock tree generation method provided in the present application. In the method, the database module 309 includes a network identification database and a device identification database. Figure 4 The clock tree generation system shown in FIG. 1 is taken as an example to introduce another clock tree generation method provided in the present application. In the method, the database module 309 includes a network identification database and a device identification database.Figure 4 As shown, the clock tree generation method includes a network identification database and a device identification database in the database, and specifically includes:

[0106] S401: The interface display module 301 acquires the netlist file and the request for generating the clock tree.

[0107] The user can upload the circuit diagram or the netlist file of the circuit system and other information through the interface displayed by the interface display module 301 for acquiring the circuit system information. The type and content of the circuit system information can refer to the foregoing step S210, which will not be described here. The following takes the netlist file as an example for description.

[0108] In addition, the interface display module 301 can also display the related control for generating the clock tree, and the user can select the control through clicking or other operations to trigger the clock tree generation system to execute the subsequent steps and generate the clock tree.

[0109] For example, Figure 5 An interface 501 for acquiring the circuit system information is shown. The control 502 in the interface 501 can be used for the user to select whether to generate the SI use case. If the user selects to generate the SI use case, the signal simulation analysis can be performed on the circuit system, including generating the clock tree and the like. The control 503 can be used for the user to upload the netlist file of the circuit system, such as the TEL file with the file suffix.tel. The input box 504 can be used for the user to input the related note information of the circuit system. The input box 505 can be used for the user to select the collaborative analysis person of the circuit system.

[0110] Exemplarily, Figure 6 A partial circuit diagram of a circuit system is shown, which includes an oscillator OSC1, a resistor R5287 and a clock driver U2. The OSC1 includes a pin NC / 3-ST (No. 1), which represents that the pin does not need to be connected (NC) and the OSC1 has a three-state output (3-ST). The OSC1 further includes a ground pin GND (No. 2), an output pin OUT (No. 3) and a power supply pin VDD (No. 4). The U2 includes a clock signal input pin CLKIN (No. 1), an output enable pin OE (No. 2), a ground pin GND (No. 4), a power supply pin VDD (No. 6) and output terminal pins 1Y0 to 1Y3 (No. 3, No. 5, No. 7 and No. 8). In addition, the output pin OUT of the OSC1 is connected to one end of the R5287, and the signal output from the other end of the R5287 is recorded as RMII_CLK_50M_IN and input to the clock signal input pin CLKIN of the U2.

[0111] Figure 7 for Figure 6 The netlist file corresponding to the circuit diagram shown includes a declaration package ($PACKAGES), an attribute package ($A_PROPERTIES), a connection information package ($NETS), and a schedule ($SCHEDULE). $PACKAGES defines the names and specifications of each component in the circuit system, including the OSC1 output signal frequency of 50MHz and the resistance of R5287 of 33Ω. $A_PROPERTIES defines the reference designators for each component, such as... Figure 7 As shown, the tag number of R5287 is "07XXX36", the tag number of OSC1 is "12XXX00", and the tag number of U2 is "39XXX95". The $NETS defines the connection relationships between devices. For example, "'$1N524'; OSC1.3 R5287.1" indicates that pin 3 of OSC1 is connected to one end of R5287, and the signal is denoted as "$1N524". "'RMII_CLK_50MHZ_IN'; R5287.2 U2.1" indicates that the other end of R5287 is connected to pin 1 of U2, and the signal is denoted as "RMII_CLK_50MHZ_IN".

[0112] S402: The interface display module 301 sends the netlist file to the netlist parsing module 302.

[0113] After the interface display module 301 obtains the netlist file, it will send the netlist file to the netlist parsing module 302 via API 308, and the netlist parsing module 302 will parse the netlist file.

[0114] S403: Netlist parsing module 302 parses the netlist file to obtain the network identifier and device connection relationship of each network.

[0115] After obtaining the netlist file, the netlist parsing module 302 will parse it to obtain the network identifiers of each network in the circuit system, as well as the identification information and connection relationships of each device within each network. The parsed information can be found in the aforementioned documentation. Figure 6 and Figure 7 Related descriptions.

[0116] S404: The netlist parsing module 302 sends the network identifiers of each network to the clock network analysis module 303.

[0117] The netlist parsing module 302 will send the network identifiers of each network in the circuit system obtained from the netlist file to the clock network analysis module 303, so that the clock network analysis module 303 can analyze and obtain the clock network in the circuit system.

[0118] S405a: The clock network analysis module 303 sends a request to the database module 309 to obtain network identifier configuration data.

[0119] The request to obtain network identifier configuration data is used to request the database module 309 to send the network identifier configuration data to the clock network analysis module 303. The network identifier configuration data includes identifier information for multiple clock networks, and may also include the correspondence between other network identifiers and their network types. Optionally, the network identifier configuration data may also include network identifier filtering data. The network identifier configuration data in the database module 309 may be obtained by summarizing the network identifiers of a large number of circuit systems.

[0120] S405b: Database module 309 sends network identifier configuration data to clock network analysis module 303.

[0121] After obtaining the network identifier configuration data, the clock network analysis module 303 can also display the network identifier configuration data on the interface. For example... Figure 8 As shown, interface 801 displays a display box 802 showing network identifier configuration data. Controls 803 in display box 802 can be used by the user to add keywords for network identifiers to be identified and network identifiers to be filtered. Display box 804 displays some clock keywords (“CLK”, “XTAL”) and corresponding keywords to be filtered (“VCC”, “EN_IN”, and “OUT”). Controls 805a to 805c can be used to delete the corresponding keywords. Control 806 can restore the network identifier configuration data to the system default state, for example, without saving the user's operation, restoring it to the original state. Control 807 can be used by the user to save the current changes. Control 808 can be used by the user to cancel the current operation and / or close display box 804.

[0122] S406: Clock network analysis module 303 identifies the clock network based on the network identifier of each network.

[0123] The clock network analysis module 303 will identify the network identifier of the clock network based on the network identifier configuration data. For example, a network name containing clock keywords such as "CLK" or "XTAL" is a clock network. See step S220 above for details, which will not be repeated here.

[0124] Optionally, the clock network analysis module 303 may also determine whether the clock network is complete. Specifically, the clock network may be sent to the interface display module 301, which will then display the clock network. The user will then determine whether the clock network is complete based on the displayed clock network and obtain the user's judgment result.

[0125] S407: The clock network analysis module 303 sends the network identification of the clock network to the clock link analysis module 304.

[0126] The clock network analysis module 303 sends the identified network identification of the clock network to the clock link analysis module 304, so that the clock link analysis module 304 can analyze the identified clock device.

[0127] S408: The netlist analysis module 302 sends the device connection relationship to the clock link analysis module 304.

[0128] The netlist analysis module 302 can send the device connection relationship to the clock link analysis module 304 after analyzing the device connection relationship, that is, the step S408 is executed before the step S403, or the step S408 can be executed at any time after the step S403.

[0129] S409: The clock link analysis module 304 determines the device through which the clock signal flows.

[0130] The clock link analysis module 304 can determine the connection relationship of each device in the clock network and the connection relationship of the device connected to the clock network according to the clock network and the device connection relationship. Further, the clock device through which the clock signal flows can be determined.

[0131] S410: The clock link analysis module 304 sends the identification information of the device through which the clock signal flows to the device symbol generation module 305.

[0132] The clock link analysis module 304 can send the identification information of the device through which the clock signal flows to the device symbol generation module 305, so that the device symbol generation module 305 can identify the type and pin direction of each device, and further obtain the flow direction of the clock signal in the clock link.

[0133] S411a: The device symbol generation module 305 sends a request for obtaining device identification configuration data to the database module 309.

[0134] The device symbol generation module 305 obtains the device identification configuration data in the database module 309 for identifying the type and pin direction of each device. The device identification configuration data includes the correspondence relationship between the identification information of a plurality of devices and the type thereof, and further includes the pin information of each device. The device identification configuration data can further include the type information of whether the device belongs to a clock source device, a clock conversion device, and a clock demand device, and the type information of whether the device belongs to a penetrable device. For details, reference can be made to the foregoing step S230, which will not be described here.

[0135] S411b: The database module 309 sends the device identification configuration data to the device symbol generation module 305.

[0136] S412: The device symbol generation module 305 determines the clock device and the direction of the clock link.

[0137] According to the device identification configuration data, the device symbol generation module 305 can determine the type of each clock device, and then select the clock device from the devices through which the clock signal flows. The pin information corresponding to each clock device is obtained, and the flow direction of the clock signal between the clock devices is determined according to the pin information, that is, the direction of the clock link is determined.

[0138] In some embodiments, the clock link analysis module 304 and the device symbol generation module 305 can determine the clock device through the flow shown in FIG. 4. Figure 9 As shown in FIG. 5, the flow includes: Figure 9

[0139] S901: Obtain the clock network.

[0140] Specifically, the clock link analysis module 304 obtains the clock network according to the network identifier of the clock network identified by the clock network analysis module 303.

[0141] S902: Determine whether the device type connected by the network is a small device.

[0142] The device symbol generation module 305 determines whether the device connected by the clock network is a small device, and if so, step S904 is performed, and if not, step S903 is performed.

[0143] Specifically, the clock link analysis module 304 can determine the clock device through which the clock signal flows according to the clock network and the device connection relationship. The device symbol generation module 305 determines whether the device connected by the clock network is a small device. The small device refers to a single device other than an integrated chip, such as a resistor, a capacitor, a magnetic bead, etc.

[0144] S903: Draw the cut-off device.

[0145] If the device connected by the clock network is not a small device, it means that the device is a clock demand device, and the device symbol generation module 305 needs to be drawn in the clock tree. Then the device symbol generation module 305 draws the device as a clock cut-off device.

[0146] S904: Determine whether the small device is penetrated.

[0147] ​If the device connected by the clock network is a small device, the device symbol generation module 305 will further determine whether the small device can be penetrated. If yes, step S906 is executed, and if no, step S905 is executed. The small device is a device with small impedance in the direct current circuit, such as a resistor with small resistance value, an inductor, a magnetic bead, a copper sheet, a safety tube, and a forward connected diode.

[0148] Specifically, the device symbol generation module 305 can further obtain the pin information of the small device from the device identification configuration data, and determine whether the small device can be penetrated according to the polarity of the pin in the pin information. For example, the pin type is collector (C) and the pin polarity is positive, the pin type is drain (D) and the pin polarity is negative, and the pin type is L and the pin polarity is nonpolar.

[0149] S905: draw a cut-off device.

[0150] If the small device connected by the clock network is not a penetrable device, it means that the small device can also consume the clock signal and needs to be drawn in the clock tree, and the device symbol generation module 305 will draw the device as a cut-off device.

[0151] S906: determine whether the network at the end of the small device is a power supply / ground.

[0152] If the small device is a penetrable device, it will be further determined whether the small device is a power supply / ground, and if yes, step S907 is executed. If no, the flow is ended, or the method is executed again to determine the next clock network.

[0153] S907: draw a power supply / ground symbol.

[0154] If the small device is a power supply / ground, the device symbol generation module 305 will draw it as a power supply / ground.

[0155] After determining the type of the device, the device symbol generation module 305 will further obtain the pin information corresponding to the clock device. For example, Figure 10As shown, the interface 1001 shows the pin information of the device "39130129". Among them, the display box 1002 shows the name of the device "39130129", the display box 1003 shows the description of the device, including that the device belongs to a clock driver, the output frequency is 100MHz-133.33MHz, and the working voltage can be 3.3V-3.3V-4.6V, etc. The display box 1004 shows the serial number, name, type and direction of each pin of the device. Specifically, it includes the clock signal input pin CLKIN (pin serial number 1), the pin direction of which is IN, that is, the input end. The output enable pin OE (pin serial number 2), the pin direction of which is IN, that is, the input end. The ground pin GND (pin serial number 4), the pin direction of which is BI, that is, the low level end. The power supply pin VDD (pin serial number 6), the pin direction of which is IN, that is, the input end. And the output end pins 1Y0 to 1Y3 (pin serial number 3, pin serial number 5, pin serial number 7 and pin serial number 8), the pin directions of which are all OUT.

[0156] After the device symbol generation module 305 obtains the pin direction of the clock device, it can determine the signal source end and the signal destination end of the clock signal. As shown in the following figure, the device symbol generation module 305 determines the signal source end and the signal destination end of the clock signal. Figure 11 As shown, the device symbol generation module 305 sends the determined signal source end and signal destination end to the interface display module 301, and the interface display module 301 displays the clock network information of the task "Board1" in the interface 1101. The display box 1102 in the interface 1101 can operate the source end and the destination end information of multiple clock networks, and the display box 1107 shows the signal source end and the signal destination end of multiple clock networks, for example, the signal source end of the clock network with the network name "CLK1" is "U43<93DGLF>-OUT", and the signal destination end is "U42 <lewis>BIU29<9ZLF>-IN”. In addition, the display box 1102 also includes controls 1103-1106, the control 1103 can be used for the user to manually add a clock network, the control 1104 can be used for the user to batch manage the identified clock network, and the control 1105 can be used for the user to batch delete the identified clock network. The control 1106 can be used to generate a clock tree, and after the user clicks the control 1106, the clock tree generation system can be triggered to generate a clock tree according to the current identified clock network.

[0157] Further, the device symbol generation module 305 can also draw a schematic diagram according to the signal source end and the signal destination end of the clock signal and send it to the interface display module 301. As shown in the schematic diagram, the schematic diagram shows the clock network information in the U4214, including CLK_PCIE7_P input to CLKOUT_SRC_P_7 of U4214, CLK_100M_DB1900R_1_P input to DF_IN of U29, and CLK_100M_DB1900_1_P output as CLK_100M_DB1900_1R_P after passing through R10349. Figure 12 Figure 11 Further, the device symbol generation module 305 can also draw a schematic diagram according to the signal source end and the signal destination end of the clock signal and send it to the interface display module 301. As shown in the schematic diagram, the schematic diagram shows the clock network information in the U4214, including CLK_PCIE7_P input to CLKOUT_SRC_P_7 of U4214, CLK_100M_DB1900R_1_P input to DF_IN of U29, and CLK_100M_DB1900_1_P output as CLK_100M_DB1900_1R_P after passing through R10349.

[0158] Optionally, the user can also set the signal source end and the signal destination end by himself. As shown in the interface 1301, the user can set a certain clock signal through the display box 1302. For example, the signal at this place is set as the signal source end by clicking the control 1303, the signal at this place is set as the signal destination end by clicking the control 1304, or the signal at this place is set as not displayed in the form by clicking the control 1305. In addition, the user can also determine the above modification by clicking the control 1306, or exit the setting and close the display box 1302 by clicking the control 1307. Figure 13

[0159] S413: The device symbol generation module 305 sends the clock device identification result to the clock tree generation module 307.

[0160] The device symbol generation module 305 can send the category of the clock device to the clock tree generation module 307, and also send the signal source end and the signal destination end of the clock signal to the clock tree generation module 307.

[0161] S414: The netlist analysis module 302 sends the identification of the device in each network and the connection relationship to the clock source identification module 306.

[0162] ​​The netlist analysis module 302 sends the identification of each device in the network and the connection relationship to the clock source identification module 306, so that the clock source identification module 306 can identify the clock source device in each device. It should be understood that this step can also be performed by the device symbol generation module 305 in step S412, and the present application does not limit this.

[0163] S415: The clock source identification module 306 determines the clock source device.

[0164] The clock source identification module 306 can identify the clock source device according to the identification information of each device according to the preset device identification configuration data. For details, reference can be made to the foregoing step S230 and the related description.

[0165] S416: The clock source identification module 306 sends the clock source device information to the clock tree generation module 307.

[0166] After the clock source identification module 306 identifies the clock source device, it will send the identification information of the clock source device to the clock tree generation module 307.

[0167] S417: The clock tree generation module 307 generates a clock tree according to the clock link and the clock source device.

[0168] The clock tree generation module 307 can determine the clock tree according to the flow direction of the clock signal and in combination with the type of the device.

[0169] Optionally, the clock tree generation module 307 will also determine the parameter information of the clock signal in combination with the type of the clock source device and the clock conversion device. The parameter information can specifically include the frequency, signal strength, phase, etc. of the clock signal. For details, reference can be made to the foregoing step S250 and the related description.

[0170] S418: The clock tree generation module 307 sends the clock tree to the interface display module 301.

[0171] The clock tree generation module 307 sends the clock tree to the interface display module 301, which can be text data such as a netlist file, or can be graphical data of the clock tree.

[0172] S419: The interface display module 301 displays the clock tree.

[0173] The interface display module 301 will display the clock tree on the interface according to the clock tree sent by the clock tree generation module 307.

[0174] Exemplarily, as shown in FIG. 4, the interface display module 301 displays the clock tree on the interface. Figure 14 As shown, a structure diagram of a clock tree is displayed in the display bar 1402 of the interface 1401. The crystal oscillator X10 is a clock source device, and its number is "1212". The No. 2 pin of the X10 inputs the signal "$3165 / XTAL..." to the K17 pin (pin name: "RTCX1") of the document encoder U42.

[0175] The pin K2 (pin name: "SPIO CLK") of the U42 inputs the signal "SPI PCH CLK" to the No. 1 pin (pin name: "A1") of the general socket J1 and the No. 3 pin (pin name: "A1") of the logic bus (LOGIC BUS) U3, respectively. The pin AP18 (pin name: "GPP F22...") of the U42 inputs the signal "SGPIO SA CLK R" to the R8 pin (pin name: "PB12D") of the complex programmable logic device (CPLD) U4, the pin T2 (pin name: "GPP A16...") of the U42 inputs the signal "CLK CPLD DET..." to the F14 pin (pin name: "PR2C") of the U4, and the pin C13 (pin name: "GPD8 SUS..") of the U42 inputs the signal "CLK PCH SUSCLK 33..." to the B9 pin (pin name: "PT18B / PC") of the port physical layer (Physical, PHY) U4. The pin BW6 (pin name: "GPP J14..") of the U42 inputs the signal "LAN SCL" to the No. 7 pin (pin name: "MDC") of the U4.

[0176] The pin 27 (pin name: "B9") of the U3 inputs the signal "SPI CLK" to the No. 16 pin (pin name: "SLCK") of the non-volatile flash (NOR Flash) U7. The pin T7 (pin name: "PB10C") of the U4 inputs the signal "SGPIO RAID CLK X6..." to the pin 22 (pin name: "A6") of the high-speed backplane connector J2. The pin T7 (pin name: "PB10C") of the U4 inputs the signal "SGPIO RAID CLK X6..." to the pin 50 (pin name: "TX2N") of the transceiver equalizer U42.

[0177] In summary, the clock tree generation system provided in the present application can identify the types of various devices and the flow direction of the clock signals according to the netlist file and the like, and then automatically draw a clock tree. The developers can view or adjust the clock architecture of the circuit system according to the clock tree. Moreover, the developers do not need to spend a lot of time drawing the clock tree, thereby improving the development efficiency of the circuit system.

[0178] The following describes another clock tree generation method provided by the present application in combination with the clock tree generation system shown in Figure 3 The clock tree generation method provided by the present application is shown in Figure 15 The clock tree generation method provided by the present application is shown in Figure 15 The circuit system information is also taken as an example of the netlist file. Figure 15 The specific implementation of the similar steps in the flow shown in Figure 2 Or Figure 4 The related content is not repeated here. As shown in Figure 15 The clock tree generation method including the device identification database in the database is shown in

[0179] S1501: The interface display module 301 obtains the netlist file and the request for generating the clock tree.

[0180] The user can upload the circuit diagram or netlist file of the circuit system through the interface display module 301 to display the interface for obtaining the circuit system information.

[0181] S1502: The interface display module 301 sends the netlist file to the netlist analysis module 302.

[0182] After the interface display module 301 obtains the netlist file, it will also send the netlist file to the netlist analysis module 302 through the API 308, and the netlist analysis module 302 will analyze the netlist file.

[0183] S1503: The netlist analysis module 302 analyzes the netlist file to obtain the network identifier of each network and the connection relationship of each device in each network.

[0184] After the netlist analysis module 302 obtains the netlist file, it will analyze the network identifier of each network in the circuit system, and the identification information and connection relationship of each device in each network.

[0185] S1504: The netlist analysis module 302 sends the network identifier of each network to the clock network analysis module 303.

[0186] The netlist analysis module 302 will send the network identifier of each network in the circuit system obtained from the netlist file to the clock network analysis module 303, so that the clock network analysis module 303 can analyze the clock network in the circuit system.

[0187] S1505: The clock network analysis module 303 identifies the clock network according to the network identifier of each network.

[0188] The clock network analysis module 303 identifies the network identification of the clock network according to the network identification configuration data. For example, the network name including the clock keyword such as "CLK", "XTAL" and the like is the clock network. The network identification configuration data can be determined based on the user preset file, can be preloaded during running, or can be input via other additional ports.

[0189] S1506: The clock network analysis module 303 sends the network identification of the clock network to the clock link analysis module 304.

[0190] The clock network analysis module 303 sends the identified network identification of the clock network to the clock link analysis module 304, so that the clock link analysis module 304 can analyze the identified clock device.

[0191] S1507: The netlist analysis module 302 sends the device connection relationship to the clock link analysis module 304.

[0192] The netlist analysis module 302 can send the device connection relationship to the clock link analysis module 304 after analyzing the device connection relationship, that is, step S1507 is executed before step S1503, or step S1507 can be executed at any time after step S1503.

[0193] S1508: The clock link analysis module 304 determines the device through which the clock signal flows.

[0194] The clock link analysis module 304 can determine the connection relationship of each device in the clock network and the connection relationship of the device connected to the clock network according to the clock network and the device connection relationship. Further, the clock device through which the clock signal flows can be determined.

[0195] S1509: The clock link analysis module 304 sends the identification information of the device through which the clock signal flows to the device symbol generation module 305.

[0196] The clock link analysis module 304 can send the identification information of the device through which the clock signal flows to the device symbol generation module 305, so that the device symbol generation module 305 can identify the type and pin direction of each device, and further obtain the flow direction of the clock signal in the clock link.

[0197] S1510a: The device symbol generation module 305 sends a request for obtaining device identification configuration data to the database module 309.

[0198] The device identification configuration data includes the correspondence between the identification information of a plurality of devices and the types thereof, and further includes the pin information of each device. The device identification configuration data can further include type information of whether the device belongs to a clock source device, a clock conversion device, a clock demand device, and the like, and type information of whether the device belongs to a penetrable device.

[0199] S1510b: The database module 309 sends the device identification configuration data to the device symbol generation module 305.

[0200] S1511: The device symbol generation module 305 determines the clock devices and the direction of the clock link.

[0201] The device symbol generation module 305 can determine the type of each clock device according to the device identification configuration data, and then select the clock device from the devices through which the clock signal flows. The pin information corresponding to each clock device is obtained, and the flow direction of the clock signal between the clock devices, i.e., the direction of the clock link, can be determined according to the pin information.

[0202] In some embodiments, the clock link analysis module 304 and the device symbol generation module 305 can determine the clock device through the flow shown in Figure 9 , and the related description thereof will not be repeated here. Figure 9

[0203] After determining the type of the device, the device symbol generation module 305 further obtains the pin information corresponding to the clock device. After obtaining the pin direction of the clock device, the device symbol generation module 305 can determine the signal source segment and the signal destination segment of the clock signal. Further, the device symbol generation module 305 can draw a schematic diagram according to the signal source segment and the signal destination segment of the clock signal, and send the schematic diagram to the display module 301. Alternatively, the user can also set the signal source segment and the signal destination segment by himself.

[0204] S1512: The device symbol generation module 305 sends the clock device identification result to the clock tree generation module 307.

[0205] The device symbol generation module 305 can send the category of the clock device to the clock tree generation module 307, and further send the signal source segment and the signal destination segment of the clock signal to the clock tree generation module 307.

[0206] S1513: The netlist analysis module 302 sends the identification and connection relationship of the devices in each network to the clock source identification module 306.

[0207] ​The netlist analysis module 302 sends the identification of each device in the network and the connection relationship to the clock source identification module 306, so that the clock source identification module 306 can identify the clock source device in each device.

[0208] S1514: The clock source identification module 306 determines the clock source device.

[0209] The clock source identification module 306 can identify the clock source device according to the identification information of each device according to the preset device identification configuration data.

[0210] S1515: The clock source identification module 306 sends the clock source device information to the clock tree generation module 307.

[0211] S1516: The clock tree generation module 307 generates a clock tree according to the clock link and the clock source device.

[0212] The clock tree generation module 307 can determine the clock tree according to the flow direction of the clock signal and in combination with the type of the device.

[0213] S1517: The clock tree generation module 307 sends the clock tree to the interface display module 301.

[0214] The clock tree generation module 307 sends the clock tree to the interface display module 301, which can be text data such as a netlist file, or graphical data of the clock tree.

[0215] S1518: The interface display module 301 displays the clock tree.

[0216] The interface display module 301 displays the clock tree on the interface according to the clock tree sent by the clock tree generation module 307.

[0217] In summary, the clock tree generation system provided by the present application can identify the type of each device and the flow direction of the clock signal according to the netlist file, and then automatically draw the clock tree. The developer can view or adjust the clock architecture of the circuit system according to the clock tree. The developer does not need to spend a lot of time drawing the clock tree, which improves the development efficiency of the circuit system.

[0218] The clock tree generation system shown in the above Figure 3 The clock tree generation method shown in the above Figure 16 The database module 309 includes a network identification database. Moreover, Figure 16 The circuit system information is taken as a netlist file as an example. Figure 16 The specific implementation of similar steps in the above Figure 2 Or Figure 4 and related content, which will not be described here. As shown in Figure 16 The clock tree generation method including a network identification database in the database, specifically includes:

[0219] S1601: The interface display module 301 acquires the netlist file and the request for generating the clock tree.

[0220] The user can upload the circuit diagram or the netlist file and other information of the circuit system through the interface displayed by the interface display module 301 for acquiring the circuit system information.

[0221] S1602: The interface display module 301 sends the netlist file to the netlist analysis module 302.

[0222] After the interface display module 301 acquires the netlist file, the interface display module 301 will also send the netlist file to the netlist analysis module 302 through the API 308, and the netlist analysis module 302 analyzes the netlist file.

[0223] S1603: The netlist analysis module 302 analyzes the netlist file to obtain the network identification of each network and the connection relationship of each device.

[0224] After the netlist analysis module 302 acquires the netlist file, the netlist analysis module 302 analyzes to obtain the network identification of each network in the circuit system, and the identification information and connection relationship of each device in each network.

[0225] S1604: The netlist analysis module 302 sends the network identification of each network to the clock network analysis module 303.

[0226] The netlist analysis module 302 sends the network identification of each network in the circuit system acquired from the netlist file to the clock network analysis module 303, so that the clock network analysis module 303 can analyze the clock network in the circuit system.

[0227] S1605a: The clock network analysis module 303 sends a request for acquiring network identification configuration data to the database module 309.

[0228] The network identification configuration data includes the identification information of a plurality of clock networks, and can also include the correspondence between other network identifications and network types. Optionally, the network identification configuration data can also include network identification filtering data. The network identification configuration data in the database module 309 can be obtained by summarizing the network identification of a large number of circuit systems.

[0229] S1605b: The database module 309 sends the network identification configuration data to the clock network analysis module 303.

[0230] The clock network analysis module 303 can display the network identification configuration data on the interface after obtaining the network identification configuration data.

[0231] S1606: The clock network analysis module 303 identifies the clock network according to the network identification of each network.

[0232] The clock network analysis module 303 identifies the network identification of the clock network according to the network identification configuration data. For example, the network name including the clock keyword such as "CLK", "XTAL" is the clock network.

[0233] S1607: The clock network analysis module 303 sends the network identification of the clock network to the clock link analysis module 304.

[0234] The clock network analysis module 303 sends the network identification of the clock network identified to the clock link analysis module 304, so that the clock link analysis module 304 can analyze and identify the clock device.

[0235] S1608: The netlist analysis module 302 sends the device connection relationship to the clock link analysis module 304.

[0236] The netlist analysis module 302 can send the device connection relationship to the clock link analysis module 304 after analyzing the device connection relationship, that is, the step S1608 is executed before the step S1603, or the step S1608 can be executed at any time after the step S1603.

[0237] S1609: The clock link analysis module 304 determines the device through which the clock signal flows.

[0238] The clock link analysis module 304 can determine the connection relationship of each device in the clock network and the connection relationship of the device connected to the clock network according to the clock network and the device connection relationship. Further, the clock device through which the clock signal flows can be determined.

[0239] S1610: The clock link analysis module 304 sends the identification information of the device through which the clock signal flows to the device symbol generation module 305.

[0240] The clock link analysis module 304 can send the identification information of the device through which the clock signal flows to the device symbol generation module 305, so that the device symbol generation module 305 can identify the type and pin direction of each device, and further obtain the flow direction of the clock signal in the clock link.

[0241] S1611: The device symbol generation module 305 determines the clock device and the direction of the clock link.

[0242] The device symbol generation module 305 can determine the type of each clock device according to the device identification configuration data, and then select the clock device from the devices through which the clock signal flows. The device symbol generation module 305 can also obtain the pin information corresponding to each clock device, and determine the flow direction of the clock signal between the clock devices according to the pin information, i.e., determine the direction of the clock link. The device identification configuration data can be determined based on a user preset file, and can be preloaded during running or input via another port.

[0243] In some embodiments, the clock link analysis module 304 and the device symbol generation module 305 can determine the clock device through the flow shown in FIG. 6. Figure 9 For details, reference can be made to the foregoing Figure 9 and related descriptions, which will not be repeated here.

[0244] After determining the type of the device, the device symbol generation module 305 can also obtain the pin information corresponding to the clock device. After obtaining the pin direction of the clock device, the device symbol generation module 305 can determine the signal source segment and the signal destination segment of the clock signal. Further, the device symbol generation module 305 can also draw a schematic diagram according to the signal source segment and the signal destination segment of the clock signal, and send the schematic diagram to the interface display module 301. Alternatively, the user can also set the signal source segment and the signal destination segment by himself / herself.

[0245] S1612: The device symbol generation module 305 sends the clock device identification result to the clock tree generation module 307.

[0246] The device symbol generation module 305 can send the category of the clock device to the clock tree generation module 307, and also send the signal source segment and the signal destination segment of the clock signal to the clock tree generation module 307.

[0247] S1613: The netlist analysis module 302 sends the identification and connection relationship of each device in the network to the clock source identification module 306.

[0248] The netlist analysis module 302 sends the identification and connection relationship of each device in the network to the clock source identification module 306, so that the clock source identification module 306 can identify the clock source device in each device.

[0249] S1614: The clock source identification module 306 determines the clock source device.

[0250] The clock source identification module 306 can identify the clock source device according to the identification information of each device according to the preset device identification configuration data.

[0251] S1615: The clock source identification module 306 sends the clock source device information to the clock tree generation module 307.

[0252] S1616: The clock tree generation module 307 generates a clock tree according to the clock links and the clock source devices.

[0253] The clock tree generation module 307 can determine the clock tree according to the flow direction of the clock signals and in combination with the types of the devices.

[0254] S1617: The clock tree generation module 307 sends the clock tree to the interface display module 301.

[0255] The clock tree generation module 307 sends the clock tree to the interface display module 301, which can be text data such as a netlist file or graphical data of the clock tree.

[0256] S1618: The interface display module 301 displays the clock tree.

[0257] The interface display module 301 displays the clock tree on the interface according to the clock tree sent by the clock tree generation module 307.

[0258] In summary, the clock tree generation system provided by the present application can identify the types of devices and the flow direction of clock signals according to a netlist file and the like, and then automatically draw a clock tree. The developer can view or adjust the clock architecture of the circuit system according to the clock tree. The developer does not need to spend a lot of time drawing the clock tree, which improves the development efficiency of the circuit system.

[0259] The clock tree generation system shown in Figure 3 The clock tree generation method provided by the present application is introduced as shown in Figure 17 The method does not include the database module 309. Moreover, Figure 17 The circuit system information is taken as a netlist file for example. Figure 17 The specific implementation of similar steps in the flow shown in Figure 2 Or Figure 4 and related content, which will not be repeated here. As shown in Figure 17 The clock tree generation method without a database specifically includes:

[0260] S1701: The interface display module 301 obtains a netlist file and a request to generate a clock tree.

[0261] The user can upload the circuit diagram or netlist file and the like of the circuit system through the interface display module 301 to display the interface for obtaining the circuit system information.

[0262] S1702: The interface display module 301 sends the netlist file to the netlist analysis module 302.

[0263] After the interface display module 301 acquires the netlist file, the netlist file will be sent to the netlist analysis module 302 through the API 308, and the netlist analysis module 302 analyzes the netlist file.

[0264] S1703: The netlist analysis module 302 analyzes the netlist file to obtain the network identifier of each network and the device connection relationship.

[0265] After the netlist analysis module 302 acquires the netlist file, the network identifier of each network in the circuit system and the identifier information and connection relationship of each device in each network are obtained by analysis.

[0266] S1704: The netlist analysis module 302 sends the network identifier of each network to the clock network analysis module 303.

[0267] The netlist analysis module 302 sends the network identifier of each network in the circuit system obtained from the netlist file to the clock network analysis module 303, so that the clock network analysis module 303 can analyze the clock network in the circuit system.

[0268] S1705: The clock network analysis module 303 identifies the clock network according to the network identifier of each network.

[0269] The clock network analysis module 303 identifies the network identifier of the clock network according to the network identifier configuration data. For example, the network name including the clock keywords such as "CLK", "XTAL" is the clock network. The network identifier configuration data can be determined based on the user preset file, can be preloaded during running, or can be input via other ports.

[0270] S1706: The clock network analysis module 303 sends the network identifier of the clock network to the clock link analysis module 304.

[0271] The clock network analysis module 303 sends the network identifier of the clock network identified to the clock link analysis module 304, so that the clock link analysis module 304 can analyze and identify the clock device.

[0272] S1707: The netlist analysis module 302 sends the device connection relationship to the clock link analysis module 304.

[0273] The netlist analysis module 302 can send the device connection relationship to the clock link analysis module 304 after analyzing the device connection relationship, that is, step S1707 is executed before step S1703, or step S1707 can be executed at any time after step S1703.

[0274] S1708: The clock link analysis module 304 determines the device through which the clock signal flows.

[0275] The clock link analysis module 304 can determine the connection relationship of each device in the clock network and the connection relationship of the devices connected to the clock network according to the clock network and the device connection relationship. Further, the clock device through which the clock signal flows can be determined.

[0276] S1709: The clock link analysis module 304 sends the identification information of the device through which the clock signal flows to the device symbol generation module 305.

[0277] The clock link analysis module 304 can send the identification information of the device through which the clock signal flows to the device symbol generation module 305, so that the device symbol generation module 305 can identify the type and pin direction of each device, and further obtain the flow direction of the clock signal in the clock link.

[0278] S1710: The device symbol generation module 305 determines the clock device and the direction of the clock link.

[0279] The device symbol generation module 305 can determine the type of each clock device according to the device identification configuration data, and further select the clock device from the device through which the clock signal flows. The pin information corresponding to each clock device is obtained, and the flow direction of the clock signal between the clock devices, i.e. the direction of the clock link, can be determined according to the pin information. The device identification configuration data can be determined based on a user preset file, and can be preloaded during running or input via another port.

[0280] In some embodiments, the clock link analysis module 304 and the device symbol generation module 305 can determine the clock device through the flow shown in Figure 9 The foregoing Figure 9 and related descriptions can be referred to, and will not be described here.

[0281] After determining the type of the device, the device symbol generation module 305 further obtains the pin information corresponding to the clock device. After the device symbol generation module 305 obtains the pin direction of the clock device, the signal source segment and the signal destination segment of the clock signal can be determined. Further, the device symbol generation module 305 can also draw a schematic diagram according to the signal source segment and the signal destination segment of the clock signal, and send it to the interface display module 301. Alternatively, the user can also set the signal source segment and the signal destination segment.

[0282] S1711: The device symbol generation module 305 sends the clock device identification result to the clock tree generation module 307.

[0283] The device symbol generation module 305 can send the category of the clock device to the clock tree generation module 307, and can also send the signal source segment and the signal destination of the clock signal to the clock tree generation module 307.

[0284] S1712: The netlist analysis module 302 sends the identification of the devices in each network and the connection relationship to the clock source identification module 306.

[0285] The netlist analysis module 302 sends the identification of the devices in each network and the connection relationship to the clock source identification module 306, so that the clock source identification module 306 can identify the clock source device in each device.

[0286] S1713: The clock source identification module 306 determines the clock source device.

[0287] The clock source identification module 306 can identify the clock source device according to the identification information of each device according to the preset device identification configuration data.

[0288] S1714: The clock source identification module 306 sends the clock source device information to the clock tree generation module 307.

[0289] S1715: The clock tree generation module 307 generates a clock tree according to the clock link and the clock source device.

[0290] The clock tree generation module 307 can determine the clock tree according to the flow direction of the clock signal and in combination with the type of the device.

[0291] S1716: The clock tree generation module 307 sends the clock tree to the interface display module 301.

[0292] The clock tree generation module 307 can send the clock tree as text data such as a netlist file to the interface display module 301, or can send the clock tree as graphic data.

[0293] S1717: The interface display module 301 displays the clock tree.

[0294] The interface display module 301 displays the clock tree on the interface according to the clock tree sent by the clock tree generation module 307.

[0295] In summary, the clock tree generation system provided by the present application can identify the type of each device and the flow direction of the clock signal according to a netlist file, and can further automatically draw a clock tree. The developer can view or adjust the clock architecture of the circuit system according to the clock tree. The developer does not need to spend a lot of time drawing the clock tree, which improves the development efficiency of the circuit system.

[0296] To solve the problem that a large amount of time is consumed in manually drawing a clock tree, the application provides a clock tree generation apparatus 1800, which can automatically draw a clock tree according to the types of devices and the flow direction of clock signals identified from a netlist file and the like. Figure 18 As shown in the figure, the clock tree generation apparatus 1800 can include an acquisition unit 1810, a determination unit 1820, and a generation unit 1830.

[0297] The acquisition unit 1810 is configured to acquire the network identification of at least one network in a circuit system, the identification information of devices in the at least one network, and the connection state between the devices. The determination unit 1820 is configured to determine, according to the network identification of the at least one network, a clock network in the at least one network, the clock network being configured to output at least one clock signal. The determination unit 1830 is further configured to acquire the identification information of at least one device in the clock network and the connection relationship between the at least one device and other devices in the circuit system. The determination unit 1820 is further configured to determine, according to the identification information of the at least one device, the type of the at least one device; and determine, according to the connection relationship of the at least one device, the flow direction of the at least one clock signal in the circuit system. The generation unit 1830 is configured to generate a clock tree corresponding to the clock network according to the type of the at least one device and the flow direction of the at least one clock signal.

[0298] In some embodiments, the determination unit 1820 is further configured to determine, according to the identification information of the at least one device, a clock source device in the at least one device of the clock network, the clock source device being configured to generate a clock signal.

[0299] In other embodiments, the acquisition unit 1810 is further configured to acquire, according to the identification information of the devices in the at least one network in the circuit system and the connection state between the devices, the identification information of devices connected to the clock network. The determination unit 1820 is further configured to determine, according to the identification information of the devices connected to the clock network, a clock demand device, the clock demand device being a device consuming a clock signal.

[0300] In other embodiments, the determination unit 1820 is further configured to determine, according to the identification information of the at least one device, a clock conversion device in the at least one device of the clock network, the clock conversion device being configured to change the parameter value of a clock signal.

[0301] In other embodiments, the generation unit 1830 is further configured to generate, according to the clock source device, the clock conversion device, the clock demand device, and the flow direction of the at least one clock signal, a clock tree corresponding to the circuit system, the clock tree including the parameter value of the at least one clock signal at the pin of the clock source device, the clock conversion device, and the clock demand device.

[0302] In some embodiments, the obtaining unit 1810 is further configured to obtain device identification configuration data, the device identification configuration data comprising a correspondence between identification information of at least one device and a type of the at least one device; and the determining unit 1820 is further configured to determine the type of the at least one device according to the device identification configuration data and the identification information of the at least one device.

[0303] In some embodiments, the device identification configuration data is from a device identification database connected to the electronic device.

[0304] In some embodiments, the obtaining unit 1810 is further configured to obtain network identification configuration data, the network identification configuration data comprising a correspondence between at least one network identification and a network type; and the determining unit 1820 is further configured to determine a clock network in the at least one network according to the network identification configuration data and the network identification of the at least one network.

[0305] In some embodiments, the network identification configuration data is from a network identification database connected to the electronic device.

[0306] In some embodiments, the determining unit 1820 is further configured to determine a netlist file describing the circuit system; and the obtaining unit 1810 is further configured to parse the netlist file to obtain the network identification of the at least one network in the circuit system, the identification information of the devices in the at least one network, and the connection state between the devices.

[0307] In some embodiments, the identification information of the at least one device comprises one or more of a code, a bit number, and a keyword of the at least one device.

[0308] In some embodiments, the circuit system further comprises one or more of a power network and a bus network; the clock source device comprises one or more of a crystal oscillator, a clock oscillator, a resonant tank, a resistor-capacitor oscillator, a silicon oscillator, and an atomic clock; the clock conversion device comprises one or more of a frequency synthesizer, a frequency divider, a phase-locked loop, a direct digital frequency synthesizer, and a clock driver; and the parameter value of the clock signal comprises one or more of a frequency, a signal strength, and a phase.

[0309] In summary, the clock tree generation apparatus 1800 provided by the present application can identify the types of the devices and the flow direction of the clock signals according to the netlist file, and further automatically draw a clock tree. The developer can view or adjust the clock architecture of the circuit system according to the clock tree. The developer does not need to spend a lot of time drawing the clock tree, and the development efficiency of the circuit system is improved.

[0310] The above describes the method of the embodiments of the present application in detail. In order to better implement the above-mentioned solutions of the embodiments of the present application, the related equipment for implementing the above-mentioned solutions is also provided.

[0311] Figure 19 This is a schematic diagram of the structure of a computing device 1900 provided in this application. The computing device 1900 may be the clock tree generation device 1800 mentioned above. Figure 19 As shown, the computing device 1900 includes a processor 1910, a communication interface 1920, and a memory 1930. The processor 1910, communication interface 1920, and memory 1930 can be interconnected via an internal bus 1940, or they can communicate via wireless transmission or other means. This embodiment uses a connection via bus 1940 as an example. Bus 1940 can be a Peripheral Component Interconnect Express (PCIe) bus, an Extended Industry Standard Architecture (EISA) bus, a Unified Bus (Ubus or UB), a Compute Express Link (CXL), a Cache Coherent Interconnect for Accelerators (CCIX), etc. Bus 1940 can be divided into an address bus, a data bus, a control bus, etc. In addition to the data bus, bus 1940 can also include a power bus, a control bus, and a status signal bus. However, for clarity, all buses are labeled as bus 1940 in the figure.

[0312] Processor 1910 may consist of at least one general-purpose processor, such as a central processing unit (CPU), or a combination of a CPU and hardware chips. The aforementioned hardware chips may be application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or combinations thereof. The aforementioned PLDs may be complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), generic array logic (GALs), or any combination thereof. Processor 1910 executes various types of digital storage instructions, such as software or firmware programs stored in memory 1930, enabling computing device 1900 to provide a variety of services.

[0313] The memory 1930 is configured to store program code, and controlled by the processor 1910 to execute the processing steps of the clock tree generation method in the above embodiments. The program code can include one or more software modules, and the one or more software modules can be Figure 18 The software modules provided in the embodiments, such as the obtaining unit, the generating unit, and the determining unit: the obtaining unit is configured to obtain network identification of at least one network in a circuit system, identification information of devices in the at least one network, and connection states between the devices. The determining unit is configured to determine a clock network in the at least one network according to the network identification of the at least one network, the clock network being configured to output at least one clock signal. The obtaining unit is further configured to obtain identification information of at least one device in the clock network and connection relationships of the at least one device with other devices in the circuit system. The determining unit is further configured to determine a type of the at least one device according to the identification information of the at least one device, and determine a flow direction of the at least one clock signal in the circuit system according to the connection relationships of the at least one device. The generating unit is configured to generate a clock tree corresponding to the clock network according to the type of the at least one device and the flow direction of the at least one clock signal.

[0314] It should be noted that the embodiments can be implemented by a general physical server, for example, an ARM server or an X86 server, or a virtual machine based on a general physical server combined with an NFV technology, and the virtual machine refers to a complete computer system having complete hardware system functions, which is simulated by software and runs in a completely isolated environment, and the application does not make specific limitations.

[0315] The memory 1930 can include a volatile memory, such as a random access memory (RAM), and can also include a non-volatile memory, such as a read-only memory (ROM), a flash memory, a hard disk drive (HDD), or a solid-state drive (SSD), or a combination thereof. The memory 1930 can store program codes, and the program codes can be executed by the processor 1910 to perform the above steps S210-S250 and optional steps thereof, or the steps S401-S419 and optional steps thereof, or the steps S1501-S1518 and optional steps thereof, or the steps S1601-S1618 and optional steps thereof. Figure 2 The steps S210-S250 and optional steps thereof in the embodiments, or the steps S401-S419 and optional steps thereof, or the steps S1501-S1518 and optional steps thereof, or the steps S1601-S1618 and optional steps thereof Figure 4 The steps S401-S419 and optional steps thereof in the embodiments, or the steps S210-S250 and optional steps thereof, or the steps S1501-S1518 and optional steps thereof, or the steps S1601-S1618 and optional steps thereof Figure 15 The steps S1501-S1518 and optional steps thereof in the embodiments, or the steps S401-S419 and optional steps thereof, or the steps S210-S250 and optional steps thereof, or the steps S1601-S1618 and optional steps thereof Figure 16 The steps S1601-S1618 and optional steps thereof in the embodiments, or the steps S401-S419 and optional steps thereof, or the steps S210-S250 and optional steps thereof, or the steps S1501-S1518 and optional steps thereof Figure 17 The steps S1701-S1717 and optional steps thereof in the embodiment are not described here again.

[0316] The communication interface 1920 can be a wired interface (for example, an Ethernet interface), can be an internal interface (for example, a peripheral component interconnect express (PCIe) bus interface), a wired interface (for example, an Ethernet interface), or a wireless interface (for example, a cellular network interface or a wireless local area network interface), used for communication with other devices or modules.

[0317] Need to be explained, Figure 19 Only one possible implementation of the embodiments of the present application, in actual application, the computing device 1900 can also include more or less components, not limited here. For the content not shown or described in the embodiments of the present application, please refer to the foregoing Figure 2 、 Figure 4 、 Figure 15 、 Figure 16 and Figure 17 The related description in the embodiments, which will not be described here again.

[0318] It should be understood that, Figure 2 The computing device shown can also be a computer cluster composed of at least one server, which is not limited in the present application.

[0319] The embodiments of the present application also provide a computer readable storage medium, the computer readable storage medium stores instructions, when the instructions are run on the processor, Figure 4 、 Figure 15 、 Figure 16 、 Figure 17 or Figure 2 The method flow shown is implemented.

[0320] The embodiments of the present application also provide a computer program product, when the computer program product is run on the processor, Figure 4 、 Figure 15 、 Figure 16 、 Figure 17 or Figure 2 Figure 4 Figure 15 Figure 16 Figure 17 Figure 2 Figure 4 Figure 15 Figure 16 Figure 17 Figure 2 Figure 4 Figure 15 Figure 16 Figure 17 The method flow shown is implemented.

[0321] The above-described embodiments can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented by software, the above-described embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the processes or functions described in the embodiments of the present application are wholly or partially generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices.

[0322] The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center through wired (for example, coaxial cable, optical fiber, digital subscriber line (DSL), or wireless (for example, infrared, wireless, microwave, etc.).

[0323] The computer-readable storage medium can be any available medium accessible by a computer or a data storage device such as a server, data center, etc. containing a set of one or more available media. The available media can be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a high-density digital video disc (DVD), or a semiconductor medium. The semiconductor medium can be an SSD.

[0324] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto. Any skilled person in the art can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present application, and these modifications or replacements should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.< / lewis>

Claims

1. A method for generating a clock tree, characterized in that, Applied to electronic devices, the method includes: Obtain the network identifier of at least one network in the circuit system, as well as the identification information of the devices in the at least one network and the connection status between the devices; Based on the network identifier of the at least one network, a clock network is determined in the at least one network, the clock network being used to output at least one clock signal; Determine the identification information of at least one device in the clock network and the connection relationship between the at least one device and other devices in the circuit system; Based on the identification information of the at least one device, determine the type of the at least one device; and based on the connection relationship of the at least one device, determine the flow direction of at least one clock signal in the circuit system; and A clock tree corresponding to the circuit system is generated based on the type of the at least one device and the direction of the at least one clock signal.

2. The method according to claim 1, characterized in that, Determining the type of the at least one device based on its identification information includes: Based on the identification information of the at least one device, a clock source device is determined among the at least one devices in the clock network, the clock source device being used to generate a clock signal.

3. The method according to claim 2, characterized in that, Determining the type of the at least one device based on its identification information includes: Based on the identification information of devices in at least one network in the circuit system and the connection status between devices, obtain the identification information of devices connected to the clock network; Based on the identification information of the devices connected to the clock network, clock-demanding devices are identified, which are devices that consume clock signals.

4. The method according to claim 3, characterized in that, Determining the type of the at least one device based on its identification information includes: Based on the identification information of the at least one device, a clock conversion device is determined in at least one device of the clock network, the clock conversion device being used to change the parameter value of the clock signal.

5. The method according to claim 4, characterized in that, The step of generating a clock tree corresponding to the circuit system based on the type of the at least one device and the direction of the at least one clock signal includes: A clock tree corresponding to the circuit system is generated based on the clock source device, the clock conversion device, the clock demand device, and the flow of the at least one clock signal. The clock tree includes the parameter values ​​of the at least one clock signal at the pins of the clock source device, the clock conversion device, and the clock demand device.

6. The method according to claim 1, characterized in that, The method further includes: Obtain device identification configuration data, which includes at least one device identification information and its type correspondence; Determining the type of the at least one device based on its identification information includes: The type of the at least one device is determined based on the device identification configuration data and the identification information of the at least one device.

7. The method according to claim 6, characterized in that, The device identification configuration data comes from a device identification database connected to the electronic device.

8. The method according to claim 1, characterized in that, The method further includes: Obtain network identifier configuration data, wherein the network identifier configuration data includes at least one correspondence between network identifiers and network types; Determining the clock network in the at least one network based on the network identifier of the at least one network includes: The clock network is determined in the at least one network based on the network identifier configuration data and the network identifier of the at least one network.

9. The method according to claim 8, characterized in that, The network identifier configuration data comes from a network identifier database connected to the electronic device.

10. The method according to claim 1, characterized in that, The acquisition of the network identifier of at least one network in the circuit system, the identification information of devices in the at least one network, and the connection status between devices includes: Determine the netlist file used to describe the circuit system; The netlist file is parsed to obtain the network identifier of at least one network in the circuit system, the identification information of the devices in the at least one network, and the connection status between the devices.

11. The method according to claim 1, characterized in that, The identification information of the at least one device includes one or more of the device's code, tag number, and keywords.

12. The method according to claim 5, characterized in that, The circuit system also includes one or more power networks and bus networks; The clock source device includes one or more of a crystal oscillator, a clock oscillator, a resonant tank circuit, a resistor-capacitor oscillator, a silicon oscillator, and an atomic clock; The clock conversion device includes one or more of a frequency synthesizer, a frequency divider, a phase-locked loop, a direct digital frequency synthesizer, and a clock driver; The parameters of the clock signal include one or more of the following: frequency, signal strength, and phase.

13. A readable medium, characterized in that, The readable medium contains instructions that, when executed by the processor of the electronic device, cause the electronic device to perform the method of any one of claims 1 to 12.

14. An electronic device, characterized in that, include: Memory is used to store instructions executed by one or more processors of an electronic device; And a processor, one of the processors of the electronic device, for executing the instructions to cause the electronic device to implement the method of any one of claims 1 to 12.

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