A GPU-Accelerated Circuit Simulation Method Based on Matrix Semi-Tensor Product

Abstract

The present invention discloses a GPU-accelerated circuit simulation method based on the semi-tensor product of matrices, comprising the steps of: parsing circuit information and converting it into a semi-tensor product matrix; representing the nodes in the circuit as matrix chain expressions; randomly selecting a node and normalizing its matrix chain expression; introducing a semi-tensor product matrix encoding method and a CUDA parallel computing architecture for GPU acceleration to obtain the operation result of the matrix chain expression; extracting a temporary truth table, swapping the values in the corresponding positions of the temporary truth table according to the arrangement order of the variables to obtain the actual truth table of the node, and extracting the simulation information of the node; repeating the above steps to obtain the circuit simulation result. The method of the present invention greatly improves the circuit simulation efficiency while ensuring the correctness of the simulation result. Compared with the simulation method of the currently most performant semi-tensor product circuit simulator, the circuit simulation method of the present invention has a speed improvement of about 7.79 times in terms of calculation speed.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and particularly to a GPU-accelerated circuit simulation method based on the semi-tensor product of matrices. Background Art

[0002] A fast and efficient logic emulator is a key component of modern logic synthesis tools and plays an important role in tasks such as combinational circuit equivalence verification, equivalence class classification in technology-independent optimization, and extraction of remapping functions. As the circuit scale grows, the simulation execution time becomes increasingly critical. In addition, with the development of advanced technologies, various different logic representation methods have emerged in logic synthesis, such as AIG, XMG, and k-LUT networks. A logic simulation method that can adapt to these different representation methods will have better scalability.

[0003] In recent years, the development of circuit simulation methods has been closely intertwined with the field of logic synthesis, and significant progress has been made especially in improving design efficiency, optimizing algorithms, and integrating intelligent technologies. To meet the requirements of large-scale circuit simulation, existing methods have made remarkable progress in reducing computational complexity, such as using sparse matrix solving and model reduction techniques. For example, the KLU algorithm can accelerate matrix solving and significantly reduce the gate-level netlist simulation time. In addition, parallel computing and heterogeneous hardware acceleration (such as GPUs and FPGAs) enable distributed execution of matrix calculations, thereby further improving the simulation speed. Despite these advancements, a key bottleneck still exists: traditional simulation methods are difficult to fully utilize the computational advantages of matrix theory because there is a gap between the logic representation and the matrix representation.

[0004] In recent years, simulation methods based on the semi-tensor product (STP) have received extensive attention in the fields of logic circuit modeling, state space analysis, and automatic design optimization. As a mathematical tool, STP can efficiently handle high-dimensional logic systems by transforming Boolean logic operations into matrix operations, providing new ideas for the analysis and synthesis of complex circuits. The core advantage of using the STP simulation method is that it represents logic functions as matrices and performs Boolean operations through matrix multiplication. This method can efficiently handle high-dimensional systems, but as the circuit scale grows, it will lead to exponential memory overhead. The continuous expansion of internal matrices not only causes memory shortage problems but also significantly increases the calculation time. Summary of the Invention

[0005] To solve the problem that STP is inefficient or even unable to calculate due to the excessive matrix scale in logic synthesis applications, the present invention provides a GPU-accelerated circuit simulation method based on the semi-tensor product of matrices that significantly improves the speed while ensuring the correctness of the simulation results, and this method greatly improves the circuit simulation efficiency.

[0006] The technical solution adopted by the present invention to solve the above technical problems is as follows: A GPU-accelerated circuit simulation method based on the semi-tensor product of matrices, comprising the following steps:

[0007] Step 1: Parse the bench file containing circuit information, define a data set mtx to represent the relationship between nodes in the bench file, and convert the circuit information into a semi-tensor product matrix;

[0008] Step 2: According to the relationship between nodes in the circuit and based on the semi-tensor product matrix representing the circuit information, represent the nodes in the circuit as a matrix chain expression composed of the data set mtx and the original circuit input PI;

[0009] Step 3: Randomly select a node in the bench file, and perform normalization processing on the matrix chain expression represented by this node to obtain a normalized matrix chain expression;

[0010] Step 4: Introduce a semi-tensor product matrix encoding method and a CUDA parallel computing architecture for GPU acceleration, distribute the matrices in the normalized matrix chain expression to multiple threads of the GPU for semi-tensor product matrix parallel operations, and obtain the operation result of the matrix chain expression, which is represented as a logic matrix. According to the operation characteristics of the semi-tensor product, the first row value of the logic matrix represented by the operation result represents the truth table of the node randomly selected in Step 3;

[0011] Step 5: Extract the first row value of the logic matrix represented by the operation result as a temporary truth table, obtain the weights of different variables in the temporary truth table, calculate the correspondence between the values in the temporary truth table and the weights of different variables, and exchange the values in the corresponding positions of the temporary truth table according to the arrangement order of the variables to obtain the actual truth table of this node, and extract the simulation information of this node according to the actual truth table;

[0012] Step 6: Repeat Step 3 to Step 5 until all nodes in the bench file are traversed, obtain the simulation information of the entire bench file, that is, obtain the circuit simulation result.

[0013] Preferably, the semi-tensor product matrix obtained by conversion in Step 1 is denoted as M x , which satisfies the following formula (1) or (2) or (3) or (4) or (5):

[0014]

[0015] In formula (1), M n represents the unary logical operation "NOT". In formulas (2) to (5), M c , M d, M i , M e respectively represent the binary logical operations "AND", "OR", "IMPLICATION" and "EQUIVALENCE".

[0016] Preferably, in step 3, the process of normalization is as follows: First, find the same-named variable of any variable in the matrix chain expression. After finding the first same-named variable and the second same-named variable, delete the first same-named variable in the matrix chain expression, and insert a power-reducing matrix at the position before the second same-named variable. For the matrix between the first same-named variable and the second same-named variable, according to the pseudo-commutativity of the semi-tensor product, if the matrix is a logical matrix, insert identity matrices of different dimensions in the middle of the matrix chain expression; if the matrix is a variable matrix, insert a permutation matrix in the middle of the matrix chain expression; repeat the above operations until there are no same-named variables in the matrix chain expression, and then move all variables with a quantity of 1 to the rightmost side of the matrix chain expression to obtain a normalized matrix chain expression.

[0017] More preferably, in step 3, the specific process of normalization is as follows:

[0018] Step 3.1: Find the first same-named variable of the first variable in the matrix chain expression and determine its position. Then, search for the second same-named variable from the position of the first same-named variable backward. If the second same-named variable is found, delete the first same-named variable in the matrix chain expression, and at the same time insert a power-reducing matrix Mr at the position before the second same-named variable, and enter step 3.2; if the second same-named variable is not found, repeat the above operations until the first same-named variable and the second same-named variable of a certain variable are found in the matrix chain expression, and enter step 3.2;

[0019] Step 3.2: Process the matrix between the first same-named variable and the second same-named variable of the same variable. According to the pseudo-commutativity of the semi-tensor product, if the matrix is a logical matrix, for the logical matrix that performs a Kronecker product with an identity matrix, multiply the dimension of the identity matrix by 2. If there is no identity matrix before the logical matrix to perform a Kronecker product operation, add an identity matrix I2 with a dimension of 2 before the logical matrix; if the matrix is a variable matrix, insert a permutation matrix Mw in the middle of the matrix chain expression;

[0020] Step 3.3: Repeat steps 3.1 to 3.2 until there are no same-named variables in the matrix chain expression, that is, after the quantity of all variables in the matrix chain expression is 1, move all variables with a quantity of 1 to the rightmost side of the matrix chain expression according to the existing process of the semi-tensor product canonical form, and calculate the final result of the semi-tensor product of all logical matrices and all variable matrices to obtain a normalized matrix chain expression.

[0021] Preferably, the encoding rule of the semi-tensor product matrix encoding method introduced in step 4 is as follows: a logical matrix A ∈ M with dimensions m×n is m×n encoded as a row vector X in the form of [x(0), x(1),..., x(n)], where the value of x(0) is equal to m, representing the number of rows of matrix A. According to the characteristic that only one element in each column of the semi-tensor product matrix is 1 and the rest are 0, x(i) is used to represent the row number of the element "1" in the i-th column of matrix A minus 1. On the basis of the above encoding rule, a CUDA parallel computing architecture is introduced for GPU acceleration. The matrices in the normalized matrix chain expression are distributed among multiple threads of the GPU for parallel semi-tensor product matrix operations. According to the number of rows and columns of the matrices in the matrix chain expression, sub-matrix calculation tasks are dynamically allocated among the basic units inside the GPU to perform parallel semi-tensor product matrix operations, and the operation result of the matrix chain expression is obtained. This operation result is represented as a logical matrix. According to the operation characteristics of the semi-tensor product, the first row value of the logical matrix represented by this operation result is the truth table of the randomly selected node in step 3.

[0022] Preferably, the specific process of step 5 is as follows: extract the first row value of the logical matrix represented by this operation result as a temporary truth table, obtain the binary relationship between each variable in the temporary truth table and the position of the original variable in the temporary truth table. Then, for each variable, it is rearranged according to the given index. Next, according to the order of the rearranged variables, the values in the temporary truth table are sorted according to the binary relationship, and finally, a truth table identical to the calculation result of the existing semi-tensor product canonical form is obtained.

[0023] Compared with the prior art, the present invention has the following advantages:

[0024] 1. The GPU-accelerated circuit simulation method based on matrix semi-tensor product of the present invention is a circuit simulation method based on matrix semi-tensor product with circuit information as input. On the premise of ensuring the correctness of the simulation result, it converts the Boolean logic calculation in circuit simulation into mathematical calculation. By combining the logical operation of matrix semi-tensor product with faster calculation speed, a new method for normalizing the matrix chain expression is introduced to accelerate the solution speed of the semi-tensor product. Variables with the same name are preferentially merged to reduce the scale of the identity matrix generated during the normalization process of the matrix chain expression, thereby effectively reducing the overall complexity during matrix calculation. A truth table exchange method applicable to the operation result of the semi-tensor product is introduced. The method of exchanging the truth table is used to replace inserting the exchange matrix and performing semi-tensor product calculation. By exchanging the positions of the truth tables, the number of new matrices generated during the normalization process is reduced, thereby shortening the length of the matrix chain, reducing the number and complexity of semi-tensor product operations, improving the operation efficiency, achieving the effect of accelerating the circuit simulation speed, and greatly improving the circuit simulation efficiency.

[0025] 2. The circuit simulation method of the present invention introduces the semi-tensor product matrix encoding method and the CUDA parallel computing architecture for GPU acceleration. By utilizing the operation characteristics of the semi-tensor product and taking CUDA as the acceleration engine, the multiple threads of the GPU are used to quickly obtain the calculation results, which can further improve the operation efficiency of the semi-tensor product and has more advantages in terms of memory and speed. In GPU acceleration, according to the characteristics of the semi-tensor product calculation of matrices and the conventional matrix multiplication, the matrices in the normalized matrix chain expression are distributed among multiple threads of the GPU for semi-tensor product matrix parallel operations, and the operation results of the matrix chain expression are quickly obtained.

[0026] 3. Compared with the simulation method of the currently optimal semi-tensor product circuit emulator, the circuit simulation method of the present invention has increased the calculation speed by about 7.79 times, can effectively reduce the circuit simulation time, provides a new research idea for the design of circuit simulation methods, and has strong practical significance in the development of circuit simulation method design and the application of circuit simulation to logic synthesis, etc. Description of the Drawings

[0027] Figure 1 is a calculation example of matrix semi-tensor product multiplication;

[0028] Figure 2 is the matrix chain expression of the nodes in the circuit of the embodiment;

[0029] Figure 3 is the matrix chain expression obtained from the existing semi-tensor product canonical form;

[0030] Figure 4 is the matrix chain expression obtained by normalizing the method of the present invention;

[0031] Figure 5 is an example of the semi-tensor product matrix encoding method introduced by the method of the present invention;

[0032] Figure 6 are the temporary truth table obtained by the method of the present invention and the finally obtained truth table;

[0033] Figure 2 In (a) of, 1, 2, 3, 4, 5 represent the inputs of the circuit, po0 and po1 represent the outputs of the circuit, the AND node represents logical AND, the solid line with a single arrow represents the connection relationship of the nodes, and the dashed line with a single arrow represents logical NOT. Detailed Embodiment

[0034] The following further describes the present invention in detail with reference to the embodiments of the drawings.

[0035] Figure 1 is a calculation example of matrix semi-tensor product multiplication, where A ∈ M m×n and B ∈ Mp×q , The symbol ⊗ represents the calculation symbol of the semi - tensor product, · represents the conventional matrix multiplication, and I t represents the identity matrix of dimension t, where t is the least common multiple of n and p. is the Kronecker product of two matrices with arbitrary dimensions. The Kronecker product is an operation between two matrices of arbitrary sizes, denoted as If A ∈ M m×n and B ∈ M p×q , the Kronecker product is a block matrix of size mn×pq, and its definition formula is where a ij represents the element in the i - th row and j - th column of matrix A. Through the Kronecker product, two matrices with mismatched dimensions can be expanded to dimensions where conventional matrix multiplication can be performed, thus realizing matrix multiplication between matrices of arbitrary dimensions.

[0036] Example: Taking the circuit shown in (a) of Figure 2 as an example, the circuit simulation method based on matrix semi - tensor product accelerated by the GPU of the present invention is used for simulation, including the following steps:

[0037] Step 1: Parse the bench file containing circuit information, define the data set mtx to represent the relationships between nodes in the bench file, and convert the circuit information into a semi - tensor product matrix M x , which satisfies the following formula (1) or (2) or (3) or (4) or (5):

[0038]

[0039] In formula (1), M n represents the unary logical operation "NOT". In formulas (2) - (5), M c , M d , M i , M e represent the binary logical operations "AND", "OR", "IMPLICATION" and "EQUIVALENCE" respectively.

[0040] Step 2: According to the relationships between nodes in the circuit and based on the semi - tensor product matrix representing the circuit information, represent the nodes in the circuit as a matrix - chain expression composed of the data set mtx and the original circuit input PI, as shown in (b) of Figure 2 .

[0041] Step 3: Randomly select a node in the bench file and perform normalization processing on the matrix - chain expression represented by this node. The specific process is as follows:

[0042] Step 3.1. The existing semi-tensor product canonical form directly moves all variables to the far right of the matrix chain expression, and then, according to the sorting of the variables, exchanges the positions of the variables by inserting permutation matrices, and at the same time reduces the power of the variables with power reduction matrices. The obtained result is as shown in Figure 3 ; Different from the existing semi-tensor product canonical form, we find the first same-name variable of the first variable in the matrix chain expression and determine its position. Then, starting from the position of the first same-name variable, we search for the second same-name variable backward. If the second same-name variable is found, we delete the first same-name variable in the matrix chain expression, and at the same time insert the power reduction matrix Mr in front of the second same-name variable, and enter Step 3.2; If the second same-name variable is not found, we repeat the above operations until the first same-name variable and the second same-name variable of a certain variable are found in the matrix chain expression, and then enter Step 3.2;

[0043] Step 3.2. Process the matrices between the first same-name variable and the second same-name variable of the same variable. According to the pseudo-commutativity of the semi-tensor product, if the matrix is a logic matrix, for the logic matrix that is Kronecker product with the identity matrix, multiply the dimension of the identity matrix by 2. If there is no identity matrix in front of the logic matrix for Kronecker product operation, add an identity matrix I2 with dimension 2 in front of the logic matrix; If the matrix is a variable matrix, insert a permutation matrix Mw in the middle of the matrix chain expression.

[0044] Step 3.3. Repeat Step 3.1 to Step 3.2 until there are no same-name variables in the matrix chain expression, that is, after the number of all variables in the matrix chain expression is 1, according to the process of the existing semi-tensor product canonical form, move all variables with the number of 1 to the far right of the matrix chain expression, and calculate the final result of the semi-tensor product of all logic matrices and all variable matrices, and obtain the normalized matrix chain expression as shown in Figure 4 ; In

[0045] Figure 4 , the first row is the result of merging the same-name variables, and the second row is the final result of moving all variables with the number of 1 to the far right of the matrix chain expression. Comparing the result of the second row in Figure 4 with Figure 3 , it can be clearly seen that after adopting the method of the present invention, the dimension of the largest identity matrix is reduced from 32 to 8, greatly reducing the matrix dimension in calculation and avoiding large-scale matrix calculations.

[0046] Step 4. Introduce a semi-tensor product matrix encoding method, and its encoding rule is: For a logic matrix A ∈ M with dimension m×n m×nEncoded as a row vector $\mathbf{X}=[x(0),x(1),\cdots,x(n)]$, where the value of $x(0)$ is equal to $m$, representing the number of rows of matrix $\mathbf{A}$, and according to the characteristic that only one element in each column of the semi-tensor product matrix is 1 and the rest are 0, $x(i)$ represents the row number of the element "1" in the $i$-th column of matrix $\mathbf{A}$ minus 1. Figure 5 This is an example of the semi-tensor product matrix encoding method introduced by the method of the present invention. For a logical matrix $\mathbf{A}\in\mathcal{M}$ of dimension $m\times n$ m×n After encoding using the semi-tensor product matrix encoding method introduced by the method of the present invention, the matrix can completely contain all the information of the original matrix, and the space complexity is reduced by $n$ times.

[0047] Matrix operation is a common compute-intensive task. By dividing the matrix into small blocks or sub-matrices, not only can memory usage be optimized, duplicate data access be reduced, but also the utilization of memory bandwidth and the degree of parallelism of computation can be improved. This makes the GPU an ideal choice for performing large-scale matrix multiplication. And there are a large number of matrix operations in the STP calculation process, such as Kronecker product and conventional matrix multiplication, which makes the STP calculation a GPU-friendly calculation. Utilizing multiple cores to calculate STP distributively can effectively improve the calculation speed, and introducing the GPU can effectively reduce the time required for circuit simulation. Therefore, based on the above encoding rules, the CUDA parallel computing architecture is introduced for GPU acceleration. The matrices in the normalized matrix chain expression are distributed among multiple threads of the GPU for semi-tensor product matrix parallel operation. According to the number of rows and columns of the matrices in the matrix chain expression, the sub-matrix calculation tasks are dynamically allocated among the basic units inside the GPU to perform semi-tensor product matrix parallel operation to obtain the operation result of the matrix chain expression. The operation result is represented as a logical matrix. According to the operation characteristics of the semi-tensor product, the first row value of the logical matrix represented by the operation result represents the truth table of the randomly selected node in step 3. The above GPU acceleration method can improve the efficiency of the STP calculation process. In large-scale matrix operations such as Kronecker product operation and matrix multiplication, its inherent parallelism makes STP particularly suitable for GPU acceleration. During the entire STP calculation process, on the one hand, all matrices in the operation process have a high sparsity, and encoding can greatly reduce the memory and the number of threads opened by the GPU; on the other hand, the matrices participating in the operation all have certain characteristics, and traditional matrix compression methods (such as CSR, COO, etc.) cannot well reflect these characteristics. Therefore, we propose to encode the matrix and then use the GPU to perform STP calculation, and this method has more advantages in terms of memory and speed.

[0048] Step 5: Extract the first row values of the logical matrix represented by the operation result as the temporary truth table, obtain the weights of different variables in the temporary truth table, calculate the corresponding relationship between the values in the temporary truth table and the weights of different variables, and exchange the values in the temporary truth table at the corresponding positions according to the arrangement order of the variables to obtain the actual truth table of this node. Extract the simulation information of this node according to the actual truth table.

[0049] The specific process of Step 5 is as follows: Extract the first row values of the logical matrix represented by the operation result as the temporary truth table, obtain the binary relationship between each variable in the temporary truth table and the position of the original variable in this temporary truth table. Then, rearrange each variable according to the given index. Next, according to the arranged variable order, sort the values in the temporary truth table according to the binary relationship. Finally, obtain a truth table that is the same as the calculation result of the existing semi-tensor product canonical form.

[0050] Through the method of Step 5 of the present invention, the final result is directly rearranged through the corresponding relationship between the temporary truth table and the variables, avoiding complex matrix operations and greatly saving resource consumption. The temporary truth table obtained through the method of Step 5 above and the finally obtained truth table are shown in Figure 6 , Figure 6 In it, the left table is the temporary truth table before the exchange, and the right table is the finally obtained truth table after the exchange. In the left table, a, b, and c respectively represent the truth table results obtained before the variables x1, x2, and x3 are exchanged. In the right table, a, b, and c respectively represent the truth table results obtained after the variables x1, x2, and x3 are exchanged. The truth table result obtained after this exchange is the same as the calculation result of the existing semi-tensor product canonical form.

[0051] Step 6: Repeat Steps 3 to 5 until all nodes in the bench file are traversed, and obtain the simulation information of the entire bench file, that is, obtain the circuit simulation result.

[0052] The simulation method of the currently optimal semi-tensor product circuit emulator is LS (H. Pan, R. Zhang, Y. Xia, L. Wang, F. Yang, X. Zeng, and Z. Chu, "A semi-tensor product based circuit simulation for sat-sweeping," in 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2024, pp. 1-6.). Performance tests were conducted on LS, the circuit simulation method of the present invention (i.e., the method with GPU), and the method without GPU acceleration (i.e., the method without GPU, which is different from the circuit simulation method of the present invention in that it does not use GPU acceleration) to measure the simulation time of these three circuit simulation methods for different test cases. The performance test comparison results of the three circuit simulation methods are shown in Table 1. As can be seen from Table 1, compared with the simulation method of the currently optimal semi-tensor product circuit emulator, the GPU-accelerated circuit simulation method based on matrix semi-tensor product proposed in the present invention has increased the calculation speed by approximately 7.79 times.

[0053] Table 1

[0054]

Claims

1. A GPU-accelerated circuit simulation method based on the semi-tensor product of matrices, characterized in that It includes the following steps: Step 1: Parse the bench file containing circuit information, define the data set mtx to represent the relationships between nodes in the bench file, and convert the circuit information into a semi-tensor product matrix; Step 2: According to the relationships between nodes in the circuit and based on the semi-tensor product matrix representing the circuit information, represent the nodes in the circuit as a matrix chain expression composed of the data set mtx and the original circuit input PI; Step 3: Randomly select a node in the bench file, and perform normalization processing on the matrix chain expression represented by this node to obtain a normalized matrix chain expression; Step 4: Introduce the semi-tensor product matrix encoding method and the CUDA parallel computing architecture for GPU acceleration, distribute the matrices in the normalized matrix chain expression to multiple threads of the GPU for semi-tensor product matrix parallel operations, and obtain the operation result of the matrix chain expression, which is represented as a logic matrix; The encoding rule of the semi-tensor product matrix encoding method introduced in step 4 is as follows: A logical matrix A ∈ M with dimensions m×n is encoded as a row vector X in the form of [x(0), x(1),..., x(n)], where the value of x(0) is equal to m, representing the number of rows of matrix A. According to the characteristic that only one element in each column of the semi-tensor product matrix is 1 and the rest are 0, x(i) represents the row number of the element "1" in the i-th column of matrix A minus 1. On the basis of the above encoding rule, a CUDA parallel computing architecture is introduced for GPU acceleration. The matrices in the normalized matrix chain expression are distributed among multiple threads of the GPU for parallel semi-tensor product matrix operations. According to the number of rows and columns of the matrices in the matrix chain expression, sub-matrix calculation tasks are dynamically allocated among the basic units inside the GPU to perform parallel semi-tensor product matrix operations, and the operation result of the matrix chain expression is obtained. This operation result is represented as a logical matrix. According to the operation characteristics of the semi-tensor product, the first row value of the logical matrix represented by this operation result is the truth table of the randomly selected node in step 3; m×n ​ Step 5: Extract the first row value of the logic matrix represented by this operation result as a temporary truth table, obtain the weights of different variables in the temporary truth table, calculate the corresponding relationship between the values in the temporary truth table and the weights of different variables, and exchange the values in the corresponding positions of the temporary truth table according to the arrangement order of the variables to obtain the actual truth table of this node, and extract the simulation information of this node according to the actual truth table; Step 6: Repeat Step 3 to Step 5 until all nodes in the bench file are traversed, obtain the simulation information of the entire bench file, that is, obtain the circuit simulation result.

2. The GPU-accelerated circuit simulation method based on the semi-tensor product of matrices according to claim 1, characterized in that Denote the semi-tensor product matrix obtained by the conversion in Step 1 as M x , which satisfies the following formula (1) or (2) or (3) or (4) or (5): In formula (1), M n represents the unary logical operation "NOT". In formulas (2) to (5), M c , M d , M i , M e represent the binary logical operations "AND", "OR", "IMPLIES", and "EQUIVALENT", respectively.

3. The GPU-accelerated circuit simulation method based on the semi-tensor product of matrices according to claim 1, wherein In Step 3, the process of normalization processing is as follows: First, find the same-named variable of any variable in the matrix chain expression. After finding the first same-named variable and the second same-named variable, delete the first same-named variable in the matrix chain expression, and insert a power-down matrix at the position before the second same-named variable. For the matrices between the first same-named variable and the second same-named variable, according to the pseudo-commutativity of the semi-tensor product, if this matrix is a logic matrix, insert identity matrices of different dimensions in the middle of the matrix chain expression; If this matrix is a variable matrix, insert a transposition matrix in the middle of the matrix chain expression; repeat the above operations until there are no same-named variables in the matrix chain expression, and then move all variables with a quantity of 1 to the far right of the matrix chain expression to obtain a normalized matrix chain expression.

4. The GPU-accelerated circuit simulation method based on the semi-tensor product of matrices according to claim 3, wherein In Step 3, the specific process of normalization processing is as follows: Step 3.1: Find the first same-named variable of the first variable in the matrix chain expression and determine the position of the first same-named variable. Then, start searching for the second same-named variable from the position of the first same-named variable. If the second same-named variable is found, delete the first same-named variable in the matrix chain expression, and at the same time insert a power-down matrix Mr at the position before the second same-named variable, and enter Step 3.2; if the second same-named variable is not found, repeat the above operations until the first same-named variable and the second same-named variable of a certain variable are found in the matrix chain expression, and enter Step 3.2; Step 3.

2. Process the matrix between the first and second same-named variables of the same variable. According to the pseudo-commutativity of the semi-tensor product, if the matrix is a logical matrix, for the logical matrix that is Kronecker product with the identity matrix, multiply the dimension of the identity matrix by 2. If there is no identity matrix before the logical matrix for Kronecker product operation, add an identity matrix I2 with dimension 2 before the logical matrix; if the matrix is a variable matrix, insert the permutation matrix Mw in the middle of the matrix chain expression. Step 3.

3. Repeat Step 3.1 to Step 3.2 until there are no same-named variables in the matrix chain expression, that is, after the number of all variables in the matrix chain expression is 1, move all variables with the number of 1 to the rightmost of the matrix chain expression according to the existing semi-tensor product canonical form process, and calculate the final result of the semi-tensor product of all logical matrices and all variable matrices to obtain the normalized matrix chain expression.

5. The GPU-accelerated circuit simulation method based on the semi-tensor product of matrices according to claim 1, characterized in that, The specific process of Step 5 is as follows: Extract the first row value of the logical matrix represented by the operation result as the temporary truth table, obtain the binary relationship between each variable in the temporary truth table and the position of the original variable in the temporary truth table. Then, rearrange each variable according to the given index, and sort the values in the temporary truth table according to the binary relationship according to the rearranged variable order, and finally obtain a truth table that is the same as the calculation result of the existing semi-tensor product canonical form.

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