Method for controlling display screen and display driving circuit and main processor thereof

Abstract

The invention discloses a method for controlling a display screen and a display driving circuit and a main processor thereof. The method is used for a display driving circuit and comprises the following steps of: starting timing in a time interval for receiving first frame display data so as to generate a timing result; determining whether a timeout occurs according to the timing result; and outputting a control signal to instruct a main processor to transmit second frame display data while the timeout occurs.

Description

Technical Field

[0001] The present invention relates to a method for controlling a display screen, and more particularly to a method for controlling a display screen by using multi-frequency display (MFD) and adaptive refresh panel (ARP) timing. Background Art

[0002] In a display system, an application processor (AP) can transmit display data to a display driving circuit through a Mobile Industry Processor Interface (MIPI). There are two common transmission modes on the Mobile Industry Processor Interface: command mode and video mode. Most of the existing multi-frequency display (MFD) specifications are developed in the command mode. Among them, the display driving circuit is equipped with a frame buffer for storing display data from the application processor. However, the prior art does not plan the application of multi-frequency display for the video mode without a random access memory (RAM). Summary of the Invention

[0003] Therefore, the main object of the present invention is to propose a method for controlling a display screen by using multi-frequency display (MFD) for the video mode, and at the same time adopting the timing scheme of an adaptive refresh panel (ARP) to achieve the purpose of power saving.

[0004] An embodiment of the present invention discloses a method for controlling a display screen for a display driving circuit. The method includes the following steps: starting timing within a time interval for receiving a first frame of display data to generate a timing result; judging whether a timeout occurs according to the timing result; and outputting a control signal to instruct a main processor to transmit a second frame of display data when the timeout occurs.

[0005] Another embodiment of the present invention discloses a display driving circuit for controlling a display screen. The display driving circuit is used to start timing within a time interval for receiving a first frame of display data to generate a timing result; judge whether a timeout occurs according to the timing result; and output a control signal to instruct a main processor to transmit a second frame of display data when the timeout occurs.

[0006] Another embodiment of the present invention discloses a method for controlling a display screen, which is used for a main processor. The method includes the following steps: transmitting a first frame of display data to a display driving circuit for driving the display screen; after transmitting the first frame of display data, receiving a control signal from the display driving circuit; and transmitting a second frame of display data in response to the control signal.

[0007] Another embodiment of the present invention discloses a main processor for controlling a display screen. The main processor is used to transmit a first frame of display data to a display driving circuit for driving the display screen; after transmitting the first frame of display data, receive a control signal from the display driving circuit; and transmit a second frame of display data in response to the control signal. Description of the Drawings

[0008] Figure 1 Shows the refresh operations on 4 consecutive image frames to achieve different frame rates in different regions.

[0009] Figure 2 Is a schematic diagram of an MFD operation of a display system in command mode.

[0010] Figure 3 Is a schematic diagram of an MFD operation of another display system in video mode.

[0011] Figure 4 Shows the basic timing of MFD applied to video mode.

[0012] Figure 5 Shows the timing of MFD performed at variable frame rates.

[0013] Figure 6 Is a waveform diagram of a display control timing according to an embodiment of the present invention.

[0014] Figure 7 Shows the detailed timing of the display driving circuit switching from MFD mode to ARP mode.

[0015] Figure 8 Is a waveform diagram of another display control timing according to an embodiment of the present invention.

[0016] Figure 9 Shows another implementation of switching from MFD mode to ARP mode.

[0017] Figure 10 Shows another implementation of switching from ARP mode to MFD mode.

[0018] Figure 11 Shows that the display driving circuit forces full-screen refresh at a high frequency within multiple frames after entering MFD mode.

[0019] Figure 12 It shows that the display driving circuit controls the refresh frequency in some regions by using the mechanism of sequential frequency reduction in the MFD mode.

[0020] Figure 13 It shows the timing diagram of the main processor transmitting partial display data to the display driving circuit in the video mode.

[0021] Figure 14 It shows that in another alternative embodiment, the main processor stops sending the horizontal synchronization signal.

[0022] Figure 15 It shows the multi-frame rate control combining the vertical direction and the horizontal direction.

[0023] Figure 16 It shows the MFD operation integrating the ARP mode.

[0024] Figure 17 It is the flowchart of the control process of the first embodiment of the present invention.

[0025] Figure 18 It is the flowchart of the control process of another embodiment of the present invention.

[0026] Among them, the reference numerals are explained as follows:

[0027] F1 to F4 Image frames

[0028] A1 to A4 Regions

[0029] 20, 30 Display systems

[0030] 202, 302 Main processors

[0031] 204, 304 Display driving circuits

[0032] 206, 306 Display screens

[0033] 212, 312 Receiving circuits

[0034] 214 Memories

[0035] 216, 316 Processing circuits

[0036] 218, 318 Output driving circuits

[0037] VS Vertical synchronization signal

[0038] HS Horizontal synchronization signal

[0039] TE Control signal

[0040] EM Light emission control signal

[0041] CMD Instruction

[0042] VBP Vertical Back Porch

[0043] VFP Vertical Front Porch

[0044] DAT1 - DAT7 Display Data

[0045] DAT1P - DAT5P Partial Display Data

[0046] VFP_EXT Extended Vertical Front Porch Interval

[0047] 170, 180 Control Flow

[0048] 1702 - 1706, 1802 - 1806 Steps Detailed Implementation Manner

[0049] In the present invention, a multi - frequency display (MFD) capable of partial refresh can be implemented in the video mode of the Mobile Industry Processor Interface (MIPI). To reduce power consumption and be closer to the application of the command mode, when the main processor does not update the image, the frequency of sending images by the Mobile Industry Processor Interface can be reduced, achieving a power - saving mode where the full - screen display frequency drops to an extremely low frame rate (such as 1 Hz). The present invention can combine with the Adaptive Refresh Panel (ARP) mode of video transmission to achieve an automatic switching behavior and complete the power - saving timing control on the Mobile Industry Processor Interface.

[0050] In an embodiment of the present invention, the automatic switching of the MFD and ARP timings does not require the main processor to send instructions. As long as the frequency of the main processor sending images drops to a certain extent, it can trigger a timeout. According to the judgment of the timeout, the display driving circuit can output a control signal to the main processor to enter the ARP mode and initiate the operation of full - screen frequency reduction. When the main processor needs to update the screen, it can immediately adopt the MFD operation to perform full - screen refresh or partial - refresh display, so as to achieve the advanced power - saving application function of a display driving circuit without a memory in combination with MFD control.

[0051] A simple description of MFD is as follows. The traditional variable frame rate mechanism adjusts the frame rate of the full screen, that is, all pixels on the display screen must be refreshed simultaneously or not refreshed simultaneously during a frame period allocated for displaying a frame of the picture. However, to meet the applications where there are both dynamic images and static images on the screen, the display screen is allowed to refresh only some pixels during a frame period, which is the basic mechanism of MFD.

[0052] Figure 1 illustrates the refresh operations on four consecutive image frames F1 to F4 to achieve different frame rates in different regions A1 to A4. Based on the frame rate configuration on the display screen, image frame F1 is a full refresh while image frames F2 to F4 are partial refreshes. More specifically, in image frames F2 and F4, regions A2 and A3 are assigned as static image regions, and their scan signals are locked, so the corresponding pixels are not refreshed, and the panel refresh is performed in regions A1 and A4 assigned as dynamic image regions. In image frame F3, region A3 is assigned as a static image region, and its scan signal is locked, so the corresponding pixels are not refreshed, and the panel refresh is performed in regions A1, A2, and A4 assigned as dynamic image regions. Assuming the base frame rate of the panel is 120 Hz, the refresh operations can be repeated in a series of consecutive image frames in the Figure 1 shown assignment manner to achieve lower frame rates, such as 60 Hz and 30 Hz.

[0053] As Figure 1 shown, the display screen can be divided into four regions A1 to A4 with their respective frame rates. In fact, the display screen can be divided in any appropriate manner according to the image content. In the case where some regions of some image frames do not need to be refreshed, the corresponding gate lines can be locked at a level that can turn off the pixels, so that the display data cannot be input to refresh the pixels; other regions are refreshed normally. In this way, a high frame rate (such as 120 Hz) can be used for display in the dynamic image region to maintain good image quality, while in the static image region, a lower frame rate refresh (such as 60 Hz, 30 Hz, or even 1 Hz, etc.) is used to achieve the purpose of power saving.

[0054] As described above, the currently common MFD specifications are all developed in the command mode, which is applied to a display driving circuit equipped with a frame buffer. Figure 2 is a schematic diagram of a display system 20 performing MFD operations in the command mode. The display system 20 includes a main processor 202, a display driving circuit 204, and a display screen 206. The main processor 202 can be a core processor of the display system 20 and can serve as a video source or video providing unit to provide display data for the display screen 206 to perform display. In one embodiment, the main processor 202 can be an application processor (AP) of a mobile phone or a central processing unit (CPU) of a computer. And those skilled in the art should understand that the main processor mentioned in this specification represents any type of processor or processing device that can be used to control display operations and can be implemented in any way.

[0055] The display driving circuit 204 can be used to process display data and convert the display data into data voltages for output to the pixels on the display screen 206. In one embodiment, the display driving circuit 204 can be implemented in an integrated circuit (IC) to implement a display driver integrated circuit (DDIC). Those skilled in the art should understand that the display driving circuit mentioned in this specification represents a driving circuit that can be used to drive a display screen and can be implemented in any manner.

[0056] As Figure 2 shown, the display driving circuit 204 includes a receiving circuit 212, a memory 214, a processing circuit 216, and an output driving circuit 218. The receiving circuit 212 can receive display data from the main processor 202 through the Mobile Industry Processor Interface and receive instructions (such as the "0x2C" instruction) for writing data to the frame buffer from the main processor 202, where the "0x2C" instruction is an instruction defined by the Mobile Industry Processor Interface specification for writing data to the frame buffer, and the frame buffer can be implemented in the memory 214. Examples of the memory 214 can include random access memory (RAM), but are not limited thereto. The processing circuit 216 can be used to process and adjust the display data to meet various purposes, such as improving visual effects and / or enhancing image quality. The output driving circuit 218 can output display data voltages to the display screen 206 and output corresponding gate / light control signals to turn on the corresponding pixels so that they can receive the display data voltages.

[0057] The display screen 206 can be any type of display device, which can be an organic light emitting diode (OLED) panel, a liquid crystal display (LCD) panel, or any other panel that can perform display by receiving scan control, but is not limited thereto.

[0058] When the main processor 202 transmits display data to the display driving circuit 204, the display data can be written to the frame buffer inside the memory 214. Based on the display data stored in the frame buffer, the display driving circuit 204 can use an internal clock to independently control the panel refresh timing to perform full-screen frame rate conversion or the timing control of MFD. Through the panel refresh timing of the display driving circuit 204, the output driving circuit 218 can output display data voltages to the display screen 206 at a predetermined time point and correspondingly output gate control signals to the gate on array (GOA) circuit of the display screen 206. At Figure 2In the example, the dynamic video area near the top can be displayed at a higher frame rate (e.g., 120 Hz), while other areas can display static images at a reduced frequency of 1 Hz to save power, that is, refreshed once every 120 frames.

[0059] However, to reduce circuit costs, the display system can be changed to use a display driver circuit without a memory in conjunction with the video mode of the Mobile Industry Processor Interface to send images. For example, Figure 3 FIG. is a schematic diagram of another display system 30 performing MFD operation in video mode. The display system 30 includes a main processor 302, a display driver circuit 304, and a display screen 306. The display driver circuit 304 may further include a receiving circuit 312, a processing circuit 316, and an output driver circuit 318. The operations of the main processor 302, the display driver circuit 304, and the display screen 306 are respectively similar to those of the main processor 202, the display driver circuit 204, and the display screen 206, except that the display driver circuit 304 does not include a memory for implementing a frame buffer.

[0060] In video mode, the display driver circuit 304 does not have a frame buffer set. Therefore, when the main processor 302 transmits display data to the display driver circuit 304, the display driver circuit 304 can directly transfer the display data to the display screen 306 for refreshing. The display driver circuit 304 can receive a vertical synchronization signal VS and a horizontal synchronization signal HS from the main processor 302 to perform frame rate conversion. More specifically, the display driver circuit 304 starts the next frame period only when it receives a packet of the vertical synchronization signal VS. The main difference between the video mode and the command mode timings is that the display driver circuit 304 in the video mode is mainly controlled by an external clock, and it can control the panel refresh through the timing control signals from the main processor 302. These timing control signals can include the vertical synchronization signal VS and the horizontal synchronization signal HS. In contrast, the panel refresh operation in the command mode reads the display data from the frame buffer of the display driver circuit 304 itself, and its display timing is completely controlled by the display driver circuit 304 itself.

[0061] Therefore, under the transmission architecture of the video mode, the implementation of MFD is slightly different from that in the command mode. In the command mode (as Figure 2 shown), the display data transmitted to the display driver circuit 204 is paired with a write instruction (such as "0x2C") to be stored in the frame buffer. When the main processor 202 outputs the display data, it needs to additionally transmit address information to indicate which address in the frame buffer or the memory 214 the display data should be written to. At this time, the main processor 202 can only output the part of the display data to be updated to the display driver circuit 204. In contrast, in the video mode (as Figure 3As shown, the display data is not written into the frame buffer but directly transmitted to the display screen 306 for refreshing. Therefore, the main processor 302 can transmit the synchronization signals VS and HS for timing control to replace the write instruction, enabling the display driving circuit 304 to perform panel refreshing through the synchronization signals VS and HS from the main processor 302.

[0062] In addition, in the command mode, the address information associated with the display data transmission must be replaced by the position information of the display lines or pixels to be refreshed in the video mode. According to the current Mobile Industry Processor Interface (MIPI) specification, the main processor should transmit full-screen display data to the display driving circuit in the video mode, and the display driving circuit can perform partial pixel refreshing based on the position information provided by the main processor, thus achieving MFD control in the video mode.

[0063] Figure 4 FIG. shows the basic timing of MFD applied to the video mode, which shows a vertical synchronization signal VS, a horizontal synchronization signal HS, display data, an emission control signal EM, and a control signal TE. The main processor can transmit the synchronization signals VS and HS to control the timing of the display driving circuit for panel refreshing. Among them, the vertical synchronization signal VS comes from the Mobile Industry Processor Interface, and the horizontal synchronization signal HS can come from the Mobile Industry Processor Interface or be transmitted through an additional General Purpose Output (GPO) interface.

[0064] As mentioned above, since the current Mobile Industry Processor Interface specification indicates that the main processor must transmit full-screen display data to the display driving circuit in the video mode, therefore, the data transmitted through the Mobile Industry Processor Interface includes full-screen display data, Vertical Back Porch (VBP), and Vertical Front Porch (VFP), and it can also transmit an instruction CMD carrying the position information of the partial display lines to be refreshed. Therefore, based on the position information of the display lines to be refreshed, the display driving circuit can obtain the corresponding display data to refresh the corresponding pixels on the display screen and ignore other unused display data. In this example, the instruction CMD carrying the position information of the display lines to be refreshed is transmitted at the vertical front porch of the previous frame, but those skilled in the art should understand that the main processor can provide the instruction to the display driving circuit in any way (such as through other positions on the Mobile Industry Processor Interface channel or through other transmission interfaces), and is not limited to this.

[0065] As Figure 4As shown, the main processor can transmit full-screen display data DAT1 to DAT5 for the image frames F1 to F5 respectively, and transmit an instruction CMD carrying the position information of the display lines to be refreshed. Therefore, the display driving circuit can use partial display data DAT1P to DAT5P to refresh pixels on the display lines to be refreshed in the image frames F1 to F5, thereby implementing the MFD operation. The partial display data DAT1P to DAT5P are respectively parts of the full-screen display data DAT1 to DAT5, and can be indicated by the corresponding instructions CMD for partial refresh. For example, the partial display data DAT1P is a part of the display data DAT1 in the refresh area on the image frame F1, the partial display data DAT2P is a part of the display data DAT2 in the refresh area on the image frame F2, and so on.

[0066] In addition, if the display driving circuit is used to drive a light-emitting diode panel or an organic light-emitting diode panel, it is necessary to output a light emission control signal EM to control the timing of light emission. As Figure 4 shown, the pulse of the light emission control signal EM is preferably synchronized with the vertical synchronization signal VS to avoid the display brightness error between image frames. The control signal TE is a signal for the display driving circuit to indicate the main processor to output display data, and can be transmitted through another general-purpose output interface. For example, as Figure 3 shown, the display driving circuit 304 can transmit the control signal TE to the main processor 302. And in Figure 4 , since the main processor actively updates part of the images on the image frames F1 to F5, the display driving circuit does not need to output any pulses of the control signal TE.

[0067] In the video mode, since the display driving circuit completely controls the panel refresh based on the external synchronization signal from the main processor, when the frequency of the external synchronization signal changes, the panel refresh timing of the display driving circuit will be adjusted accordingly. For example, in applications with variable refresh rates, the transmission timing of the vertical synchronization signal VS is variable, and the main processor can change the frequency by extending the vertical front edge. As Figure 5 shown, the main processor can control the frame rate to dynamically drop to 1 / 2 or 1 / 3 of the initial value, and the time from the completion of the transmission of the display data (such as DAT2 and DAT3) to the next vertical synchronization signal VS is set as an extended vertical front edge interval. In this example, assuming the original frame rate is equal to 120 Hz, by extending the vertical front edge interval, the frame rates of the image frames F2 and F3 can be dropped to 40 Hz and 60 Hz respectively.

[0068] Similarly, under a display architecture with variable frequency or variable frame rate, the display driving circuit can also perform partial refresh in the same way, that is, determine the positions of the display pixels to be refreshed according to the position information from the main processor, and use partial display data (such as DAT1P to DAT4P) to refresh the specified area at a predetermined frequency, so as to achieve different refresh rates in different areas of the display screen.

[0069] The Mobile Industry Processor Interface Association has proposed an ARP mechanism that can perform sequential frequency downshift in video mode. The current Low Temperature Polycrystalline Oxide (LTPO) panel supports extremely low frame rates such as 1Hz. If the display screen directly switches from a high frame rate display of 120Hz to an extremely low frame rate of 1Hz, a large-scale frequency downshift is likely to cause various visual effects problems such as screen flickering. Therefore, a sequential frequency downshift mechanism is required to gradually decrease from, for example, 120Hz, 60Hz, 30Hz, 15Hz to 1Hz. In command mode, the display data is stored in the frame buffer of the display driving circuit, so the display driving circuit can generate the timing of sequential frequency downshift by itself. However, in video mode, the display driving circuit does not have a frame buffer set up, but receives a vertical synchronization signal from the main processor for timing control. Therefore, the ARP mechanism needs to be used for communication between the display driving circuit and the main processor to achieve the control of sequential frequency downshift. That is to say, the frequency of the vertical synchronization signal and the display data output decreases sequentially until the target frequency (such as 1Hz).

[0070] When the display driving circuit desires to refresh the panel, it can output a control signal (i.e., the control signal TE in Figures 3 - 5 ) to the main processor to instruct the main processor to transmit a frame of display data. According to ARP, the display driving circuit can gradually decrease the frequency of the output control signal TE (i.e., gradually extend the transmission interval of the control signal TE), so that the timing of the main processor outputting the display data meets the requirements of sequential frequency downshift refresh. As described above, the control signal TE can be transmitted through a general-purpose output interface connected between the main processor and the display driving circuit. In an embodiment of the present invention, the control signal TE represents a pulse generated on a control port (such as a general-purpose output port), and the interval between the control signals TE represents the interval between two pulses on the control port used to transmit the control signal TE.

[0071] Sometimes, the main processor may want to actively update the screen content. In this case, regardless of whether the control signal TE is received, the main processor will send the updated display data to the display driver circuit. For example, a user of a mobile phone may send a touch command, triggering a certain application and entering a new screen. At this time, the main processor needs to actively send the new display data to the display driver circuit. When the main processor actively sends the display data, the display screen can return to the high-frequency display of 120Hz until the screen is no longer updated; when the main processor does not actively update the screen content, it is necessary to send the picture by triggering the control signal TE. At this time, the display driver circuit can output the control signal TE to the main processor at an appropriate time point to control the main processor to gradually decrease the picture sending frequency to an extremely low frequency value (such as 1Hz) by using the sequential frequency reduction mechanism.

[0072] The present invention can combine the application of the ARP timing and the MFD timing under the display architecture of the video mode to enhance the power-saving effect of the display system. The ARP mode is the operation of the mobile industry processor interface in the static picture to send pictures in a sequential frequency reduction manner and enter the low-frequency power-saving mode, while the MFD is the mechanism that the dynamic picture area on the display screen is refreshed at a high speed and other areas use a lower refresh rate. In the embodiment of the present invention, the main processor does not need to send any instructions for mode switching to the display driver circuit, and the display driver circuit can switch between the ARP mode and the MFD mode. That is to say, the display driver circuit can switch the operation mode without receiving any instructions from the main processor to indicate.

[0073] Figure 6 It is a waveform diagram of the display control timing of the first embodiment of the present invention, which adopts the display architecture of the video mode and the display driver circuit is not provided with a frame buffer. Figure 6 It shows the waveforms of the respective signals transmitted through the mobile industry processor interface connected between the main processor and the display driver circuit, which includes a vertical synchronization signal VS, a horizontal synchronization signal HS, and display data. In this example, the main processor can use the ARP operation to send pictures in a sequential frequency reduction manner, and while outputting each frame of display data, the main processor can also transmit the position information of the display lines to be updated for the display driver circuit to select some pixels on the display screen for partial refresh. Under the ARP operation, the main processor can actively send the display data to the display driver circuit when the picture needs to be updated, or transmit the display data to the display driver circuit in response to the indication of the control signal TE received from the display driver circuit.

[0074] Figure 6The timing of switching from the MFD mode to the ARP mode is shown. First, the displayed screen is mainly a dynamic image. Therefore, the main processor continuously updates the screen and transmits the display data of a series of image frames to the display driving circuit at full speed through the Mobile Industry Processor Interface. The display driving circuit can be in the MFD mode, where the display driving circuit uses the received display data for partial refresh (i.e., refreshing some pixels on the display screen). At this time, the power consumption required by the system is relatively large, but partial refresh operations can still be used to achieve a certain degree of power saving.

[0075] Next, when the displayed screen stops changing (i.e., it is converted to a full-screen static image), the main processor stops updating the image and starts to output the display data at a reduced frequency. At this time, the frequency of transmitting the display data through the Mobile Industry Processor Interface decreases, and the interval between adjacent vertical synchronization signals VS also lengthens accordingly. In this case, the display driving circuit leaves the MFD mode and enters the ARP mode. To avoid visual problems caused by a sharp drop in the display frequency, the display driving circuit can output a control signal TE (not shown) at a specific time point to instruct the main processor to transmit the display data, thereby controlling the main processor to output the display data to the display driving circuit in a sequential frequency reduction manner. The detailed settings of the sequential frequency reduction can be arbitrarily configured according to system requirements. In this example, the image transmission frequency of the main processor can sequentially decrease from 120Hz, 20Hz, 15Hz to 1Hz.

[0076] In other words, in the ARP mode, the display driving circuit can actively output the control signal TE according to a predetermined timing to control the main processor to perform sequential frequency reduction for image transmission, and the main processor can perform image transmission according to the instruction of the control signal TE. In this case, the refresh rate in the ARP mode is mainly controlled by the display driving circuit.

[0077] In one embodiment, the display driving circuit can judge whether to enter the ARP mode by timing. For example, Figure 7 The detailed timing of the display driving circuit switching from the MFD mode to the ARP mode is further shown. In addition to the vertical synchronization signal VS, the horizontal synchronization signal HS, and the display data, Figure 7 The waveform of the control signal TE and the panel refresh behavior under the mode switching operation are also shown.

[0078] As Figure 7 shown, the display driving circuit is first in the MFD mode. It can use partial display data DAT1P and DAT2P to perform partial refresh on the display screen in the dynamic image area according to the display data DAT1 and DAT2 from the main processor. Similarly, the instruction carrying the position information of the partial display lines to be refreshed can be transmitted through the previous vertical front edge or any other time slot, which is omitted for simplicity in Figure 7Based on the content of the screen, the main processor can send images in a variable frame rate manner. Among them, the decreasing frame rate can be achieved by adding an extended vertical front porch interval VFP_EXT.

[0079] The display driving circuit can start timing within each time interval for receiving a frame of display data. More specifically, the display driving circuit can start timing at the time point when it receives a vertical synchronization signal VS from the main processor each time. Among them, the vertical synchronization signal VS indicates the start of a time interval for transmitting a frame of display data. The display driving circuit can also set a timeout length to determine whether a timeout occurs according to the timing result. When the timing result indicates that no vertical synchronization signal VS has been received during a predetermined period exceeding the timeout length, the display driving circuit can determine that a timeout has occurred and enter the ARP mode. A timeout means that the main processor has not actively updated the screen for a period of time, indicating that the frequency of the main processor outputting the vertical synchronization signal VS has dropped below a certain level. For example, the display driving circuit can set the timeout length to a suitable value so that the display driving circuit is expected to enter the ARP mode when the output frequency of the vertical synchronization signal VS drops below 20 Hz (i.e., the image sending frequency of the main processor drops below 20 Hz).

[0080] At the time point when the timing time times out, the display driving circuit can leave the MFD mode to enter the ARP mode, and the display driving circuit outputs a control signal TE to the main processor to indicate that its operation mode has switched to the ARP mode. In response to the control signal TE, the main processor can transmit a frame of display data and send a vertical synchronization signal VS used to indicate the corresponding frame period. In an embodiment, the display driving circuit can raise the level of the corresponding general-purpose output port to transmit the control signal TE through the general-purpose output port. Since the main processor actively sends images not in response to a screen change, the output display data can be the same as the previous frame of display data (i.e., DAT2). Then, in the ARP mode, the display driving circuit can output the control signal TE at some specific time points according to the ARP specification of the Mobile Industry Processor Interface. Triggered by the control signal TE, the main processor can transmit the display data of a series of image frames according to the sequential frequency reduction timing, so that the frame rate gradually drops to 1 Hz.

[0081] The above timing scheme for determining whether a timeout occurs can be implemented in any way. In an embodiment, a timeout counter can be used to calculate the number of horizontal synchronization signals HS continuously received after the display driving circuit receives the vertical synchronization signal VS, so as to determine whether a timeout occurs. Therefore, when the accumulated number of horizontal synchronization signals HS exceeds a certain specific value, it means that the display driving circuit determines that a timeout has occurred and enters the ARP mode.

[0082] In this case, when the main processor wants to stop updating the display data and enter the low-frequency display interval, there is no need to separately transmit an instruction or notification to the display driving circuit. The display driving circuit can use an overtime counter or timer to determine overtime, and decide whether to enter the ARP mode according to whether overtime occurs, so as to implement a full-screen frequency reduction mechanism. In contrast, in the existing ARP mode, the main processor needs to transmit an instruction to the display driving circuit to notify the display driving circuit to enter the ARP mode. In the existing method, it is difficult for the main processor to efficiently determine the MFD mode with high-frequency image transmission or the ARP mode with low-frequency image transmission in various usage scenarios, so the power-saving effect is very limited.

[0083] In an embodiment of the present invention, in order to avoid visual problems, the display driving circuit will force a full-screen refresh with one frame of display data after entering the ARP mode, that is, pause the partial refresh operation of the MFD. In the full-screen refresh operation, the display driving circuit can use a complete frame of display data (such as DAT2) to refresh all pixels on the display screen. This is because when the display screen is refreshed at a very low refresh rate (such as 1 Hz), if a partial refresh mechanism is added, the display frequency of the unrefreshed area will drop below 1 Hz, or even below 0.1 Hz. However, too low a refresh rate will reduce the smoothness of the picture and / or cause other unexpected visual problems. Therefore, it is preferably to force a full-screen refresh in the ARP mode to maintain the display quality.

[0084] Therefore, when the display driving circuit enters the ARP mode, it can perform a full-screen refresh in a sequential frequency reduction manner, such as from 120 Hz, 60 Hz... to a very low frame rate of 1 Hz, as Figure 7 shown. At this time, although the main processor still transmits the information of the display line to be refreshed while sending the image, the display driving circuit can ignore this information and force a full-screen refresh.

[0085] Figure 8 FIG. is a waveform diagram of another display control timing in an embodiment of the present invention, which illustrates the timing control of the display driving circuit leaving the ARP mode and entering the MFD mode. Similarly, Figure 8 shows the vertical synchronization signal VS, horizontal synchronization signal HS, display data, and control signal TE transmitted between the main processor and the display driving circuit. In this example, the display driving circuit was originally in the ARP mode, where the display data (i.e., DAT2) remains unchanged, and the main processor transmits the display data at a very low frequency of, for example, 1 Hz.

[0086] When the main processor wants to actively update the display screen, it will actively transmit a vertical synchronization signal VS and output a new frame of display data to the display driving circuit. At this time, the display driving circuit can return to the MFD mode. For the display driving circuit, it is set to indicate the main processor to send a picture at a specific time point by outputting a control signal TE, so as to achieve an extremely low frequency in the ARP mode. However, if the display driving circuit receives a new frame of display data from the main processor and this new frame of display data is not transmitted in response to the control signal TE, that is, the display data is not received at any time point indicated by the control signal TE and expected by the display driving circuit, it means that this new display data is the picture sent by the main processor to actively update the screen content. In this case, the display driving circuit can determine that the main processor starts to update the screen, and thus leaves the ARP mode to enter the MFD mode.

[0087] As described above, the display driving circuit can send a control signal TE to indicate the main processor to send a picture. In Figure 8 the embodiment, the control port of TE is usually at a low level. When the display driving circuit requests the main processor to send a picture, it can pull the control port to a high level as the output of the control signal TE, and the main processor can transmit the vertical synchronization signal VS and a frame of display data accordingly. However, if the main processor outputs the vertical synchronization signal VS when the control port of TE is still at a low level, it means that the next picture sent is the main processor actively updating the display data. At this time, the display driving circuit can enter the MFD mode in response to the reception of the display data.

[0088] It should be noted that in a preferred embodiment, the first frame (or the first few frames) when the display driving circuit just enters the MFD mode should be forced to perform a full-screen refresh. Generally speaking, in the ARP mode, the frequency of the main processor sending pictures may drop to about 1 Hz level. Entering the MFD mode represents the situation where the main processor actively updates the display data. According to the image content, the main processor may update the entire screen or a part of the screen. Therefore, if the display driving circuit still maintains the low-frequency display of some static image areas when entering the MFD mode, tearing effects, dropped pictures, or other unexpected visual effects may occur. In this case, this problem can be solved by one or more frames of forced full-screen refresh. At this time, although the main processor may transmit the display line information to be refreshed while sending pictures, the display driving circuit can ignore this information and perform a full-screen refresh.

[0089] In Figure 8In an embodiment, after the display driving circuit receives the display data DAT2, the timing has not reached the starting point during the next frame period and the control signal TE during the next frame period is not output. For example, the length of the extended vertical front porch period VFP_EXT has not reached its predetermined length, such as 119 blank frame periods (taking a frame rate of 1 Hz as an example). At this time, the display driving circuit receives the vertical synchronization signal VS and the next frame display data DAT3 from the main processor. In this case, regardless of whether the main processor transmits the information of the partial display lines to be refreshed, the display driving circuit can use the display data DAT3 to perform full-screen refreshing on this image frame. Next, the display driving circuit and the main processor can operate normally in the MFD mode. Among them, the main processor updates the display data in the dynamic image area, and the display driving circuit receives the display data (such as DAT4 and DAT5) and performs partial refreshing on the display screen accordingly (such as through the partial display data DAT4P and DAT5P) to achieve different frame rates in different areas in the MFD operation, thereby achieving the power-saving effect of the MFD.

[0090] It can be seen from this that the purpose of the present invention is to propose a timing control mechanism that can switch the display driving circuit between the MFD mode and the ARP mode in the video mode of the mobile industry processor interface. Those skilled in the art can make modifications or changes accordingly, and are not limited thereto. For example, Figure 7 the timing is only one implementation manner for the display driving circuit to switch from the MFD mode to the ARP mode, and Figure 8 the timing is only one implementation manner for the display driving circuit to switch from the ARP mode to the MFD mode. Under the display architecture of the video mode, the display control timing of the present invention can be adjusted or changed in many different aspects, and all of them should fall within the scope of the present invention.

[0091] Figure 9 Another implementation manner of switching from the MFD mode to the ARP mode is shown. Similarly, the display driving circuit can send the control signal TE at the time point of timeout to instruct the main processor to send the picture, but the timeout length setting and / or the refresh frequency when the display driving circuit enters the ARP mode can be adjusted to appropriate values according to system requirements. In an exemplary embodiment, when the display driving circuit enters the ARP mode, the display data from the main processor can be transmitted at a starting frequency, and this starting frequency can be determined according to the timeout length.

[0092] Please refer back to Figure 7, when the frequency at which the main processor sends images drops to a lower frequency (such as 20 Hz), the display driver circuit can leave the MFD mode and enter the ARP mode. After entering the ARP mode, the display driver circuit first refreshes the display screen at a frame rate of 120 Hz, and then refreshes it in a sequential frequency reduction manner. In this case, there is a large frequency jump between the MFD mode and the ARP mode. To make the frequency conversion process when entering the ARP mode smoother, the display driver circuit can directly refresh at a suitable frequency (such as 30 Hz) after entering the ARP mode, where the equivalent refresh frequency when timeout occurs is equal to 60 Hz. The display driver circuit then cooperates with the sequential frequency reduction mechanism of ARP to gradually reduce the refresh frequency to 1 Hz, thereby achieving smooth frequency reduction, as Figure 9 shown.

[0093] Figure 10 Another implementation manner of switching from the ARP mode to the MFD mode is shown. Similarly, when the display driver circuit receives a vertical synchronization signal VS without responding to the indication of the control signal TE, it can be determined that the main processor wants to actively send images, and accordingly switch to the MFD mode. However, the display refresh method of the display driver circuit after entering the MFD mode can be adjusted according to system requirements. In an exemplary embodiment, the display driver circuit can perform partial refresh in the first frame in the MFD mode according to an instruction indicating the position or display line to be refreshed on the display screen.

[0094] Please refer back to Figure 8 , the first frame after the display driver circuit enters the MFD mode can be forced to perform full-screen refresh to avoid visual effects problems. In contrast, in the Figure 10 embodiment, the first frame after the display driver circuit enters the MFD mode is not forced to perform full-screen refresh, but partial refresh is performed with partial display data DAT3P according to the information of the display line to be refreshed provided by the main processor. This information can be transmitted through any interface between the main processor and the display driver circuit, such as the vertical front edge of the Mobile Industry Processor Interface, which is omitted in Figure 10 for simplicity. Next, the display driver circuit can perform partial refresh operations using partial display data DAT4P and DAT5P taken from the full-screen display data DAT4 and DAT5.

[0095] For example, in a certain application, the display system may have a higher requirement for power saving than for image quality. Therefore, partitioned multi-frequency refresh can be started when the display driver circuit enters the MFD mode, so that the power-saving effect achieved by MFD is optimized.

[0096] In another embodiment, when the display driving circuit enters the MFD mode from the ARP mode, it can be forced to perform full-screen refreshing several times at a higher frequency to ensure good visual effects. In other words, after the display driving circuit enters the MFD mode, it can be forced to perform full-screen refreshing for a predetermined number of frames with the received display data. For example, as Figure 11 shown, when the display driving circuit receives the vertical synchronization signal VS that does not respond to the control signal TE output by the display driving circuit, it can enter the MFD mode from the ARP mode. At this time, the display driving circuit can receive updated display data (such as DAT3, DAT4...) from the main processor along with the position or display line information of partial refreshing. During the first three frames after entering the MFD mode, the display driving circuit sends the control signal TE to instruct the main processor to transmit the display data DAT3 to DAT5, and uses the received display data DAT3 to DAT5 to perform full-screen refreshing on the display screen (that is, ignores the position or display line information of partial refreshing carried by the instructions of the main processor), so as to ensure that the display screen performs full-screen refreshing at a base frequency of, for example, 120 Hz. And partial refreshing starts again in subsequent image frames.

[0097] In some applications, the display system plays videos at a relatively low frame rate (such as 30 Hz), so the main processor sends images according to this low frame rate. If the display driving circuit still refreshes the display screen at a low frequency when entering the MFD mode, it may cause some visual effect problems, such as screen flickering, ghosting, or tearing. To solve this problem, the display driving circuit can be forced to perform full-screen refreshing at a higher frequency for several consecutive frames after entering the MFD mode. Therefore, the display driving circuit needs to output the control signal TE at a higher frequency for several consecutive frames to ensure that the main processor sends images at a higher frequency, so that the display screen can perform high-frequency full-screen refreshing. In this way, various visual effect problems caused by partial refreshing of the display screen when entering the MFD mode in the low-frequency display state can be avoided. In Figure 11 the embodiment, the display driving circuit performs full-screen refreshing at a refresh rate of 120 Hz during three consecutive frames. In another embodiment, when the display driving circuit enters the MFD mode, it can be forced to perform full-screen refreshing on the display screen within N image frames through a frequency of 120 Hz, 60 Hz, or any other appropriate frequency, where N can be any positive integer.

[0098] In another embodiment, the display driving circuit can also use a sequential frequency reduction mechanism to control the refresh frequency of some areas in the MFD mode. For example, as Figure 12As shown, in the MFD mode, the main processor continuously transmits full-screen display data along with the display line information to be refreshed to the display driver circuit, and the display driver circuit performs partial refresh on the panel accordingly. Considering the visual effect problems that may occur if the refresh rate drops suddenly from 120Hz to 1Hz in some areas where the dynamic picture is converted to a static picture, the ARP mechanism can be used to perform sequential frequency reduction.

[0099] In this case, the display driver circuit can output a control signal TE to instruct the main processor to transmit the entire frame of display data in a sequential frequency reduction manner, for example Figure 12 in the embodiment of from 60Hz, 40Hz, 10Hz, 5Hz to 1Hz. Correspondingly, the main processor can transmit the entire frame of display data to the display driver circuit at a specific time point indicated by the control signal TE. Therefore, the display driver circuit can follow the sequential frequency reduction setting and use the entire frame of display data to refresh the display screen during the corresponding frame period, where the partial refresh information for these image frames can be ignored.

[0100] The display driver circuit can calculate the time points for full-screen refresh according to the frequency reduction setting, and transmit the control signal TE at these time points to instruct the main processor to send the picture. The display driver circuit also forces full-screen refresh during the corresponding frame period, and performs partial refresh (if any display data is received) at the positions indicated by the instructions provided by the main processor during other frame periods. More specifically, full-screen refresh can be performed in a sequential frequency reduction manner; and partial refresh (or possibly full-screen refresh) can still be performed during other frame periods when the picture is partially or fully updated and the main processor transmits the corresponding display data.

[0101] It should be noted that in the MFD mode, the main processor will adjust the picture transmission frequency according to whether the picture content needs to be updated and its update frequency. For example, the main processor may reduce the picture transmission frequency by extending the time of the vertical front porch (i.e., VFP_EXT) and extending the interval of the vertical synchronization signal VS. In this case, the display driver circuit needs to calculate the time points for full-screen refresh (i.e., the time points for transmitting the control signal TE) according to the actual timing, and cannot calculate only based on the vertical synchronization signal VS. In other words, the way the display driver circuit determines the frequency reduction should consider both the vertical synchronization signal VS and the length of the extended vertical front porch interval (i.e., VFP_EXT), and / or consider the absolute time including the data transmission period and the extended vertical front porch interval for frequency calculation. In one embodiment, the display driver circuit can use a counter to calculate the number of horizontal synchronization signals HS, or use a timer to calculate the real time, to achieve effective sequential frequency reduction control.

[0102] Under the display architecture of the video mode of the Mobile Industry Processor Interface, the present invention proposes a switching control method between the MFD mode and the ARP mode for the display system to achieve the purpose of power saving while ensuring the display quality. The above embodiments are only used to illustrate the exemplary method of signal transmission between the main processor and the display driving circuit, but the present invention is not limited thereto. The following embodiments illustrate more feasible variations.

[0103] In the above embodiment, according to the specification of the Mobile Industry Processor Interface, whether the display screen is to perform full-screen refresh or partial refresh, the main processor must transmit full-screen display data to the display driving circuit in a predetermined format, and the display driving circuit selects the area to be refreshed according to the information of the display lines to be refreshed carried by the instruction transmitted by the main processor. In other embodiments, the main processor is allowed to transmit only partial display data to be refreshed to the display driving circuit. In this case, if only a partial area on the panel needs to be refreshed, the main processor only needs to transmit the display data in the corresponding time slot.

[0104] Figure 13 The timing diagram shows that the main processor transmits partial display data DAT1P - DAT5P to the display driving circuit in the video mode. When the MFD operation is applied to the video mode, the display driving circuit is set to refresh a partial area on the panel. Therefore, the main processor only needs to transmit the display data DAT1P - DAT5P corresponding to the pixels to be refreshed in the allocated time slots, and the other time slots can be left blank (or used to carry other information). In this example, the main processor can still send instructions to indicate the position of the partial refresh. Alternatively, the display driving circuit performs partial refresh only based on the partial display data DAT1P - DAT5P received through the Mobile Industry Processor Interface, and thus does not require relevant instructions.

[0105] Figure 14 Another alternative embodiment is shown. As described above, the purpose of the ARP scheme is mainly to save power, achieving an extremely low frame rate through a sequential frequency reduction mechanism to significantly reduce the power consumption required for the transmission of the Mobile Industry Processor Interface. Since the main processor transmits display data at an extremely low frame rate (such as 1 Hz), the blank interval may reach a length of 119 or 59 frame periods. To further enhance the power saving effect, the main processor can stop transmitting the horizontal synchronization signal HS (such as turning off the transmission of the Mobile Industry Processor Interface) during the blank interval and instead transmit the horizontal synchronization signal HS through a general-purpose output interface. Alternatively, the main processor can also stop transmitting the horizontal synchronization signal HS during the blank interval and let the display driving circuit generate the horizontal synchronization signal HS internally to use the internal horizontal synchronization signal HS for necessary display timing control.

[0106] In the MFD mode, in addition to the relatively common frame rate configurations in the vertical direction, the new generation of MFD solutions can combine the frame rate configurations in the vertical and horizontal directions. For example, as Figure 15 shown, the display system supports MFD control in the vertical and horizontal directions. When the main processor transmits display data (such as DAT1 to DAT5), it can transmit partial refresh position information in the corresponding instructions. This position information can include coordinate information in both the X and Y directions, enabling the display driver circuit to refresh the pixels in a specific area indicated by the coordinate information on the display screen. Through the combination of frame rate configurations in the vertical and horizontal directions, the area to be refreshed by partial display data DAT1P to DAT5P on an image frame can include some pixels in a row, thereby achieving more flexible MFD control and optimizing the power-saving effect achieved by MFD operations.

[0107] In another embodiment, the MFD operation can be integrated with the ARP mode. For example, as Figure 16 shown, the display driver circuit can be set to maintain the ARP mode and support the MFD function simultaneously. Specifically, in the ARP mode, the display driver circuit can directly perform partial refresh according to the position to be refreshed or the information of the display line provided by the main processor, and the image transmission frequency is completely controlled by the main processor. In this example, the display driver circuit completely performs panel refresh according to the vertical synchronization signal VS provided by the main processor and the position to be refreshed or the information of the display line. More specifically, during the period of displaying dynamic images, the main processor can continuously transmit updated display data to the display driver circuit at full speed; during the period of displaying static images (indicating that the screen does not update), the main processor automatically triggers sequential frequency reduction for power saving. No additional timing control mechanism for the display driver circuit is added, and the operation mode is not switched.

[0108] In this example, since the panel refresh method is completely based on the display data provided by the main processor, when the display driver circuit receives display data accompanied by the corresponding information of the area to be refreshed, the display driver circuit can refresh the corresponding pixels according to this information. If a frame of the display screen needs to be fully refreshed, the main processor can transmit the relevant information of the area to be refreshed covering the entire panel to the display driver circuit, or not transmit any partial refresh information. In this way, the display driver circuit knows that the display screen needs to be fully refreshed and thus performs a full-screen refresh operation.

[0109] The above operations regarding data transmission and panel refresh can be summarized into a control flow 170, as Figure 17 shown. The control flow 170 can be implemented in a display driver circuit, such as the display driver circuit in any of the above embodiments. As Figure 17 shown, the control flow 170 includes the following steps:

[0110] Step 1702: Start timing within a time interval for receiving a first frame of display data to generate a timing result.

[0111] Step 1704: Determine whether timeout occurs according to the timing result.

[0112] Step 1706: Output a control signal TE to instruct the main processor to transmit a second frame of display data when timeout occurs.

[0113] It should be noted that the above operations regarding data transmission and panel refreshing can also be summarized into another control flow 180, as Figure 18 shown. The control flow 180 can be implemented in a main processor, such as the main processor in any of the above embodiments. As Figure 18 shown, the control flow 180 includes the following steps:

[0114] Step 1802: Transmit a first frame of display data to the display driving circuit for driving the display screen. Step 1804: After transmitting the first frame of display data, receive a control signal TE from the display driving circuit.

[0115] Step 1806: Transmit a second frame of display data in response to the control signal TE.

[0116] For the detailed operations and variations of the control flows 170 and 180, reference can be made to the descriptions in the above paragraphs, which will not be elaborated here.

[0117] In summary, the present invention integrates the applications of MFD and ARP in the video mode of the mobile industry processor interface. In addition to maintaining the cost advantage of no memory in the video mode, it can also reduce the panel refreshing area through the partial refreshing mechanism to save power consumption, and utilize the sequential frequency reduction mechanism of ARP to achieve an extremely low refresh rate, so as to achieve the purpose of power saving without affecting the visual effect. In addition to the decrease in the refresh rate of the display screen, the amount of data transmitted through the mobile industry processor interface is also greatly reduced, making the power saving effect multiplicative. Furthermore, in the present invention, the display driving circuit can switch between the MFD mode and the ARP mode by itself without the need for the main processor to transmit instructions or notifications to indicate, which can further improve the efficiency of display operation. Specifically, the display driving circuit in the MFD mode can perform timing to determine that the main processor does not update the screen when timeout occurs (representing that the transmission of display data is lower than a certain specific frequency), and enter the ARP mode for sequential frequency reduction to save the power consumption of the mobile industry processor interface. The display driving circuit in the ARP mode can automatically enter the MFD mode when receiving an active screen transmission from the main processor and start partial refresh display in the MFD mode.

[0118] In one embodiment, to ensure the display quality, the display driving circuit may force a full-screen refresh during the first N frames after entering the MFD mode, and send a control signal TE at the corresponding time point to instruct the main processor to send the image. In one embodiment, the display driving circuit may ensure the visual effect of the low frame rate area (i.e., the static image area) through sequential frequency reduction control in the MFD mode. In one embodiment, the main processor is allowed to only transmit the display data to be refreshed to the display driving circuit, so that the display driving circuit performs partial refresh according to the received display data and / or in combination with the indication of the area to be refreshed. In one embodiment, the main processor may stop transmitting the horizontal synchronization signal after sending the image, and the display driving circuit instead uses the internal horizontal synchronization signal to perform the timing control of the display screen. In one embodiment, the information of the area to be refreshed transmitted by the main processor includes the pixel coordinate information in the horizontal and vertical directions, so that the display driving circuit can perform partial refresh display in the horizontal and vertical directions correspondingly. In one embodiment, the display driving circuit may perform partial refresh according to the display lines to be refreshed provided by the main processor in the ARP mode, and directly control the panel refresh by the main processor. Except for the cases of contradiction or infeasibility with each other, the above embodiments can be combined with each other to further enhance the power saving effect and improve the display quality.

[0119] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for controlling a display screen, used in a display driving circuit, characterized in that: The method includes: Starting timing within a time interval for receiving a first frame of display data to generate a timing result; Determining whether a timeout occurs according to the timing result; and When the timeout occurs, a control signal is output to instruct a main processor to transmit a second frame of display data.

2. The method according to claim 1, characterized in that The display driving circuit operates in a first operation mode, and the method further comprises: When the timeout occurs, the first operation mode is left to enter a second operation mode.

3. The method according to claim 2, characterized in that The first operation mode includes a multi-frequency display operation, while the second operation mode does not include the multi-frequency display operation.

4. The method according to claim 3, characterized in that In the multi-frequency display operation, the display driving circuit performs partial refresh using the first frame of display data.

5. The method according to claim 2, characterized in that Also includes: In the second operation mode, a plurality of display data are received in a sequentially down-clocked manner.

6. The method according to claim 5, characterized in that The sequential down-clocking for the plurality of display data is triggered by outputting a plurality of control signals to the main processor.

7. The method according to claim 5, characterized in that When the display driving circuit is in the second operation mode, the plurality of display data remain unchanged.

8. The method according to claim 5, characterized in that The plurality of display data are transmitted at a starting frequency, and the starting frequency is determined according to a timeout length.

9. The method according to claim 2, characterized in that Also includes: After entering the first operation mode from the second operation mode, full screen refresh is performed using a plurality of display data of a predetermined number of frames.

10. The method according to claim 2, characterized in that The display driving circuit is in the second operation mode, and the method further comprises: receiving a third frame of display data in non-response to the control signal; and When the third frame of display data is received, the second operation mode is left to enter the first operation mode.

11. The method according to claim 2, characterized in that The display driving circuit is in the first operation mode, and the method further comprises: Outputting a plurality of control signals to instruct the main processor to transmit a plurality of complete frames of display data in a sequentially down-clocked manner; receiving the plurality of complete frames of display data; and The display screen is refreshed by using the multiple complete frames of display data in the sequential frequency reduction manner.

12. The method according to claim 1, characterized in that The step of starting timing within the time interval for receiving the first frame of display data comprises: The timing starts when a synchronization signal for the first frame of display data is received.

13. The method according to claim 1, characterized in that The step of starting timing within the time interval for receiving the first frame of display data comprises: The timing starts when the time interval for receiving the first frame of display data starts.

14. The method according to claim 1, wherein: The step of determining whether the timeout occurs according to the timing result includes: When the timing result indicates that no vertical synchronization signal is received during a predetermined period, it is determined that the timeout occurs.

15. The method according to claim 1, wherein: Also includes: The second frame of display data is used to perform full-screen refresh.

16. The method according to claim 1, wherein: The display driving circuit operates in a first operation mode, and the method further comprises: Without receiving an instruction from the main processor, the first operation mode is left to enter a second operation mode.

17. The method according to claim 1, wherein: The display driving circuit includes a timeout counter for determining whether the timeout occurs.

18. A display driving circuit for controlling a display screen, characterized in that: The display driver circuit is used to: Starting timing within a time interval for receiving a first frame of display data to generate a timing result; Determining whether a timeout occurs according to the timing result; and When the timeout occurs, a control signal is output to instruct a main processor to transmit a second frame of display data.

19. A method for controlling a display screen, used in a main processor, characterized in that: The method comprises: transmitting a first frame of display data to a display driving circuit for driving the display screen; After transmitting the first frame of display data, receiving a control signal from the display driving circuit; and A second frame of display data is transmitted in response to the control signal.

20. The method of claim 19, wherein: The control signal is generated according to a timing result of the display driving circuit.

21. The method of claim 20, wherein: The display driving circuit operates in a first operation mode, and leaves the first operation mode to enter a second operation mode according to the timing result.

22. The method according to claim 21, characterized in that The first operation mode includes a multi-frequency display operation, while the second operation mode does not include the multi-frequency display operation.

23. The method of claim 22, wherein: In the multi-frequency display operation, the display driving circuit performs partial refresh using the first frame of display data.

24. The method of claim 21, wherein: Also includes: After receiving the control signal, the plurality of display data are transmitted in a sequentially down-converting manner.

25. The method of claim 24, wherein: The sequential down-conversion of the plurality of display data is triggered by receiving a plurality of control signals from the display driving circuit.

26. The method of claim 24, wherein: When the display driving circuit is in the second operation mode, the plurality of display data remain unchanged.

27. The method of claim 24, wherein: Also includes: The plurality of display data are transmitted at a starting frequency, and the starting frequency is determined according to a timeout length of the display driving circuit.

28. The method of claim 21, wherein: The display driving circuit is in the second operation mode, and the method further comprises: transmitting a third frame of display data without responding to the control signal of the display driving circuit; When the display driving circuit receives the third frame of display data, it leaves the second operation mode and enters the first operation mode.

29. The method of claim 19, wherein: Also includes: In response to a plurality of control signals from the display driving circuit, a plurality of complete frame display data are transmitted; wherein the plurality of complete frame display data are used to refresh the display screen by a sequential frequency reduction method.

30. The method of claim 21, wherein: The main processor does not send a command to the display driving circuit to instruct the display driving circuit to leave the first operation mode and enter the second operation mode.

31. A main processor for controlling a display screen, characterized in that: The main processor is used to: Transmitting a first frame of display data to a display driving circuit for driving the display screen; After transmitting the first frame of display data, receiving a control signal from the display driving circuit; as well as A second frame of display data is transmitted in response to the control signal.

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