Driving selection circuit, display screen and electronic equipment

Abstract

The invention provides a driving selection circuit, a display screen and electronic equipment, relates to the technical field of display, and aims to solve the problem of how to control on and off of an oxide TFT (Thin Film Transistor) in a pixel circuit. The driving selection circuit is applied to a display screen, and the display screen comprises a pixel circuit, a display driving integrated circuit and a GOA circuit. The pixel circuit includes an oxide TFT. The driving selection circuit comprises a selection circuit and a driving circuit. And the selection circuit is electrically connected with the driving circuit and is used for outputting a high level or a low level to the driving circuit according to a row driving signal from the GOA circuit and a control signal from the display driving integrated circuit. The driving circuit is used for outputting a corresponding scanning signal according to the high level or the low level from the selection circuit. The scanning signals are used for controlling the corresponding oxide TFTs in the pixel circuits to be switched on or switched off. Therefore, the driving frequency of the driving transistor in the pixel circuit can be controlled, the working frequency of the pixel circuit is further controlled, and different display areas of the display screen are refreshed.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of display technologies, and particularly to a driving selection circuit, a display screen, and an electronic device. Background Art

[0002] Currently, the refresh method of the display screen on an electronic device is full-screen refresh. When only a part of the display screen has a high refresh rate of the display image, the full-screen refresh method will generate a high device power consumption. To reduce the device power consumption, it is necessary to control different regions of the display screen to display at different frequencies, that is, zoned display. For a pixel circuit using Low Temperature Polycrystalline Oxide (LTPO) technology, to achieve the refresh of different display regions of the display screen, it is necessary to control the operating frequency of the pixel circuit. However, the operating frequency of the pixel circuit is related to the driving frequency of the driving transistor in the pixel circuit, and the driving frequency of the driving transistor is related to the on-state of the Thin Film Transistor (TFT) in the pixel circuit. Therefore, it is crucial to control the on and off of the oxide TFT in the pixel circuit. Summary of the Invention

[0003] The embodiments of the present application provide a driving selection circuit, a display screen, and an electronic device, aiming to solve the problem of how to control the on and off of the oxide TFT in the pixel circuit.

[0004] In a first aspect of the embodiments of the present application, a driving selection circuit is provided. The driving selection circuit is applied to a display screen, and the display screen includes a pixel circuit, a display driving integrated circuit, and a Gate On Array (GOA) circuit. The pixel circuit includes an oxide TFT. The driving selection circuit includes a selection circuit and a driving circuit. The selection circuit is electrically connected to the driving circuit and is configured to output a high level or a low level to the driving circuit according to a row driving signal from the GOA circuit and a control signal from the display driving integrated circuit. The driving circuit is configured to output a corresponding scan signal according to the high level or the low level from the selection circuit. The scan signal is used to control the corresponding oxide TFT in the pixel circuit to be turned on or off.

[0005] In this embodiment, the driving selection circuit outputs a corresponding scan signal according to the row driving signal from the GOA circuit and the control signal from the display driving integrated circuit, thereby controlling the corresponding oxide TFT in the pixel circuit to be turned on or off. Thereby, the driving frequency of the driving transistor in the pixel circuit can be controlled, and further the operating frequency of the pixel circuit can be controlled, so as to achieve the refresh of different display regions of the display screen and reduce the device power consumption.

[0006] In one embodiment, the selection circuit includes a first input terminal, a second input terminal, a control terminal, and an output terminal. The first input terminal and the second input terminal of the selection circuit are respectively used for receiving a first row driving signal and a second row driving signal from the GOA circuit. The first row driving signal and the second row driving signal respectively correspond to different rows of pixels in the pixel array of the display screen. The control terminal of the selection circuit is used for receiving a control signal from the display driving integrated circuit. The output terminal of the selection circuit is connected to the driving circuit, and is used for outputting a high level or a low level to the driving circuit according to the first row driving signal, the second row driving signal, and the control signal.

[0007] In this embodiment, based on the control signal being at a low level, when both the first row driving signal and the second row driving signal are at a low level or a high level, or when the first row driving signal is at a low level and the second row driving signal is at a high level, the scanning signal is at a low level, turning off the corresponding oxide TFT in the pixel circuit. Based on the control signal being at a high level, when the first row driving signal is at a low level and the second row driving signal is at a high level or a low level, the scanning signal is at a low level, turning off the corresponding oxide TFT in the pixel circuit. Based on the control signal being at a high level, when the first row driving signal is at a high level and the second row driving signal is at a high level or a low level, the scanning signal is at a high level, turning on the corresponding oxide TFT in the pixel circuit. Based on the control signal changing from a high level to a low level, when the first row driving signal is at a high level and the second row driving signal is at a high level or a low level, the scanning signal is at a high level, turning on the corresponding oxide TFT in the pixel circuit. Based on the control signal changing from a high level to a low level, when both the first row driving signal and the second row driving signal are at a low level, the scanning signal is at a low level, turning off the corresponding oxide TFT in the pixel circuit.

[0008] In another embodiment, the selection circuit further includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a capacitor. The gates of the first transistor, the third transistor, and the fifth transistor are connected together and form the first input terminal of the selection circuit. The second pole of the first transistor serves as the control terminal of the selection circuit, and the first pole of the first transistor is electrically connected to the second pole of the second transistor. The gate of the second transistor serves as the second input terminal of the selection circuit, and the first pole of the second transistor is electrically connected to the gates of the fourth transistor, the sixth transistor, and the first pole of the capacitor. The second pole of the capacitor is connected to a negative voltage source. The first pole of the third transistor is electrically connected to the second pole of the fourth transistor, and the second pole of the third transistor is connected to the negative voltage source. The first poles of the fourth transistor, the second pole of the fifth transistor, and the second pole of the sixth transistor are connected together and form the output terminal of the selection circuit. The first poles of the fifth transistor and the sixth transistor are connected to a positive voltage source.

[0009] In this embodiment, the positive voltage source is used to output a high level, and the negative voltage source is used to output a low level. The first transistor and the fifth transistor are both turned on when the first row driving signal is at a low level and turned off when the first row driving signal is at a high level. The second transistor is turned on when the second row driving signal is at a high level and turned off when the second row driving signal is at a low level. The third transistor is turned on when the first row driving signal is at a high level and turned off when the first row driving signal is at a low level. The conduction states of the fourth transistor and the sixth transistor are both associated with the conduction states of the first transistor, the second transistor, and the capacitor.

[0010] In another embodiment, the second transistor, the third transistor, and the fourth transistor are all oxide TFTs and have the same polarity. The first transistor, the second transistor, and the sixth transistor have the same polarity and are opposite to the polarity of the second transistor or the third transistor or the fourth transistor.

[0011] In another embodiment, the driving circuit includes an input terminal and an output terminal. The input terminal of the driving circuit is electrically connected to the output terminal of the selection circuit. The output terminal of the driving circuit is used to output a scanning signal.

[0012] In another embodiment, the driving circuit further includes a first driving transistor and a second driving transistor. The gates of the first driving transistor and the second driving transistor are connected to form the input terminal of the driving circuit. The second pole of the first driving transistor and the first pole of the second driving transistor are connected to form the output terminal of the driving circuit. The first pole of the first driving transistor is connected to the positive voltage source, and the second pole of the second driving transistor is connected to the negative voltage source.

[0013] In this embodiment, the first driving transistor is turned on when the input terminal of the driving circuit receives a low level and turned off when the input terminal of the driving circuit receives a high level. The second driving transistor is turned on when the input terminal of the driving circuit receives a high level and turned off when the input terminal of the driving circuit receives a low level.

[0014] In another embodiment, the second driving transistor is an oxide TFT, and the first driving transistor has a polarity opposite to that of the second driving transistor.

[0015] In another embodiment, the driving selection circuit further includes a reset circuit. The reset circuit is electrically connected to the selection circuit and is used to control the corresponding oxide TFT in the pixel circuit to be turned on.

[0016] In this embodiment, since the off-state current (Ioff) of the oxide TFT is small and it is easy to accumulate charges, therefore, by setting a reset circuit in the driving selection circuit, the corresponding oxide TFT in the pixel circuit is reset to release the accumulated charges. That is, the oxide TFT in the pixel circuit is controlled to be turned on to release the charges, thereby improving the stability of the driving TFT in the pixel circuit.

[0017] In another embodiment, the reset circuit includes a reset transistor. The gate of the reset transistor is used to receive a reset signal. During reset, the reset signal is at a low level. The first pole of the reset transistor is connected to the selection circuit, and the second pole of the reset transistor is connected to a positive voltage source.

[0018] In this embodiment, the first pole of the reset transistor is electrically connected to the first pole of the second transistor, the gate of the fourth transistor, the gate of the sixth transistor, and the first pole of the capacitor.

[0019] In another embodiment, the driving selection circuit further includes a reset circuit. The reset circuit is electrically connected to the selection circuit and is used to control the corresponding oxide TFT in the pixel circuit to turn on and control the oxide TFT in the driving circuit to turn on.

[0020] In this embodiment, on the one hand, the reset circuit resets the corresponding oxide TFT in the pixel circuit, thereby improving the stability of the driving TFT in the pixel circuit. On the other hand, the reset circuit resets the oxide TFT in the driving circuit, thereby improving the stability of the driving circuit.

[0021] In another embodiment, the reset circuit includes a first reset transistor and a second reset transistor. The gate of the first reset transistor is used to receive a first reset signal. During reset, the first reset signal is at a low level. The first pole of the first reset transistor is connected to the selection circuit, and the second pole of the first reset transistor is connected to a positive voltage source. The gate of the second reset transistor is used to receive a second reset signal. During reset, the second reset signal is at a low level. The first pole of the second reset transistor is connected to the selection circuit, and the second pole of the second reset transistor is connected to a negative voltage source.

[0022] In this embodiment, both the first reset transistor and the second reset transistor are electrically connected to the first pole of the second transistor, the gate of the fourth transistor, the gate of the sixth transistor, and the first pole of the capacitor. During reset, the reset time of the first reset signal is earlier than the reset time of the second reset signal. When the first reset signal is at a low level, the scan signal is at a high level, causing the corresponding oxide TFT in the pixel circuit to turn on. Therefore, the oxide TFT releases charge, thereby improving the stability of the driving TFT in the pixel circuit. When the second reset signal is at a low level, the scan signal is at a low level, causing the oxide TFT in the driving circuit to turn on. Therefore, the oxide TFT releases charge, thereby improving the stability of the driving circuit.

[0023] In a second aspect of the embodiments of the present application, a display screen is provided. The display screen includes a pixel circuit, a display driving integrated circuit, a GOA circuit, and the driving selection circuit of the embodiments of the present application. The pixel circuit includes oxide TFTs. The driving selection circuit is configured to output corresponding scanning signals according to a row driving signal from the GOA circuit and a control signal from the display driving integrated circuit. The scanning signals are used to control the conduction or cutoff of the corresponding oxide TFTs in the pixel circuit.

[0024] In a third aspect of the embodiments of the present application, an electronic device is provided. The electronic device includes the display screen of the embodiments of the present application.

[0025] For the technical effects brought by the second aspect and the third aspect of the embodiments of the present application, reference may be made to the relevant description of the driving selection circuit in the first aspect above, which will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a schematic structural diagram of a display screen provided by an embodiment of the present application.

[0027] Figure 2 It is a schematic structural diagram of a pixel circuit provided by an example.

[0028] Figure 3 It is a schematic diagram of the partitioned display of a display screen provided by an example.

[0029] Figure 4 It is a waveform schematic diagram of a control signal and a fifth scanning signal during the partitioned display of a display screen provided by an example.

[0030] Figure 5A It is a schematic diagram of the connection relationship of a driving selection circuit provided by an example.

[0031] Figure 5B It is Figure 5A a schematic structural diagram of the driving selection circuit shown.

[0032] Figure 6A It is Figure 5B a schematic diagram of the working principle of the driving selection circuit shown in the first display area under the first scenario.

[0033] Figure 6B It is Figure 5B a schematic diagram of the working principle of the driving selection circuit shown in the first display area under the second scenario.

[0034] Figure 6C It is Figure 5B a schematic diagram of the working principle of the driving selection circuit shown in the first display area under the third scenario.

[0035] Figure 6D It is Figure 5BWaveform schematic diagram of each signal in the driving selection circuit shown in the first display area.

[0036] Figure 7A is Figure 5B Schematic diagram of the working principle of the driving selection circuit shown in the second display area under scenario one.

[0037] Figure 7B is Figure 5B Schematic diagram of the working principle of the driving selection circuit shown in the second display area under scenario two.

[0038] Figure 7C is Figure 5B Schematic diagram of the working principle of the driving selection circuit shown in the second display area under scenario three.

[0039] Figure 7D is Figure 5B Schematic diagram of the working principle of the driving selection circuit shown in the second display area under scenario four.

[0040] Figure 7E is Figure 5B Waveform schematic diagram of each signal in the driving selection circuit shown in the second display area.

[0041] Figure 8A is Figure 5B Schematic diagram of the working principle of the driving selection circuit at the junction of the second display area and the third display area under scenario one.

[0042] Figure 8B is Figure 5B Schematic diagram of the working principle of the driving selection circuit at the junction of the second display area and the third display area under scenario two.

[0043] Figure 8C is Figure 5B Schematic diagram of the working principle of the driving selection circuit at the junction of the second display area and the third display area under scenario three.

[0044] Figure 8D is Figure 5B Schematic diagram of the working principle of the driving selection circuit at the junction of the second display area and the third display area under scenario four.

[0045] Figure 8E is Figure 5B Waveform schematic diagram of each signal in the driving selection circuit at the junction of the second display area and the third display area.

[0046] Figure 9A is the structural schematic diagram of the driving selection circuit provided by another embodiment of the present application.

[0047] Figure 9B isFigure 9A Waveform schematic diagrams of the reset signal and the scan signal in the driving selection circuit shown.

[0048] Figure 10A It is a schematic structural diagram of a driving selection circuit provided by another embodiment of the present application.

[0049] Figure 10B is Figure 10A Waveform schematic diagrams of the reset signal and the scan signal in the driving selection circuit shown. Detailed implementation manners

[0050] It should be noted that in the embodiments of the present application, "several" means one or more, and "a plurality" means two or more than two. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone, where A and B may be singular or plural. The terms "first", "second", etc. in the description and claims of the present application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0051] In the embodiments of the present application, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection. "Electrical connection" includes cases where constituent elements are connected together through elements having a certain electrical effect. Examples of "elements having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions. A transistor refers to an element including at least three terminals: a gate, a drain, and a source. In the related description of a transistor, the first pole may be the drain, the second pole may be the source, or the first pole may be the source and the second pole may be the drain. In the case of using transistors with opposite polarities or when the current direction changes, the functions of the "source" and "drain" are sometimes interchanged, that is, the "source" and "drain" can be interchanged with each other.

[0052] In the embodiments of the present application, the display screen may be a foldable display screen or a non-foldable display screen, and the display screen includes a display panel. The display panel may adopt Organic Light-Emitting Diode (OLED), Active-Matrix Organic Light Emitting Diode (AMOLED), Flex Light-Emitting Diode (FLED), Mini-LED, Micro-LED, Micro-OLED, Quantum Dot Light Emitting Diode (QLED), etc.

[0053] The structure of the display screen will be introduced below by taking the OLED display screen as an example.

[0054] As Figure 1 shown, the display screen 100 includes a pixel array 110, a pixel circuit 120, a peripheral driving circuit 130, and a Display Driver Integrated Circuit (DDIC) 140. Among them, the pixel array 110 is located above the pixel circuit 120, the peripheral driving circuit 130, and the DDIC 140, and the pixel circuit 120, the peripheral driving circuit 130, and the DDIC 140 are located on the same layer. The pixel array 110 is formed by arranging a plurality of pixels, and a corresponding pixel circuit 120 is provided below each pixel. For example, a typical distribution of the pixel array is 1920*1080 pixels, and 1920 corresponding pixel circuits 120 are arranged in the row direction and 1080 corresponding pixel circuits 120 are arranged in the column direction. The pixel circuit 120 includes an OLED, and by controlling the OLED to be lit or extinguished, the corresponding pixel can be controlled to present a bright state or a dark state.

[0055] The peripheral driving circuit 130 includes a row driving circuit 131 and a column driving circuit 132. Both the row driving circuit 131 and the column driving circuit 132 are electrically connected to the DDIC 140. Among them, the row driving circuit 131 is used to generate a row driving signal for driving the pixel circuits 120 corresponding to a row of pixels in the pixel array 110 according to a control signal from the DDIC 140. The essence of the row driving circuit 131 is a linear controller, and the direction of the linear controller is single, that is, scanning from the first row of pixels to the last row of pixels in the pixel array 110, or scanning from the last row of pixels to the first row of pixels in the pixel array 110. When displaying a frame of image, after the first row of pixels presents a bright state, it needs to maintain the bright state until the last row of pixels also presents a bright state, so as to realize the display and refresh of a frame of image. The column driving circuit 132 is used to linearly load the data signal directly or indirectly (for example, through a time shifter) into the pixel circuits 120 corresponding to a column of pixels according to a control signal from the DDIC 140, that is, loading in sequence according to the column order in the pixel array 110.

[0056] In some embodiments, the pixel circuit 120 may adopt the low temperature polycrystalline oxide (LTPO) technology combining low temperature poly-silicon (LTPS) and indium gallium zinc oxide (IGZO). Exemplarily, as Figure 2 shown, the pixel circuit 120 includes an OLED, a storage capacitor Cst, transistors Q1 to Q6, and oxide transistors M1 to M2.

[0057] Among them, the gate of the transistor Q1 is connected to the first pole of the oxide transistor M1, the first pole of the oxide transistor M2, and the first pole of the storage capacitor Cst. The first pole of the transistor Q1 is connected to the second pole of the transistor Q2, the first pole of the transistor Q5, and the second pole of the transistor Q6. The second pole of the transistor Q1 is connected to the first pole of the transistor Q3 and the second pole of the oxide transistor M1. The first pole of the transistor Q2 and the second pole of the storage capacitor Cst are both connected to the first power supply VDD. The second pole of the transistor Q3 is connected to the anode of the OLED and the first pole of the transistor Q4. The cathode of the OLED is connected to the second power supply VSS.

[0058] In this embodiment, the gates of the transistor Q2 and the transistor Q3 are both used to receive the scan signal Scan1. The gates of the transistor Q4 and the transistor Q5 are both used to receive the scan signal Scan2. The gate of the transistor Q6 is used to receive the scan signal Scan3. The gate of the oxide transistor M1 is used to receive the scan signal Scan4. The gate of the oxide transistor M2 is used to receive the scan signal Scan5.

[0059] The second pole of the oxide transistor M2 is used to receive the reset voltage Vref1. The second pole of the transistor Q4 is used to receive the reset voltage Vref2. The second pole of the transistor Q5 is used to receive the reset voltage Vref3. The first pole of the transistor Q6 is used to receive the data signal Data.

[0060] In this embodiment, the transistor Q1 is a driving thin film transistor (TFT), and the oxide transistors M1 and M2 are both oxide TFTs. Among them, the oxide transistors M1 and M2 are used to control the transistor Q1 to turn on or off, thereby controlling the OLED to light up or go out, and further controlling the pixel corresponding to the OLED to present a bright state or a dark state. Since the oxide TFT has the characteristic of low leakage current, the brightness of the OLED can be maintained for a long time, so that the low-frequency display and high brightness retention rate of the display screen can be achieved, and thus the power consumption can be reduced by reducing the refresh rate of the static picture. The refresh rate refers to the number of times the electron beam repeatedly scans the image on the display screen, and the unit is Hertz (Hz). In other words, the refresh rate represents the number of times the picture on the display screen is refreshed per second. The higher the refresh rate of the display screen, the smoother the display of the dynamic picture.

[0061] Therefore, in some embodiments, according to the needs of the display picture, different regions of the display screen can be controlled to display at different frequencies, that is, zoned display, to reduce power consumption. For example, as Figure 3 shown, the pixel array of the display screen includes k rows of pixels. In the scenario of displaying a video picture, the display screen can be divided into three display regions. Among them, the first display region 201 includes the 1st to (n - 1)th rows of pixels, the second display region 202 includes the nth to mth rows of pixels, and the third display region 203 includes the (m + 1)th to kth rows of pixels. Among them, the second display region 202 is a high-frequency display region with a relatively high refresh rate (for example, 120 Hz) and is used to display dynamic pictures, such as displaying video pictures. The first display region 201 and the third display region 203 are both low-frequency display regions with a relatively low refresh rate (for example, 10 Hz) and are used to display static pictures. For example, the first display region 201 displays the status bar, and the third display region 203 displays the return key, home key, etc.

[0062] It can be understood that to achieve low-frequency display in the first display area 201 and the third display area 203, and high-frequency display in the second display area 202, it is necessary to control the refresh rate of each display area. The refresh rate of each display area is related to the operating frequency of the pixel circuit corresponding to each pixel. As described above, taking the pixel circuit 120 as an example, the operating frequency of the pixel circuit 120 is related to the driving frequency of the transistor Q1, and the driving frequency of the transistor Q1 is related to the conduction state of the oxide transistors M1 / M2. Each time the screen is refreshed, by inputting the scan signals Scan4 / Scan5 to the pixel circuit 120, the oxide transistors M1 / M2 are turned on, thereby controlling the driving frequency of the transistor Q1, and further controlling the operating frequency of the pixel circuit 120.

[0063] Obviously, to achieve the refresh of different display areas of the display screen, it is crucial to control the conduction and cutoff of the oxide TFTs (for example, oxide transistors M1, M2) in the pixel circuit.

[0064] It can be understood that taking Figure 2 the shown scan signal Scan5 as an example, as Figure 4 shown, when controlling the conduction and cutoff of the oxide TFTs in the pixel circuit, since the control signal Ctrol from the DDIC is at a high level in the high-frequency display area and at a low level in the low-frequency display area, and the pulse width of the control signal Ctrol is much larger than the pulse width of the scan signal Scan5. Therefore, in the high-frequency display area, when the control signal Ctrol is at a high level, it is necessary to control the scan signal Scan5 to be at a high level. Similarly, in the low-frequency display area, when the control signal Ctrol is at a low level, it is necessary to control the scan signal Scan5 to be at a low level. However, at the junction of the high-frequency display area and the low-frequency display area, that is, the m-th row of pixels, since the control signal Ctrol jumps, the scan signal Scan5 will be abnormally cut off, thus affecting the display effect.

[0065] Based on this, the embodiments of the present application provide a driving selection circuit, a display screen, and an electronic device, aiming to solve the problem that the scan signal of the oxide TFT in the pixel circuit is abnormally cut off.

[0066] Figure 5A It is a schematic connection diagram of a driving selection circuit provided by an example.

[0067] Please refer to Figure 1 and Figure 5A together. In some embodiments, Figure 1The shown row driving circuit 131 may include an array substrate gate driver (GOA) circuit 200 and a driving selection circuit 500. The GOA circuit 200 is electrically connected to the DDIC 140 and is configured to generate a row driving signal for driving the pixel circuits 120 corresponding to one row of pixels. The driving selection circuit 500 is electrically connected to the GOA circuit 200, the DDIC 140, and the pixel circuits 120, and is configured to control the corresponding oxide TFTs in the pixel circuits 120 to turn on or off according to the row driving signal from the GOA circuit 200 and the control signal from the DDIC 140.

[0068] Figure 5B is Figure 5A The structural schematic diagram of the shown driving selection circuit.

[0069] As Figure 5B shown, the driving selection circuit 500 includes a selection circuit 510 and a driving circuit 520. The selection circuit 510 is electrically connected to the GOA circuit (not shown in the figure), the DDIC (not shown in the figure), and the driving circuit 520, and is configured to output a high level or a low level to the driving circuit 520 according to the row driving signal from the GOA circuit and the control signal from the DDIC. The driving circuit 520 is electrically connected to the pixel circuit (not shown in the figure), and is configured to output a scanning signal of the corresponding oxide TFT to the pixel circuit according to the high level or the low level from the selection circuit 510, so as to control the corresponding oxide TFT to turn on or off.

[0070] The selection circuit 510 includes a first input terminal, a second input terminal, a control terminal, and an output terminal. The first input terminal of the selection circuit 510 is configured to receive the row driving signal Gatei from the GOA circuit. The second input terminal of the selection circuit 510 is configured to receive the row driving signal Gatej from the GOA circuit. Among them, the row driving signal Gatei is associated with the pixel circuit corresponding to the i-th row of pixels. The row driving signal Gatej is associated with the pixel circuit corresponding to the j-th row of pixels. Among them, i and j are integers, and i is greater than j. For example, when i is 3, and j is 1 or 2, the first input terminal of the selection circuit 510 receives the row driving signal Gate3, and the row driving signal Gate3 is associated with the pixel circuit corresponding to the 3rd row of pixels. The second input terminal of the selection circuit 510 receives the row driving signal Gate1 or Gate2, and the row driving signal Gate1 / Gate2 is associated with the pixel circuit corresponding to the 1st / 2nd row of pixels. Another example is that when i is 1, and j is 0, the first input terminal of the selection circuit 510 receives the row driving signal Gate1, and the second input terminal of the selection circuit 510 receives the row driving signal Gate0, where the row driving signal Gate0 is a preset value.

[0071] The control terminal of the selection circuit 510 is electrically connected to the DDIC and is used to receive the control signal Ctrol from the DDIC.

[0072] The output terminal of the selection circuit 510 is electrically connected to the driving circuit 520 and is used to output a high level or a low level to the driving circuit 520 according to the row driving signals Gatei, Gatej and the control signal Ctrol.

[0073] The selection circuit 510 further includes transistors T1 to T6 and a capacitor C. Among them, the gates of the transistor T1, the transistor T3 and the transistor T5 are connected together to form a node N4. The node N4 serves as the first input terminal of the selection circuit 510. The second pole of the transistor T1 serves as the control terminal of the selection circuit 510. The first pole of the transistor T1 is electrically connected to the second pole of the transistor T2.

[0074] The gate of the transistor T2 serves as the second input terminal of the selection circuit 510. The first pole of the transistor T2 is connected to the gates of the transistor T4, the transistor T6 and the first pole of the capacitor C to form a node N2. The second pole of the capacitor C is connected to the negative voltage source VGL.

[0075] The first pole of the transistor T3 is electrically connected to the second pole of the transistor T4, and the second pole of the transistor T3 is connected to the negative voltage source VGL.

[0076] The first pole of the transistor T4 is electrically connected to the second poles of the transistor T5 and the transistor T6 to form a node N3. The node N3 serves as the output terminal of the selection circuit 510. The first poles of the transistor T5 and the transistor T6 are both connected to the positive voltage source VGH.

[0077] In this embodiment, the positive voltage source VGH is used to output a high level, such as a DC voltage greater than 0, such as 7V, 8V, etc. The negative voltage source VGL is used to output a low level, such as a DC voltage less than or equal to 0, such as -7V, -8V, etc.

[0078] The driving circuit 520 includes an input terminal and an output terminal. The input terminal of the driving circuit 520 is electrically connected to the output terminal of the selection circuit 510 and is used to receive a high level or a low level from the selection circuit 510. The output terminal of the driving circuit 520 is electrically connected to the pixel circuit corresponding to the i-th row of pixels and is used to output a corresponding scanning signal to the pixel circuit corresponding to the i-th row of pixels according to the high level or the low level output by the selection circuit 510, thereby controlling the corresponding oxide TFT in the pixel circuit corresponding to the i-th row of pixels to be turned on or off.

[0079] The driving circuit 520 further includes driving transistors T7 to T8. Among them, the gates of driving transistor T7 and driving transistor T8 are electrically connected to form a node N1. The node N1 serves as the input terminal of the driving circuit 520 and is electrically connected to the node N3 of the selection circuit 510. The second pole of driving transistor T7 and the first pole of driving transistor T8 are electrically connected to form a node N5. The node N5 serves as the output terminal of the driving circuit 520. The first pole of driving transistor T7 is connected to the positive voltage source VGH. The second pole of driving transistor T8 is connected to the negative voltage source VGL.

[0080] In this embodiment, transistors T2 to T4 and driving transistor T8 are oxide TFTs and have the same polarity. Transistor T2 conducts when the row driving signal Gatej is at a high level and turns off when the row driving signal Gatej is at a low level. Transistor T3 conducts when the row driving signal Gatei is at a high level and turns off when the row driving signal Gatei is at a low level. Transistor T4 conducts when the voltage at node N2 is at a high level and turns off when the voltage at node N2 is at a low level. Driving transistor T8 conducts when the voltage at node N1 is at a high level and turns off when the voltage at node N1 is at a low level.

[0081] Transistors T1, T5 to T6 and driving transistor T7 have the same polarity, and are opposite to the polarity of transistor T2 / T3 / T4 or driving transistor T8. Both transistor T1 and T5 conduct when the row driving signal Gatei is at a low level and turn off when the row driving signal Gatei is at a high level. Transistor T6 conducts when the voltage at node N2 is at a low level and turns off when the voltage at node N2 is at a high level. Driving transistor T7 conducts when the voltage at node N1 is at a low level and turns off when the voltage at node N1 is at a high level.

[0082] The following Figure 3 and several scenarios are used to introduce in detail the working principle of the driving selection circuit 500.

[0083] In this embodiment, for the first display area 201, such as the pixels in the 1st to (n - 1)th rows, the following scenarios are included:

[0084] Scenario 1, the control signal Ctrol and the row driving signals Gate(n - 2) and Gate(n - 1) are all at a low level.

[0085] Scenario 2, the control signal Ctrol and the row driving signal Gate(n - 1) are both at a low level, and the row driving signal Gate(n - 2) is at a high level.

[0086] Scenario 3, the control signal Ctrol is at a low level, and the row driving signals Gate(n - 2) and Gate(n - 1) are both at a high level.

[0087] Correspondingly, please refer to Figures 6A to 6D , Figures 6A to 6C which are respectively Figure 5B the schematic diagrams of the driving selection circuit shown in the working principles of Scenario 1 to Scenario 3 in the first display area. Figure 6D is Figure 5B the waveform schematic diagram of each signal in the driving selection circuit shown in the first display area.

[0088] As Figure 6A shown, in Scenario 1 of the first display area 201, when i is greater than or equal to 1 and less than or equal to n - 1, since the row driving signals Gatei and Gatej are both low levels, the transistors T3 and T2 are respectively turned off under the control of the row driving signals Gatei and Gatej. The transistor T5 is turned on under the control of the row driving signal Gatei, so that the high level output by the positive voltage source VGH is applied to the node N3. Since the node N1 is electrically connected to the node N3, the voltage of the node N1 is close to the high level output by VGH, thereby driving the transistor T8 to turn on and driving the transistor T7 to turn off, so that the low level output by the negative voltage source VGL is applied to the node N5. Thus, the driving selection circuit 500 outputs a low level.

[0089] As Figure 6B shown, in Scenario 2 of the first display area 201, when i is greater than or equal to 1 and less than or equal to n - 1, since the row driving signal Gatei is at a low level, the transistor T3 is turned off under the control of the row driving signal Gatei, and the transistor T1 is turned on under the control of the row driving signal Gatei. Also, since the row driving signal Gatej is at a high level, the transistor T2 is turned on under the control of the row driving signal Gatej, so that the control signal Ctrol is applied to the node N2. Since the control signal Ctrol is at a low level, the voltage of the node N2 is at a low level, whereby the transistor T6 is turned on, so that the high level output by the positive voltage source VGH is applied to the node N3. At the same time, the capacitor C stores the voltage of the node N2. In addition, the transistor T5 is turned on under the control of the row driving signal Gatei, so that the high level output by the positive voltage source VGH is applied to the node N3. Since the transistor T5 is in parallel with the transistor T6, the voltage of the node N3 is close to the high level output by the positive voltage source VGH. Since the node N1 is electrically connected to the node N3, the voltage of the node N1 is close to the high level output by the positive voltage source VGH, thereby driving the transistor T8 to turn on and driving the transistor T7 to turn off, so that the low level output by the negative voltage source VGL is applied to the node N5. Thus, the driving selection circuit 500 outputs a low level.

[0090] As Figure 6CAs shown, in Scenario 3 of the first display area 201, when i is greater than or equal to 1 and less than or equal to n - 1, since the row driving signal Gatei is at a high level, transistors T1 and T5 are turned off under the control of the row driving signal Gatei. And since the voltage of node N2 remains at a low level due to capacitor C, transistor T6 is turned on, causing the high level output by the positive voltage source VGH to be applied to node N3. Since node N1 is electrically connected to node N3, the voltage of node N1 approaches the high level output by the positive voltage source VGH, thereby driving transistor T8 to turn on and driving transistor T7 to turn off, causing the low level output by the negative voltage source VGL to be applied to node N5. Thus, the driving selection circuit 500 outputs a low level.

[0091] As Figure 6D shown, Ctrol is the control signal of the DDIC, Gate(n - 2) is the row driving signal of the pixel circuit corresponding to the (n - 2)-th row of pixels, Gate(n - 1) is the row driving signal of the pixel circuit corresponding to the (n - 1)-th row of pixels, and Out(1) to Out(n - 1) are the scanning signals output by the driving selection circuit 500 corresponding to the 1st to (n - 1)-th rows of pixels, respectively.

[0092] Obviously, for various scenarios of the first display area 201, such as Scenarios 1 to 3 above, when the control signal Ctrol is at a low level, regardless of whether the row driving signals Gatei and Gatej generated by the GOA circuit are at a high level or a low level, the driving selection circuit 500 will continuously output a low level. For example Figure 6D shown, the scanning signals Out(1) to Out(n - 1), thereby controlling the corresponding oxide TFTs in the pixel circuit to turn off, causing the first display area 201 to maintain a low-frequency display.

[0093] It can be understood that since both the third display area 203 and the first display area 201 are low-frequency display areas, the scenarios of the third display area 203 are substantially the same as those of the first display area 201. The working principle of the driving selection circuit 500 in the third display area 203 can refer to the relevant description of the first display area 201 and will not be elaborated here.

[0094] In this embodiment, for the second display area 202, for example, the (n)-th to (m - 1)-th rows of pixels, the following scenarios are included:

[0095] Scenario 1: The control signal Ctrol and the row driving signal Gate(n - 1) are both at a high level, and the row driving signal Gate(n) is at a low level.

[0096] Scenario 2: The control signal Ctrol and the row driving signals Gate(n - 1) and Gate(n) are all at a high level.

[0097] Scenario 3: The control signal Ctrol and the row driving signal Gate(n) are both at high level, and the row driving signal Gate(n - 1) is at low level.

[0098] Scenario 4: The control signal Ctrol is at high level, and the row driving signals Gate(n - 1) and Gate(n) are both at low level.

[0099] Correspondingly, please refer to Figures 7A to 7E , Figures 7A to 7D which are respectively Figure 5B the working principle diagrams of the driving selection circuit shown in the scenarios 1 to 4 in the second display area. Figure 7E is Figure 5B the waveform schematic diagrams of each signal in the driving selection circuit shown in the second display area.

[0100] As Figure 7A shown, in scenario 1 of the second display area 202, when i is greater than or equal to n and less than or equal to m - 1, since the row driving signal Gatei is at low level, the transistor T3 is turned off under the control of the row driving signal Gatei, while the transistor T1 is turned on under the control of the row driving signal Gatei. Also, since the row driving signal Gatej is at high level, the transistor T2 is turned on under the control of the row driving signal Gatej, enabling the control signal Ctrol to be applied to the node N2. Since the control signal Ctrol is at high level, the voltage of N2 is at high level. Meanwhile, the capacitor C stores the voltage of the node N2. In addition, the transistor T5 is turned on under the control of the row driving signal Gatei, enabling the high level output by the positive voltage source VGH to be applied to the node N3. Since the node N1 is electrically connected to the node N3, the voltage of the node N1 is close to the high level output by the positive voltage source VGH, thereby driving the transistor T8 to be turned on and driving the transistor T7 to be turned off, enabling the low level output by the negative voltage source VGL to be applied to the node N5. Thus, the driving selection circuit 500 outputs a low level.

[0101] As Figure 7BAs shown, in Scene 2 of the second display area 202, when i is greater than or equal to n and less than or equal to m - 1, since the row driving signal Gatei is at a high level, transistors T1 and T5 are turned off under the control of the row driving signal Gatei, while transistor T3 is turned on under the control of the row driving signal Gatei. Also, since the row driving signal Gatej is at a high level, transistor T2 is turned on under the control of the row driving signal Gatej. And since the voltage of node N2 remains at a high level due to capacitor C, transistor T4 is turned on, causing the low level output by the negative voltage source VGL to be applied to node N3. Since node N1 is electrically connected to node N3, the voltage of node N1 approaches the low level output by the negative voltage source VGL, thereby driving transistor T7 to turn on and driving transistor T8 to turn off, causing the high level output by the positive voltage source VGH to be applied to node N5. Thus, the driving selection circuit 500 outputs a high level.

[0102] As Figure 7C shown, in Scene 3 of the second display area 202, when i is greater than or equal to n and less than or equal to m - 1, since the row driving signal Gatei is at a high level, transistors T1 and T5 are turned off under the control of the row driving signal Gatei, while transistor T3 is turned on under the control of the row driving signal Gatei. Also, since the row driving signal Gatej is at a low level, transistor T2 is turned off under the control of the row driving signal Gatej. And since the voltage of node N2 remains at a high level due to capacitor C, transistor T4 is turned on, causing the low level output by the negative voltage source VGL to be applied to node N3. Since node N1 is electrically connected to node N3, the voltage of node N1 approaches the low level output by the negative voltage source VGL, thereby driving transistor T7 to turn on and driving transistor T8 to turn off, causing the high level output by the positive voltage source VGH to be applied to node N5. Thus, the driving selection circuit 500 outputs a high level.

[0103] As Figure 7D shown, in Scene 4 of the second display area 202, when i is greater than or equal to n and less than or equal to m - 1, since both the row driving signals Gatei and Gatej are at a low level, transistors T3 and T2 are turned off respectively under the control of the row driving signals Gatei and Gatej, while transistor T5 is turned on under the control of the row driving signal Gatei, causing the high level output by the positive voltage source VGH to be applied to node N3. Since node N1 is electrically connected to node N3, the voltage of node N1 approaches the high level output by the positive voltage source VGH, thereby driving transistor T8 to turn on and driving transistor T7 to turn off, causing the low level output by the negative voltage source VGL to be applied to node N5. Thus, the driving selection circuit 500 outputs a low level.

[0104] As Figure 7EAs shown, Ctrol is the control signal of the DDIC, Gate(n - 1) is the row driving signal of the pixel circuit corresponding to the (n - 1)-th row of pixels, Gate(n) is the row driving signal of the pixel circuit corresponding to the n-th row of pixels, and Out(n) to Out(m - 1) are the scanning signals output by the driving selection circuit 500 corresponding to the n-th to (m - 1)-th rows of pixels respectively.

[0105] Obviously, for various scenarios of the second display area 202, such as Scenario 1 to Scenario 3 above, when the control signal Ctrol is at a high level and the row driving signal Gatei generated by the GOA circuit is at a high level, the driving selection circuit 500 outputs a high level. When the row driving signal Gatei generated by the GOA circuit is at a low level, the driving selection circuit 500 outputs a low level. Since the pulse width of the control signal Ctrol is much larger than the pulse width of the row driving signal Gatei, the scanning signal output by the driving selection circuit 500 has the same phase and pulse width as the row driving signal Gatei. For example Figure 7E the scanning signals Out(n) to Out(m - 1) shown.

[0106] In this embodiment, for the junction of the second display area 202 and the third display area 203, such as the m-th row of pixels, the following scenarios are included:

[0107] Scenario 1, the control signal Ctrol, the row driving signals Gate(m) and Gate(m - 1) are all at a high level.

[0108] Scenario 2, the control signal Ctrol is at a low level, and the row driving signals Gate(m) and Gate(m - 1) are both at a high level.

[0109] Scenario 3, the control signal Ctrol and the row driving signal Gate(m - 1) are both at a low level, and the row driving signal Gate(m) is at a high level.

[0110] Scenario 4, the control signal Ctrol, the row driving signals Gate(m) and Gate(m - 1) are all at a low level.

[0111] Correspondingly, please refer to Figures 8A to 8E , Figures 8A to 8D which are Figure 5B the working principle diagrams of the driving selection circuit at the junction of the second display area and the third display area under Scenarios 1 to 4 respectively. Figure 8E is Figure 5B the waveform schematic diagrams of each signal in the driving selection circuit at the junction of the second display area and the third display area.

[0112] As Figure 8AAs shown, in Scenario 1 at the junction of the second display area 202 and the third display area 203, when i is equal to m, since the row driving signal Gatei is at a high level, transistors T1 and T5 are turned off under the control of the row driving signal Gatei, while transistor T3 is turned on under the control of the row driving signal Gatei. Also, since the row driving signal Gatej is at a high level, transistor T2 is turned on under the control of the row driving signal Gatej. And since the voltage of node N2 remains at a high level due to capacitor C, transistor T4 is turned on, causing the low level output by the negative voltage source VGL to be applied to node N3. Since node N1 is electrically connected to node N3, the voltage of node N1 is close to the low level output by the negative voltage source VGL, thereby driving transistor T7 to turn on and driving transistor T8 to turn off, causing the high level output by the positive voltage source VGH to be applied to node N5. Thus, the driving selection circuit 500 outputs a high level.

[0113] As Figure 8B shown, in Scenario 2 at the junction of the second display area 202 and the third display area 203, when i is equal to m, since the row driving signal Gatei is at a high level, transistor T3 is turned on under the control of the row driving signal Gatei, while transistors T1 and T5 are turned off under the control of the row driving signal Gatei. Since transistor T1 is turned off, a change in the control signal Ctrol will not change the voltage of node N2. Also, since the row driving signal Gatej is at a high level, transistor T2 is turned on under the control of the row driving signal Gatej. And since the voltage of node N2 remains at a high level due to capacitor C, transistor T4 is turned on, causing the low level output by the negative voltage source VGL to be applied to N3. Since node N1 is electrically connected to node N3, the voltage of node N1 is close to the low level output by the negative voltage source VGL, thereby driving transistor T7 to turn on and driving transistor T8 to turn off, causing the high level output by the positive voltage source VGH to be applied to node N5. Thus, the driving selection circuit 500 outputs a high level.

[0114] As Figure 8CAs shown, in Scenario 3 at the junction of the second display area and the third display area, when i is equal to m, since the row driving signal Gatei is at a high level, the transistor T3 is turned on under the control of the row driving signal Gatei, while the transistors T1 and T5 are turned off under the control of the row driving signal Gatei. Since the transistor T1 is turned off, a change in the control signal Ctrol will not change the voltage of the node N2. Also, since the row driving signal Gatej is at a low level, the transistor T2 is turned off under the control of the row driving signal Gatej. And since the voltage of the node N2 remains at a high level due to the capacitor C, the transistor T4 is turned on, causing the low level output by the negative voltage source VGL to be applied to N3. Since the node N1 is electrically connected to the node N3, the voltage of the node N1 is close to the low level output by the negative voltage source VGL, thereby driving the transistor T7 to be turned on and driving the transistor T8 to be turned off, causing the high level output by the positive voltage source VGH to be applied to the node N5. Thus, the driving selection circuit 500 outputs a high level.

[0115] As Figure 8D shown, in Scenario 4 at the junction of the second display area and the third display area, when i is equal to m, since both the row driving signals Gatei and Gatej are at low levels, the transistors T3 and T2 are respectively turned off under the control of the row driving signals Gatei and Gatej. While the transistor T5 is turned on under the control of the row driving signal Gatei, causing the high level output by the positive voltage source VGH to be applied to the node N3. Since the node N1 is electrically connected to the node N3, the voltage of the node N1 is close to the high level output by the positive voltage source VGH, thereby driving the transistor T8 to be turned on and driving the transistor T7 to be turned off, causing the low level output by the negative voltage source VGL to be applied to the node N5. Thus, the driving selection circuit 500 outputs a low level.

[0116] As Figure 8E shown, Ctrol is the control signal of the DDIC, Gate(m - 1) is the row driving signal of the pixel circuit corresponding to the (m - 1)-th row of pixels, Gate(m) is the row driving signal of the pixel circuit corresponding to the m-th row of pixels, and Out(m) is the scanning signal output by the driving selection circuit 500 corresponding to the m-th row of pixels.

[0117] Obviously, for various scenarios at the junction of the second display area 202 and the third display area 203, such as the above Scenarios 1 to 4, when the control signal Ctrol changes, that is, changes from a high level to a low level, if the row driving signal Gatei generated by the GOA circuit is at a high level, the driving selection circuit 500 outputs a high level. If the row driving signal Gatei generated by the GOA circuit is at a low level, the driving selection circuit 500 outputs a low level. For example Figure 8EThe scanning signal Out(m) shown. Thus, the scanning signal output by the driving selection circuit 500 is consistent with the row driving signal Gatei, and the row driving signal Gatei will not be abnormally cut off due to the jump of the control signal Ctrol, thereby improving the display performance.

[0118] Figure 9A It is a schematic structural diagram of a driving selection circuit provided by another embodiment of the present application.

[0119] Compared with Figure 5B the driving selection circuit 500 shown, the driving selection circuit 500A provided in this embodiment further includes a reset circuit 530A. The reset circuit 530A is electrically connected to the selection circuit 510 and is used to control the corresponding oxide TFT in the pixel circuit to conduct.

[0120] As Figure 9A shown, the reset circuit 530A includes a reset transistor T9. The gate of the reset transistor T9 is used to receive the reset signal RST1. The first pole of the reset transistor T9 is electrically connected to the node N2 and the first pole of the transistor T2. The second pole of the reset transistor T9 is connected to the positive voltage source VGH.

[0121] When the reset circuit 530A is reset, since the row driving signal Gatei is at a high level and the reset signal RST1 is at a low level, the reset transistor T9 is turned on under the control of the reset signal RST1, and the high level output by the positive voltage source VGH is applied to the node N2. Since the voltage of the node N2 is at a high level, the transistor T4 is turned on, and the transistor T3 is turned on under the control of the row driving signal Gatei, so that the low level output by the negative voltage source VGL is applied to the node N3. Since the node N1 is electrically connected to the node N3, the voltage of the node N1 is close to the low level output by the negative voltage source VGL, thereby driving the transistor T7 to conduct and driving the transistor T8 to turn off, so that the high level output by the positive voltage source VGH is applied to the node N5. Thus, the driving selection circuit 500A outputs a high level.

[0122] Figure 9B is Figure 9A a schematic waveform diagram of the reset signal and the scanning signal in the driving selection circuit shown.

[0123] As Figure 9B shown, RST1 is the reset signal of the reset circuit 530A, and the reset signal RST1 is at a low level during reset. Out is the scanning signal output by the driving selection circuit 500A. The scanning signal Out is at a high level when the reset circuit 530A is reset, so that the corresponding oxide TFT in the pixel circuit conducts.

[0124] It can be understood that in the pixel circuit, due to the small off-state current (Ioff) of the oxide TFT, charges are likely to accumulate. Therefore, by providing a reset circuit 530A in the driving selection circuit 500A, the corresponding oxide TFT in the pixel circuit is reset to release the accumulated charges. That is, the oxide TFT in the pixel circuit is controlled to conduct, so that the oxide TFT releases charges, thereby improving the stability of the driving TFT in the pixel circuit.

[0125] Figure 10A It is a schematic structural diagram of a driving selection circuit provided by another embodiment of the present application.

[0126] Compared with Figure 9A the driving selection circuit 500A shown, the difference between the driving selection circuit 500B provided in this embodiment and the driving selection circuit 500A is that the structure of the reset circuit 530B in the driving selection circuit 500B is different from the structure of the reset circuit 530A in the driving selection circuit 500A. Specifically, the reset circuit 530B includes reset transistors T9 and T10.

[0127] It can be understood that the function, connection relationship and working principle of the reset transistor T9 in the reset circuit 530B are the same as those of the reset transistor T9 in the reset circuit 530A, and will not be elaborated here.

[0128] As Figure 10A shown, the gate of the reset transistor T10 is used to receive the reset signal RST2. The first pole of the reset transistor T10 is electrically connected to the node N2, the gate of the transistor T6 and the first pole of the capacitor C. The second pole of the reset transistor T10 is connected to the negative voltage source VGL.

[0129] It can be understood that the reset transistor T10 is used to control the oxide TFT in the driving circuit 520 to conduct. Specifically, when the reset circuit 530B is reset, since the row driving signal Gatei is at a high level, the reset signal RST1 is at a high level, and the reset signal RST2 is at a low level, the reset transistor T10 is turned on under the control of the reset signal RST2, so that the low level output by the negative voltage source VGL is applied to the node N2. Since the voltage of the node N2 is at a low level, the transistor T6 is turned on, so that the high level output by the positive voltage source VGH is applied to the node N3. Since the node N1 is electrically connected to the node N3, the voltage of the node N1 is close to the high level output by the positive voltage source VGH, thereby driving the transistor T8 to conduct and the transistor T7 to turn off, so that the low level output by the negative voltage source VGL is applied to the node N5. Thus, the driving selection circuit 500B outputs a low level.

[0130] Figure 10B is Figure 10A a schematic waveform diagram of the reset signal and the scan signal in the driving selection circuit shown.

[0131] As Figure 10B shown, both RST1 and RST2 are reset signals. During reset, both reset signals RST1 and RST2 are at low level, but the reset time of reset signal RST1 is earlier than that of reset signal RST2.

[0132] Out is the scan signal output by the driving selection circuit 500B. Among them, when the reset signal RST1 is at low level, the scan signal Out is at high level, causing the corresponding oxide TFT in the pixel circuit to turn on. Therefore, the oxide TFT releases charges, thereby improving the stability of the driving TFT in the pixel circuit. When the reset signal RST2 is at low level, the scan signal Out is at low level, causing the oxide TFT in the driving circuit 520 to turn on. Therefore, the oxide TFT releases charges, thereby improving the stability of the driving circuit 520.

[0133] The embodiment of the present application also provides a row driving circuit, which includes a GOA circuit and a driving selection circuit. The driving selection circuit is electrically connected to the GOA circuit, the DDIC, and the pixel circuit. The DDIC is used to provide control signals to the GOA circuit and the driving selection circuit.

[0134] Among them, the driving selection circuit is the driving selection circuit provided by the embodiment of the present application, such as the driving selection circuit 500 shown in FIG. 5, or Figure 9A the driving selection circuit 500A shown in Figure 10A or the driving selection circuit 500B shown in

[0135] The embodiment of the present application also provides a display screen, which includes a pixel array, pixel circuits, a peripheral driving circuit, and a DDIC. The pixel array is formed by arranging a plurality of pixels, and a corresponding pixel circuit is provided below each pixel. The peripheral driving circuit includes a column driving circuit and the row driving circuit of the embodiment of the present application. Both the column driving circuit and the row driving circuit are electrically connected to the pixel circuits and the DDIC. The DDIC is used to provide control signals to the column driving circuit and the row driving circuit.

[0136] The embodiment of the present application also provides an electronic device, which includes a processor, a memory, and the display screen provided by the embodiment of the present application.

[0137] The above has described the embodiments of the present application in detail with reference to the drawings. However, the present application is not limited to the above embodiments. Within the knowledge scope of those of ordinary skill in the art to which the present application pertains, various changes can be made without departing from the gist of the present application.

Claims

1. A driving selection circuit, applied to a display screen, characterized in that, The display screen includes a pixel circuit, a display driving integrated circuit, and a GOA circuit. The pixel circuit includes oxide TFTs, and the driving selection circuit includes a selection circuit and a driving circuit; The selection circuit is electrically connected to the driving circuit and is configured to output a high level or a low level to the driving circuit according to a row driving signal from the GOA circuit and a control signal from the display driving integrated circuit; The driving circuit is configured to output a corresponding scanning signal according to the high level or the low level from the selection circuit, and the scanning signal is used to control conduction or cutoff of the corresponding oxide TFT in the pixel circuit.

2. The drive selection circuit according to claim 1, wherein The selection circuit includes a first input terminal, a second input terminal, a control terminal, and an output terminal; The first input terminal and the second input terminal of the selection circuit are respectively configured to receive a first row driving signal and a second row driving signal from the GOA circuit, and the first row driving signal and the second row driving signal respectively correspond to different rows of pixels in the pixel array of the display screen; The control terminal of the selection circuit is configured to receive the control signal from the display driving integrated circuit; The output terminal of the selection circuit is connected to the driving circuit and is configured to output the high level or the low level to the driving circuit according to the first row driving signal, the second row driving signal, and the control signal.

3. The drive selection circuit according to claim 2, wherein The selection circuit further includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a capacitor; The gates of the first transistor, the third transistor, and the fifth transistor are connected together and form the first input terminal of the selection circuit; The second pole of the first transistor serves as the control terminal of the selection circuit, and the first pole of the first transistor is electrically connected to the second pole of the second transistor; The gate of the second transistor serves as the second input terminal of the selection circuit, and the first pole of the second transistor is electrically connected to the gates of the fourth transistor, the sixth transistor, and the first pole of the capacitor; the second pole of the capacitor is connected to a negative voltage source; The first pole of the third transistor is electrically connected to the second pole of the fourth transistor, and the second pole of the third transistor is connected to the negative voltage source; The first poles of the fourth transistor, the second pole of the fifth transistor, and the second pole of the sixth transistor are connected together and form the output terminal of the selection circuit; The first poles of the fifth transistor and the sixth transistor are connected to a positive voltage source.

4. The drive selection circuit according to claim 3, wherein The second transistor, the third transistor, and the fourth transistor are all oxide TFTs and have the same polarity; The first transistor, the second transistor, and the sixth transistor have the same polarity and are opposite to the polarity of the second transistor, the third transistor, or the fourth transistor.

5. The drive selection circuit according to any one of claims 2 to 4, characterized in that, The driving circuit includes an input terminal and an output terminal; The input terminal of the driving circuit is electrically connected to the output terminal of the selection circuit; The output terminal of the driving circuit is configured to output the scanning signal.

6. The drive selection circuit according to claim 5, characterized in that The driving circuit further includes a first driving transistor and a second driving transistor; The gates of the first driving transistor and the second driving transistor are connected to form the input end of the driving circuit; The second pole of the first driving transistor and the first pole of the second driving transistor are connected to form the output end of the driving circuit; The first pole of the first driving transistor is connected to a positive voltage source, and the second pole of the second driving transistor is connected to a negative voltage source.

7. The drive selection circuit according to claim 6, wherein The second driving transistor is the oxide TFT, and the first driving transistor has a polarity opposite to that of the second driving transistor.

8. The drive selection circuit according to any one of claims 1 to 7, characterized in that The driving selection circuit further includes a reset circuit; The reset circuit is electrically connected to the selection circuit for controlling the corresponding oxide TFT in the pixel circuit to turn on.

9. The drive selection circuit according to claim 8, wherein The reset circuit includes a reset transistor; The gate of the reset transistor is used to receive a reset signal; during reset, the reset signal is the low level; The first pole of the reset transistor is connected to the selection circuit, and the second pole of the reset transistor is connected to a positive voltage source.

10. The drive selection circuit according to any one of claims 1 to 7, characterized in that, The driving selection circuit further includes a reset circuit; The reset circuit is electrically connected to the selection circuit for controlling the corresponding oxide TFT in the pixel circuit to turn on and controlling the oxide TFT in the driving circuit to turn on.

11. The drive selection circuit according to claim 10, characterized in that, The reset circuit includes a first reset transistor and a second reset transistor; The gate of the first reset transistor is used to receive a first reset signal; during reset, the first reset signal is the low level; the first pole of the first reset transistor is connected to the selection circuit, and the second pole of the first reset transistor is connected to a positive voltage source; The gate of the second reset transistor is used to receive a second reset signal; during reset, the second reset signal is the low level; the first pole of the second reset transistor is connected to the selection circuit, and the second pole of the second reset transistor is connected to a negative voltage source.

12. A display screen, characterized in that, The display screen includes a pixel circuit, a display driving integrated circuit, a GOA circuit, and the driving selection circuit according to any one of claims 1 to 11. The pixel circuit includes an oxide TFT; the driving selection circuit is configured to output a corresponding scanning signal according to a row driving signal from the GOA circuit and a control signal from the display driving integrated circuit, and the scanning signal is used to control the corresponding oxide TFT in the pixel circuit to turn on or off.

13. An electronic device, characterized in that, The electronic device includes the display screen according to claim 12.

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