Memory device with non-uniform refresh

Abstract

Embodiments of the present disclosure relate to a memory device with non-uniform refresh, including an IC memory controller for controlling an integrated circuit (IC) memory device including a memory cell array configured into a plurality of banks, each bank including a plurality of segments, an IC memory controller for an IC memory device having a plurality of segments, each segment of the plurality of segments being accessible via a bank address and a segment address, the IC memory controller comprising: command generation circuitry to generate a segment-by-segment value representing a segment-by-segment refresh rate for self-refresh logic in the IC memory device; and an interface circuit for transmitting the segment-by-segment value representing the segment-by-segment refresh rate to an IC memory device, the IC memory device being disposed outside the IC memory controller.

Description

[0001] Cross - reference to related applications

[0002] This application is a divisional application of a patent application for an invention titled "Memory Device with Non-Uniform Refresh", with international application number PCT / US2019 / 039050, international filing date of June 25, 2019, date of entry into the Chinese national phase of August 25, 2020, and Chinese national application number 201980015322.4. Technical Field

[0003] The disclosure herein relates to memory systems, and more particularly to memory devices, controllers, and methods for changing a refresh rate based on a per-segment basis. Brief Description of the Drawings

[0004] Embodiments of the present disclosure are illustrated by way of example and not limitation in the figures of the accompanying drawings, and in the drawings, where like reference numerals refer to like elements, and in the drawings:

[0005] Figure 1 An embodiment of a memory system employing non-uniform refresh is shown.

[0006] Figure 2 Shows during Figure 1 An example flowchart of operations performed during the operation of the memory system.

[0007] Figure 3 Shows for Figure 1 A code / decoding table of an embodiment of mode refresh bit encoding / decoding for the memory system. Detailed Description

[0008] Embodiments of memory devices, controllers, associated methods, and integrated circuits are disclosed herein. An embodiment of a memory device includes an array of memory cells configured as a plurality of banks. Each bank includes a plurality of segments. A register storage stores per-segment values representing a per-segment refresh rate. A refresh logic refreshes each segment according to the corresponding per-segment value. Substantial power savings attributable to refresh operations can be achieved by non-uniformly changing the per-segment refresh rate based on an acceptable error rate associated with the data stored in each segment.

[0009] The specific embodiments described herein provide an apparatus and method for changing a refresh rate based on a per-segment basis and according to a pre-specified error criterion associated with the data stored in each segment. The refresh rate can thus be increased or decreased in a manner that tightens or relaxes the read data errors attributable to the refresh operation to correspondingly refresh the memory cells.

[0010] ReferenceFigure 1 , shows a memory system generally designated as 100, which includes a memory controller 102 coupled to a memory device 104 via a bus 106. For one embodiment, the memory controller is a DRAM controller, where the memory device is implemented as a dynamic random access (DRAM) memory device. In some embodiments, the memory controller and the memory device may be embodied as integrated circuits or chips. Other embodiments may use the memory controller as circuitry in a general-purpose processor. Specific embodiments of the DRAM memory controller and the memory device may conform to various DRAM standards, including double data rate (DDR) variants, low power (LPDDR) versions, and graphics (GDDR) types. Other embodiments may include, for example, multi-chip modules employing stacked memory dies or stacked packages. Such embodiments may be used with memory modules. Additional embodiments may stack memory dies and logic dies together in a common package, or in separate packages stacked on top of each other.

[0011] Further reference Figure 1 , the memory controller 102 includes a controller interface 107 for transferring data, commands, and control signals between the memory controller and the memory device 104. Command generation circuitry 109 generates read / write and mode register write (MRW) commands for transmission to the memory device. For one embodiment, as described below, the command generation circuitry 109 generates an MRW command for storing a value associated with a per-segment refresh rate into a mode register on the memory device. The physical memory allocator 112 determines the bank and segment addresses of the physical memory corresponding to the memory requested by the host / processor 114. The memory controller may also include auto-refresh logic 116 to generate refresh commands externally applied to the DRAM memory device during an auto-refresh operation. Auto-refresh occurs when the memory system is active to support an electronic device in an active operation.

[0012] Continuing reference Figure 1 , the host / processor 114 may take the form of a general-purpose processor responsive to instructions generated by an operating system (OS) 118. The OS in turn allocates logical memory in response to memory requested by a given application 120, and for one embodiment, generates a tag for the allocated memory, as described more fully below.

[0013] Further reference Figure 1, the memory device 104 includes an array of volatile memory cells, which in one embodiment are organized into banks 122 and 124. Each bank is in turn organized as a plurality of addressable segments 126. In one embodiment, each memory device includes eight banks, where each bank has eight segments. The memory device may include any memory integrated circuit (IC) chip having volatile memory cells that maintain a given charge state through periodic refresh operations.

[0014] Continuing to refer Figure 1 , to perform a refresh operation on a per-segment basis, one embodiment of the memory device integrates refresh logic 128. The refresh logic 128 controls internal DRAM operations for self-refresh, auto-refresh, or both. In one embodiment, the refresh logic 128 includes a refresh counter that keeps track of the next address to be refreshed. The mode register circuit 130 provides register storage for per-segment refresh rate values based on an acceptable data error threshold or BER generated by the application 120 and the OS 118. When performing a per-segment non-uniform self-refresh operation, the refresh logic 128 accesses the register value.

[0015] Further referring Figure 1 , the memory device 104 includes a memory interface 131 that receives data, commands, and control signals from the memory controller 102. As described above, for one embodiment, the controller interface 107 on the memory controller uses an accompanying mode register write (MRW) command to transfer per-segment refresh rate values for a given segment to the memory interface 131. In response to the MRW command, the per-segment refresh rate values are loaded and stored in the mode register circuit 130.

[0016] For some embodiments, the memory device 104 may employ a temperature detection circuit 132 such as a temperature sensor to operate in accordance with temperature-compensated self-refresh (TCSR) techniques to assist in the per-segment non-uniform self-refresh operation described herein. Other embodiments may employ a temperature detection circuit on the memory controller 102. For one embodiment, a global refresh rate for the memory device segments may be established via the TCSR method, where the per-segment non-uniform refresh rate multiplier is stored in the mode register circuit 130 as a per-segment refresh rate value selectively applied to the global refresh rate for finer refresh rate control.

[0017] In operation, in both the self-refresh and auto-refresh cases, the "per-segment non-uniform refresh" operation is performed by Figure 1Memory system management, although most of the discussion herein focuses on embodiments that change the refresh rate on a per-segment basis during self-refresh operations. Generally, auto-refresh occurs during the active operation of an electronic device, while self-refresh occurs when the electronic device is in a "sleep" or inactive mode to reduce power consumption. DRAM, which is independent of the memory controller itself, uses, for example, a ring oscillator and a counter to generate row addresses on the chip to time the self-refresh. The controller triggers auto-refresh on a per-command basis, where each auto-refresh command will indicate to the DRAM to refresh one or more rows.

[0018] Utilize Figure 1 An electronic device with a memory system typically runs one or more applications for a user. Before actual operation, a pre-configuration process will be executed to initialize and optimize the memory system settings of the application. A given application may need to load different types of data into the memory device 104, such as program code and / or bulk data utilized by the application. In some cases, it may be desirable to have a very low error threshold associated with the program code data, such as the bit error rate (BER), to ensure proper program execution. On the other hand, in some cases, bulk data such as image or audio data can be managed at a higher error rate while still enabling acceptable use of the application.

[0019] Now refer to Figure 2 , in one embodiment, to manage the classification of different types of data using different acceptable BER parameters, at 202, the OS 118 and the application 120 cooperate to classify the requested memory according to the acceptable data error threshold, such as BER, during memory allocation, and at 204, mark the requested memory according to the classification. At 206, the memory controller 102 receives allocation information from the host / processor 114 and generates a physical memory allocation according to the bank and segment addresses. At 208, the memory controller also writes the mode register bit information for non-uniform refresh operations into the memory device mode register. At 210, the memory controller also issues auto-refresh commands during operation. In one embodiment, the rate at which the memory controller issues auto-refresh is the same as the rate used when non-uniform refresh (NUR) is not used. In another embodiment, when NUR is used, the memory controller uses a different rate for issuing auto-refresh commands.

[0020] Figure 3Shows an exemplary mode register decoder diagram for participating in mode register bits in a per-segment refresh operation. The diagram is organized into rows representing eight segments (labeled S0 - S7) and columns representing eight banks (labeled B0 - B7). Each bank and segment includes a set of mode bits to indicate refresh parameter values, such as an absolute refresh rate, or a modifier value for modifying the global refresh rate. For one embodiment, the bank / segment bits are set according to the following code:

[0021] 00: Refresh the bank or segment at the nominal value (e.g., 64 ms).

[0022] 01: Refresh the bank or segment 2 times longer than the nominal value (128 milliseconds).

[0023] 10: Refresh the bank or segment 4 times longer than the nominal value (256 milliseconds).

[0024] 11: Refresh the bank or segment 8 times longer than the nominal value (ls).

[0025] In the case where both the bank and segment bits show a code specifying a refresh rate other than the nominal rate, the bank code overrides the segment code. Although a two-bit encoding is shown and described herein for a particular embodiment, additional bits can be provided to provide even finer granularity. For example, the additional bits can specify additional refresh rates / modifiers and / or specify individual segments.

[0026] Further reference Figure 3 , as an example, the first part of the diagram shows at 302 the segment code "11" for the fifth segment S4. At 304, the nominal code "00" for bank B0 specifies a 64 ms refresh rate for segments S0 - S3 and S5 - S7 of bank B0, while the refresh rate for segment S4 is specified at 306 as ls. The code 01 for bank B1 overrides the code 11 for segment S4 and thus specifies a 128 ms refresh rate for all eight segments of bank B1 (shown at 210). Although Figure 3 shows a decoder chart that specifies absolute settings relative to a nominal value, the codes can alternatively represent per-segment multiplier factors to be applied to a global refresh setting, such as a setting associated with a temperature-compensated self-refresh scheme (TCSR).

[0027] Typically, when a memory device operates under self-refresh conditions, the TCSR provides a way to reduce power consumption. The temperature detection circuit 132 detects the ambient temperature of the memory device, and the global refresh rate change is performed in response to the detected temperature. The increase / decrease in the refresh rate generally compensates for the increase / decrease in the leakage rate in volatile memory cells at different temperatures. In such an embodiment, the temperature detection circuit 132 detects the operating temperature of the memory device 104, generates corresponding temperature information, and provides the temperature information to the refresh logic 128. Then, the refresh logic can apply appropriate global refresh rate settings (stored in the mode register circuit 130) based on the temperature, and apply a per-segment multiplier to the non-uniform refresh rate among the respective segments based on the non-uniform bits stored in the mode register circuit.

[0028] In one embodiment, the memory controller issues auto-refresh commands at the same rate as when not using NUR. When the refresh counter points to a row in a segment with a longer refresh time assigned by the NUR bit in the mode register, the refresh logic on the DRAM will regularly skip the execution of the refresh. For example, when the assigned refresh rate of a segment is 128 ms and the memory controller issues an auto-refresh command every 64 ms, the refresh logic will skip every second refresh of that segment.

[0029] At the memory controller, the auto-refresh controller can employ an alternative form of per-segment refreshing for auto-refresh operations. As described above, auto-refresh typically occurs during the active operation of an electronic device. Having knowledge of the acceptable bit error rates for different allocated memory regions, a variable per-segment refresh rate can be executed by the auto-refresh controller on the memory controller by, for example, skipping appropriate segments when an external global refresh command is issued.

[0030] The memory systems, devices, and methods described above provide a more fine-grained per-segment non-uniform refresh, which allows for more efficient power savings achievable by the memory system. The embodiments described herein are well-suited for mobile device applications where power efficiency is a key concern.

[0031] When such data and / or instruction-based representations of the above circuits are received within a computer system via one or more computer-readable media, they can be processed by a processing entity (e.g., one or more processors) within the computer system in conjunction with the execution of one or more other computer programs to generate a representation or image of the physical manifestation of such circuits. The one or more other computer programs include, but are not limited to, netlist generation programs, layout and routing programs, etc. This representation or image can then be used, for example, in device manufacturing by enabling the generation of one or more masks for forming the various components of the circuit during the device manufacturing process.

[0032] In the foregoing description and in the drawings, specific terms and drawing symbols have been set forth to provide a thorough understanding of the present invention. In some instances, the terms and symbols may imply specific details that are not required to practice the present invention. For example, any one of a specific number of bits, signal path widths, signaling or operating frequencies, component circuits or devices, etc., may be different from those described above in alternative embodiments. Also, the interconnection between circuit elements or circuit blocks shown or described as a multi-conductor signal link may alternatively be a single-conductor signal link, and a single-conductor signal link may alternatively be a multi-conductor signal link. Signal and signaling paths shown or described as single-ended may also be differential, and vice versa. Similarly, in alternative embodiments, a signal described or depicted as having a high logic level active or a low logic level active may have the opposite logic level. The component circuits within an integrated circuit device may be implemented using metal oxide semiconductor (MOS) technology, bipolar technology, or any other technology capable of implementing logic and analog circuits. Regarding terms, when a signal is driven to a low or high logic state (or charged to a high logic state or discharged to a low logic state) to indicate a specific condition, the signal is said to be "asserted". Conversely, a signal is "de-asserted" to indicate that the signal is driven (or charged or discharged) to a state other than the asserted state (including a high or low logic state, or a floating state that may occur when the signal driving circuit transitions to a high impedance state, such as an open-drain or open-collector state). When a signal driving circuit asserts (or de-asserts, if explicitly stated or indicated by context) a signal on a signal line coupled between the signal driving circuit and a signal receiving circuit, the signal driving circuit is said to "output" the signal to the signal receiving circuit. When a signal is asserted on a signal line, the signal line is said to be "activated", and when the signal is de-asserted, the signal line is said to be "de-activated". Additionally, a prefix symbol " / " appended to a signal name indicates that the signal is an active-low signal (i.e., the asserted state is a logic low state). A bar over a signal name (e.g., ) is also used to indicate an active-low signal. The term "coupled" as used herein means a direct connection as well as a connection through one or more intermediate circuits or structures. "Programming" an integrated circuit device may include, for example but not limited to, loading control values into registers or other storage circuits within the device in response to host instructions to control aspects of the operation of the device, establishing a device configuration, or controlling aspects of the operation of the device through a one-time programming operation (e.g., blowing a fuse within a configuration circuit during device production), and / or connecting one or more selected pins or other contact structures of the device to a reference voltage line (also referred to as tying) to establish a particular device configuration or aspect of operation of the device. The term "exemplary" is used to denote an example, rather than a preference or requirement.

Claims

1. An IC memory controller for controlling an IC memory device, the IC memory device including a memory cell array configured as a plurality of banks, each bank including a plurality of segments, each of the plurality of segments being accessible via a bank address and a segment address, the IC memory controller including: command generation circuitry for generating a per-segment value representing a per-segment refresh rate for self-refresh logic in the IC memory device; and interface circuitry for transmitting the per-segment value representing the per-segment refresh rate to the IC memory device, the IC memory device being disposed external to the IC memory controller.

2. The IC memory controller according to claim 1, implemented as an IC dynamic random access memory DRAM memory controller.

3. The IC memory controller according to claim 1, wherein: the command generation circuitry is for generating a mode register write MRW command associated with each per-segment value for a given segment among the plurality of segments.

4. The IC memory controller according to claim 1, wherein the per-segment refresh rate represents a refresh rate relative to a nominal refresh rate.

5. The IC memory controller according to claim 1, further including: temperature-compensated refresh circuitry for cooperating with refresh logic in the IC memory device to refresh each segment based on temperature.

6. The IC memory controller according to claim 5, wherein the per-segment refresh rate represents a multiplication value applied to a global-temperature-based refresh rate determined by the temperature-compensated refresh circuitry.

7. The IC memory controller according to claim 1, further including: auto-refresh logic for generating refresh commands to selectively refresh each segment according to corresponding per-segment values during an auto-refresh operation mode.

8. A method of operation in an IC memory controller for controlling an IC memory device, the IC memory device including a memory cell array configured as a plurality of banks, each bank including a plurality of segments, each of the plurality of segments being accessible via a bank address and a segment address, the method including: using command generation circuitry to generate a per-segment value representing a per-segment refresh rate for self-refresh logic in the IC memory device; and using interface circuitry to transmit the per-segment value representing the per-segment refresh rate to the IC memory device, the IC memory device being disposed external to the IC memory controller.

9. The method according to claim 8, wherein: the transmission conforms to a dynamic random access memory DRAM protocol.

10. The method according to claim 8, wherein: using the command generation circuitry to generate including generating a mode register write MRW command associated with each per-segment value for a given segment among the plurality of segments.

11. The method according to claim 8, wherein the per-segment refresh rate represents a refresh rate relative to a nominal rate.

12. The method according to claim 8, further including: A refresh circuit using temperature compensation generates a temperature-based refresh rate to cooperate with the per-segment values to refresh each segment based on temperature.

13. The method according to claim 12, wherein the per-segment refresh rate represents a multiplication value applied to the temperature-based refresh rate generated by the temperature-compensated refresh circuit.

14. The method according to claim 13, further comprising: Using an auto-refresh logic to generate a refresh command during an auto-refresh operation mode according to corresponding per-segment values to selectively refresh each segment.

15. An integrated circuit (IC) chip, comprising: A dynamic random access memory (DRAM) control circuit for controlling an IC DRAM memory device, the IC DRAM memory device including a DRAM memory cell array configured as a plurality of banks, each bank including a plurality of segments, each segment in the plurality of segments being accessible via a bank address and a segment address, the DRAM control circuit including: A command generator for generating a per-segment value representing a per-segment refresh rate for an auto-refresh logic in the IC DRAM memory device; and An input / output (I / O) circuit for transmitting the per-segment value representing the per-segment refresh rate to the IC DRAM memory device, the IC DRAM memory device being disposed outside the IC chip.

16. The IC chip according to claim 15, wherein: The per-segment values can be freely different from each other.

17. The IC chip according to claim 15, wherein each per-segment refresh rate in the per-segment refresh rates represents an absolute refresh rate.

18. The IC chip according to claim 15, further comprising: A temperature-compensated refresh circuit for cooperating with the IC DRAM memory device to refresh each segment based on temperature; And wherein each per-segment refresh rate in the per-segment refresh rates represents a multiplication value applied to a globally temperature-based refresh rate determined by the temperature-compensated refresh circuit.

19. The IC chip according to claim 15, wherein: The command generator is used to generate a mode register write (MRW) command associated with each per-segment value for a given segment in the plurality of segments.

20. The IC chip according to claim 15, further comprising: An auto-refresh logic for generating a refresh command during an auto-refresh operation mode according to corresponding per-segment values to selectively refresh each segment.

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