Memory device and operating method thereof

Abstract

A memory device includes a memory circuit, a redistribution layer, and a resistor circuit. The redistribution layer is coupled to the memory circuit. The resistor circuit is coupled to the memory circuit. The resistor circuit includes a first resistor group and a second resistor group. The first resistor group includes a first resistor and a second resistor. The second resistor group comprises a third resistor and a fourth resistor. After the first resistor and the second resistor are coupled in parallel according to the impedance value of the redistribution layer and the third resistor and the fourth resistor are coupled in parallel according to the impedance value of the redistribution layer, the first resistor group and the second resistor group are coupled in parallel according to the impedance value of the memory circuit. In this way, the signal integrity (SI) of the signal written to the memory device is not affected. In addition, the invention also discloses a method for operating the memory device.

Description

Technical Field

[0001] The present disclosure relates to a memory technology, and more particularly to a memory device and a method of operating a memory device. Background Art

[0002] In order to enable an integrated circuit (IC) to be applied to different component modules, a redistribution layer (RDL) is coupled to / formed in the IC to change the contact positions of the IC, so that the contact positions match different component modules. However, the additional lines of the RDL increase the impedance of the IC (such as a dynamic random access memory (DRAM)), thereby affecting the signal integrity (SI) of the signals written to the DRAM. Therefore, how to design to solve the above problems is an important issue in the art. Summary of the Invention

[0003] Embodiments of the present invention include a memory device. The memory device includes a memory circuit, a redistribution layer, and a resistor circuit. The redistribution layer is coupled to the memory circuit. The resistor circuit is coupled to the memory circuit. The resistor circuit includes a first resistor group and a second resistor group. The first resistor group includes a first resistor and a second resistor. The second resistor group includes a third resistor and a fourth resistor. After the first resistor and the second resistor are coupled in parallel according to the impedance value of the redistribution layer and the third resistor and the fourth resistor are coupled in parallel according to the impedance value of the redistribution layer, the first resistor group and the second resistor group are coupled in parallel according to the impedance value of the memory circuit.

[0004] In some embodiments, the resistor circuit further includes a third resistor group, the third resistor group includes a fifth resistor and a sixth resistor, the fifth resistor and the sixth resistor are coupled in parallel according to the impedance value of the redistribution layer, and the first resistor group, the second resistor group, and the third resistor group are coupled in parallel according to the impedance value of the memory circuit.

[0005] In some embodiments, the resistor circuit further includes a fourth resistor group, the fourth resistor group includes a seventh resistor and an eighth resistor, the seventh resistor and the eighth resistor are coupled in parallel according to the impedance value of the redistribution layer, and the first resistor group, the second resistor group, the third resistor group, and the fourth resistor group are coupled in parallel according to the impedance value of the memory circuit.

[0006] In some embodiments, the resistor circuit further includes a fifth resistor group, the fifth resistor group includes a ninth resistor and a tenth resistor, the ninth resistor and the tenth resistor are coupled in parallel according to the impedance value of the redistribution layer, and the first resistor group, the second resistor group, the third resistor group, the fourth resistor group, and the fifth resistor group are coupled in parallel according to the impedance value of the memory circuit.

[0007] In some embodiments, the resistor circuit further includes a sixth resistor group, the sixth resistor group includes an eleventh resistor and a twelfth resistor, the eleventh resistor and the twelfth resistor are coupled in parallel according to the impedance value of the redistribution layer, and the first resistor group, the second resistor group, the third resistor group, the fourth resistor group, the fifth resistor group, and the sixth resistor group are coupled in parallel according to the impedance value of the memory circuit.

[0008] In some embodiments, the resistor circuit further includes a seventh resistor group, the seventh resistor group includes a thirteenth resistor and a fourteenth resistor, the thirteenth resistor and the fourteenth resistor are coupled in parallel according to the impedance value of the redistribution layer, and the first resistor group, the second resistor group, the third resistor group, the fourth resistor group, the fifth resistor group, the sixth resistor group, and the seventh resistor group are coupled in parallel according to the impedance value of the memory circuit.

[0009] In some embodiments, the first resistor group further includes a fifth resistor, the second resistor group further includes a sixth resistor, and the first resistor, the second resistor, and the fifth resistor are coupled in parallel according to the impedance value of the redistribution layer and the third resistor, the fourth resistor, and the sixth resistor are coupled in parallel according to the impedance value of the redistribution layer.

[0010] An embodiment of the present invention includes a memory device. The memory device includes a memory circuit, a redistribution layer, and a resistor circuit. The redistribution layer is coupled to the memory circuit. The resistor circuit is coupled to the memory circuit. The resistor circuit includes a first resistor group and a second resistor group. The first resistor group includes a first resistor, a second resistor, and a first fuse. The first fuse is coupled to the second resistor. The second resistor group includes a third resistor, a fourth resistor, and a second fuse. The second fuse is coupled to the fourth resistor. After the first resistor and the second resistor are coupled in parallel through the first fuse according to the impedance value of the redistribution layer and the third resistor and the fourth resistor are coupled in parallel through the second fuse according to the impedance value of the redistribution layer, the first resistor group and the second resistor group are coupled in parallel according to the impedance value of the memory circuit.

[0011] In some embodiments, the resistor circuit further includes a third resistor group, the third resistor group includes a fifth resistor, a sixth resistor, and a third fuse, the third fuse is coupled to the sixth resistor, the fifth resistor and the sixth resistor are coupled in parallel via the third fuse according to the impedance value of the redistribution layer, and the first resistor group, the second resistor group, and the third resistor group are coupled in parallel according to the impedance value of the memory circuit.

[0012] In some embodiments, the resistor circuit further includes a fourth resistor group, the fourth resistor group includes a seventh resistor, an eighth resistor, and a fourth fuse, the fourth fuse is coupled to the eighth resistor, the seventh resistor and the eighth resistor are coupled in parallel via the fourth fuse according to the impedance value of the redistribution layer, and the first resistor group, the second resistor group, the third resistor group, and the fourth resistor group are coupled in parallel according to the impedance value of the memory circuit.

[0013] In some embodiments, the resistor circuit further includes a fifth resistor group, the fifth resistor group includes a ninth resistor, a tenth resistor, and a fifth fuse, the fifth fuse is coupled to the tenth resistor, the ninth resistor and the tenth resistor are coupled in parallel via the fifth fuse according to the impedance value of the redistribution layer, and the first resistor group, the second resistor group, the third resistor group, the fourth resistor group, and the fifth resistor group are coupled in parallel according to the impedance value of the memory circuit.

[0014] In some embodiments, the resistor circuit further includes a sixth resistor group, the sixth resistor group includes an eleventh resistor, a twelfth resistor, and a sixth fuse, the sixth fuse is coupled to the twelfth resistor, the eleventh resistor and the twelfth resistor are coupled in parallel via the sixth fuse according to the impedance value of the redistribution layer, and the first resistor group, the second resistor group, the third resistor group, the fourth resistor group, the fifth resistor group, and the sixth resistor group are coupled in parallel according to the impedance value of the memory circuit.

[0015] In some embodiments, the resistor circuit further includes a seventh resistor group, the seventh resistor group includes a thirteenth resistor, a fourteenth resistor, and a seventh fuse, the seventh fuse is coupled to the fourteenth resistor, the thirteenth resistor and the fourteenth resistor are coupled in parallel via the seventh fuse according to the impedance value of the redistribution layer, and the first resistor group, the second resistor group, the third resistor group, the fourth resistor group, the fifth resistor group, the sixth resistor group, and the seventh resistor group are coupled in parallel according to the impedance value of the memory circuit.

[0016] In some embodiments, the first resistor group further includes a fifth resistor and a third fuse, the third fuse is coupled to the fifth resistor, the second resistor group further includes a sixth resistor and a fourth fuse, the fourth fuse is coupled to the sixth resistor, and the first resistor, the second resistor, and the fifth resistor are coupled in parallel through the first fuse and the third fuse according to the impedance value of the redistribution layer, and the third resistor, the fourth resistor, and the sixth resistor are coupled in parallel through the second fuse and the fourth fuse according to the impedance value of the redistribution layer.

[0017] Embodiments of the present invention include a method of operating a memory device. The method includes: coupling a resistor circuit to a memory circuit; coupling a redistribution layer to the memory circuit; coupling the first resistor and the second resistor in parallel according to the impedance value of the redistribution layer; coupling the third resistor and the fourth resistor in parallel according to the impedance value of the redistribution layer; and after the first resistor and the second resistor are coupled in parallel and the third resistor and the fourth resistor are coupled in parallel, coupling the first resistor group and the second resistor group in parallel according to the impedance value of the memory circuit.

[0018] In some embodiments, the resistor circuit includes a first resistor group and a second resistor group, the first resistor group includes a first resistor and a second resistor, and the second resistor group includes a third resistor and a fourth resistor.

[0019] In some embodiments, the method further includes: coupling the fifth resistor and the sixth resistor in parallel according to the impedance value of the redistribution layer; and after the first resistor and the second resistor are coupled in parallel, the third resistor and the fourth resistor are coupled in parallel, and the fifth resistor and the sixth resistor are coupled in parallel, coupling the third resistor group, the first resistor group, and the second resistor group in parallel according to the impedance value of the memory circuit.

[0020] In some embodiments, the resistor circuit further includes a third resistor group, and the third resistor group includes a fifth resistor and a sixth resistor.

[0021] In some embodiments, the method further includes: coupling the fifth resistor, the first resistor, and the second resistor in parallel according to the impedance value of the redistribution layer; coupling the sixth resistor, the third resistor, and the fourth resistor in parallel according to the impedance value of the redistribution layer; and after the fifth resistor, the first resistor, and the second resistor are coupled in parallel and the sixth resistor, the third resistor, and the fourth resistor are coupled in parallel, coupling the first resistor group and the second resistor group in parallel according to the impedance value of the memory circuit, where the first resistor group further includes the fifth resistor, and the second resistor group further includes the sixth resistor.

[0022] In some embodiments, the method further includes: coupling a first fuse to a second resistor; and coupling a second fuse to a fourth resistor, wherein the first resistor and the second resistor are coupled in parallel through the first fuse, and the third resistor and the fourth resistor are coupled in parallel through the second fuse. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. It should be understood that the various features are not drawn to scale in accordance with standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity.

[0024] Figure 1 is a schematic diagram of a memory device according to some embodiments of the present case.

[0025] Figure 2 is a schematic diagram of a resistor circuit according to some embodiments of the present case.

[0026] Figure 3 is a schematic diagram of a resistor circuit according to some embodiments of the present case.

[0027] Figure 4 is a schematic diagram of a resistor circuit according to some embodiments of the present case.

[0028] Figure 5 is according to some embodiments of the present case for operating Figure 1 of a memory device.

[0029] Figure 6 is according to some embodiments of the present case for operating Figure 1 of a memory device. DETAILED DESCRIPTION

[0030] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components, materials, values, steps, or arrangements, etc. are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. Other components, materials, values, steps, or arrangements, etc. may also be considered. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features are formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. Additionally, the present disclosure may repeat reference numerals and / or words in various examples. This repetition is for simplicity and clarity purposes and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0031] In addition, the space-related terms used herein, such as "beneath", "under", "below", "above", "on", etc., are for ease of description to describe the relationship of one element or feature to another (other) element or feature as shown in the figures. These space-related terms are intended to include different orientations of the device during use or operation in addition to the orientation shown in the figures. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the space-related descriptors used herein should be interpreted accordingly in a similar manner.

[0032] As used herein, when an element is referred to as "connected" or "coupled", it may mean "electrically connected" or "electrically coupled". "Connected" or "coupled" can also be used to indicate that two or more elements cooperate or interact with each other. In addition, although terms such as "first", "second",... are used herein to describe different elements, these terms are only used to distinguish elements or operations described by the same technical term. Unless the context clearly indicates otherwise, these terms do not particularly refer to or imply an order or sequence, nor are they used to limit this case.

[0033] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this case belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and this case, and will not be interpreted in an idealized or overly formal sense unless clearly defined herein.

[0034] The terms used herein are for the purpose of describing particular embodiments only and are not limiting. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include the plural forms, including "at least one". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items. It should also be understood that when used in this specification, the terms "comprises" and / or "comprising" specify the presence and / or components of the stated features, regions, wholes, steps, operations, elements, but do not preclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components and / or combinations thereof.

[0035] The following will disclose multiple embodiments of this case with the accompanying drawings. For the sake of clarity, many practical details will be described together in the following narrative. However, it should be understood that these practical details are not used to limit this case. That is to say, in some embodiments of this disclosure, these practical details are not necessary. In addition, for the purpose of simplifying the drawings, some existing conventional structures and elements will be shown in a simple schematic manner in the drawings.

[0036] Figure 1 is a schematic diagram of a memory device 100 illustrated according to some embodiments of the present case. As Figure 1 shown, the memory device 100 includes a memory circuit 110, a resistor circuit 120, and a redistribution layer 130. The memory circuit 110 is coupled to the resistor circuit 120 and the redistribution layer 130.

[0037] In some embodiments, the memory device 100 has an impedance RM (not shown) with an impedance value ZM. The resistor circuit 120 has an impedance RR (not shown) with an impedance value ZR. The redistribution layer has an impedance RL (not shown) with an impedance value ZL. In some embodiments, the impedance value ZM is approximately equal to the sum of the impedance value ZL and the impedance value ZR. In some embodiments, in the memory device 100 without the redistribution layer 130, the impedance value ZM is approximately equal to the impedance value ZR. In some embodiments, the impedance value ZR corresponds to the impedance value of the memory circuit 110.

[0038] In some embodiments, the memory circuit 110 is implemented as a dynamic random access memory (DRAM) or a die. In some embodiments, the resistor circuit 120 is used to adjust the impedance of the input / output (I / O) of the memory circuit 110 according to various operations of the memory circuit 110 and the impedance value ZM of the memory device 100. In some embodiments, the redistribution layer 130 is used to change the I / O contact positions of the memory circuit 110.

[0039] Figure 2 is a schematic diagram of a resistor circuit 200 illustrated according to some embodiments of the present case. As Figure 2 shown, the resistor circuit 200 includes resistor banks RS1 and RS2.

[0040] As Figure 2 shown, the resistor bank RS1 includes a fuse F11, resistors R11 and R12. The resistor bank RS2 includes a fuse F21, resistors R21 and R22. One end of the resistor R11 is coupled to the node N11, and the other end is coupled to the node N12. One end of the resistor R12 is coupled to the node N13, and the other end is coupled to the node N12. One end of the fuse F11 is coupled to the node N13. One end of the resistor R21 is coupled to the node N21, and the other end is coupled to the node N22. One end of the resistor R22 is coupled to the node N23, and the other end is coupled to the node N22. One end of the fuse F21 is coupled to the node N23.

[0041] In some embodiments, resistor banks RS1 and RS2 are coupled in parallel by coupling nodes N11 and N21 and coupling nodes N12 and N22. Resistors R11 and R12 are coupled in parallel by coupling node N11 and the other end of fuse F11. Resistors R21 and R22 are coupled in parallel by coupling node N21 and the other end of fuse F21.

[0042] Please refer to Figure 1 and Figure 2 , resistor circuit 200 is an embodiment of resistor circuit 120. Resistor circuit 200 is coupled to memory circuit 110 through node N11. In some embodiments, resistor bank RS1 is used to receive a power supply voltage VDDQ (not shown) through node N12. In some embodiments, resistor banks RS1 and RS2 are coupled in parallel according to various operations of memory circuit 110. In some embodiments, resistors R11 and R12 are coupled in parallel and resistors R21 and R22 are coupled in parallel according to the impedance value ZL of impedance RL in rewiring layer 130.

[0043] In some embodiments, resistor circuit 200 includes different numbers of resistor banks, each of which has a configuration similar to that as Figure 2 shown. For example, resistor circuit 200 includes resistor banks RS1 to RSn, where n is an integer greater than 1. In some embodiments, in a DRAM configuration, n is 7.

[0044] In some embodiments, each of resistor banks RS1 to RSn includes different numbers of resistors and fuses, where the resistors and fuses have a configuration similar to that as Figure 2 shown. For example, the number of resistors in each of resistor banks RS1 to RSn is m, where m is an integer greater than 1. Correspondingly, the number of fuses in each of resistor banks RS1 to RSn is m - 1.

[0045] Figure 3 is a schematic diagram of resistor circuit 300 illustrated according to some embodiments of the present case. Compared with Figure 2 the resistor circuit 200 in Figure 3 the resistor circuit 300 in

[0046] As Figure 3As shown, resistor bank RS3 includes fuse F31, resistors R31 and R32. Resistor bank RS4 includes fuse F41, resistors R41 and R42. Resistor bank RS5 includes fuse F51, resistors R51 and R52. Resistor bank RS6 includes fuse F61, resistors R61 and R62. Resistor bank RS7 includes fuse F71, resistors R71 and R72. One end of resistor R31 is coupled to node N31 and the other end is coupled to node N32. One end of resistor R32 is coupled to node N33 and the other end is coupled to node N32. One end of fuse F31 is coupled to node N33. One end of resistor R41 is coupled to node N41 and the other end is coupled to node N42. One end of resistor R42 is coupled to node N43 and the other end is coupled to node N42. One end of fuse F41 is coupled to node N43. One end of resistor R51 is coupled to node N51 and the other end is coupled to node N52. One end of resistor R52 is coupled to node N53 and the other end is coupled to node N52. One end of fuse F51 is coupled to node N53. One end of resistor R61 is coupled to node N61 and the other end is coupled to node N62. One end of resistor R62 is coupled to node N63 and the other end is coupled to node N62. One end of fuse F61 is coupled to node N63. One end of resistor R71 is coupled to node N71 and the other end is coupled to node N72. One end of resistor R72 is coupled to node N73 and the other end is coupled to node N72. One end of fuse F71 is coupled to node N73.

[0047] In some embodiments, resistor banks RS1 and RS3 are coupled in parallel by coupling node N11 to N31 and coupling node N12 to N32. Resistor banks RS1 and RS4 are coupled in parallel by coupling node N11 to N41 and coupling node N12 to N42. Resistor banks RS1 and RS5 are coupled in parallel by coupling node N11 to N51 and coupling node N12 to N52. Resistor banks RS1 and RS6 are coupled in parallel by coupling node N11 to N61 and coupling node N12 to N62. Resistor banks RS1 and RS7 are coupled in parallel by coupling node N11 to N71 and coupling node N12 to N72.

[0048] In some embodiments, resistors R31 and R32 are coupled in parallel by coupling node N31 to the other end of fuse F31. Resistors R41 and R42 are coupled in parallel by coupling node N41 to the other end of fuse F41. Resistors R51 and R52 are coupled in parallel by coupling node N51 to the other end of fuse F51. Resistors R61 and R62 are coupled in parallel by coupling node N61 to the other end of fuse F61. Resistors R71 and R72 are coupled in parallel by coupling node N71 to the other end of fuse F71.

[0049] Please refer to Figures 1 to 3 , the resistor circuit 300 is an embodiment of the resistor circuit 200. In some embodiments, some or all of the resistor banks RS1 to RS7 are coupled in parallel according to various operations of the memory circuit 110. In some embodiments, some or all of the resistors R11 to R71 and R12 to R72 are respectively coupled in parallel according to the impedance value ZL of the impedance RL in the redistribution layer 130.

[0050] Figure 4 is a schematic diagram of the resistor circuit 400 illustrated according to some embodiments of the present case. Compared with Figure 2 the resistor circuit 200 in Figure 4 the resistor circuit 400 in

[0051] also includes the resistor R13 and the fuse F12 in the resistor bank RS1, and the resistor R23 and the fuse F22 in the resistor bank RS2. Figure 4 As shown in

[0052] one end of the resistor R13 is coupled to the node N14, and the other end is coupled to the node N12. One end of the fuse F12 is coupled to the node N14. One end of the resistor R23 is coupled to the node N24, and the other end is coupled to the node N22. One end of the fuse F22 is coupled to the node N24.

[0053] Please refer to Figure 1 , Figure 2 and Figure 4 , the resistor circuit 400 is an embodiment of the resistor circuit 200. In some embodiments, some or all of the resistors R11 to R13 and R21 to R23 are respectively coupled in parallel according to the impedance value ZL of the impedance RL in the redistribution layer 130.

[0054] In some embodiments, each of the resistors in the resistor circuit 120, such as each of the resistors R11 to R71, R12 to R72, R13, and R23, is referred to as an on-die terminal (ODT) resistor. In some embodiments, each of the resistors in the resistor circuit 120 is implemented as a variable resistor. In some embodiments, each of the resistors in the resistor circuit 120 has an impedance value RZQ. In some embodiments, the impedance value RZQ is approximately 240 ohms.

[0055] In some embodiments, each of the fuses in resistor circuit 120, such as each of fuses F11 to F71, F12, and F22, is reusable. In some embodiments, each of the fuses in resistor circuit 120 is implemented as a transistor. Examples of transistors include, but are not limited to, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, P-channel / N-channel field-effect transistors (PFETs / NFETs), fin field-effect transistors (FinFETs), planar metal-oxide-semiconductor transistors with raised source / drain, etc. In some embodiments, each of the fuses in resistor circuit 120 couples or decouples each of the nodes in resistor circuit 120, such as nodes N11 to N71, N13 to N73, N14, and N24, according to the voltage level applied to the fuses in resistor circuit 120. For example, in Figure 2 when a high voltage level, such as 2.5 volts, is applied, fuse F11 couples to node N11, and when a low voltage level, such as 0 volts, is applied, fuse F11 decouples node N11.

[0056] Figure 5 is a flowchart of method 500 for operating Figure 1 memory device 100 according to some embodiments of the present case. In Figure 5 method 500 includes operations 502, 504, and 506.

[0057] In operation 502, a ZQ calibration long (ZQCL) instruction is executed, and the impedance value RZQ of each of the resistors in resistor circuit 120, such as each of resistors R11 to R71, R12 to R72, R13, and R23 in Figures 2 to 4 is reset to an impedance value, such as 240 ohms. In some embodiments, the ZQCL instruction is used to calibrate the drive strength and termination value of the DRAM. In some embodiments, the ZQCL instruction is typically completed within 512 DRAM clock cycles. In some embodiments, within 1024 DRAM clock cycles after operation 502 is completed, memory circuit 110 pauses and does not allow other operations to be executed.

[0058] In operation 504, one or more resistors of each resistor bank in resistor circuit 120, such as resistors R11 and R12 in resistor bank RS1 in Figure 2 , resistors R21 and R22 in resistor bank RS2, Figure 3 resistors in resistor banks RS1 to RS7 in Figure 4The resistors in resistor groups RS1 to RS2 are coupled in parallel according to the impedance value ZL of the redistribution layer 130. In some embodiments, the impedance value ZR is approximately equal to or less than the difference between the impedance value RZQ and the impedance value ZL.

[0059] For example, when the impedance value ZL is RZQ / 2, the impedance value ZR is approximately equal to or less than RZQ / 2. Accordingly, resistor R11 and R12 are coupled in parallel, resistor R21 and R22 are coupled in parallel, resistor R31 and R32 are coupled in parallel, resistor R41 and R42 are coupled in parallel, resistor R51 and R52 are coupled in parallel, resistor R61 and R62 are coupled in parallel, and resistor R71 and R72 are coupled in parallel.

[0060] As another example, when the impedance value ZL is 2RZQ / 3, the impedance value ZR is approximately equal to or less than RZQ / 3. Accordingly, resistors R11 to R13 are coupled in parallel and resistors R21 to R23 are coupled in parallel.

[0061] In operation 506, the memory circuit 110 performs general operations, such as operations OP1 to OP7 (not shown). In some embodiments, operations OP1 to OP7 correspond to various operations performed in the memory circuit 110 and to different impedance values in the memory circuit 110, such as the impedance value ZR of the resistor circuit 120. Accordingly, the resistor circuit 120 adjusts the impedance value ZR by coupling one or more of resistor groups RS1 to RSn in parallel.

[0062] For example, when the memory circuit 110 performs operation OP1, the impedance value of the memory circuit 110 corresponds to the impedance value RZQ. Accordingly, the resistor circuit 120 adjusts the impedance value ZR by coupling the resistor bank RS1. When the memory circuit 110 performs operation OP2, the impedance value of the memory circuit 110 corresponds to the impedance value RZQ / 2. Accordingly, the resistor circuit 120 adjusts the impedance value ZR by coupling the resistor banks RS1 and RS2. When the memory circuit 110 performs operation OP3, the impedance value of the memory circuit 110 corresponds to the impedance value RZQ / 3. Accordingly, the resistor circuit 120 adjusts the impedance value ZR by coupling the resistor banks RS1 to RS3. When the memory circuit 110 performs operation OP4, the impedance value of the memory circuit 110 corresponds to the impedance value RZQ / 4. Accordingly, the resistor circuit 120 adjusts the impedance value ZR by coupling the resistor banks RS1 to RS4. When the memory circuit 110 performs operation OP5, the impedance value of the memory circuit 110 corresponds to the impedance value RZQ / 5. Accordingly, the resistor circuit 120 adjusts the impedance value ZR by coupling the resistor banks RS1 to RS5. When the memory circuit 110 performs operation OP6, the impedance value of the memory circuit 110 corresponds to the impedance value RZQ / 6. Accordingly, the resistor circuit 120 adjusts the impedance value ZR by coupling the resistor banks RS1 to RS6. When the memory circuit 110 performs operation OP7, the impedance value of the memory circuit 110 corresponds to the impedance value RZQ / 7. Accordingly, the resistor circuit 120 adjusts the impedance value ZR by coupling the resistor banks RS1 to RS7.

[0063] Figure 6 is a flowchart of a method 600 for operating a memory device 100 according to some embodiments of the present case. In Figure 1 it, the method 600 includes operations 602, 604, 606, 608, and 610. Figure 6 In operation 602, the resistor circuit 120 is coupled to the memory circuit 110.

[0064] In operation 604, the redistribution layer 130 is coupled to the memory circuit 110.

[0065] In operation 606, the resistors R11 and R12 are coupled in parallel according to the impedance value ZL of the redistribution layer 130.

[0066] In operation 608, the resistors R21 and R22 are coupled in parallel according to the impedance value ZL of the redistribution layer 130.

[0067] In operation 608, the resistors R21 and R22 are coupled in parallel according to the impedance value ZL of the redistribution layer 130.

[0068] In operation 610, after the resistors R11 and R12 are coupled in parallel and the resistors R21 and R22 are coupled in parallel, the resistor banks RS1 and RS2 are coupled in parallel according to the impedance value of the memory circuit 110.

[0069] In some practices, when an integrated circuit (IC) is applied to various component modules, a redistribution layer (RDL) is coupled to / formed in the IC to change the contact positions of the IC, such that the additional lines of the RDL increase the impedance of the IC (such as a DRAM). As a result, the signal integrity (SI) of the signal written to the DRAM is affected.

[0070] Compared with the above practices, in some embodiments of the present disclosure, when operation 504 is performed, one or more resistors in each of the resistor groups of the resistor circuit 120 are coupled in parallel according to the impedance value ZL of the redistribution layer 130, such that the impedance value ZR of the memory circuit 110 is approximately equal to or less than the difference between the impedance value RZQ and the impedance value ZL of the redistribution layer 130. Therefore, the signal integrity (SI) of the signal written to the memory device 100 is not affected.

[0071] In summary, in some embodiments of the present disclosure, when the memory circuit 110 is coupled to the redistribution layer 130, the resistor circuit 120 increases the impedance of the memory circuit 110 to maintain the signal integrity of the signal written to the memory device 100.

[0072] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand various aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same benefits as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations can be made without departing from the spirit and scope of the present disclosure.

[0073]

Symbol Description

[0074] 100: Memory device

[0075] 110: Memory circuit

[0076] 120, 200, 300, 400: Resistor circuit

[0077] 130: Redistribution layer

[0078] 500, 600: Method

[0079] 502, 504, 506, 602, 604, 606, 608, 610: Operation

[0080] RM, RR, RL: Impedance

[0081] ZM, ZR, ZL, RZQ: Impedance values

[0082] RS1 to RSn: Resistor groups

[0083] F11, F12, F21, F22, F31, F41, F51, F61, F71: Fuses

[0084] R11 to R13, R21 to R23, R31, R32, R41, R42, R51, R52, R61, R62, R71, R72: Resistors

[0085] N11 to N14, N21 to N24, N31 to N33, N41 to N43, N51 to N53, N61 to N63, N71 to N73: Nodes.

Claims

1. A memory device, characterized in that: Include: Memory circuit; a redistribution layer coupled to the memory circuit; and A resistor circuit is coupled to the memory circuit and includes a first resistor group and a second resistor group, The first resistor group includes a first resistor and a second resistor, The second resistor group includes a third resistor and a fourth resistor, and After the first resistor and the second resistor are coupled in parallel according to the impedance value of the redistribution layer and the third resistor and the fourth resistor are coupled in parallel according to the impedance value of the redistribution layer, the first resistor group and the second resistor group are coupled in parallel according to the impedance value of the memory circuit.

2. The memory device according to claim 1, wherein The resistor circuit further comprises a third resistor group, The third resistor group includes a fifth resistor and a sixth resistor, The fifth resistor and the sixth resistor are coupled in parallel according to the impedance value of the redistribution layer, and The first resistor group, the second resistor group and the third resistor group are coupled in parallel according to the impedance value of the memory circuit.

3. The memory device according to claim 2, wherein The resistor circuit further comprises a fourth resistor group, The fourth resistor group includes a seventh resistor and an eighth resistor, The seventh resistor and the eighth resistor are coupled in parallel according to the impedance value of the redistribution layer, and The first resistor group, the second resistor group, the third resistor group and the fourth resistor group are coupled in parallel according to the impedance value of the memory circuit.

4. The memory device of claim 3, wherein The resistor circuit further comprises a fifth resistor group, The fifth resistor group includes a ninth resistor and a tenth resistor, The ninth resistor and the tenth resistor are coupled in parallel according to the impedance value of the redistribution layer, and The first resistor group, the second resistor group, the third resistor group, the fourth resistor group, and the fifth resistor group are coupled in parallel according to the impedance value of the memory circuit.

5. The memory device of claim 4, wherein The resistor circuit further comprises a sixth resistor group, The sixth resistor group includes an eleventh resistor and a twelfth resistor, The eleventh resistor and the twelfth resistor are coupled in parallel according to the impedance value of the redistribution layer, and The first resistor group, the second resistor group, the third resistor group, the fourth resistor group, the fifth resistor group, and the sixth resistor group are coupled in parallel according to the impedance value of the memory circuit.

6. The memory device of claim 5, wherein The resistor circuit further comprises a seventh resistor group, The seventh resistor group includes a thirteenth resistor and a fourteenth resistor, The thirteenth resistor and the fourteenth resistor are coupled in parallel according to the impedance value of the redistribution layer, and The first resistor group, the second resistor group, the third resistor group, the fourth resistor group, the fifth resistor group, the sixth resistor group, and the seventh resistor group are coupled in parallel according to the impedance value of the memory circuit.

7. The memory device of claim 1, wherein The first resistor group further comprises a fifth resistor, The second resistor group further includes a sixth resistor, and The first resistor, the second resistor and the fifth resistor are coupled in parallel according to the impedance value of the redistribution layer, and the third resistor, the fourth resistor and the sixth resistor are coupled in parallel according to the impedance value of the redistribution layer.

8. A memory device, characterized in that: Include: Memory circuit; a redistribution layer coupled to the memory circuit; and A resistor circuit is coupled to the memory circuit and includes a first resistor group and a second resistor group, The first resistor group includes a first resistor, a second resistor and a first fuse, wherein the first fuse is coupled to the second resistor. The second resistor group includes a third resistor, a fourth resistor and a second fuse, the second fuse is coupled to the fourth resistor, and After the first resistor and the second resistor are coupled in parallel through the first fuse according to the impedance value of the redistribution layer and the third resistor and the fourth resistor are coupled in parallel through the second fuse according to the impedance value of the redistribution layer, the first resistor group and the second resistor group are coupled in parallel according to the impedance value of the memory circuit.

9. The memory device of claim 8, wherein The resistor circuit further comprises a third resistor group, The third resistor group includes a fifth resistor, a sixth resistor and a third fuse, wherein the third fuse is coupled to the sixth resistor. The fifth resistor and the sixth resistor are coupled in parallel through the third fuse according to the impedance value of the redistribution layer, and The first resistor group, the second resistor group and the third resistor group are coupled in parallel according to the impedance value of the memory circuit.

10. The memory device of claim 9, wherein The resistor circuit further comprises a fourth resistor group, The fourth resistor group includes a seventh resistor, an eighth resistor and a fourth fuse, wherein the fourth fuse is coupled to the eighth resistor. The seventh resistor and the eighth resistor are coupled in parallel through the fourth fuse according to the impedance value of the redistribution layer, and The first resistor group, the second resistor group, the third resistor group and the fourth resistor group are coupled in parallel according to the impedance value of the memory circuit.

11. The memory device of claim 10, wherein The resistor circuit further comprises a fifth resistor group, The fifth resistor group includes a ninth resistor, a tenth resistor, and a fifth fuse, wherein the fifth fuse is coupled to the tenth resistor. The ninth resistor and the tenth resistor are coupled in parallel through the fifth fuse according to the impedance value of the redistribution layer, and The first resistor group, the second resistor group, the third resistor group, the fourth resistor group, and the fifth resistor group are coupled in parallel according to the impedance value of the memory circuit.

12. The memory device of claim 11, wherein The resistor circuit further comprises a sixth resistor group, The sixth resistor group includes an eleventh resistor, a twelfth resistor and a sixth fuse, wherein the sixth fuse is coupled to the twelfth resistor. The eleventh resistor and the twelfth resistor are coupled in parallel through the sixth fuse according to the impedance value of the redistribution layer, and The first resistor group, the second resistor group, the third resistor group, the fourth resistor group, the fifth resistor group, and the sixth resistor group are coupled in parallel according to the impedance value of the memory circuit.

13. The memory device of claim 12, wherein The resistor circuit further comprises a seventh resistor group, The seventh resistor group includes a thirteenth resistor, a fourteenth resistor and a seventh fuse, wherein the seventh fuse is coupled to the fourteenth resistor. The thirteenth resistor and the fourteenth resistor are coupled in parallel through the seventh fuse according to the impedance value of the redistribution layer, and The first resistor group, the second resistor group, the third resistor group, the fourth resistor group, the fifth resistor group, the sixth resistor group, and the seventh resistor group are coupled in parallel according to the impedance value of the memory circuit.

14. The memory device of claim 8, wherein The first resistor group further includes a fifth resistor and a third fuse, wherein the third fuse is coupled to the fifth resistor. The second resistor group further includes a sixth resistor and a fourth fuse, the fourth fuse is coupled to the sixth resistor, and The first resistor, the second resistor and the fifth resistor are coupled in parallel through the first fuse and the third fuse according to the impedance value of the redistribution layer, and the third resistor, the fourth resistor and the sixth resistor are coupled in parallel through the second fuse and the fourth fuse according to the impedance value of the redistribution layer.

15. A method of operating a memory device, characterized in that: Include: coupling the resistor circuit to the memory circuit; coupling a redistribution layer to the memory circuit; According to the impedance value of the redistribution layer, a first resistor and a second resistor are coupled in parallel; According to the impedance value of the redistribution layer, a third resistor and a fourth resistor are coupled in parallel; as well as After the first resistor and the second resistor are coupled in parallel and the third resistor and the fourth resistor are coupled in parallel, a first resistor group and a second resistor group are coupled in parallel according to the impedance value of the memory circuit.

16. The method according to claim 15, wherein The resistor circuit includes the first resistor group and the second resistor group, The first resistor group includes the first resistor and the second resistor, and The second resistor group includes the third resistor and the fourth resistor.

17. The method according to claim 16, wherein: Also includes: According to the impedance value of the redistribution layer, a fifth resistor and a sixth resistor are coupled in parallel; as well as After the first resistor and the second resistor are coupled in parallel, the third resistor and the fourth resistor are coupled in parallel, and the fifth resistor and the sixth resistor are coupled in parallel, the third resistor group, the first resistor group, and the second resistor group are coupled in parallel according to the impedance value of the memory circuit.

18. The method according to claim 17, wherein The resistor circuit further includes the third resistor group, and The third resistor group includes the fifth resistor and the sixth resistor.

19. The method according to claim 16, wherein: Also includes: According to the impedance value of the redistribution layer, a fifth resistor, the first resistor and the second resistor are coupled in parallel; According to the impedance value of the redistribution layer, a sixth resistor, the third resistor and the fourth resistor are coupled in parallel; as well as After the fifth resistor, the first resistor and the second resistor are coupled in parallel and the sixth resistor, the third resistor and the fourth resistor are coupled in parallel, the first resistor group and the second resistor group are coupled in parallel according to the impedance value of the memory circuit, The first resistor group further includes the fifth resistor, and The second resistor group further includes the sixth resistor.

20. The method according to claim 16, wherein: Also includes: coupling the first fuse to the second resistor; as well as A second fuse is coupled to the fourth resistor, wherein The first resistor and the second resistor are coupled in parallel through the first fuse, and The third resistor and the fourth resistor are coupled in parallel through the second fuse.

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