Symbol weight mapping method and device based on memristor array
By using a single-column memristor array and a single analog-to-digital converter for signed weight mapping in an in-memory computing neural network accelerator, the problem of large number of analog-to-digital converters and accumulation of quantization errors in the prior art is solved, and more efficient and accurate calculations are achieved.
Patent Information
- Application Number
- CN202510332765.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-20
- Publication Date
- 2025-06-27
AI Technical Summary
The existing signed number weight mapping scheme has the problem of large number of analog-to-digital converters and serious accumulation of quantization errors, which affects the energy efficiency and accuracy of in-memory computing neural network accelerators.
A single-column memristor array is used to store signed weights, and the accumulated current is quantized through a single analog-to-digital converter to realize signed calculation results, reduce the number of quantization times, and simplify the circuit structure.
The number of analog-to-digital converters and the accumulation of quantization errors is reduced, the calculation accuracy is improved, and the power consumption, area and delay overhead is significantly reduced.
Smart Images
Figure CN120220764A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of integrated circuit technology, and more particularly to a signed weight mapping method and apparatus based on a memristor array. Background Art
[0002] Due to its powerful visual processing capabilities, convolutional neural networks have been widely applied to various visual tasks. However, their intensive computational requirements pose severe challenges to the computing power and energy efficiency of processors. Under the current von Neumann architecture, the frequent data transfer between processing units and storage units has become the main bottleneck restricting the improvement of processor computing power and energy efficiency.
[0003] To break through this bottleneck, in-memory computing neural network inference accelerators based on non-volatile memory have emerged. Such accelerators utilize the characteristics of in-situ high-parallel computing to achieve a 10- to 1000-fold improvement in computing power and energy efficiency compared to general-purpose processors. However, the performance of in-memory computing accelerators is largely affected by the neural network weight mapping method.
[0004] Existing signed number weight mapping schemes, such as Figure 1 As shown, two columns of memristors are used to represent a weight vector. One column is used to store positive weights, and the other column is used to store negative weights. The input vector is respectively multiplied and accumulated with these two columns of memristors to obtain a positive accumulated current and a negative accumulated current. Subsequently, these two accumulated currents are quantized through an analog-to-digital converter, and then the positive accumulated current is subtracted from the negative accumulated current through digital circuits to obtain a signed operation result.
[0005] However, this method of separately quantizing and then subtracting has obvious problems. On the one hand, it requires at least two analog-to-digital converters (or time-division multiplexing one ADC but reducing parallelism), increasing the area and power consumption overhead of the analog-to-digital converter. On the other hand, since the positive and negative accumulated currents are separately quantized, quantization errors will accumulate, seriously affecting the energy efficiency and accuracy of the accelerator. Therefore, exploring more efficient weight mapping and quantization methods is crucial for improving the performance of in-memory computing neural network accelerators. Future research needs to focus on how to reduce the number of analog-to-digital converters, reduce quantization errors, and improve the overall energy efficiency and accuracy of the accelerator. Summary of the Invention
[0006] (I) Technical Problems to be Solved
[0007] To solve the problems of large quantization overhead and error accumulation in existing technologies, the present disclosure provides a signed weight mapping method and apparatus based on a memristor array. By using a column of memristors to store signed weights, only one analog-to-digital converter is needed to quantify the accumulated current, and a signed calculation result can be obtained. This can halve the quantization times, and thus the area, power consumption, and delay overhead of the readout circuit can be halved.
[0008] (II) Technical Solutions
[0009] In view of the above technical problems, embodiments of the present disclosure propose a signed weight mapping method and apparatus based on a memristor array.
[0010] According to a first aspect of the present disclosure, there is provided a signed weight mapping method based on a memristor array. The memristor array includes a single-column memristor array. The method includes: applying an input signal to a bit line terminal of the memristor; performing a multiply-accumulate operation on the input signal to obtain an accumulated current; and quantifying the accumulated current by using a single analog-to-digital converter to obtain a signed weight.
[0011] In some exemplary embodiments, before applying the input signal to the bit line terminal of the memristor, it further includes: dividing the conductance states of the memristor into a positive weight region, a negative weight region, and a zero value region.
[0012] In some exemplary embodiments, dividing the conductance states of the memristor into a positive weight region, a negative weight region, and a zero value region includes: evenly dividing the conductance range of the memristor into 2N + 1 conductance states, where N is a positive integer; sorting the 2N + 1 conductance states from small to large to obtain a conductance state sequence of the memristor; defining the (N + 1)-th conductance state in the conductance state sequence as 0; defining the 1st to N-th conductance states in the conductance state sequence as negative weights; defining the (N + 2)-th to (2N + 1)-th conductance states in the conductance state sequence as positive weights; where all conductance states that are 0 form the zero value region; all conductance states that are negative weights form the negative weight region; and all conductance states that are positive weights form the positive weight region.
[0013] In some exemplary embodiments, performing a multiply-accumulate operation on the input signal includes: implementing the multiply-accumulate operation of the memristor array based on Ohm's law and Kirchhoff's current law.
[0014] In some exemplary embodiments, quantifying the accumulated current by using a single analog-to-digital converter to obtain a signed weight includes: sampling the accumulated current by using a single analog-to-digital converter; quantifying the amplitude of the accumulated current by using a single analog-to-digital converter; and converting the amplitude of the quantified current into a binary digital signal to obtain a signed weight.
[0015] In some exemplary embodiments, the numerical range corresponding to the magnitude of the cumulative current corresponding to the conductance states of the negative weight region from small to large after quantization is from -N to -1; the numerical range corresponding to the magnitude of the cumulative current corresponding to the conductance states of the positive weight region from small to large after quantization is from 1 to N; the sign bit of the conductance state of the negative weight is defined as 1; the sign bit of the conductance state of the positive weight is defined as 0.
[0016] In some exemplary embodiments, converting the magnitude of the quantized current into a binary digital signal includes: converting the magnitude of the quantized current into a binary digital signal based on the numerical range corresponding to the magnitude of the cumulative current after quantization and the conductance state.
[0017] In some exemplary embodiments, the method further includes: adjusting the conductance value of the memristor to implement weight update; and storing the updated weight by using the non-volatile characteristic of the memristor.
[0018] According to a second aspect of the present disclosure, there is provided a signed weight mapping device based on a memristor array. The memristor array includes a single-column memristor array. The device includes: a signal input module for applying an input signal to the bit line end of the memristor; an operation module for performing a multiply-accumulate operation on the input signal to obtain a cumulative current; and a quantization module for quantizing the cumulative current by using a single analog-to-digital converter to obtain a signed weight.
[0019] In some exemplary embodiments, the device further includes: a setting module for dividing the conductance states of the memristors into a positive weight region, a negative weight region, and a zero value region.
[0020] (III) Beneficial effects
[0021] As can be seen from the above technical solutions, a signed weight mapping method and device based on a memristor array provided by the embodiments of the present disclosure have at least the following beneficial effects:
[0022] (1) Using a single column of memristors to store signed weights, only one analog-to-digital converter is needed to quantize the cumulative current, so that a signed calculation result can be obtained, avoiding the use of a subtractor, simplifying the circuit structure, and being able to halve the quantization times. Therefore, the area, power consumption, and delay overhead of the readout circuit can be halved.
[0023] (2) Reducing the accumulation of quantization errors and improving the calculation accuracy.
[0024] (3) Significantly reducing the power consumption, area, and delay overhead. Description of the drawings
[0025] Through the following description of the embodiments of the present disclosure with reference to the drawings, the above content and other objects, features, and advantages of the present disclosure will become clearer. In the drawings:
[0026] Figure 1 A schematic diagram schematically showing an existing signed number weight mapping scheme;
[0027] Figure 2 A schematic diagram schematically showing a signed weight mapping method based on a memristor array according to an embodiment of the present disclosure;
[0028] Figure 3 A flowchart schematically showing a signed weight mapping method based on a memristor array according to an embodiment of the present disclosure;
[0029] Figure 4 A schematic diagram schematically showing the conductance weight correspondence of a mapping scheme according to an embodiment of the present disclosure;
[0030] Figure 5 A comparative schematic diagram schematically showing a signed weight mapping method based on a memristor array according to an embodiment of the present disclosure and a conventional method; and
[0031] Figure 6 A structural block diagram schematically showing a signed weight mapping device based on a memristor array according to an embodiment of the present disclosure. Detailed implementation manners
[0032] To make the objectives, technical solutions and advantages of the present disclosure more clear and understandable, the present disclosure will be further described in detail below with reference to specific embodiments and the accompanying drawings. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.
[0033] The present disclosure provides a signed weight mapping method based on a memristor array, which uses only one column of memristive devices to represent signed weights, applies a voltage at the bit line end of the memristor as an input, and then uses Kirchhoff's current law and Ohm's law to complete the multiply-accumulate operation. Different from the existing scheme that uses two columns of memristors to store signed weights and quantizes them separately, this scheme uses only one column of memristors to store signed weights. Therefore, only one analog-to-digital converter is needed to quantize the accumulated current, and a signed calculation result can be obtained, which can halve the quantization times. Therefore, the area, power consumption, and delay overhead of the readout circuit can be halved. Combining Figures 2 - 5 A detailed introduction to the signed weight mapping method based on a memristor array according to an embodiment of the present disclosure will be given.
[0034] Figure 2 A schematic diagram schematically showing a signed weight mapping method based on a memristor array according to an embodiment of the present disclosure; Figure 3A flowchart of a signed weight mapping method based on a memristor array according to an embodiment of the present disclosure is schematically shown.
[0035] From Figure 2 and Figure 3 it can be seen that the signed weight mapping method based on a memristor array according to an embodiment of the present disclosure includes steps S110 - S130.
[0036] In step S110, an input signal is applied to the bit line terminal of the memristor.
[0037] A memristor, as a special electronic component, has the ability to remember the amount of charge passing through it, and its conductance state changes with the amount of charge passing through. According to Ohm's law, when a voltage is applied to the memristor, a corresponding current is generated, and the magnitude of this current is closely related to the current conductance state of the memristor.
[0038] To more finely control and manage the conductance state of the memristor, before step S110, it further includes: dividing the conductance state of the memristor into a positive weight region, a negative weight region, and a zero value region.
[0039] Specifically, the conductance range of the memristor is evenly divided into 2N + 1 conductance states, where N is a positive integer; the 2N + 1 conductance states are sorted from small to large to obtain the conductance state sequence of the memristor; the (N + 1)-th conductance state in the conductance state sequence is defined as 0 as a reference point; the 1st to N-th conductance states in the conductance state sequence are defined as negative weights, indicating that their corresponding current directions or effects are "negative", and these negative weight conductance states can be used to represent negative synaptic weights or negative input signals in neuromorphic computing; the (N + 2)-th to (2N + 1)-th conductance states in the conductance state sequence are defined as positive weights, indicating that their corresponding current directions or effects are "positive", and these positive weight conductance states can be used to represent positive synaptic weights or positive input signals in neuromorphic computing; among them, all conductance states that are 0 form the zero value region; all conductance states with negative weights form the negative weight region; and all conductance states with positive weights form the positive weight region. Through such a conductance state division, we can achieve the mapping and calculation of signed weights, providing greater flexibility and accuracy for neuromorphic computing.
[0040] In step S120, a multiply-accumulate operation is performed on the input signal to obtain an accumulated current.
[0041] The multiply-accumulate operation is performed using a memristor array. This is achieved based on Ohm's law and Kirchhoff's current law. When an input signal (voltage) is applied to the memristor array, each memristor generates a corresponding current according to its conductance state. These currents are aggregated in a specific manner in the array to form an accumulated current. This accumulated current actually reflects the interaction result between the input signal and the conductance state of the memristor.
[0042] Specifically, if the input signal is a positive voltage, then the memristors with positive weights will generate forward currents, the memristors with negative weights will generate reverse currents, and the memristors in the zero-value region will not generate currents. After these currents are aggregated in the array, an aggregated current is formed, and its magnitude and direction depend on the interaction between the input signal and the conductance states of the memristors. Similarly, if the input signal is a negative voltage, then the memristors with positive weights will generate reverse currents, the memristors with negative weights will generate forward currents, and the memristors in the zero-value region still will not generate currents. After these currents are aggregated in the array, an aggregated current is also formed. Through such multiply-accumulate operations, we can achieve the matrix multiplication operation between the input signal and the conductance states of the memristors, providing an efficient calculation method for neuromorphic computing.
[0043] In step S130, a single analog-to-digital converter is used to quantize the aggregated current to obtain signed weights.
[0044] In some exemplary embodiments, step S130 includes steps S131 - S133.
[0045] In step S131, a single analog-to-digital converter is used to sample the aggregated current. Sampling is the first step of analog-to-digital conversion, which determines the accuracy and speed of analog-to-digital conversion. Through sampling, the continuous aggregated current can be converted into discrete sampling points, providing a basis for the subsequent quantization process.
[0046] In step S132, a single analog-to-digital converter is used to quantize the magnitude of the aggregated current. Quantization is the process of converting continuous sampling points into discrete digital signals. Through quantization, the magnitude of the aggregated current can be mapped to a specific numerical range, providing convenience for subsequent digital signal processing.
[0047] In step S133, the magnitude of the quantized current is converted into a binary digital signal to obtain signed weights. This conversion process is based on the quantized numerical range and conductance states.
[0048] Specifically, it is defined that the numerical range corresponding to the magnitude of the aggregated current after quantization for the conductance states increasing from small to large in the negative weight region is from -N to -1; the numerical range corresponding to the magnitude of the aggregated current after quantization for the conductance states increasing from small to large in the positive weight region is from 1 to N; it is defined that the sign bit of the conductance state of the negative weight is 1; it is defined that the sign bit of the conductance state of the positive weight is 0.
[0049] Convert the amplitude of the quantized current into a binary digital signal based on the numerical range and conductance state corresponding to the amplitude quantization of the accumulated current. Through such a conversion process, signed weights can be obtained, which contain both the magnitude information and the sign information of the weights. These signed weights can be used in subsequent neuromorphic calculations to achieve more complex calculation functions and higher calculation accuracy.
[0050] In the embodiments of the present disclosure, the conductance value of the memristor can also be adjusted to update the weights, and the updated weights can be stored by utilizing the non-volatile characteristics of the memristor.
[0051] The method proposed in the embodiments of the present disclosure only requires one analog-to-digital converter to complete the quantization processing of all signals, simplifying the circuit design. Traditional circuit designs may require multiple analog-to-digital converters to process different signals, while this method realizes a more concise circuit design by utilizing a memristor array and a single analog-to-digital converter.
[0052] Figure 4 Schematically shows a schematic diagram of the conductance weight correspondence of the mapping scheme according to the embodiments of the present disclosure.
[0053] As Figure 4 shown, assuming that the representable conductance range of the memristor is from 10 uS to 160 uS, and each 10 uS represents a conductance state, then a total of 15 conductance states can be represented. It is stipulated that greater than the intermediate conductance state (80 uS - 90 uS) is positive and the sign bit is 0; less than the intermediate conductance state is negative and the sign bit is 1, so that -7 to +7 can be represented. Based on the sign bit and the numerical range, the conductance weight mapping relationship is obtained using binary.
[0054] Figure 5 Schematically shows a comparison schematic diagram of the signed weight mapping method based on the memristor array according to the embodiments of the present disclosure and the traditional method.
[0055] From Figure 5 it can be seen that this scheme only needs to quantize one column of weights, which not only reduces the number of analog-to-digital converters by half but also avoids the use of subtractors. Therefore, the present disclosure can effectively improve the overall calculation performance. According to the simulation results, the calculation power consumption can be reduced by 39%, the area overhead can be reduced by 56%, the quantization error can be reduced by 50%, and the calculation delay will also be reduced by 60%.
[0056] Figure 6 Schematically shows a structural block diagram of the signed weight mapping device based on the memristor array according to the embodiments of the present disclosure.
[0057] As Figure 6As shown, the signed weight mapping device 800 based on a memristor array in this embodiment, where the memristor array includes a single-column memristor array, and the device includes a signal input module 810, an operation module 820, and a quantization module 830.
[0058] The signal input module 810 is configured to apply an input signal to the bit line terminal of the memristor.
[0059] The operation module 820 is configured to perform a multiply-accumulate operation on the input signal to obtain an accumulated current.
[0060] The quantization module 830 is configured to quantize the accumulated current by using a single analog-to-digital converter to obtain a signed weight.
[0061] The device may further include: a setting module configured to divide the conductance states of the memristors into a positive weight region, a negative weight region, and a zero value region.
[0062] According to an embodiment of the present disclosure, any multiple of the signal input module 810, the operation module 820, and the quantization module 830 may be combined and implemented in one module, or any one of them may be split into multiple modules. Alternatively, at least part of the functions of one or more of these modules may be combined with at least part of the functions of other modules and implemented in one module. According to an embodiment of the present disclosure, at least one of the signal input module 810, the operation module 820, and the quantization module 830 may be at least partially implemented as a hardware circuit, such as a field programmable gate array (FPGA), a programmable logic array (PLA), a system on chip, a system on substrate, a system on package, an application specific integrated circuit (ASIC), or any other reasonable manner of integrating or packaging circuits, etc., implemented by hardware or firmware, or implemented in any one of the three implementation manners of software, hardware, and firmware, or in any appropriate combination of several of them. Alternatively, at least one of the signal input module 810, the operation module 820, and the quantization module 830 may be at least partially implemented as a computer program module, and when the computer program module is run, it may execute the corresponding functions.
[0063] Those skilled in the art can understand that the features described in the various embodiments of the present disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in the present disclosure. In particular, without departing from the spirit and teachings of the present disclosure, the features described in the various embodiments of the present disclosure can be combined and / or combined in various ways. All such combinations and / or combinations fall within the scope of the present disclosure.
Claims
1. A signed weight mapping method based on a memristor array, wherein the memristor array comprises a single-column memristor array, characterized in that: The method comprises: applying an input signal to a bit line terminal of the memristor; Performing a multiplication-accumulation operation on the input signal to obtain an accumulated current; The accumulated current is quantized using a single analog-to-digital converter to obtain a signed weight.
2. The method according to claim 1, characterized in that Before applying the input signal to the bit line terminal of the memristor, the method further includes: dividing the conductivity state of the memristor into a positive weight region, a negative weight region and a zero value region.
3. The method according to claim 2, characterized in that The step of dividing the conductance state of the memristor into a positive weight region, a negative weight region and a zero value region comprises: Dividing the conductance range of the memristor into 2N+1 conductance states, where N is a positive integer; Arrange the 2N+1 conductance states from small to large to obtain a conductance state sequence of the memristor; defining the N+1th conductivity state in the conductivity state sequence as 0; defining the first to Nth conductivity states in the conductivity state sequence as negative weights; Defining the N+2th to 2N+1th conductivity states in the conductivity state sequence as positive weights; wherein all the conductivity states that are 0 constitute the zero value region; All the conductivity states with negative weights constitute the negative weight region; and All of the conductance states with positive weights constitute the positive weight region.
4. The method according to claim 1, characterized in that The performing multiplication-accumulation operation on the input signal includes: implementing the multiplication-accumulation operation of the memristor array based on Ohm's law and Kirchhoff's current law.
5. The method according to claim 3, characterized in that: The step of quantizing the accumulated current by using a single analog-to-digital converter to obtain a signed weight comprises: The accumulated current is sampled using a single analog-to-digital converter; quantizing the amplitude of the accumulated current using a single analog-to-digital converter; The amplitude of the quantized current is converted into a binary digital signal to obtain a signed weight.
6. The method according to claim 5, characterized in that The amplitude of the accumulated current corresponding to the conductivity state in the negative weight region from small to large is quantized to a value range of -N to -1; The amplitude of the accumulated current corresponding to the conductivity state in the positive weight region from small to large is quantized to a value range of 1 to N; Defining the sign bit of the negative weighted conductivity state to be 1; The sign bit of the conductivity state defining the positive weight is 0.
7. The method according to claim 6, characterized in that Converting the quantized current amplitude into a binary digital signal includes: Based on the numerical range corresponding to the quantized amplitude of the accumulated current and the conductivity state, the quantized amplitude of the current is converted into a binary digital signal.
8. The method according to claim 1, characterized in that The method further includes: adjusting the conductance value of the memristor to update the weight; and The non-volatile property of memristors is exploited to store updated weights.
9. A signed weight mapping device based on a memristor array, wherein the memristor array comprises a single-column memristor array, characterized in that: The device comprises: A signal input module, used for applying an input signal to a bit line terminal of the memristor; An operation module, used for performing multiplication and accumulation operation on the input signal to obtain an accumulated current; The quantization module is used to quantize the accumulated current using a single analog-to-digital converter to obtain a weight with a sign.
10. The device according to claim 9, characterized in that The device also includes: A setting module is used to divide the conductance state of the memristor into a positive weight region, a negative weight region and a zero value region.