Chip detection method and device, electronic equipment and storage medium
By acquiring and evaluating the initial and target calibration parameters of the communication chip and determining the chip usage requirements, the frequent chip replacement problem caused by insufficient efuse space is solved, and the effect of reducing production costs and improving resource utilization efficiency is achieved.
Patent Information
- Application Number
- CN202311835470.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-27
- Publication Date
- 2025-06-27
AI Technical Summary
In the prior art, communication chips such as Wi-Fi chips can easily lead to insufficient efuse space during repeated calibration and writing, which in turn leads to frequent replacement of chips, increasing production costs and waste of resources.
In the case where the remaining space of the target storage area is smaller than the storage space of the target calibration parameters, the initial calibration parameters are acquired, and the target evaluation parameters are determined based on the target calibration parameters and the initial calibration parameters. When the target evaluation parameters meet the evaluation conditions, make sure the chip meets the usage requirements and reduce duplicate writes and chip replacement.
Reduces the probability of repeated writes of calibration parameters, reduces chip loss and replacement, improves chip reuse rate, thereby reducing production costs and improving resource utilization efficiency.
Smart Images
Figure CN120220779A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of testing technologies, and particularly to a chip detection method, apparatus, electronic device, and storage medium. Background Art
[0002] In the production process of electronic products, products carrying communication chips such as Wi-Fi (Wireless Fidelity) chips need to undergo performance calibration testing to ensure that the chips have stable and reliable performance during normal operation. These performance parameters include, but are not limited to, wireless signal strength, frequency response, anti-interference ability, etc. Summary of the Invention
[0003] The present disclosure provides a chip detection method, apparatus, electronic device, and storage medium to solve or alleviate one or more technical problems in the prior art.
[0004] In a first aspect, the present disclosure provides a chip detection method, including:
[0005] When the remaining space in the target storage area is less than the storage space of the target calibration parameter, obtaining the initial calibration parameter stored in the target storage area, where the target storage area is a non-volatile storage area in the chip, the target calibration parameter is the calibration parameter obtained by performing non-first calibration on the chip, and the initial calibration parameter is the calibration parameter of the chip written into the target storage area most recently;
[0006] Determining a target evaluation parameter based on the target calibration parameter and the initial calibration parameter;
[0007] When the target evaluation parameter meets the evaluation condition, determining that the chip meets the usage requirements.
[0008] In a second aspect, the present disclosure provides a chip detection apparatus, including:
[0009] An obtaining unit, configured to obtain the initial calibration parameter stored in the target storage area when the remaining space in the target storage area is less than the storage space of the target calibration parameter, where the target storage area is a non-volatile storage area in the chip, the target calibration parameter is the calibration parameter obtained by performing non-first calibration on the chip, and the initial calibration parameter is the calibration parameter of the chip written into the target storage area most recently;
[0010] A first determination unit, configured to determine a target evaluation parameter based on the target calibration parameter and the initial calibration parameter;
[0011] A second determination unit, configured to determine that the chip meets the usage requirements when the target evaluation parameter meets the evaluation condition.
[0012] In a third aspect, an electronic device is provided, including:
[0013] at least one processor; and
[0014] a memory communicatively connected to the at least one processor; wherein,
[0015] the memory stores instructions executable by the at least one processor, and when the instructions are executed by the at least one processor, the at least one processor is enabled to execute any method in the embodiments of the present disclosure.
[0016] In a fourth aspect, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to cause the computer to execute any method in the embodiments of the present disclosure.
[0017] According to the chip detection method, device, electronic device and storage medium provided by the embodiments of the present disclosure, when the remaining space of the target storage area is less than the storage space of the target calibration parameter, the initial calibration parameter stored in the target storage area is obtained, wherein the target storage area is a non-volatile storage area in the chip, the target calibration parameter is the calibration parameter obtained by performing non-first calibration on the chip, and the initial calibration parameter is the calibration parameter of the chip written into the target storage area most recently; based on the target calibration parameter and the initial calibration parameter, a target evaluation parameter is determined; when the target evaluation parameter meets the evaluation condition, it is determined that the chip meets the usage requirements. The chip detection method can reduce the probability of repeated writing of calibration parameters, reduce chip loss, improve the reuse rate of the chip, thereby reducing costs and improving resource utilization efficiency.
[0018] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] In the drawings, unless otherwise specified, the same reference numerals throughout the drawings denote the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments provided by the present disclosure and should not be regarded as limiting the scope of the present disclosure.
[0020] Figure 1 is a flowchart of a chip detection method provided by an embodiment of the present disclosure;
[0021] Figure 2 is a flowchart of a chip detection method provided by an embodiment of the present disclosure;
[0022] Figure 3It is a schematic block diagram of a chip detection device provided by an embodiment of the present disclosure;
[0023] Figure 4 It is a block diagram of an electronic device for implementing the chip detection method of the embodiment of the present disclosure. Specific embodiments
[0024] The following will further describe the present disclosure in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements having the same or similar functions. Although various aspects of the embodiments are shown in the drawings, the drawings do not have to be drawn to scale unless otherwise specified.
[0025] The embodiments of the present disclosure provide a chip detection method, device, electronic device, and storage medium. Specifically, the chip detection method of the embodiments of the present disclosure can be executed by an electronic device, where the electronic device can be a device such as a terminal or a server. The terminal can be a device such as a smart phone, a tablet computer, a notebook computer, a smart voice interaction device, a smart home appliance, a wearable smart device, an aircraft, a smart vehicle terminal, etc. The terminal can also include a client, and the client can be an audio client, a video client, a browser client, an instant messaging client, or a small program, etc. The server can be an independent physical server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, Content Delivery Network (CDN), and big data and artificial intelligence platforms.
[0026] The present disclosure relates to chip detection, especially the detection and calibration of communication chips such as Wi-Fi chips. The following explains the proprietary terms involved in the embodiments of the present disclosure:
[0027] efuse (Electronic Fuse): A storage device used to store chip configuration and calibration data. It is usually a piece of non-volatile memory, which means that the data in it remains unchanged after power-off or restart.
[0028] NVM (Non-volatile Memory): Refers to a type of memory that can retain data after power-off or restart. efuse is a type of NVM, so the data stored in it remains unchanged in the case of power-off.
[0029] Calibration: A process of adjusting the functions and performance of a chip to ensure the accuracy and reliability of its transmission and reception of wireless signals. efuse can be used to store calibration parameters, such as power calibration, frequency calibration, and gain calibration, etc.
[0030] In the related art, taking a communication chip as a Wi-Fi chip as an example, in order to apply the calibrated Wi-Fi performance parameters to an actual product, these parameters need to be written into the efuse (programmable read-only memory) space of the Wi-Fi chip. Efuse is a non-erasable memory. Since it cannot be erased, it cannot be modified or tampered with after being written. Therefore, writing the Wi-Fi performance parameters into the efuse space can ensure that these parameters will not be accidentally changed during subsequent use.
[0031] Before writing the parameters, a strict calibration process is usually carried out first. Professional test instruments and equipment are used to precisely measure and adjust the Wi-Fi chip. The calibrated performance parameters will be recorded and converted into binary form, and then written into the efuse space through a specific programming algorithm.
[0032] After writing the Wi-Fi performance parameters into the efuse space, the chip will read these parameters during normal use to configure and optimize the transmission and reception of wireless signals. This can ensure the reliability and performance stability of the product in different environments.
[0033] However, in actual production, situations such as retesting, rework, and repair caused by machine equipment or human factors often occur. These situations may affect the accuracy and stability of the Wi-Fi performance parameters, and secondary or even tertiary writing is required.
[0034] When the above situations occur, it is necessary to recalibrate the performance parameters of the Wi-Fi chip and rewrite them into the efuse space. However, when repeatedly writing the performance parameters, it should be noted that the efuse space is a read-only memory, and each write will consume a certain amount of space. Therefore, repeated writing will compress the efuse space of the Wi-Fi chip.
[0035] When the performance parameters cannot be written into the efuse space, the product test fails, and usually, the need to replace the Wi-Fi chip will be triggered because the inability to directly complete the product test means that these products cannot be shipped out of the factory. Therefore, the Wi-Fi chip needs to be replaced on the production line, which will not only increase additional labor and time costs but also bring more scrap and disposal costs. In addition, since replacing the chip requires additional material procurement and inventory management, this will also bring additional complexity and cost pressure to the overall production process.
[0036] In addition, frequent replacement of Wi-Fi chips may also affect the production progress, extend the product delivery cycle, and affect customer satisfaction. Especially in large-scale production scenarios, even minor changes can have a chain effect on the entire production plan, ultimately leading to uncontrollable cost increases and delivery delays.
[0037] To solve at least one of the above problems, embodiments of the present disclosure provide a chip detection method, apparatus, electronic device, and storage medium. When the remaining space in the target storage area is less than the storage space of the target calibration parameter, the initial calibration parameter stored in the target storage area is obtained, where the target storage area is a non-volatile storage area in the chip, the target calibration parameter is the calibration parameter obtained by non-first calibration of the chip, and the initial calibration parameter is the calibration parameter of the chip written into the target storage area most recently; based on the target calibration parameter and the initial calibration parameter, a target evaluation parameter is determined; when the target evaluation parameter meets the evaluation condition, it is determined that the chip meets the usage requirements. The chip detection method can reduce the probability of repeated writing of calibration parameters, reduce chip loss, improve the reuse rate of chips, thereby reducing costs and improving resource utilization efficiency.
[0038] The solutions of the present disclosure are described below with reference to the accompanying drawings. It should be noted that the description order of the following embodiments does not limit the priority order of the embodiments.
[0039] Figure 1 is a flowchart of a chip detection method provided by an embodiment of the present disclosure; please refer to Figure 1 Embodiments of the present disclosure provide a chip detection method 100, including steps S101 to S103.
[0040] Step S101, when the remaining space in the target storage area is less than the storage space of the target calibration parameter, obtain the initial calibration parameter stored in the target storage area, where the target storage area is a non-volatile storage area in the chip, the target calibration parameter is the calibration parameter obtained by non-first calibration of the chip, and the initial calibration parameter is the calibration parameter of the chip written into the target storage area most recently;
[0041] Step S102, determine a target evaluation parameter based on the target calibration parameter and the initial calibration parameter;
[0042] Step S103, when the target evaluation parameter meets the evaluation condition, determine that the chip meets the usage requirements.
[0043] It can be understood that the method 100 can be used in a communication chip. Taking a Wi-Fi chip as an example, in scenarios such as when an electronic product containing a Wi-Fi chip fails and needs to be repaired, or during the factory inspection of an electronic product. For example, during the factory inspection, if it is found that the electronic product has a fault and components on the main board (such as electronic devices around the Wi-Fi chip) are replaced or adjusted again, then due to the change of components on the main board, the performance parameters of the communication chip may change. At this time, it is necessary to re-detect and calibrate the Wi-Fi chip to obtain the target calibration parameters of the chip. The target calibration parameters usually need to be written into the target storage area in the chip.
[0044] The target storage area can be a non-volatile storage area in the chip, that is, a programmable read-only storage space. In some embodiments, the target storage space is the efuse space in the chip. It can be understood that the data stored in the target storage area can be written, read, but cannot be erased and rewritten, and after restarting, the data will not be lost. Therefore, after writing data multiple times, there may be a problem of insufficient space. The remaining space of the target storage area is the available storage space of the target storage area.
[0045] The target calibration parameters are the performance parameters of the chip after detection and calibration, such as including but not limited to parameters such as wireless signal strength, frequency response, and anti-interference ability. The storage space of the target calibration parameters is the data space required to store the target calibration parameters. It can be understood that the target calibration parameters are the calibration parameters obtained by performing non-first calibration on the chip, that is, there are already calibration parameters of the current chip stored in the target storage area before, which are the initial calibration parameters.
[0046] The initial calibration parameters can be the current calibration parameters of the chip, that is, the calibration parameters of the chip written into the target storage area last time before the target calibration parameters. For example, when the target calibration parameters are obtained by secondary calibration, the initial calibration parameters can be the calibration parameters written into the chip for the first time during production. For example, when the target calibration parameters are obtained by tertiary calibration, the initial calibration parameters can be the calibration parameters written into the chip by secondary calibration.
[0047] In step S101, when the remaining space of the target storage area is less than the storage space of the target calibration parameters, it means that the target calibration parameters cannot be written into the target storage area. At this time, the initial calibration parameters can be obtained from the target storage area.
[0048] In step S102, the target evaluation parameters can be determined according to the initial calibration parameters and the target calibration parameters. The target evaluation parameters can be used to characterize the degree of difference between the initial calibration parameters and the target calibration parameters.
[0049] In step S103, the evaluation condition can be a differential degree range, a threshold value, etc. When the target evaluation parameter meets the evaluation condition, it indicates that the difference between the initial calibration parameter and the target calibration parameter is small. It can be understood that the initial calibration parameter of the chip is still within the qualified range of the current chip. At this time, the chip meets the usage requirements, that is, it can continue to use the initial calibration parameter, and the chip can also continue to be used.
[0050] It can be understood that in the related technology, when the performance parameter (calibration parameter) cannot be written into the efuse space,
[0051] the product test fails, usually triggering the need to replace the Wi-Fi chip. In this embodiment, by evaluating the initial calibration parameter and the target calibration parameter and determining whether the target evaluation parameter meets the evaluation condition, some chips that can still be used although the target performance parameter cannot be written into the target storage space can be retained, which can reduce the probability of repeated writing of the calibration parameter, reduce chip loss, improve the reuse rate of the chip, thereby reducing costs and improving resource utilization efficiency.
[0052] In addition, the part of the chips that can still be used screened out in this embodiment do not need to be replaced, which can reduce the labor and time costs of chip replacement, reduce the scrap rate and scrap cost. At the same time, since this part of the chips do not need to be repurchased and managed in inventory, it reduces the complexity and cost pressure brought by the production process. And it can improve the impact on the production schedule caused by frequent chip replacement, shorten the product delivery cycle, and improve customer satisfaction.
[0053] In some embodiments, step S102 determines the target evaluation parameter based on the target calibration parameter and the initial calibration parameter, which may include: calculating the target absolute value of the difference between the target calibration parameter and the initial calibration parameter, and determining the target absolute value as the target evaluation parameter.
[0054] By calculating the difference between the target calibration parameter and the initial calibration parameter, and then taking the absolute value of the difference (i.e., the target absolute value) as the target evaluation parameter, the target evaluation parameter for evaluating the difference between the two can be accurately obtained.
[0055] Of course, in other embodiments, other methods can also be used to determine the target evaluation parameter. For example, the target evaluation parameter can be obtained through an empirical value table of the difference between the target calibration parameter and the initial calibration parameter.
[0056] In some embodiments, calculating the target absolute value of the difference between the target calibration parameter and the initial calibration parameter, and determining the target absolute value as the target evaluation parameter includes:
[0057] Calculate the first absolute value of the difference between the frequency offset parameter in the target calibration parameter and the initial frequency offset parameter in the initial calibration parameter, and the target evaluation parameter includes the first absolute value;
[0058] The target evaluation parameter meets the evaluation condition, including: the first absolute value does not exceed the first threshold range.
[0059] In this embodiment, the target calibration parameter may include a frequency offset parameter, which is used to record the frequency offset amount between the transmitted signal and the received signal. The frequency offset parameter refers to the amplitude of the frequency swing of the frequency modulation wave, generally referring to the maximum frequency deviation, which affects the spectral bandwidth of the frequency modulation wave. It can be understood that frequency offset is a unique phenomenon in frequency modulation waves, referring to the offset of a fixed frequency modulation wave frequency to both sides. A frequency modulation wave is a form of electromagnetic wave and a tool for transmitting signals.
[0060] The frequency offset parameter is one of the main calibration parameters of the chip, and the initial calibration parameter also includes the initial frequency offset parameter. When calculating the target evaluation parameter, it can be obtained by calculating the difference between the frequency offset parameter and the initial frequency offset parameter and calculating the first absolute value of this difference. It can be understood that the target evaluation parameter may include at least one parameter, and the first absolute value may be one of the target evaluation parameters.
[0061] The evaluation condition includes the first threshold range for the frequency offset parameter. When the first absolute value is within the first threshold range, it is determined that the chip meets the usage requirements. Through the frequency offset parameter and the initial frequency offset parameter, it is possible to more accurately evaluate whether the chip can be reused.
[0062] In some embodiments, calculating the target absolute value of the difference between the target calibration parameter and the initial calibration parameter and determining the target absolute value as the target evaluation parameter may further include:
[0063] Calculate the second absolute value of the difference between the power gain offset parameter in the target calibration parameter and the initial power gain offset parameter in the initial calibration parameter, and the target evaluation parameter includes the second absolute value;
[0064] The target evaluation parameter meets the evaluation condition, including: the first absolute value does not exceed the first threshold range and the second absolute value does not exceed the second threshold range.
[0065] In this embodiment, the target calibration parameter may include a power gain offset parameter, which is used to record the transmitted power gain offset amount. Power gain refers to the ratio of the output power to the input power in a circuit or system and is used to measure the ability of the circuit or system to enhance the input signal. The power gain offset parameter is used to characterize the offset of the power gain.
[0066] The power gain offset parameter is one of the main calibration parameters of the chip, and the initial calibration parameters also include the initial power gain offset parameter. When calculating the target evaluation parameter, it can be obtained by the difference between the power gain offset parameter and the initial power gain offset parameter, and calculating the second absolute value of this difference. It can be understood that the target evaluation parameter can include at least one parameter, and the second absolute value can be one of the target evaluation parameters.
[0067] The evaluation conditions include a first threshold range for the frequency offset parameter and a second threshold range for the power gain offset parameter. When the first absolute value is within the first threshold range and the second absolute value is within the second threshold range, it is determined that the chip meets the usage requirements.
[0068] The chip's reusability can be evaluated more accurately through the frequency offset parameter and the power gain offset parameter.
[0069] In some embodiments, method 100 may further include:
[0070] Determine the first threshold range based on the standard frequency offset range and the first safety factor, where the first safety factor is a value greater than 0 and less than 1;
[0071] Determine the second threshold range based on the standard power gain offset range and the second safety factor, where the second safety factor is a value greater than 0 and less than 1.
[0072] In this embodiment, the first safety factor is the reference coefficient of the standard frequency offset range, which can be a number less than 1. For example, it can be 0.2, 0.5, 0.8, etc.
[0073] It can be understood that the standard frequency offset range can be the standard range of the chip's frequency offset. For example, the standard frequency offset range is [-10, 10], and the first safety factor is 0.5. The endpoint values of this range interval can be reduced based on the first safety factor. For example, multiply the right endpoint of the range interval by the first safety factor, multiply 10 by 0.5, as the right endpoint of the first threshold range, and the left endpoint takes the value 0, so as to obtain the first threshold range [0, 5].
[0074] The second safety factor is the reference coefficient of the standard power gain offset range, which can be a number less than 1. For example, it can be 0.2, 0.5, 0.8, etc. The first safety factor and the second safety factor can be different or the same.
[0075] It can be understood that the standard power gain offset range can be the standard range of the power gain offset of the chip. For example, the standard power gain offset range is [-2, 2], and the second safety factor is 0.5. The endpoint values of this range interval can be reduced based on the second safety factor. For example, multiply the right endpoint of the range interval by the second safety factor, multiply 2 by 0.5, as the right endpoint of the second threshold range, and take the left endpoint value as 0, thus obtaining the second threshold range [0, 1].
[0076] In this embodiment, the value ranges of the standard frequency offset range and the standard power gain offset range can vary according to different chip manufacturers, etc. For example, in one embodiment, the standard power gain offset range is [-1, 1].
[0077] Through the first safety factor and the second safety factor above, available chips can be screened with more stringent evaluation conditions, further ensuring the usage effect of the chips.
[0078] In other embodiments, the calibration parameters can also include rate parameters, temperature parameters, etc. The rate parameters are used to characterize the data transmission rate, and the temperature parameters are used to characterize the operating temperature of the chip.
[0079] In some embodiments, calculating the target absolute value of the difference between the target calibration parameter and the initial calibration parameter and determining the target absolute value as the target evaluation parameter may further include: calculating the third absolute value of the difference between the rate parameter in the target calibration parameter and the initial rate parameter in the initial calibration parameter, and the target evaluation parameter includes the third absolute value.
[0080] The target evaluation parameter meeting the evaluation conditions includes: the first absolute value not exceeding the first threshold range, the second absolute value not exceeding the second threshold range, and the third absolute value not exceeding the third threshold range.
[0081] In other embodiments, calculating the target absolute value of the difference between the target calibration parameter and the initial calibration parameter and determining the target absolute value as the target evaluation parameter may further include: calculating the third absolute value of the difference between the rate parameter in the target calibration parameter and the initial rate parameter in the initial calibration parameter, calculating the fourth absolute value of the difference between the temperature parameter in the target calibration parameter and the initial temperature parameter in the initial calibration parameter, and the target evaluation parameter includes the third absolute value and the fourth absolute value.
[0082] The target evaluation parameter meeting the evaluation conditions includes: the first absolute value not exceeding the first threshold range, the second absolute value not exceeding the second threshold range, the third absolute value not exceeding the third threshold range, and the fourth absolute value not exceeding the fourth threshold range.
[0083] In some embodiments, method 100 further includes: when the remaining space in the target storage area is greater than or equal to the storage space of the target calibration parameter, writing the target calibration parameter into the remaining space in the target storage area.
[0084] In this embodiment, when the remaining space in the target storage area is greater than or equal to the storage space of the target calibration parameter, it indicates that the target calibration parameter can be written into the target storage area. At this time, the target calibration parameter can be directly written into the target storage area, ensuring the accuracy of the chip performance parameters.
[0085] In addition, when the remaining space in the target storage area is less than the storage space of the target calibration parameter and the target evaluation parameter does not meet the evaluation condition, it indicates that the chip does not meet the usage requirements and is a defective chip. At this time, a new chip needs to be replaced.
[0086] Figure 2 is a schematic flowchart of a chip detection method provided by an embodiment of the present disclosure; please refer to Figure 2 In this embodiment, a chip detection method is provided. Taking a Wi-Fi chip as an example of the chip, this method can improve the secondary utilization rate of Wi-Fi chips of products on the production line, and the method has high feasibility and reliability. The method provided in this embodiment is applicable to products that need to write target calibration parameters into the efuse (target storage area) of the Wi-Fi chip.
[0087] The chip detection method includes the following steps S201 to step S210:
[0088] Step S201, obtain the target calibration parameter, and determine the space required for writing the target calibration parameter into the efuse, that is, the storage space of the target calibration parameter, which can be denoted as need_free_space.
[0089] Step S202, check the remaining space of the efuse (target storage area), and read the current remaining space of the efuse inside the Wi-Fi chip, which can be denoted as free_space (remaining space).
[0090] Step S203, judge the remaining space of the efuse, and judge whether free_space is greater than or equal to need_free_space (the storage space of the target calibration parameter). If so, execute step S204. If free_space < need_free_space, execute step S206.
[0091] Step S204, if free_space >= need_free_space, directly write the target calibration parameter into the efuse space (target storage area).
[0092] Step S205: Send a first prompt message indicating that the chip meets the usage requirements to the user terminal.
[0093] Step S206: Read the initial calibration parameters in the efuse. Read the existing efuse data (initial calibration parameters) in the current Wi-Fi chip, and record them as hw_freq_efuse and hw_txpower_efuse according to the initial frequency offset parameter and the initial power gain offset parameter respectively.
[0094] The target calibration parameters can also include freq_efuse (frequency offset parameter) and txpower_efuse (power gain offset parameter). freq_efuse: The efuse data used to record the frequency offset between the transmitted signal and the received signal. txpower_efuse: The efuse data used to record the power gain offset of the transmitted power.
[0095] Step S207: Determine the target evaluation parameters, calculate the first absolute value of the difference between freq_efuse in the target calibration parameters of the Wi-Fi chip and hw_freq_efuse in the initial calibration parameters, Δfreq_efuse = |freq_efuse - hw_freq_efuse|.
[0096] Calculate the second absolute value of the difference between txpower_efuse in the target calibration parameters of the Wi-Fi chip and hw_txpower_efuse in the initial calibration parameters, Δtxpower_efuse = |txpower_efuse - hw_txpower_efuse|. The target evaluation parameters include the first absolute value and the second absolute value.
[0097] Step S208: Determine whether the target evaluation parameters meet the evaluation conditions. For example, determine whether Δfreq_efuse < 5 and Δtxpower_efuse < 1. If both of these conditions are met, this Wi-Fi chip can continue to be used and step S205 can be executed. Otherwise, only the Wi-Fi chip can be replaced and step S209 is executed.
[0098] Step S209: Send a second prompt message indicating that the chip does not meet the usage requirements to the user terminal.
[0099] Step S210: End.
[0100] It can be understood that the standard range of frequency offset is between [-10, 10]. Since the chips for which Δfreq_efuse needs to be converted are the chips with the efuse fully written. To prevent the situation where the difference is close to the critical value, a range that is more stringent than the normal standard range can be adopted. For example, the range can be reduced by half through the first safety factor (0.5). Therefore, the first frequency threshold range can be taken as [0, 5].
[0101] Because the standard range of power gain offset usually adopts the range of [-2, 2]. Similarly, taking the second safety factor as 0.5, the second threshold range is [0, 1].
[0102] It can be understood that when retesting the Wi-Fi chip, it is inevitable that the calibration parameters need to be written into the efuse two or three times. If the calibration parameters are inconsistent with the previous calibration parameters and the efuse space is full, an error will surely occur. That is, the need to replace the Wi-Fi chip is triggered, which will further lead to an increase in cost. The method provided in this embodiment can reduce the scrap rate of Wi-Fi chips during the production process and improve the production yield. By implementing this solution, the production line can effectively manage and optimize the use of Wi-Fi chips, improve their reuse rate, thereby reducing costs and improving resource utilization efficiency.
[0103] Figure 3 It is a schematic block diagram of a device provided in another embodiment of the present disclosure. Please refer to Figure 3 The embodiment of the present disclosure provides a chip detection device 300, including the following units 301 to 303:
[0104] An acquisition unit 301, configured to acquire the initial calibration parameters stored in the target storage area when the remaining space of the target storage area is less than the storage space of the target calibration parameters, where the target storage area is a non-volatile storage area in the chip, the target calibration parameters are the calibration parameters obtained by performing non-first calibration on the chip, and the initial calibration parameters are the calibration parameters of the chip written into the target storage area most recently;
[0105] A first determination unit 302, configured to determine a target evaluation parameter based on the target calibration parameter and the initial calibration parameter;
[0106] A second determination unit 303, configured to determine that the chip meets the usage requirements when the target evaluation parameter meets the evaluation conditions.
[0107] In some embodiments, the first determination unit 302 is further configured to: calculate the target absolute value of the difference between the target calibration parameter and the initial calibration parameter, and determine the target absolute value as the target evaluation parameter.
[0108] In some embodiments, the first determination unit 302 is further configured to:
[0109] Calculate a first absolute value of the difference between the frequency offset parameter in the target calibration parameter and the initial frequency offset parameter in the initial calibration parameter, where the target evaluation parameter includes the first absolute value;
[0110] The target evaluation parameter meets the evaluation condition, including: the first absolute value does not exceed the first threshold range.
[0111] In some embodiments, the first determination unit 302 is further configured to:
[0112] Calculate a second absolute value of the difference between the power gain offset parameter in the target calibration parameter and the initial power gain offset parameter in the initial calibration parameter, where the target evaluation parameter includes the second absolute value;
[0113] The target evaluation parameter meets the evaluation condition, including: the first absolute value does not exceed the first threshold range and the second absolute value does not exceed the second threshold range.
[0114] In some embodiments, the apparatus 300 further includes: a third determination unit, and the third determination unit is configured to:
[0115] Determine the first threshold range based on the standard frequency offset range and the first safety factor, where the first safety factor is a value greater than 0 and less than 1;
[0116] Determine the second threshold range based on the standard power gain offset range and the second safety factor, where the second safety factor is a value greater than 0 and less than 1.
[0117] In some embodiments, the apparatus 300 further includes: a first storage unit, configured to write the target calibration parameter into the remaining space of the target storage area when the remaining space of the target storage area is greater than or equal to the storage space of the target calibration parameter.
[0118] For the specific functions and examples of the modules and sub - modules of the apparatus in the embodiments of the present disclosure, reference may be made to the relevant descriptions of the corresponding steps in the above - mentioned method embodiments, which will not be elaborated herein.
[0119] The embodiments of the present disclosure provide an electronic device, including:
[0120] At least one processor; and
[0121] A memory communicatively connected to the at least one processor; wherein,
[0122] The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method of any one of the above - mentioned embodiments.
[0123] An embodiment of the present disclosure provides a non-transitory computer-readable storage medium storing computer instructions, where the computer instructions are used to cause a computer to execute the method according to any one of the above embodiments.
[0124] Figure 4 is a block diagram of an electronic device for implementing the chip detection method of the embodiments of the present disclosure. As Figure 4 shown, the electronic device includes: a memory 410 and a processor 420. A computer program that can run on the processor 420 is stored in the memory 410. The number of the memory 410 and the processor 420 can be one or more. The memory 410 can store one or more computer programs. When the one or more computer programs are executed by the electronic device, the electronic device executes the method provided in the above method embodiments. The electronic device may further include: a communication interface 430, configured to communicate with external devices and perform data interaction and transmission.
[0125] If the memory 410, the processor 420, and the communication interface 430 are implemented independently, the memory 410, the processor 420, and the communication interface 430 can be connected to each other through a bus and complete communication therebetween. The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. For the sake of convenience of representation, Figure 4 only a thick line is shown in the figure, but it does not mean that there is only one bus or one type of bus.
[0126] Optionally, in a specific implementation, if the memory 410, the processor 420, and the communication interface 430 are integrated on a chip, the memory 410, the processor 420, and the communication interface 430 can complete communication therebetween through an internal interface.
[0127] It should be understood that the above-mentioned processor may be a Central Processing Unit (CPU), or other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc. It is worth noting that the processor may be a processor that supports the Advanced RISC Machines (ARM) architecture.
[0128] Further, optionally, the above-mentioned memory may include a read-only memory and a random access memory, and may also include a non-volatile random access memory. The memory may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may include a Read-Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically EPROM (EEPROM), or a flash memory. The volatile memory may include a Random Access Memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available. For example, Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Double Data Date SDRAM (DDR SDRAM), Enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), and Direct RAMBUS RAM (DR RAM).
[0129] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present disclosure are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (such as coaxial cable, optical fiber, Digital Subscriber Line (DSL)) or wireless (such as infrared, Bluetooth, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer, or a data storage device such as a server or data center that includes one or more integrated available media. The available medium can be a magnetic medium (such as a floppy disk, hard disk, magnetic tape), an optical medium (such as a Digital Versatile Disc (DVD)), or a semiconductor medium (such as a Solid State Disk (SSD)), etc. It should be noted that the computer-readable storage medium mentioned in the present disclosure can be a non-volatile storage medium, in other words, a non-transitory storage medium.
[0130] Those of ordinary skill in the art can understand that all or part of the steps for implementing the above embodiments can be completed by hardware, or can be completed by a program instructing relevant hardware. The program can be stored in a computer-readable storage medium, and the storage medium mentioned above can be a read-only memory, a magnetic disk, an optical disc, etc.
[0131] In the description of the embodiments of the present disclosure, the descriptions referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.
[0132] In the description of the embodiments of the present disclosure, unless otherwise specified, " / " means "or". For example, A / B may mean A or B. The "and / or" herein is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B may mean: A exists alone, A and B exist simultaneously, and B exists alone.
[0133] In the description of the embodiments of the present disclosure, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present disclosure, unless otherwise specified, "a plurality of" means two or more.
[0134] The foregoing are only exemplary embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included within the protection scope of the present disclosure.
Claims
1. A chip detection method, comprising: When the remaining space in the target storage area is less than the storage space of the target calibration parameter, obtaining the initial calibration parameter stored in the target storage area, where the target storage area is a non-volatile storage area in the chip, the target calibration parameter is the calibration parameter obtained by performing non-first calibration on the chip, and the initial calibration parameter is the calibration parameter of the chip that was most recently written into the target storage area; Determining a target evaluation parameter based on the target calibration parameter and the initial calibration parameter; When the target evaluation parameter meets the evaluation condition, determining that the chip meets the usage requirements.
2. The method according to claim 1, wherein Determining a target evaluation parameter based on the target calibration parameter and the initial calibration parameter, comprising: Calculating a target absolute value of the difference between the target calibration parameter and the initial calibration parameter, and determining the target absolute value as the target evaluation parameter.
3. The method according to claim 2, wherein, Calculating a target absolute value of the difference between the target calibration parameter and the initial calibration parameter, and determining the target absolute value as the target evaluation parameter, comprising: Calculating a first absolute value of the difference between the frequency offset parameter in the target calibration parameter and the initial frequency offset parameter in the initial calibration parameter, and the target evaluation parameter includes the first absolute value; The target evaluation parameter meets the evaluation condition, including: the first absolute value does not exceed the first threshold range.
4. The method according to claim 3, wherein Calculating a target absolute value of the difference between the target calibration parameter and the initial calibration parameter, and determining the target absolute value as the target evaluation parameter, further comprising: Calculating a second absolute value of the difference between the power gain offset parameter in the target calibration parameter and the initial power gain offset parameter in the initial calibration parameter, and the target evaluation parameter includes the second absolute value; The target evaluation parameter meets the evaluation condition, including: the first absolute value does not exceed the first threshold range and the second absolute value does not exceed the second threshold range.
5. The method according to claim 4, further comprising: Determining the first threshold range based on a standard frequency offset range and a first safety factor, where the first safety factor is a value greater than 0 and less than 1; Determining the second threshold range based on a standard power gain offset range and a second safety factor, where the second safety factor is a value greater than 0 and less than 1.
6. The method according to claim 1, further comprising: When the remaining space in the target storage area is greater than or equal to the storage space of the target calibration parameter, writing the target calibration parameter into the remaining space of the target storage area.
7. A chip detection device, comprising: An acquisition unit, configured to obtain the initial calibration parameter stored in the target storage area when the remaining space in the target storage area is less than the storage space of the target calibration parameter, where the target storage area is a non-volatile storage area in the chip, the target calibration parameter is the calibration parameter obtained by performing non-first calibration on the chip, and the initial calibration parameter is the calibration parameter of the chip that was most recently written into the target storage area; A first determination unit, configured to determine a target evaluation parameter based on the target calibration parameter and the initial calibration parameter; A second determination unit, configured to determine that the chip meets the usage requirements when the target evaluation parameter meets the evaluation conditions.
8. The device according to claim 7, wherein The first determination unit is further configured to: Calculate a target absolute value of the difference between the target calibration parameter and the initial calibration parameter, and determine the target absolute value as the target evaluation parameter.
9. The device according to claim 8, wherein The first determination unit is further configured to: Calculate a first absolute value of the difference between the frequency offset parameter in the target calibration parameter and the initial frequency offset parameter in the initial calibration parameter, where the target evaluation parameter includes the first absolute value; The target evaluation parameter meets the evaluation conditions, including: the first absolute value does not exceed a first threshold range.
10. The apparatus according to claim 9, wherein, The first determination unit is further configured to: Calculate a second absolute value of the difference between the power gain offset parameter in the target calibration parameter and the initial power gain offset parameter in the initial calibration parameter, where the target evaluation parameter includes the second absolute value; The target evaluation parameter meets the evaluation conditions, including: the first absolute value does not exceed the first threshold range and the second absolute value does not exceed a second threshold range.
11. The apparatus according to claim 10, further comprising: A third determination unit, where the third determination unit is configured to: Determine the first threshold range based on a standard frequency offset range and a first safety factor, where the first safety factor is a value greater than 0 and less than 1; Determine the second threshold range based on a standard power gain offset range and a second safety factor, where the second safety factor is a value greater than 0 and less than 1.
12. The device according to any one of claims 7-11, further comprising: A first storage unit, configured to write the target calibration parameter into the remaining space of the target storage area when the remaining space of the target storage area is greater than or equal to the storage space of the target calibration parameter.
13. An electronic device, comprising: At least one processor; And A memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method according to any one of claims 1-6.
14. A non-transitory computer-readable storage medium storing computer instructions, wherein, The computer instructions are used to cause the computer to execute the method according to any one of claims 1-6.