Test method for evaluating Flash reliability in SOC

Abstract

A test method for evaluating Flash reliability in an SOC (system on chip) relates to the technical field of SOC memories, and comprises the following steps of: accessing an external clock into an SOC chip as a synchronous clock for operating a Flash memory unit; setting an initial value of operation time; carrying out one-time operation on at least one block of the Flash storage unit; reading data; and judging whether the read data meets a preset condition or not, if not, adjusting the operation time to perform operation again, and if yes, obtaining the boundary time of the Flash block of the test. By dynamically adjusting the erasing, writing and reading time parameters, the reliability of the Flash memory and the boundary data of erasing, writing and reading can be accurately measured, and the reliability of the Flash memory can be accurately evaluated.

Description

Technical Field

[0001] The present invention relates to the technical field of SOC memory, and particularly to a test method for evaluating the reliability of Flash in SOC. Background Art

[0002] The non-volatile storage unit Flash, as the core data storage carrier of SOC, the stored data directly affects key operations such as the performance of analog units in the chip, the loading of system configuration parameters, and the normal startup of programs. Therefore, the reliability of Flash memory is the cornerstone of the overall chip reliability evaluation, which is directly related to the functional integrity of the chip.

[0003] However, due to process manufacturing deviations, the chip working in a high-temperature environment for a long time, or the Flash being erased and written multiple times, etc., the conversion between the two states ("1" state and "0" state) of the Flash storage unit becomes slower, resulting in delay faults, and consequences such as data loss or errors, function failures, and shortened lifespan, which have a serious impact on the chip itself and its terminal applications. For example, a Flash storage unit failure causes a mobile phone / tablet to fail to start or start frequently.

[0004] Traditional reliability verification relies on machine testing or aging testing. However, the erase and write times of these tests are fixed, and they cannot simulate dynamic faults caused by process deviations or environmental changes. Moreover, the test cycle is long and the cost is high. Therefore, for the Fabless operation mode, a low-cost and highly flexible test method is needed to accurately evaluate the reliability of the Flash memory by dynamically adjusting the erase and write time parameters.

[0005] Existing patents CN201410589708.5 "A screening test method for flash memory reliability", CN202310182421.X "A reliability test and prediction method for flash memory for long-term storage", CN202211339013.2 "A reliability test method and reliability test device for flash memory". In the above patents, the erase and write times in the test process are fixed, and none of them involve the technical solution of performing relevant tests by dynamically adjusting the erase and write time parameters. Summary of the Invention

[0006] The purpose of the present invention is to propose a test method for evaluating the reliability of Flash in SOC. By dynamically adjusting the erase, write, and read time parameters, under the condition of limited test resources, accurately determine the reliability of the Flash memory and the boundary data of erase, write, and read, and achieve an accurate evaluation of the reliability of the Flash memory.

[0007] The technical solution adopted by the present invention to achieve its invention purpose is a test method for evaluating the reliability of Flash in SOC, including the following steps:

[0008] (1) Connect an external clock to the SOC chip and use it as the synchronous clock for operating the Flash memory cells. The operations include erasing, writing, and reading.

[0009] (2) Set the initial values of the operation times. Specifically, when testing the erase boundary time, write boundary time, and read boundary time respectively, the initial values of the erase, write, and read times need to be set respectively.

[0010] (3) Perform an operation on at least one block of the Flash memory cells.

[0011] (4) Read the data on the at least one block.

[0012] (5) Determine whether the read data meets the preset conditions. If not, adjust the operation time and go to step (3). If so, obtain the boundary time of the Flash block for this test.

[0013] Preferably, the initial values of the erase, write, and read operation times set in step (2) are respectively less than the erase, write, and read times recommended by the foundry for the Flash memory cells.

[0014] As a further preferred solution, when testing the erase boundary time, the "performing an operation" in step (3) is specifically erasing data, the "reading data" in step (4) is specifically reading data normally, that is, reading according to the recommended read time of the foundry for the Flash memory cells, the "preset conditions" in step (5) are specifically all "1", and the "adjusting the operation time" is increasing the erase time.

[0015] As another further preferred solution, when testing the write boundary time, the "performing an operation" in step (3) is specifically writing the target value, the "reading data" in step (4) is specifically reading data normally, that is, reading according to the recommended read time of the foundry for the Flash memory cells, the "preset conditions" in step (5) are specifically equal to the written target value, and the "adjusting the operation time" is increasing the write time.

[0016] As still another further preferred solution, when testing the read boundary time, the "performing an operation" in step (3) is specifically writing the target value, the "reading data" in step (4) is specifically reading data according to the set read time, the "preset conditions" in step (5) are specifically equal to the written target value, and the "adjusting the operation time" is increasing the read time.

[0017] The beneficial effects of the present invention are:

[0018] By dynamically adjusting the erasure, writing, and reading time parameters, the present invention can accurately determine the boundary time data of Flash memory erasure, writing, and reading at low cost under the condition of limited test resources, thereby helping to evaluate the storage period of important internal data of chip products, achieving accurate evaluation of the reliability of Flash memory, and providing a direct basis for process improvement, design reinforcement, and reliability model construction. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 FIG. is a schematic structural diagram of a floating gate MOS device;

[0020] Figure 2 FIG. is a schematic structural diagram of a common NMOS device;

[0021] Figure 3 FIG. is a schematic diagram showing the relationship between the amount of charge transfer and time during the erase / write process of a floating gate MOS device;

[0022] Figure 4 FIG. is a flowchart for testing the erasure boundary time in Embodiment 1 of the present invention;

[0023] Figure 5 FIG. is a flowchart for testing the write boundary time in Embodiment 2 of the present invention;

[0024] Figure 6 FIG. is a flowchart for testing the read boundary time in Embodiment 3 of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] In order to more clearly understand the above objects, features, and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0026] The working principle of a typical single Flash memory cell is as follows:

[0027] The basic storage unit of a Flash memory is a floating gate MOS device (floating gate mos), and its structure is different from that of a conventional NMOS device as shown in FIGS. Figure 1 and Figure 2 respectively.

[0028] The floating-gate MOS device has an additional oxide layer and a floating-gate layer compared with the conventional MOS device. There are oxide layers above and below the floating-gate layer. Therefore, under normal pressure and temperature, it is very difficult for electrons to flow in or out. However, under high-voltage conditions, electrons can flow in and out through mechanisms such as tunneling effect. By using external conditions to make electrons be stored or overflow from the floating-gate layer in large quantities, the floating-gate MOS device can have a relatively large / low threshold voltage, enabling the device to represent information of 1 or 0. For example, under the condition of applying 20V to the control gate, electrons are concentrated in the floating-gate layer, and the device obtains a relatively large threshold voltage (referred to as the write operation). During normal use, the gate voltage is only 5V, so the device cannot conduct. If an external voltage of 20V is applied to the substrate and electrons flow out of the floating-gate layer, the device obtains a relatively low threshold voltage (referred to as the erase operation), and a gate voltage of 5V can make the device conduct.

[0029] In the above erase / write process, the duration of the external condition has a direct impact on the amount of electric charge, and the charge transfer amount Q FG has a relationship with the duration t as Figure 3 shown. After a sufficiently long time, the change speed of the electric charge amount will slow down, and the corresponding threshold voltage will also tend to be stable and will not change continuously. Therefore, during erase / write, the erase / write time needs to be properly controlled. If the time is too long, the erase / write of the entire chip will be slow, affecting the efficiency and wasting resources; if the time is too short, the threshold voltage may not reach the expected value, affecting data accuracy.

[0030] In the prior art, the erase / write time parameters of Flash memory are usually given by the foundry in the form of a fixed range. Customers can only design based on these recommended values and cannot know the specific measured boundary data of the erase / write. Due to reasons such as technical secrecy, the foundry will not disclose the measured boundary values of these key parameters. However, these data are crucial for customers to evaluate the long-term reliability of Flash memory. Customers can determine whether the data storage period of the Flash memory cell meets the product life requirements by observing whether there is a significant shift in the erase / write time boundary.

[0031] The present invention connects an external clock to the SOC chip as the high-frequency synchronous clock for erase / write / read, and then dynamically changes the duration of Flash erase / write / read through programming, that is, by configuring a programmable circuit with software to convert the clock signal into a timing control signal, so as to make the erase / write / read time controllable.

[0032] The processes of testing the erase, write, and read boundary times will be described in detail below.

[0033] Embodiment 1

[0034] Figure 4The first specific implementation manner of the test method for evaluating the Flash reliability in the SOC of the present invention is shown, that is, testing the erase boundary time, which includes the following steps:

[0035] (1) Connect an external clock (up to 100 MHZ) to the SOC chip as the synchronous clock for the erase operation of the Flash memory cell;

[0036] (2) Set an initial erase time, and the value of this initial erase time is much less than the recommended erase time of the Flash memory cell to ensure that the Flash memory cell cannot change its state at this initial time;

[0037] (3) Perform an erase operation on one or several blocks of the Flash memory cell;

[0038] (4) Normally read the data in the above area, that is, read according to the recommended read time of the Flash memory cell by the foundry;

[0039] (5) Judge whether the read data is all "1". If not, increase the erase time and go to step (3). If so, obtain the erase boundary time of the Flash block in this test.

[0040] In the above loop working process, at the beginning, because the erase time is not enough, the read data is not all "1" at this time. Repeatedly increase the erase time until the read data is all "1", and one or several blocks of the Flash cell are successfully erased. At this time, the erase time is the erase boundary time of the Flash block.

[0041] Example 2

[0042] Figure 5 The second specific implementation manner of the test method for evaluating the Flash reliability in the SOC of the present invention is shown, that is, testing the write boundary time, which includes the following steps:

[0043] (1) Connect an external clock (up to 100 MHZ) to the SOC chip as the synchronous clock for the write operation of the Flash memory cell;

[0044] (2) Set an initial write time, and the value of this initial write time is much less than the recommended write time of the Flash memory cell to ensure that the Flash memory cell cannot change its state at this initial time;

[0045] (3) Perform a write target value operation on one or several blocks of the Flash memory cell;

[0046] (4) Normally read the data in the above area, that is, read according to the recommended read time of the Flash memory cell by the foundry;

[0047] (5) Determine whether the read data meets the target value written. If not, increase the write time and go to step (3). If so, obtain the write boundary time of the Flash block for this test.

[0048] During the above loop operation, at the beginning, because the write time was insufficient, the read data was not equal to the target value written at this time. The write time was repeatedly increased until the read data was equal to the target value written. One or several blocks of the Flash unit were successfully written, and the write time at this time was the write boundary time of the Flash block.

[0049] Embodiment 3

[0050] Figure 6 Illustrate the third specific implementation manner of the test method for evaluating the Flash reliability in the SOC of the present invention, that is, testing the read boundary time, including the following steps:

[0051] (1) Connect an external clock (up to 100MHZ) to the SOC chip as the synchronous clock for reading the Flash storage unit.

[0052] (2) Set the initial read time, and the value of this initial read time is much less than the recommended read time of the Flash storage unit.

[0053] (3) Perform an operation of writing the target value to one or several blocks of the Flash storage unit.

[0054] (4) Read the data in the above area according to the set read time.

[0055] (5) Determine whether the read data meets the target value written. If not, increase the read time and go to step (3). If so, obtain the read boundary time of the Flash block for this test.

[0056] During the above loop operation, at the beginning, because the read time was insufficient, the read data was not equal to the target value written at this time. The read time was repeatedly increased until the read data was equal to the target value written. One or several blocks of the Flash unit were successfully read, and the read time at this time was the read boundary time of the Flash block.

Claims

1. A test method for evaluating the reliability of Flash in SOC, characterized in that: The following steps are involved: (1) Connecting an external clock to the SOC chip as a synchronous clock for operating the Flash storage unit, including erasing, writing, and reading; (2) setting an initial value of the operation time; (3) performing an operation on at least one block of the Flash storage unit; (4) reading data on the at least one block; (5) Determine whether the read data meets the preset conditions. If not, adjust the operation time and go to step (3). If yes, obtain the boundary time of the Flash block under test.

2. A test method for evaluating Flash reliability in SOC according to claim 1, characterized in that: The initial values ​​of the erase, write, and read operation times set in step (2) are respectively smaller than the erase, write, and read times recommended by the process factory for the Flash storage unit.

3. A test method for evaluating Flash reliability in SOC according to claim 2, characterized in that: When testing the erase boundary time, the operation performed in step (3) is specifically erasing data, the data read in step (4) is specifically reading data normally, the preset conditions in step (5) are specifically all "1", and the adjustment operation time is to increase the erase time.

4. A test method for evaluating Flash reliability in SOC according to claim 2, characterized in that: When testing the write boundary time, the operation performed in step (3) is specifically to write the target value, the data read in step (4) is specifically to read the data normally, the preset condition in step (5) is specifically to be equal to the write target value, and the adjustment operation time is to increase the write time.

5. The test method for evaluating Flash reliability in SOC according to claim 2, characterized in that: When testing the read boundary time, the operation performed in step (3) is specifically to write the target value, the data read in step (4) is specifically to read the data according to the set read time, the preset condition in step (5) is specifically to be equal to the written target value, and the adjustment operation time is to increase the read time.

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