Measurement and control design method for real-time phase of phased-array antenna

Abstract

The invention relates to the technical field of phased-array antenna measurement and control, and discloses a measurement and control design method for the real-time phase of a phased-array antenna, and the method comprises the following steps: converting serial input data into parallel data through a serial-parallel conversion chip; storing the parallel data in a storage register, and controlling the parallel data to be output to a phase shifter for phase adjustment through a trigger signal; and converting parallel data of the phase shifter state into serial data through the parallel-serial conversion chip, and outputting the serial data to the main controller to complete phase state backward reading. According to the invention, the serial-to-parallel conversion chip and the parallel-to-serial conversion chip are used cooperatively, so that the signal transmission process and the wiring structure of the system are simplified. Compared with a complex connection and wiring mode in the prior art, the complexity of the system is greatly reduced, the risk of signal loss and interference is reduced, and the stability and reliability of the system are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of phased array antenna measurement and control, and specifically provides a measurement and control design method for the real-time phase of a phased array antenna. Background Art

[0002] Phased array antenna technology realizes agile beam scanning by controlling the signal phases of each channel. In a phased array antenna, the direction of the beam can be quickly changed by adjusting the phases of each antenna element, thereby achieving directional control without moving the antenna. This technology is widely used in radar, communication, satellite, and other systems with high-precision requirements. For an analog phased array system, the phase change of the signal is usually achieved by a phase shifter. The phase shifter can accurately adjust the phase of each antenna element, and then realize the beam control and scanning of the entire array.

[0003] In a spaceborne phased array antenna system, in addition to realizing real-time beam adjustment, it is also particularly important to telemeter and sense the beam pointing. To ensure that the system can sense and adjust the beam direction in real time, it is necessary to read back the phase shift state of the phase shifter. The read-back function of the phase shifter can help the system monitor the phase information of each channel in real time and make appropriate adjustments according to the actual situation, thereby ensuring the accuracy and stability of the beam pointing.

[0004] Currently, most discrete phase shifter chips do not have the real-time read-back function and lack real-time feedback on the phase shifter state. This poses a great challenge to the spaceborne phased array antenna system in terms of beam pointing sensing. In traditional technologies, the system usually relies on complex wiring structures and manual detection or periodic calibration to obtain phase information. However, this method cannot meet the requirements of rapid beam changes and is easily affected by signal loss and interference, resulting in the inability to obtain accurate phase shifter states in real time. Summary of the Invention

[0005] Aiming at the deficiencies of the prior art, the present invention provides a measurement and control design method for the real-time phase of a phased array antenna, which solves the problems of the traditional phase shifter being unable to perform real-time read-back and the difficulty in beam pointing sensing.

[0006] To achieve the above objectives, the present invention is realized through the following technical solutions: A measurement and control design method for the real-time phase of a phased array antenna includes the following steps: Convert serial input data into parallel data through a serial-to-parallel conversion chip; Store the parallel data in a storage register, and control the output of the parallel data to the phase shifter for phase adjustment through a trigger signal; Convert the parallel data of the phase shifter state into serial data through a parallel-to-serial conversion chip and output it to the main controller to complete the phase state read-back.

[0007] Preferably, the serial-to-parallel conversion chip includes a shift register for converting serial data into parallel data, and the output end of the shift register is connected to a storage register.

[0008] Preferably, the trigger signal is sent by a main controller, and the main controller controls the serial-to-parallel conversion chip through the trigger signal to convert parallel data into serial data and output it to the main controller.

[0009] Preferably, the serial-to-parallel conversion chip converts parallel input data into serial data through an internal shift register and outputs the serial data through the Qh port.

[0010] Preferably, the serial-to-parallel conversion chip and the parallel-to-serial conversion chip are connected in a cascaded manner, and the cascaded manner is used to expand the system capacity.

[0011] Preferably, the length of the transmission path of the signal from the serial-to-parallel conversion chip to the parallel-to-serial conversion chip and the propagation speed of the signal are optimized based on a transmission delay minimization control algorithm.

[0012] Preferably, during the data transmission of the signal from the serial-to-parallel conversion chip to the parallel-to-serial conversion chip, the relationship between the signal bandwidth and the signal period is optimized through the Nyquist theorem to maximize the signal transmission rate and bandwidth utilization.

[0013] Preferably, the readback data of the phase state is encoded by an error correction method, and the encoding methods include low-density parity-check code and convolutional coding.

[0014] The present invention provides a measurement and control design method for the real-time phase of a phased array antenna. It has the following beneficial effects: 1. By introducing the combined use of a serial-to-parallel conversion chip and a parallel-to-serial conversion chip, the present invention simplifies the signal transmission process and the wiring structure of the system. Compared with the complex connection and wiring methods in the prior art, the present invention greatly reduces the complexity of the system, reduces the risk of signal loss and interference, and improves the stability and reliability of the system.

[0015] 2. Through an optimization method based on a transmission delay minimization control algorithm, the present invention effectively reduces the transmission delay of the signal. In the prior art, delay often affects the response speed of the system, while the present invention ensures the accurate realization of real-time requirements by optimizing the transmission path and propagation speed, ensuring the fast response and efficient operation of the system.

[0016] 4. The error correction scheme of the present invention combines low-density parity-check codes and convolutional coding, significantly improving the reliability of data transmission. Compared with traditional simple error detection methods, the present invention can correct errors more precisely during transmission, reduce errors caused by transmission noise or signal interference, and ensure data accuracy and system efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic flowchart of the method of the present invention; DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the specification of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0019] To better understand the present invention, the above content will be described in detail below in conjunction with specific embodiments.

[0020] Please refer to the attached Figure 1 , the embodiment of the present invention provides a measurement and control design method for the real-time phase of a phased array antenna, including the following steps: Convert serial input data into parallel data through a serial-to-parallel conversion chip; In this embodiment, the serial-to-parallel conversion chip (Serial-to-Parallel-Converter) is used to convert the input serial data stream into a parallel data stream for subsequent processing. The serial-to-parallel conversion chip mainly includes multiple shift registers and corresponding control circuits, which can shift each serial input data bit in sequence to the parallel register and control the output through a trigger signal. This process effectively solves the problem of insufficient bandwidth in serial data transmission, especially in multi-channel and real-time processing systems, and can achieve parallel processing to improve the data processing ability of the system.

[0021] Specifically, in this embodiment, the working principle of the serial-to-parallel conversion chip is to convert each bit of the serial input data into parallel output through the shift register. The serial input data enters through the SER input port of the chip, undergoes the displacement operation of the shift register, and finally is output in parallel to the storage register. This operation requires the cooperation of an external clock signal and a control signal to ensure the order and integrity of the data. The storage register temporarily stores the parallel data and controls the output timing of the parallel data according to the trigger signal of the main controller.

[0022] In a possible implementation, by cascading multiple shift registers, the serial-to-parallel conversion chip can support parallel processing of multiple data channels. Each data channel corresponds to a group of shift registers, and different channels are selected for data processing through control signals, thereby supporting complex multi-channel data transmission. This method can effectively improve the scalability of the system and is applicable to real-time data readback in large-scale phased array antenna systems.

[0023] In this process, the depth and number of each shift register determine the number of parallel data bits for conversion. Generally speaking, the more bits the register has, the larger the amount of parallel data it can support, so that more data can be processed simultaneously and the signal transmission delay can be reduced. For example, if an N-bit shift register is used, N-bit parallel data can be output after each conversion. At this time, the operating frequency of the shift register should match the frequency of the external clock signal to ensure that there are no timing errors during the data conversion process.

[0024] As an option, in some embodiments, the depth of the shift register can be flexibly adjusted according to the actual needs of the system. If high real-time performance is required, a smaller depth of the shift register may be needed to reduce the data transmission delay; if the system has a large amount of data, the number of bits of the shift register can be increased to improve the transmission rate of parallel data.

[0025] Specifically, the bit width and clock frequency of the shift register meet the requirements of the data transmission rate. In practical applications, the clock frequency of the shift register is determined by the system requirements. If high-speed data transmission is needed, a high-frequency clock can be used to speed up the data processing. On the contrary, if the real-time requirement for data processing is low, a lower clock frequency can be used to reduce the system power consumption.

[0026] Furthermore, according to the required number of parallel data bits and transmission rate, different technical solutions can be used for the design of the shift register. For example, in some high-frequency and high-speed data transmission systems, using high-speed shift registers and low-delay clock circuits can ensure fast data conversion and avoid excessive delay affecting the system performance.

[0027] Among them, according to the working principle of the serial-to-parallel conversion chip, after the serial data is converted into parallel data, its transmission rate should satisfy the following relationship: R parallel =R serial ×N; where, R serial is the transmission rate of the serial data (bits per second, bps); R parallel is the transmission rate of the parallel data (bits per second, bps); N is the number of bits of the shift register (i.e., the number of parallel data bits).

[0028] In some embodiments, by adjusting the number of bits N and the transmission rate R of the shift register serial , the most suitable configuration can be selected according to different application scenarios. For example, in a low-speed system, using a smaller number of shift register bits can reduce system power consumption, while in a high-speed system, the number of bits can be increased to enhance the parallel data processing ability.

[0029] Therefore, the configuration of the serial-to-parallel conversion chip and the shift register can be adjusted according to the requirements of the specific system to meet the data transmission requirements in different application scenarios. At the same time, by optimizing the design of the shift register, the real-time performance and stability of data conversion can be ensured.

[0030] Store the parallel data in the storage register and control the output of the parallel data to the phase shifter for phase adjustment through a trigger signal; In this embodiment, the storage register is used to temporarily store the parallel data converted by the serial-to-parallel conversion chip. This storage method not only helps to alleviate the bottleneck problem brought by the serial data stream, but also ensures that data will not be lost, disordered or delayed during the data processing process. The storage register saves the parallel data to each data bit of the register, ensuring that all data bits are output in sequence at the appropriate time. The output control of the storage register depends on the trigger signal, and through this signal, the timing of data output can be accurately controlled, so as to ensure that the data can be transmitted to the phase shifter in the corresponding order to achieve precise phase adjustment of the phased array antenna.

[0031] Specifically, in this embodiment, the storage register receives the parallel data from the serial-to-parallel conversion chip and stores it in the internal register. Each data bit inside the register corresponds to the status information of a phase shifter. After the data is stored, it can be output through the trigger signal issued by the main controller. The role of the trigger signal is to control when and how to output the data in the storage register in sequence, thereby adjusting the phase state of the phase shifter. The trigger signal plays a crucial role in the operation of the entire system, and its accuracy and real-time performance directly affect the state adjustment effect of the phase shifter and the overall performance of the system.

[0032] In some embodiments, the trigger signal may be generated by the system clock signal. It can be a timed pulse signal, which can ensure that the output of the storage register is synchronized with the system clock, thus avoiding data loss or misalignment. In addition, the frequency and amplitude of the trigger signal can be flexibly adjusted according to the operation requirements of the phase shifter. The design of the control signal can be optimized according to the real-time requirements of the system. For example, in a high-frequency, low-latency system, a trigger signal with a faster frequency may be required, while in a low-speed system, a slower trigger signal frequency is sufficient to meet the requirements.

[0033] As an option, the frequency of the trigger signal is highly correlated with the phase adjustment frequency of the phase shifter. To ensure the stable operation of the system, precise timing control is usually required to ensure the smooth output of data and the real-time adjustment of the phase. The trigger signal usually adopts a pulse signal of high level or low level, which controls the output timing of each data bit of the storage register to ensure the order and correctness of the data. For example, in actual operation, the trigger signal can activate a group of register data outputs in each clock cycle, so as to realize the phase adjustment of the system in each cycle.

[0034] In another possible implementation, the capacity and bit width of the storage register can be adjusted according to the different requirements of the system. The width of each storage register bit determines the amount of data output each time, while the capacity of the storage register determines the amount of data that can be temporarily stored. In a system that needs to process a large amount of data, it may be necessary to increase the depth or bit width of the storage register to process more data bits simultaneously and reduce the system response delay.

[0035] Specifically, in a high-speed system, the phase adjustment of the phase shifter is required to be performed frequently. Therefore, the frequency of the trigger signal needs to be precisely synchronized with the clock signal of the system to ensure that the adjustment of the phase shifter can be consistent with the data transmission rate. In this case, the reading rate of the storage register, the generation frequency of the trigger signal, and the adjustment frequency of the phase shifter need to be precisely matched to ensure the real-time performance of data processing and phase adjustment.

[0036] In some embodiments, the design of the storage register can also integrate a fault detection and verification mechanism. These mechanisms are used to ensure that no errors occur during the storage and output of data, avoiding errors caused by external noise, system failures, or inaccurate timing. The verification mechanism can ensure that the output data is consistent with the input data, and the synchronization of the trigger signal is guaranteed. The integration of these functions can further improve the reliability and stability of the system, especially in some high-frequency and complex environments where the system has very high requirements for reliability.

[0037] Specifically, the working process of the storage register involves storage and output timing control. In terms of timing, the output of the register can be controlled by the trigger signal. In each clock cycle, the data in the register is output in the following manner: D out (t) = f trigger ·D in (t); where D out (t) is the parallel data output at time t; f trigger is the trigger signal, which controls the output timing of the data; D in (t) is the parallel data stored in the storage register at time t.

[0038] In some embodiments, by adjusting the frequency of the trigger signal, different timing control requirements can be achieved in different systems. For example, in a high-speed data transmission system, a higher-frequency trigger signal can meet the real-time requirements, while for some low-speed systems, a lower-frequency trigger signal can be used to reduce power consumption and improve stability.

[0039] Therefore, by precisely controlling the output timing of the storage register and the generation of the trigger signal, stable transmission of parallel data from the storage register to the phase shifter is achieved, thus ensuring accurate and real-time phase adjustment of the phased array antenna. By precisely designing the relationship between the trigger signal and the storage register, the overall performance and reliability of the system are ensured, while providing a solid technical foundation for large-scale data processing and real-time phase adjustment.

[0040] The parallel data of the phase shifter state is converted into serial data by a parallel-to-serial conversion chip and output to the main controller to complete the phase state readback.

[0041] In this embodiment, in the phased array antenna system, the state of the phase shifter needs to be fed back to the main controller in real time for precise adjustment of the phase of the antenna array. To achieve this goal, this embodiment uses a parallel-to-serial conversion chip to convert the parallel data of the phase shifter into serial data. This process not only combines multiple data streams into a single serial data stream, thus reducing the number of signal channels in the system, but also ensures the integrity and accuracy of the data during the conversion process.

[0042] Generally, the main function of the parallel-to-serial conversion chip is to convert multiple parallel input data streams into a single serial data stream. In a phased array antenna system, the state of each phase shifter is usually stored in the form of parallel data, and these parallel data need to be converted into serial data by the parallel-to-serial conversion chip to adapt to the subsequent data transmission channels. Especially when the main controller reads back the phase state, serial data transmission is more efficient. The shift register in the parallel-to-serial conversion chip gradually converts each bit of the parallel data into serial data under the control of the clock signal and transmits it according to the specified timing.

[0043] Specifically, in this embodiment, the parallel-to-serial conversion chip receives the parallel data from the phase shifter state. This parallel data stream enters the input port of the chip and is shifted bit by bit through the shift register, finally converting the parallel data into serial data. This process is controlled by the clock signal to ensure the accuracy of data transmission. Inside the parallel-to-serial conversion chip, the shift register gradually passes each bit of the parallel data stream to the next-level register through the clock signal and finally outputs it to the main controller through the serial port. The output data stream is a serial stream driven by the clock signal, conforming to the standard of serial data transmission.

[0044] In some embodiments, the serial-to-parallel conversion chip may have different parallel input data bit widths to adapt to different system requirements. For example, if the system needs to process a large amount of data, a wider data input channel can be selected, and the parallelism of the data can be increased by configuring registers with a higher number of bits, thereby improving the data transfer rate of the system. In addition, the cooperation between the clock frequency at the output end and the parallel input bit width can help further optimize the speed and stability of data transfer.

[0045] In a possible implementation, the operation of the serial-to-parallel conversion chip depends on a high-frequency clock signal, which is particularly important for applications that require high bandwidth and low latency. The clock frequency of the shift register determines the rate of data conversion, which in turn affects the speed of data output. To ensure the reliable transmission of high-speed data, in high-frequency application scenarios, a high-performance shift register can be selected and a higher clock frequency can be used to meet the real-time requirements of the system.

[0046] Furthermore, inside the serial-to-parallel conversion chip, the conversion and transmission of data also involve timing control issues. To avoid data loss or errors caused by inconsistent timing, the main controller controls the serial-to-parallel conversion chip through a trigger signal to ensure that the data is output smoothly according to the timing requirements. Specifically, the trigger signal is sent by the main controller, and the high level or low level of the trigger signal indicates when the serial-to-parallel conversion chip starts data conversion, and each bit of data is sequentially output under the drive of the clock signal in terms of timing. The trigger signal ensures the synchronous output of data and correct timing control, avoiding data misalignment or loss.

[0047] In this embodiment, the relationship between the speed of data conversion, the parallel data bit width, and the clock frequency can be described by the following formula: R serial =f clk ×Z; where, R serial is the transmission rate of the serial data (bits per second, bps); f clk is the clock frequency; Z is the parallel data bit width; and the transmission rate of the serial data is the product of the clock frequency and the parallel data bit width. By adjusting the clock frequency or the parallel bit width, the transmission rate of the system can be flexibly adjusted. For example, in a low-speed system, a lower clock frequency and a smaller parallel data width are used, while in a high-speed system, the data output rate can be increased by increasing the clock frequency or the parallel data bit width.

[0048] In some embodiments, for high-frequency and large-data-volume applications, the selected clock frequency f clk can be as high as several hundred megahertz or higher to meet the requirements of high-speed transmission. In low-frequency applications, the clock frequency can be appropriately reduced and optimized according to the actual bandwidth requirements.

[0049] Therefore, in this embodiment, the use of the serial-to-parallel and parallel-to-serial conversion chip effectively converts the parallel data of the phase shifter state into serial data. Through precise timing control and trigger signal management, the smooth transmission of data is ensured, thereby providing accurate phase state information to the main controller. By optimizing the clock frequency and parallel data bit width, the data transmission rate can be flexibly adjusted according to the system requirements to meet the data processing needs in different application scenarios. At the same time, the reasonable design of the trigger signal ensures the stability and efficiency of the system.

[0050] Moreover, the length of the transmission path between the serial-to-parallel conversion chip and the parallel-to-serial conversion chip and the signal propagation speed are optimized based on the transmission delay minimization control algorithm.

[0051] Specifically, the delay in the signal transmission process is an important factor affecting the system performance. Especially in systems that require high-speed and real-time data processing, the optimization of the transmission delay is crucial. By accurately calculating the length of the transmission path and the signal propagation speed, combined with the transmission delay minimization control algorithm, the effective control of the system delay can be achieved, thereby optimizing the response speed and data transmission efficiency of the entire system. Especially in the phased array antenna system, the precise timing of each signal is crucial. Therefore, controlling the signal transmission delay and reducing unnecessary timing errors can improve the phase shifter control accuracy and system stability.

[0052] Specifically, in this embodiment of the phased array antenna measurement and control technology, the length of the transmission path between the serial-to-parallel conversion chip and the parallel-to-serial conversion chip and the signal propagation speed are optimized through the transmission delay minimization control algorithm. This optimization algorithm is based on the actual requirements of the system and comprehensively considers various factors such as path length, signal attenuation, signal reflection, and timing control. The optimization of the transmission path length and signal propagation speed can effectively reduce the time delay in the signal transmission process, thereby improving the working efficiency of the system and ensuring the integrity and synchronization of the signal.

[0053] To achieve the minimization of the transmission delay, the transmission delay minimization control algorithm usually adopts an adaptive control method, which can dynamically adjust the path length and propagation speed according to the real-time environment and signal characteristics. This process involves signal path planning and optimization algorithms. By calculating the signal propagation speed in different transmission media and combining with the path length to achieve the best configuration, signal attenuation and reflection during the transmission process are avoided, making the transmission process as fast and stable as possible.

[0054] In a possible implementation, the control algorithm of the phased array antenna measurement and control technology can also be synchronized with the system clock signal, so that each cycle of the signal can be transmitted strictly according to the timing sequence. By controlling the selection of the signal propagation path and propagation medium, this algorithm can automatically adjust the transmission path length and propagation speed of the signal, so that the total delay experienced by the signal during the process from the serial-to-parallel conversion chip to the parallel-to-serial conversion chip is minimized. In this way, the optimization of the transmission path can minimize the transmission time of each data packet, thereby improving the data throughput of the entire system.

[0055] As an option, the optimization algorithm of the phased array antenna measurement and control technology can not only reduce the delay by adjusting the transmission path length, but also adaptively adjust the signal propagation medium according to the changes in the environment. Different transmission media (such as cables, PCBs, optical fibers, etc.) have different propagation speeds. Therefore, according to the characteristics of the transmission medium, the propagation speed of the signal will also be different. By adopting a control algorithm, according to the propagation characteristics of different media, the path and speed are adjusted in real time to further optimize the delay.

[0056] Furthermore, the optimization algorithm of the phased array antenna measurement and control technology can also take into account other performance indicators of the system, such as power consumption, signal quality, etc. In some high-frequency systems, the transmission delay may be affected by electromagnetic interference or signal attenuation. Therefore, these factors also need to be comprehensively considered during the optimization process to ensure the stable operation of the system.

[0057] To further illustrate the mathematical model of this optimization process, we introduce the following formula to describe the process of minimizing the transmission delay. And the transmission delay T d can be expressed as: where, T d is the transmission delay; L is the length of the signal transmission path; v is the propagation speed of the signal in the transmission medium.

[0058] According to this formula, the optimization of the transmission delay is achieved by adjusting the length L of the signal transmission path. In practical applications, the selection of the path length will be comprehensively adjusted based on the requirements of different systems.

[0059] And during the optimization process, the transmission delay minimization control algorithm will adjust the values of L and v so that the total transmission delay T d reaches the minimum. Specifically, the transmission delay can be reduced by adjusting the length of the transmission path, selecting an appropriate transmission medium, or by adopting other technical means (such as signal amplification, filtering, etc.) to increase the propagation speed of the signal.

[0060] This control algorithm can be dynamically adjusted based on the network topology. With the changes in various components in the system, the optimal configuration of the transmission path and propagation speed can also be updated in real time to ensure that the system can still maintain low latency and efficient data transmission under different loads and environmental conditions.

[0061] Therefore, through the transmission delay minimization control algorithm, combined with the optimal design of the transmission path length and signal propagation speed, the transmission delay between the serial-to-parallel conversion chip and the parallel-to-serial conversion chip can be significantly reduced. This optimization strategy can ensure the efficient operation of the system, improve the real-time performance and accuracy of the phase shifter control in the phased array antenna system, reduce the response time of the system, and enhance the overall performance of the system.

[0062] During the data transmission process of the signal from the serial-to-parallel conversion chip to the parallel-to-serial conversion chip, the relationship between the signal bandwidth and the signal period is optimized by the Nyquist theorem to maximize the signal transmission rate and bandwidth utilization.

[0063] Generally, in a data transmission system, the relationship between the bandwidth and the signal period directly affects the transmission efficiency of the system. To optimize the signal transmission rate and bandwidth utilization, it is usually necessary to achieve the maximum benefit of signal transmission through reasonable bandwidth configuration and signal period setting. By applying the Nyquist theorem, the maximum available transmission rate of the system can be effectively determined, thereby maximizing the utilization of the bandwidth and reducing signal transmission delay and loss caused by insufficient bandwidth.

[0064] Specifically, the Nyquist theorem of the phased array antenna measurement and control technology describes the basic principle of signal sampling. This theorem states that to avoid signal distortion, the sampling frequency should be at least twice the signal bandwidth. Applying the Nyquist theorem to this embodiment, the relationship between the signal bandwidth B and the signal period T can be expressed by the following formula: f sample ≥2B; where, f sample is the sampling frequency of the signal; B is the signal bandwidth.

[0065] Under this relationship, to achieve the best data transmission rate, it is necessary to ensure that the sampling frequency is high enough to be able to fully capture the changes in the signal and avoid distortion caused by too low sampling frequency.

[0066] Therefore, by optimizing the relationship between the signal bandwidth and the period according to the Nyquist theorem, the signal transmission rate of the system can be maximized. For example, during the signal transmission process between the serial-to-parallel conversion chip and the parallel-to-serial conversion chip, the system can adjust the bandwidth and the signal period according to the actual transmission requirements to make the signal transmission rate reach the theoretical maximum value of the system, thereby reducing data loss caused by bandwidth bottlenecks.

[0067] In a possible implementation, when designing a data transmission system using phased array antenna measurement and control technology, the signal bandwidth is reasonably planned to ensure the efficiency of data transmission. Specifically, if the signal bandwidth B increases, the required sampling frequency f sample also increases accordingly, thereby improving the transmission rate of the system. At this time, the relationship between the signal period T and the bandwidth B also needs to be appropriately adjusted to adapt to the new bandwidth requirements and ensure the stability of the signal during transmission.

[0068] Therefore, according to the application of the Nyquist theorem, the relationship between the signal bandwidth B and the signal period T can be expressed as: T = B 1 ; From this formula, it can be seen that the signal period T and the signal bandwidth B are inversely proportional. To maximize the signal transmission rate, we need to minimize the signal period as much as possible, so that more data can be transmitted by the signal per unit time. This relationship plays a key role in optimizing the entire signal transmission process.

[0069] At the same time, in an actual data transmission system, the maximum transmission rate R of the system max is also jointly affected by the signal bandwidth B and the sampling frequency f sample . Therefore, when designing the system, the sampling frequency should be ensured to meet the minimum requirements, and the system should be optimized according to the guiding principles of the Nyquist theorem: R max = 2B; This optimization process is not limited to single-channel data transmission, but can also be extended to multi-channel systems. In a multi-channel system, the bandwidth and signal period of each channel need to be optimized and adjusted according to the total bandwidth requirements of the system. In this case, the system designer can allocate bandwidth to each channel based on the Nyquist theorem and bandwidth sharing strategy to ensure that the signals of each channel can make full use of the bandwidth resources and avoid the situation of excessive or insufficient bandwidth occupancy.

[0070] Therefore, by applying the Nyquist theorem, the relationship between the signal bandwidth and the signal period is optimized, maximizing the signal transmission rate and bandwidth utilization. By reasonably selecting the sampling frequency and bandwidth configuration, this system can effectively improve the efficiency of data transmission, reduce signal loss and delay, thereby meeting the requirements of high-efficiency and real-time data transmission. This optimization scheme not only improves the performance of the phased array antenna system, but also provides an effective technical solution for other systems that require high-speed data transmission.

[0071] To further improve the bandwidth utilization of signals, the effective data transmission volume can be increased by optimizing the signal coding method. For example, in phased array antenna measurement and control technology, adopting a more efficient data coding method can effectively improve the bandwidth utilization of the system, thereby reducing the transmission of useless data and increasing the overall transmission rate of the system. Under an efficient coding scheme, although the bandwidth of the signal remains unchanged, a more efficient signal transmission can still be achieved by increasing the amount of information transmitted within each signal period.

[0072] Specifically, in a data transmission system, the transmission of data may be affected by factors such as noise, interference, and timing errors, resulting in data loss or errors. To ensure the integrity and accuracy of data, effective coding processing must be performed on the transmitted data. Error correction coding is a commonly used technical means to solve this problem. By adding redundant information to the data, the receiving end can detect and correct some errors, thereby improving the reliability and accuracy of data transmission.

[0073] Two main error correction coding methods are adopted during the transmission of the read-back phase state data, namely low-density parity-check code (LDPC) and convolutional coding. Low-density parity-check code is a modern error correction code that can achieve efficient error detection and correction with a low redundancy. Convolutional coding is a coding method based on time series. By segmenting the data stream and using a specific convolutional encoder to increase redundancy, the error recovery ability during transmission is enhanced.

[0074] In a possible implementation, as a sparse matrix code, low-density parity-check code (LDPC) in phased array antenna measurement and control technology divides the data into multiple blocks and inserts parity check bits into each data block through a check matrix to generate the encoded data. Due to the low coding redundancy and high error correction performance of low-density parity-check code, it can effectively reduce errors in most data transmissions, especially in an environment with poor transmission quality. Through this coding method, the system can detect and correct errors through a feedback mechanism, thereby ensuring the integrity of the read-back data.

[0075] A main feature of low-density parity-check code (LDPC) is that its check matrix is sparse in structure. That is to say, most of the matrix elements are zero. The sparse matrix makes the implementation of this coding method more efficient, and in large-scale data transmission, it can effectively save computing resources and improve the processing speed. By using LDPC coding, the reliability of the phase state read-back data can be significantly improved, especially in an environment with noise or signal attenuation.

[0076] As an alternative, the convolutional coding of the phased array antenna measurement and control technology generates an output with a redundant data stream by combining the input data stream with a convolutional encoder. This output data stream contains additional redundant information that can be used to correct errors that may occur at the receiving end. In some embodiments, the coding rate and constraint length of the convolutional coding can be selected according to system requirements. The constraint length usually represents the "memory" length of the convolutional encoder. A longer constraint length can provide stronger error correction capabilities but also increase the computational complexity. Convolutional coding is particularly suitable for systems that require real-time performance and high transmission rates, and can effectively improve the stability and reliability of data transmission.

[0077] Specifically, the combination of the phased array antenna measurement and control technology with low-density parity-check (LDPC) codes and convolutional coding can further enhance the robustness of the system. In a complex transmission environment, the combination of the two coding methods can provide multiple protections when errors occur. For example, in some communications, convolutional coding is first used for error detection, and then LDPC is used for error correction. This combined coding can greatly improve the error correction capabilities of the system.

[0078] In some embodiments, for the phased array antenna measurement and control technology to optimize system performance, different combination methods may be adopted for LDPC coding and convolutional coding. In scenarios where the data transmission volume is large or the real-time requirement is high, convolutional coding can be performed first to improve the transmission rate; then LDPC coding is used to further correct errors in the data to ensure the integrity and stability of the data. The joint use of these two coding methods can provide stronger anti-interference capabilities while ensuring efficient transmission and adapting to more complex network environments.

[0079] In this embodiment, the generation process of the low-density parity-check (LDPC) code can be represented by the following matrix: C = M·X; where C represents the encoded data; M is the low-density parity-check matrix; and X is the original data.

[0080] Through this matrix operation, the original data is converted into encoded data with redundancy, providing additional parity information for error detection and correction.

[0081] For convolutional coding, the coding process is usually based on the transfer function of the convolutional encoder. Given the input data stream x(t), the relationship between the output data stream y(t) of the convolutional encoder and its state s(t) is as follows: y(t) = G(s(t), x(t)); where G(s(t), x(t)) is the transfer function of the convolutional encoder, representing the relationship between the encoded output, the input data, and the state.

[0082] Therefore, through the combination of low-density parity-check (LDPC) codes and convolutional coding, powerful error detection and correction capabilities are provided, ensuring the efficient transmission and integrity of the phase state readback data. These coding methods can effectively cope with complex transmission environments, enhance the robustness of the system, and provide technical support for future high-precision and high-efficiency phased array antenna systems.

[0083] Although the embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention, and the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for measuring and controlling the real-time phase of a phased array antenna, characterized in that: The following steps are involved: Convert serial input data into parallel data through a serial-to-parallel conversion chip; The parallel data is stored in a storage register, and the parallel data is output to a phase shifter for phase adjustment by controlling the trigger signal; The parallel data of the phase shifter state is converted into serial data through a parallel-to-serial conversion chip and output to the main controller to complete the phase state readback.

2. The method for designing and measuring the real-time phase of a phased array antenna according to claim 1, characterized in that: The serial-to-parallel conversion chip includes a shift register for converting serial data into parallel data, and the output end of the shift register is connected to the storage register.

3. The method for designing and measuring the real-time phase of a phased array antenna according to claim 1, characterized in that: The trigger signal is sent by the main controller, and the main controller controls the parallel-to-serial conversion chip through the trigger signal to convert parallel data into serial data and output it to the main controller.

4. The method for designing and measuring the real-time phase of a phased array antenna according to claim 3, characterized in that: The parallel-to-serial conversion chip converts parallel input data into serial data through an internal shift register, and outputs the serial data through a Qh port.

5. The method for designing and measuring the real-time phase of a phased array antenna according to claim 4, characterized in that: The serial-to-parallel conversion chip and the parallel-to-serial conversion chip are connected in a cascade manner, and the cascade manner is used to expand system capacity.

6. The method for designing and measuring the real-time phase of a phased array antenna according to claim 5, characterized in that: The length of the transmission path of the signal from the serial-to-parallel conversion chip to the parallel-to-serial conversion chip and the propagation speed of the signal are optimized based on a transmission delay minimization control algorithm.

7. The method for designing and measuring the real-time phase of a phased array antenna according to claim 1, characterized in that: During the data transmission process of the signal from the serial-to-parallel conversion chip to the parallel-to-serial conversion chip, the relationship between the signal bandwidth and the signal period is optimized by the Nyquist theorem to maximize the signal transmission rate and bandwidth utilization.

8. The method for designing and measuring the real-time phase of a phased array antenna according to claim 1, characterized in that: The readback data of the phase state is encoded by an error correction method, and the encoding method includes low-density parity check code and convolutional coding.

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