High-power vertical cavity surface emitting laser and preparation method thereof

Abstract

The invention discloses a high-power vertical cavity surface emitting laser and a preparation method thereof. The high-power vertical cavity surface emitting laser comprises a substrate; the semiconductor epitaxial layer is positioned on one side of the substrate; the semiconductor epitaxial layer comprises at least one first region and a second region arranged around the first region; the semiconductor epitaxial layer in the second region is etched to form a groove; the filling layer is filled in the groove; the dielectric layer comprises a first dielectric layer and is positioned on one side, far away from the substrate, of the semiconductor epitaxial layer; wherein the dielectric layer comprises a first opening; the vertical projection of the first opening on the semiconductor epitaxial layer is located in the first region; the upper electrode is positioned on one side, far away from the substrate, of the first dielectric layer; the upper electrode is electrically connected with the light-emitting structure through the first opening, and the upper electrode located in the second area is separated from the filling layer through the first dielectric layer. According to the technical scheme provided by the invention, the flatness of the device is ensured, and the performance and reliability of the device are improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor technology, and in particular, to a high-power vertical cavity surface emitting laser and a method for manufacturing the same. Background Art

[0002] With the rapid development of modern electronic technology, especially new energy vehicles, the demand for vertical cavity surface emitting lasers (VCSELs) as the light source of lidar has increased greatly.

[0003] Currently, in lidar applications, the working conditions are usually narrow pulse driving, and the pulse width is 3 - 8 ns. Exactly because the pulse width is very small, compared with the DC working conditions, the laser can be driven with a larger voltage or current. However, a larger voltage or current will pose a test to the VCSEL. Especially for a VCSEL with a deep aspect ratio trench, due to the reduction of the light-emitting hole pitch or the deepening of the trench etching depth, there is a great challenge to the coverage of the trench, which affects the flatness and reliability of the device. At the same time, the capacitance of the laser itself will also affect the performance of the narrow pulse. Summary of the Invention

[0004] Embodiments of the present invention provide a high-power vertical cavity surface emitting laser and a method for manufacturing the same, which can ensure the flatness of the device while improving the performance and reliability of the device.

[0005] According to one aspect of the present invention, there is provided a high-power vertical cavity surface emitting laser, comprising:

[0006] A substrate;

[0007] A semiconductor epitaxial layer located on one side of the substrate; the semiconductor epitaxial layer includes at least one first region and a second region disposed around the first region; the first region has at least one light-emitting structure; the second region has a trench;

[0008] A filling layer filled in the trench; the material of the filling layer has high temperature resistance;

[0009] A dielectric layer, the dielectric layer includes a first dielectric layer located on the side of the semiconductor epitaxial layer away from the substrate; wherein, the dielectric layer includes a first opening; the vertical projection of the first opening on the semiconductor epitaxial layer is located in the first region;

[0010] An upper electrode located on the side of the first dielectric layer away from the substrate; the upper electrode is electrically connected to the light-emitting structure through the first opening, and the upper electrode located in the second region and the filling layer are separated by the first dielectric layer.

[0011] Optionally, the difference between the distance from the surface of the filling layer away from the substrate side to the substrate and the distance from the surface of the semiconductor epitaxial layer away from the substrate side to the substrate is less than a preset value.

[0012] Optionally, the material of the filling layer includes a metal material and / or a dielectric material.

[0013] Optionally, the metal material includes Au or Cu; the dielectric material includes a nitride or an oxide.

[0014] Optionally, along the direction pointing from the second region to the first region, the width of the trench is less than or equal to 4 um;

[0015] The depth-to-width ratio of the trench is greater than or equal to 2.

[0016] Optionally, the shape of the trench is annular; the annular trench is arranged around the light-emitting structure;

[0017] Alternatively, the shape of the trench is pore-like; a plurality of pore-like trenches are arranged around the light-emitting structure.

[0018] Optionally, the dielectric layer further includes:

[0019] A second dielectric layer, the second dielectric layer is located between the semiconductor epitaxial layer and the first dielectric layer, and on the sidewalls and bottom of the trench;

[0020] Wherein, the dielectric layer includes a first opening, the first opening penetrates through the first dielectric layer and the second dielectric layer; the upper electrode is electrically connected to the light-emitting structure through the first opening.

[0021] Optionally, the semiconductor epitaxial layer includes a lower Bragg reflector, an upper Bragg reflector, and at least one active layer located between the lower Bragg reflector and the upper Bragg reflector; wherein, the lower Bragg reflector is closer to the substrate;

[0022] At least one oxidation confinement layer is included in the active layer in the first region to perform carrier confinement.

[0023] According to another aspect of the present invention, a method for manufacturing a high-power vertical cavity surface emitting laser is provided, including:

[0024] Providing a substrate;

[0025] Forming a semiconductor epitaxial layer on one side of the substrate; the semiconductor epitaxial layer includes at least one first region and a second region arranged around the first region;

[0026] Etch the semiconductor epitaxial layer in the second region to form a trench; wherein, the semiconductor epitaxial layer in the first region is used to form a light-emitting structure;

[0027] Form a filling layer in the trench;

[0028] Form a dielectric layer on the side of the semiconductor epitaxial layer away from the substrate; wherein, the dielectric layer includes a first dielectric layer;

[0029] Etch the dielectric layer to form a first opening in the dielectric layer; the vertical projection of the first opening on the semiconductor epitaxial layer is located in the first region;

[0030] Form an upper electrode on the side of the first dielectric layer away from the substrate; the upper electrode is electrically connected to the light-emitting structure through the first opening, and the upper electrode in the second region and the filling layer are separated by the first dielectric layer.

[0031] Optionally, the material of the filling layer includes a metal material; forming a filling layer in the trench includes:

[0032] After depositing a seed metal, electroplate Cu or Au to form the filling layer;

[0033] Or, the material of the filling layer includes a dielectric material; forming a filling layer in the trench includes:

[0034] Deposit a nitride or an oxide in the trench to form the filling layer.

[0035] Optionally, before forming the filling layer in the trench, further includes:

[0036] Form a dielectric layer between the semiconductor epitaxial layer and the first dielectric layer, and on the sidewalls and bottom of the trench; wherein, forming the dielectric layer further includes forming a second dielectric layer, and the second dielectric layer is located between the semiconductor epitaxial layer and the first dielectric layer, and on the sidewalls and bottom of the trench;

[0037] Etching the dielectric layer includes:

[0038] Etch the first dielectric layer and the second dielectric layer to form a first opening penetrating the first dielectric layer and the second dielectric layer.

[0039] Beneficial effects: In the technical solution provided by the embodiments of the present invention, by filling the trenches with a filling layer, the VCSEL with high aspect ratio trenches can be improved, and the problem of poor device flatness caused by the reduction of the light-emitting hole pitch and the deepening of the trench etching depth can be solved; in addition, by separating the upper electrode from the filling layer located in the trench with the first dielectric layer, compared with the prior art in which a metal material deposited simultaneously with the upper electrode is provided in the trench, the present application can prevent the metal in the trench from contacting and charging with the pad metal to generate heat, thereby avoiding the influence on the device caused by the holes in the metal material in the trench, and further improving the reliability of the device. Moreover, it can also prevent the metal in the trench from having opposite polarities and being relatively close to the lower Bragg reflector, forming a large capacitance, thereby avoiding the influence on the performance of the laser operating in a short pulse mode.

[0040] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. Description of the Drawings

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0042] Figure 1 is a partial structural sectional view of a vertical cavity surface emitting laser provided in the prior art;

[0043] Figure 2 is a partial structural sectional view of another vertical cavity surface emitting laser provided in the prior art;

[0044] Figure 3 is a positional relationship diagram of trenches and light-emitting holes in a high-power vertical cavity surface emitting laser provided by an embodiment of the present invention;

[0045] Figure 4 is a positional relationship diagram of trenches and light-emitting holes in another high-power vertical cavity surface emitting laser provided by an embodiment of the present invention;

[0046] Figure 5 is Figure 3 the sectional structural schematic diagram along the section line AA1 in Figure 4 or the sectional structural schematic diagram along the section line BB1 in

[0047] Figure 6 is Figure 3 the sectional structural schematic diagram along the section line AA1 in Figure 4Another schematic cross-sectional structure along the section line BB1;

[0048] Figure 7 is Figure 3 either along the section line AA1 in Figure 4 Another schematic cross-sectional structure along the section line BB1 in

[0049] Figure 8 is a flowchart of a method for manufacturing a high-power vertical cavity surface emitting laser provided by an embodiment of the present invention;

[0050] Figure 9 is a flowchart of another method for manufacturing a high-power vertical cavity surface emitting laser provided by an embodiment of the present invention;

[0051] Figures 10 - 16 is a cross-sectional view of each step in the steps S210 to S280 of a method for manufacturing a high-power vertical cavity surface emitting laser provided by an embodiment of the present invention. Detailed implementation manners

[0052] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0053] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0054] As in the background art, with the decrease of the light-emitting hole pitch or the increase of the etching depth, high aspect ratio trenches are becoming more and more common. Figure 1 is a partial cross-sectional view of a vertical cavity surface emitting laser provided in the prior art, refer to Figure 1, The vertical cavity surface emitting laser includes a substrate 1 and a semiconductor epitaxial layer 2 located on one side of the substrate. The semiconductor epitaxial layer 2 includes a lower Bragg reflector, an upper Bragg reflector, and at least one active layer located between the lower Bragg reflector and the upper Bragg reflector. The semiconductor epitaxial layer 2 is etched to form trenches in the semiconductor epitaxial layer 2, thereby defining a light-emitting mesa structure. When forming the upper electrode 5 electrically connected to the light-emitting mesa structure, the metal material will be deposited in the trenches. However, due to the uniformity of the sputtered seed metal and the step coverage of the electroplated Au, holes 4 are formed in the metal deposited in the trenches of the upper electrode 5. After the upper electrode 5 is energized, the metal in the trenches becomes charged and generates heat accordingly. The thermal conductivity of the metal material is higher than that of the air in the holes 4, and the difference in the coefficient of thermal expansion may reduce the reliability of the laser. At the same time, since the polarity of the metal in the trenches is opposite to that of the lower Bragg reflector and the distance is relatively close, a large capacitance is formed between the metal in the trenches and the lower Bragg reflector; and a large capacitance will affect the performance of the laser operating in a short-pulse mode. In addition, due to the characteristics of the manufacturing process, when preparing the upper electrode 5, part of the metal will be deposited in the trenches. Therefore, the height of the upper electrode 5 above the trenches is less than the height of the upper electrode 5 at the non-trench layer, which affects the flatness of the device and is prone to misjudgment in subsequent visual inspections, affecting the yield.

[0055] Figure 2 is a partial structural sectional view of another vertical cavity surface emitting laser provided in the prior art. Refer to Figure 2 , In the prior art, an organic polymer is also used to fill the trenches to form an organic filling layer 7, such as BCB, Polyimide, etc. However, the raw material cost is relatively high, and in a high-temperature and high-humidity environment, the reliability of the organic polymer is challenged, which will also affect the reliability of the device.

[0056] In view of this, the embodiments of the present invention provide a high-power vertical cavity surface emitting laser. Figure 3 is a diagram showing the positional relationship between the trenches and the light-emitting holes in a high-power vertical cavity surface emitting laser provided by an embodiment of the present invention. Figure 4 is another diagram showing the positional relationship between the trenches and the light-emitting holes in a high-power vertical cavity surface emitting laser provided by an embodiment of the present invention; Figure 5 is Figure 3 in the sectional structural schematic diagram along the section line AA1 or Figure 4 in the sectional structural schematic diagram along the section line BB1, Figure 6 is Figure 3 in the sectional structural schematic diagram along the section line AA1 or Figure 4 in the sectional structural schematic diagram along the section line BB1 of another one, Figure 7 is Figure 3 in the sectional structural schematic diagram along the section line AA1 or Figure 4 in the sectional structural schematic diagram along the section line BB1 of another one. Refer toFigures 3 - 7 , a high-power vertical cavity surface emitting laser includes:

[0057] a substrate 10;

[0058] a semiconductor epitaxial layer 20, located on one side of the substrate 10; the semiconductor epitaxial layer 20 includes at least one first region E2 and a second region E1 disposed around the first region E2; the first region E2 has at least one light-emitting structure; the second region has a trench;

[0059] a filling layer 30, filled in the trench;

[0060] a dielectric layer 40, including a first dielectric layer 41, located on the side of the semiconductor epitaxial layer away from the substrate 10; wherein, the dielectric layer 40 includes a first opening; the vertical projection of the first opening in the semiconductor epitaxial layer 20 is located in the first region E2;

[0061] an upper electrode 50, located on the side of the first dielectric layer 41 away from the substrate 10; the upper electrode 50 is electrically connected to the light-emitting structure through the first opening, and the upper electrode 50 located in the second region E1 is separated from the filling layer 30 by the first dielectric layer 41.

[0062] Specifically, the substrate 10 can be any material suitable for forming a vertical cavity surface emitting laser, for example, gallium arsenide (GaAs). The substrate 10 can be an N-type doped semiconductor substrate or a P-type doped semiconductor substrate. In some embodiments, if the N ohmic metal and the P ohmic metal are formed on the same side of the substrate 10 and the substrate 10 does not need to act as a conductor to conduct the N ohmic metal and the P ohmic metal, the substrate 10 can be a semi-insulating substrate 10. In other embodiments, if the N ohmic metal and the P ohmic metal are formed on opposite sides of the substrate 10 and the substrate 10 needs to act as a conductor to conduct the N ohmic metal and the P ohmic metal, the substrate 10 is a conductive substrate 10. Figures 5 - 7 In this embodiment, the substrate 10 is an N-type doped semiconductor substrate, the P ohmic metal 60 is located on the side of the semiconductor epitaxial layer 20 away from the substrate, and the upper electrode 50 contacts the P ohmic metal 60 through the first opening, thereby realizing electrical connection with the light-emitting structure.

[0063] The semiconductor epitaxial layer 20 may include a lower Bragg reflection layer 21, an upper Bragg reflection layer 23, and at least one active layer 22 located between the lower Bragg reflection layer 21 and the upper Bragg reflection layer 23; wherein, the lower Bragg reflection layer 21 is closer to the substrate 10. The lower Bragg reflection layer 21, the upper Bragg reflection layer 23, and the active layer 22 may be formed by chemical vapor deposition. The lower Bragg reflection layer 21 may be formed by laminating two materials with different refractive indices, namely an aluminum gallium arsenide material layer and a gallium arsenide material layer, or by laminating two materials with different refractive indices, namely a high aluminum component aluminum gallium arsenide material layer and a low aluminum component aluminum gallium arsenide material layer. The active layer 22 is composed of a stack of GaAs and AlGaAs, or InGaAs and AlGaAs material layers, and the active layer 22 is used to convert electrical energy into light energy. When the active layer 22 is a multi-layer, a tunnel junction is provided between two adjacent active layers 22 and is connected in series by the tunnel junction. The upper Bragg reflection layer 23 may be formed by laminating two materials with different refractive indices, namely an aluminum gallium arsenide material layer and a gallium arsenide material layer, or by laminating two materials with different refractive indices, namely a high aluminum component aluminum gallium arsenide material layer and a low aluminum component aluminum gallium arsenide material layer. The upper Bragg reflection layer 23 and the lower Bragg reflection layer 21 are used to enhance the reflection of the light generated by the active layer 22 in the middle, and then emit from the surface of the upper Bragg reflection layer 23 to form a laser.

[0064] In some embodiments, the lower Bragg reflection layer 21 and the upper Bragg reflection layer 23 may also be formed of other materials. The lower Bragg reflection layer 21 and the upper Bragg reflection layer 23 include a series of alternating layers of materials with different refractive indices, wherein the effective optical thickness (the layer thickness multiplied by the refractive index of the layer) of each alternating layer is an odd integer multiple of one-fourth of the operating wavelength of the vertical cavity surface emitting laser, that is, the effective optical thickness of each alternating layer is one-fourth of an odd integer multiple of the operating wavelength of the vertical cavity surface emitting laser.

[0065] The semiconductor epitaxial layer 20 includes at least one first region E2 and a second region E1 disposed around the first region E2; the semiconductor epitaxial layer 20 of the first region E2 is used to form a light-emitting structure; trenches are provided in the semiconductor epitaxial layer 20 of the second region E1. It can be understood that the semiconductor epitaxial structure located in the second region E1 is etched by a dry etching method to form trenches, thereby forming a light-emitting mesa structure in the first region E2. After the light-emitting structure is formed, an oxidation confinement layer 202 is formed in the light-emitting structure; the oxidation confinement layer 202 has an opening, and the opening is used to define a light-emitting hole Q1 of the light-emitting structure. In this embodiment, the oxidation confinement layer 202 in each light-emitting structure is a circular ring structure. When the top view of the light-emitting structure is rectangular, the oxidation confinement layer 202 can also be a rectangular ring. Optionally, the semiconductor epitaxial layer 20 located in the first region E2 is used to form a single light-emitting structure or can also be used to form an array of light-emitting structures. A filling layer 30 is provided in the trenches, and the trenches are filled with the filling layer 30, so that the side of the semiconductor epitaxial layer 20 away from the substrate 10 has a relatively flat surface. On this basis, an upper electrode 50 is formed on the side of the first dielectric layer 41 away from the substrate 10, and the surfaces of the first dielectric layer 41 and the upper electrode 50 are flatter. Thus, the problem of poor device flatness caused by the reduction of the light-emitting hole pitch and the deepening of the trench etching depth in the VCSEL with a high aspect ratio trench can be improved. Among them, the first dielectric layer 41 has a first opening in the first region E2, so that the upper electrode 50 can be electrically connected to the light-emitting structure located in the first region E2 through the first opening, injecting current into the light-emitting structure while isolating from the filling layer 30 located in the non-light first region E1. Therefore, the material of the filling layer 30 can be a dielectric material or a material with high thermal conductivity such as a metal material. The material of the filling layer is a material with high temperature resistance and low cost, so as to achieve planarization and ensure the reliability of the laser at high temperature.

[0066] By separating the upper electrode 50 from the filling layer 30 in the trench through the first dielectric layer 41, when the material of the filling layer 30 in the trench is a metal material, it can prevent the metal in the trench from contacting and charging with the upper electrode 50 to generate heat, thereby improving the problem caused by the poor step coverage of the metal material in the trench, resulting in the formation of holes 01 in the metal in the trench, and the difference in thermal conductivity and thermal expansion coefficient between the metal and the air in the holes; furthermore, the reliability of the device can be improved. Moreover, it can also prevent a large capacitance from being formed due to the opposite polarity and close distance between the metal in the trench and the lower Bragg reflector 21; furthermore, the influence on the performance of the laser operating in a short pulse mode is avoided.

[0067] Based on the above embodiments, referring to Figure 5 , in an embodiment of the present invention, the metal material of the filling layer 30 includes Au, and an Au filling layer 31 is formed.

[0068] Specifically, due to the uniformity of the sputtered seed metal and the step coverage of the electroplated Au, holes 01 are formed in the metal within the trench. Separating the upper electrode 50 from the filling layer 30 located in the trench by the first dielectric layer 41 can prevent the metal in the trench from coming into contact with the upper electrode 50 and becoming charged to generate heat, thereby improving the problems caused by the poor step coverage of the metal material in the trench, resulting in the formation of holes 01 in the metal within the trench, and the differences in thermal conductivity and thermal expansion coefficient between the metal and the air in the holes, and further improving the reliability of the device. Moreover, it can also prevent the formation of a relatively large capacitance due to the opposite polarities and relatively close distances between the metal in the trench and the lower Bragg reflector 21, which affects the performance of the laser using the short-pulse operation mode.

[0069] Based on the above embodiments, referring to Figure 6 , in another embodiment of the present invention, the metal material of the filling layer 30 includes Cu, forming a Cu filling layer 32. Cu has better hole filling performance than Au and lower cost.

[0070] Based on the above embodiments, referring to Figure 7 , in another embodiment of the present invention, the filling layer 30 is a dielectric material, forming a dielectric filling layer 33. The dielectric material includes nitride or oxide.

[0071] Specifically, covering the surfaces of the trench and the semiconductor epitaxial layer 20 with a dielectric film can play an insulating role. The filling layer 30 made of a nitride or oxide can be formed by some techniques with good step coverage. Exemplarily, the nitride includes SiN, and SiN can be deposited by a PECVD (Plasma Enhanced Chemical Vapor Deposition) device using a TEOS (tetraethyl orthosilicate) source, or SiN can be deposited by an HDPCVD (High Density Plasma Chemical Vapor Deposition) device. The oxide includes SiO2, and SiO2 can be deposited by a PE-ALD (Plasma Enhanced - Atomic layer deposition) device. Forming a nitride or oxide by some techniques with good step coverage can form a filling layer 30 without holes 01, avoiding the impact of the holes 01 in the filling layer 30 on the device reliability.

[0072] It should be noted that when the material filled in the trench is a metal material, the dielectric layer 40 of the high-power vertical cavity surface emitting laser further includes a second dielectric layer 42; the second dielectric layer 42 is located between the semiconductor epitaxial layer 20 and the first dielectric layer 41, as well as on the side walls and bottom of the trench. Among them, the dielectric layer 40 includes a first opening that penetrates both the first dielectric layer 41 and the second dielectric layer 42 at the same time, and the vertical projection of the first opening on the semiconductor epitaxial layer 20 is located in the first region E2; the upper electrode 50 is electrically connected to the light-emitting structure through the first opening. By providing the second dielectric layer 42 in the high-power vertical cavity surface emitting laser, it is possible to prevent the metal layer in the trench from directly connecting the upper Bragg reflector 23 and the lower Bragg reflector 21, causing a short circuit in the high-power vertical cavity surface emitting laser and affecting the normal light emission of the active layer 22 located between the upper Bragg reflector 23 and the lower Bragg reflector 21. When the material filled in the trench is a dielectric material, a second dielectric layer 42 may or may not be provided between the semiconductor epitaxial layer 20 and the first dielectric layer 41, as well as on the side walls and bottom of the trench.

[0073] Based on the above embodiments, in an embodiment of the present invention, the difference between the distance from the surface of the filling layer 30 on the side away from the substrate 10 to the substrate 10 and the distance from the surface of the semiconductor epitaxial layer 20 on the side away from the substrate 10 to the substrate 10 is less than a preset value. Preferably, the distance from the surface of the filling layer 30 on the side away from the substrate 10 to the substrate 10 is equal to the distance from the surface of the semiconductor epitaxial layer 20 on the side away from the substrate 10 to the substrate 10, which can further improve the flatness of the laser.

[0074] Based on the above embodiments, in an embodiment of the present invention, along the direction from the second region E1 to the first region E2, the width of the trench is less than or equal to 4 um; the depth-to-width ratio of the trench is greater than or equal to 3.

[0075] Specifically, setting the width of the trench to be less than or equal to 4 um can make the spacing between the light-emitting structures smaller, thereby increasing the number of light-emitting structures per unit area in the high-power vertical cavity surface emitting laser and improving the light output of the high-power vertical cavity surface emitting laser. Setting the depth-to-width ratio of the trench to be greater than or equal to 2 can make the depth of the trench deeper, thereby increasing the number of active layers 22 included in the light-emitting structure, and further improving the light output of a single light-emitting structure and the light output of the high-power vertical cavity surface emitting laser.

[0076] Based on the above embodiments, refer to Figure 2 , in an embodiment of the present invention, the shape of the trench is annular; the annular trench is arranged around the light-emitting structure. In another embodiment of the present invention, refer to Figure 3, the shape of the trench is hole-shaped; a plurality of hole-shaped trenches are arranged around the light-emitting structure. The shape of the trench can be set according to actual needs.

[0077] Optionally, an ion implantation layer is provided on the side of the trench close to the light-emitting structure, and the ion implantation layer is used to isolate the filling layer 30 from the light-emitting structure.

[0078] It can be understood that due to the characteristics of the manufacturing process of the second dielectric layer 42, in the direction of the upper electrode 50 pointing to the lower Bragg reflector 21, the thickness of the second dielectric layer 42 on the side wall of the trench gradually decreases; when the depth of the trench is relatively deep, the thickness of the second dielectric layer 42 on the side wall close to the bottom of the trench is too small, or even the second dielectric layer 42 is not formed, resulting in an increased risk of device short circuit at this time. By providing an ion implantation layer on the side of the trench close to the light-emitting structure, the electrical insulation between the filling layer 30 and the light-emitting structure can be further enhanced.

[0079] An embodiment of the present invention also provides a method for manufacturing a high-power vertical cavity surface emitting laser, which is used to manufacture the high-power vertical cavity surface emitting laser according to any of the above embodiments. Figure 8 is a flowchart of a method for manufacturing a high-power vertical cavity surface emitting laser provided by an embodiment of the present invention. Refer to Figure 8 , the method for manufacturing a high-power vertical cavity surface emitting laser includes:

[0080] S110. Provide a substrate.

[0081] S120. Form a semiconductor epitaxial layer on one side of the substrate; the semiconductor epitaxial layer includes at least one first region and a second region arranged around the first region.

[0082] S130. Etch the semiconductor epitaxial layer in the second region to form a trench; wherein, the semiconductor epitaxial layer located in the first region is used to form a light-emitting structure.

[0083] S140. Form a filling layer in the trench.

[0084] Specifically, by providing a filling layer in the trench and filling the trench with the filling layer, the problem of poor device flatness caused by the reduction of the light-emitting hole pitch and the increase of the trench etching depth in the VCSEL with a high aspect ratio trench can be improved.

[0085] S150. Form a dielectric layer on the side of the semiconductor epitaxial layer away from the substrate; wherein, the dielectric layer includes a first dielectric layer.

[0086] S160. Etch the dielectric layer to form a first opening in the dielectric layer; the vertical projection of the first opening in the semiconductor epitaxial layer is located in the first region.

[0087] S170. Form an upper electrode on the side of the first dielectric layer away from the substrate; the upper electrode is electrically connected to the light-emitting structure through the first opening, and the upper electrode located in the second region is separated from the filling layer by the first dielectric layer.

[0088] Specifically, the upper electrode is disposed on the side of the first dielectric layer away from the substrate. The dielectric layer has a first opening in the first region, such that the upper electrode can contact the light-emitting structure located in the first region through the first opening, injecting current into the light-emitting structure while being isolated from the filling layer located in the non-light-emitting first region. Separating the upper electrode from the filling layer located in the trench by the first dielectric layer can prevent the metal in the trench from contacting and charging the upper electrode to generate heat when the material of the filling layer in the trench is a metal material, thereby improving the problem of temperature cycling caused by poor step coverage of the metal material in the trench resulting in holes formed in the metal in the trench, and further improving the reliability of the device. Moreover, it can also prevent a large capacitance from being formed due to the opposite polarity and close distance between the metal in the trench and the lower Bragg reflector, which affects the performance of a laser operating in a short-pulse mode.

[0089] The method for manufacturing a high-power vertical cavity surface emitting laser provided by the embodiments of the present invention can improve the flatness of the device by providing a filling layer in the trench; in addition, separating the upper electrode from the filling layer located in the trench by the first dielectric layer can prevent the metal in the trench from contacting and charging the upper electrode to generate heat compared with the prior art where part of the metal material for forming the upper electrode is formed in the trench, thereby improving the problem of temperature cycling caused by poor step coverage of the metal material in the trench resulting in holes formed in the metal in the trench, and further improving the reliability of the device. Moreover, it can also prevent a large capacitance from being formed due to the opposite polarity and close distance between the metal in the trench and the lower Bragg reflector, which affects the performance of a laser operating in a short-pulse mode.

[0090] Figure 9 It is a flowchart of another method for manufacturing a high-power vertical cavity surface emitting laser provided by the embodiments of the present invention; Figures 10 - 16 It is a sectional view of each step in steps S210 to S280 of a method for manufacturing a high-power vertical cavity surface emitting laser provided by the embodiments of the present invention. Refer to Figures 9 - 16 , the method for manufacturing a high-power vertical cavity surface emitting laser includes:

[0091] S210. Provide a substrate.

[0092] Specifically, refer to Figure 10, the substrate 10 can be any material suitable for forming a vertical cavity surface emitting laser, such as gallium arsenide (GaAs). The substrate 10 can be an N-type doped semiconductor substrate or a P-type doped semiconductor substrate 10. In this embodiment, the substrate 10 is an N-type doped semiconductor substrate 10. In some embodiments, the substrate 10 can be a semi-insulating substrate 10. In other embodiments, the substrate 10 can be a conductive substrate 10.

[0093] S220. Form a semiconductor epitaxial layer on one side of the substrate; the semiconductor epitaxial layer includes at least one first region and a second region disposed around the first region.

[0094] Specifically, continue to refer to Figure 10 , forming a semiconductor epitaxial layer 20 on one side of the substrate 10 includes successively forming a lower Bragg reflector 21, at least one active layer 22, and an upper Bragg reflector 23. Both the lower Bragg reflector 21 and the upper Bragg reflector 23 can be formed by laminating two materials with different refractive indices, namely an aluminum gallium arsenide material layer and a gallium arsenide material layer, or by laminating two materials with different refractive indices, namely a high aluminum component aluminum gallium arsenide material layer and a low aluminum component aluminum gallium arsenide material layer. The active layer 22 is composed of GaAs and AlGaAs, or InGaAs and AlGaAs material layers stacked and arranged, and the active layer 22 is used to convert electrical energy into light energy. When the active layer 22 is multiple layers, a tunnel junction is provided between two adjacent active layers 22 and is connected by the tunnel junction. In some embodiments, the lower Bragg reflector 21 and the upper Bragg reflector 23 can also be formed of other materials. The lower Bragg reflector 21 and the upper Bragg reflector 23 include a series of alternating layers of different refractive index materials, wherein the effective optical thickness (the layer thickness multiplied by the refractive index of the layer) of each alternating layer is an odd integer multiple of one-quarter of the operating wavelength of the vertical cavity surface emitting laser, that is, the effective optical thickness of each alternating layer is one-quarter of an odd integer multiple of the operating wavelength of the vertical cavity surface emitting laser.

[0095] S230. Etch the semiconductor epitaxial layer in the second region to form a trench; wherein, the semiconductor epitaxial layer in the first region is used to form a light emitting structure.

[0096] Specifically, refer to Figure 11 , use dry etching to etch the semiconductor epitaxial layer 20 in the second region to form a trench 201, thereby forming a light emitting mesa structure in the first region. The bottom of the trench 201 is etched at least to the lower Bragg reflector 21.

[0097] Refer to Figure 12, after forming the light-emitting structure in the first region, an oxidation confinement layer 202 is formed in the light-emitting structure; the oxidation confinement layer 202 has an opening for defining the light-emitting aperture Q1 of the light-emitting structure. In this embodiment, the sidewalls of the trench are oxidized by wet oxidation of highly aluminum-doped material under certain temperature conditions to form the oxidation confinement layer 202 within the upper Bragg reflector 23. The lengths of the oxidation confinement layers 202 on both sides of the trench 201 are equal. The formed aluminum oxide has a relatively high impedance, and the opening position of the oxidation confinement layer 202 is still the highly aluminum-doped aluminum gallium arsenide material. When current enters the light-emitting mesa structure, the current will flow through the opening in the oxidation confinement layer 202 to the active layer 22. In this embodiment, the oxidation confinement layer 202 in each light-emitting structure is a circular ring structure. When the top view of the light-emitting structure is rectangular, the oxidation confinement layer 202 can also be a rectangular ring.

[0098] S240. A second dielectric layer is formed on the side away from the substrate of the semiconductor epitaxial layer, as well as on the sidewalls and bottom of the trench.

[0099] Specifically, referring to Figure 13 , before forming the second dielectric layer 42, it further includes: forming an ohmic layer 60 on the surface of the semiconductor epitaxial layer 20 in the first region.

[0100] S250. A filling layer is formed in the trench.

[0101] Specifically, referring to Figure 14 , the filling layer 30 formed in the trench can be a dielectric layer or a material with high thermal conductivity such as a metal material. The metal material can be, for example, Cu or Au. Figure 14 In Figure 14 , the Cu filling layer 32 in is exemplarily drawn as a Cu filling layer 32. When the material Au is used as the material of the filling layer,

[0102] S260. The filling layer located at the hole edge of the trench is etched so that the difference between the distance from the surface of the filling layer on the side away from the substrate to the substrate and the distance from the surface of the second dielectric layer on the side away from the substrate to the substrate is less than a preset value.

[0103] Specifically, referring to Figure 15 , the filling layer 30 located at the hole edge of the trench is etched so that the difference between the distance from the surface of the filling layer 30 on the side away from the substrate 10 to the substrate 10 and the distance from the surface of the second dielectric layer 42 on the side away from the substrate 10 to the substrate 10 is less than a preset value. To increase the device density, after electroplating the metal material, an etching operation is used to etch away the Au / Cu that exceeds the trench, and only the part filling the hole is retained as much as possible to avoid affecting the spacing of other structures. When the filling layer 30 is a dielectric material, the dielectric material that exceeds the trench can also be etched away, and only the part filling the hole is retained as much as possible.

[0104] S270. Form a first dielectric layer on the side of the second dielectric layer away from the substrate.

[0105] Specifically, referring to Figure 16 , a first dielectric layer 41 is formed on the side of the second dielectric layer 42 away from the substrate 10. The material of the second dielectric layer 42 may be the same as or different from that of the first dielectric layer 41. Additionally, when the material of the filling layer 30 is a dielectric material, the materials of the three may be the same or different.

[0106] S280. Etch the first dielectric layer and the second dielectric layer to form a first opening penetrating through the first dielectric layer and the second dielectric layer.

[0107] Specifically, the vertical projection of the first opening in the semiconductor epitaxial layer is located in the first region.

[0108] S290. Form an upper electrode on the side of the first dielectric layer away from the substrate; the upper electrode is electrically connected to the light-emitting structure through the first opening and the second opening, and the upper electrode located in the second region is separated from the filling layer by the first dielectric layer. (Specifically, refer to Figure 6 )

[0109] Wherein, when the material of the filling layer 30 includes a metal material, forming the filling layer 30 in the trench includes: after depositing a seed metal, electroplating Cu or Au to form the filling layer 30. When the material of the filling layer 30 includes a dielectric material, forming the filling layer 30 in the trench includes: depositing a nitride or an oxide in the trench to form the filling layer 30. Among them, if electroplated gold is used for filling the hole, the seed metal can be selected to deposit TiW, etc. by PVD process. If the filling metal is Cu, the seed layer metal can be deposited by ALD or PVD process, such as TiN or Ru, etc.

[0110] When the material filled in the trench is a metal material, a second dielectric layer 42 needs to be provided in the high-power vertical cavity surface emitting laser to prevent the metal layer in the trench from directly connecting the upper Bragg reflector 23 and the lower Bragg reflector 21, causing a short circuit to the high-power vertical cavity surface emitting laser and affecting the normal light emission of the active layer 22. When the material filled in the trench is a dielectric material, a second dielectric layer 42 may or may not be provided between the semiconductor epitaxial layer 20 and the first dielectric layer 41, as well as on the sidewalls and bottom of the trench.

[0111] It should be noted that the preparation method of the high-power vertical cavity surface emitting laser described in any of the above embodiments is part of the device processing flow, mainly reflecting the technical solution of the present application, and other procedures or processes known in the art for manufacturing this device are omitted.

[0112] Note that the above is only a preferred embodiment of the present invention and the technical principles applied. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein. Various obvious changes, re-adjustments, and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments. Without departing from the concept of the present invention, it can also include more other equivalent embodiments, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A high-power vertical cavity surface emitting laser, characterized in that, Comprising: A substrate; A semiconductor epitaxial layer located on one side of the substrate; the semiconductor epitaxial layer includes at least one first region and a second region disposed around the first region; The first region has at least one light-emitting structure; the second region has a trench; A filling layer filled in the trench; A dielectric layer, the dielectric layer includes a first dielectric layer located on the side of the semiconductor epitaxial layer away from the substrate; wherein, a first opening is included in the dielectric layer; the vertical projection of the first opening on the semiconductor epitaxial layer is located in the first region; An upper electrode located on the side of the first dielectric layer away from the substrate; the upper electrode is electrically connected to the light-emitting structure through the first opening, and the upper electrode located in the second region and the filling layer are separated by the first dielectric layer.

2. The high-power vertical cavity surface emitting laser according to claim 1, characterized in that, The difference between the distance from the surface of the filling layer away from the substrate to the substrate and the distance from the surface of the semiconductor epitaxial layer away from the substrate to the substrate is less than a preset value.

3. The high-power vertical cavity surface emitting laser according to claim 1, characterized in that, The material of the filling layer includes a metal material or a dielectric material.

4. The high-power vertical cavity surface emitting laser according to claim 3, wherein The metal material includes Au or Cu; the dielectric material includes a nitride or an oxide.

5. The high-power vertical cavity surface emitting laser according to claim 1, wherein Along the direction from the second region to the first region, the width of the trench is less than or equal to 4 um; The depth-to-width ratio of the trench is greater than or equal to 2.

6. The high-power vertical cavity surface emitting laser according to claim 1, wherein The shape of the trench is annular; the annular trench is disposed around the light-emitting structure; Or, the shape of the trench is pore-shaped; A plurality of pore-shaped trenches are disposed around the light-emitting structure.

7. The high-power vertical cavity surface emitting laser according to claim 3, wherein The dielectric layer further includes: A second dielectric layer, the second dielectric layer is located between the semiconductor epitaxial layer and the first dielectric layer, and on the sidewalls and bottom of the trench; Wherein, the dielectric layer includes a first opening, the first opening penetrates through the first dielectric layer and the second dielectric layer; the upper electrode is electrically connected to the light-emitting structure through the first opening.

8. The high-power vertical cavity surface emitting laser according to claim 1, wherein The semiconductor epitaxial layer includes a lower Bragg reflector, an upper Bragg reflector, and at least one active layer located between the lower Bragg reflector and the upper Bragg reflector; wherein, the lower Bragg reflector is closer to the substrate; At least one oxidation confinement layer is included in the active layer located in the first region for carrier confinement.

9. A method for preparing a high-power vertical cavity surface emitting laser, characterized in that, Comprising: Providing a substrate; Forming a semiconductor epitaxial layer on one side of the substrate; The semiconductor epitaxial layer includes at least one first region and a second region disposed around the first region; Etching the semiconductor epitaxial layer in the second region to form a trench; wherein, the semiconductor epitaxial layer located in the first region is used to form a light-emitting structure; Forming a filling layer in the trench; Forming a dielectric layer on the side of the semiconductor epitaxial layer away from the substrate; wherein, the dielectric layer includes a first dielectric layer; Etch the dielectric layer to form a first opening therein; a vertical projection of the first opening on the semiconductor epitaxial layer is located in the first region; Form an upper electrode on a side of the first dielectric layer away from the substrate; the upper electrode is electrically connected to the light-emitting structure through the first opening, and the first dielectric layer separates the upper electrode located in the second region from the filling layer.

10. The method for preparing a high-power vertical cavity surface emitting laser according to claim 9, wherein The material of the filling layer includes a metal material; forming the filling layer in the trench includes: After depositing seed metal, electroplate Cu or Au to form the filling layer; Alternatively, the material of the filling layer includes a dielectric material; forming the filling layer in the trench includes: Deposit a nitride or an oxide in the trench to form the filling layer.

11. The method for manufacturing a high-power vertical cavity surface emitting laser according to claim 9, before forming the filling layer in the trench, further comprising: Form a dielectric layer between the semiconductor epitaxial layer and the first dielectric layer and on sidewalls and a bottom of the trench; wherein forming the dielectric layer further includes forming a second dielectric layer, the second dielectric layer being located between the semiconductor epitaxial layer and the first dielectric layer and on sidewalls and a bottom of the trench; Etching the dielectric layer includes: Etch the first dielectric layer and the second dielectric layer to form a first opening penetrating the first dielectric layer and the second dielectric layer.

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