Dual current protection circuit of USB current limiting switch

Abstract

The invention relates to the field of short-circuit protection of load switches, in particular to a dual-current protection circuit of a USB current-limiting switch, which comprises a current bias module, a boost clamping unit, an initialization module, an overcurrent protection module, a short-circuit protection module, a control module, an output power MOS tube, an output current induction MOS tube, an induction current detection resistor, a load resistor RL and a load capacitor CL. When a capacitive load hot plug event occurs in the load, the output power MOS tube quickly responds to reduce Vout to the voltage of the load capacitor CL and limit the peak current, and enters a current limiting mode until the load capacitor CL is charged; when the load is short-circuited, the output power MOS tube quickly responds to limit the peak current and automatically retries; and when the load is slowly increased to cause an overcurrent event of output, the output power MOS tube enters a current limiting mode, so that a reasonable protection response is made for transient impact of hot plugging of the capacitive load.

Description

Technical Field

[0001] The present invention relates to the field of short - circuit protection of load switches, and particularly to a dual - current protection circuit for a USB current - limiting switch. Background Art

[0002] Short - circuit protection of load switches is crucial for the safe operation of electrical systems. Its core objective is to quickly cut off the current when a short - circuit occurs, preventing equipment damage and safety accidents. First, determine the protection requirements based on the load type (such as resistive, inductive, capacitive) and system parameters (rated voltage, current). For resistive loads, the current increases sharply during a short - circuit, and a fuse or circuit breaker is required for instantaneous protection; for inductive loads, due to the presence of inductive energy storage, the current rises slowly but lasts for a long time during a short - circuit, and a protection device with a delay characteristic is needed; for capacitive loads, high - frequency oscillations may occur during a short - circuit, and a filter circuit and a fast - response surge protector are required.

[0003] Among them, the USB current - limiting switch is a key component integrated in the USB power management circuit. Its core function is to prevent equipment damage or safety hazards caused by over - current or short - circuit by real - time monitoring and dynamic adjustment of the output current. When a device is connected to the USB interface, the current - limiting switch starts to supply power and simultaneously starts current monitoring. If the current exceeds the set value, the chip will quickly respond and dynamically adjust the current by reducing the conduction degree of the MOSFET to bring it back within the safe range. Some high - end chips also have a soft - start function, which can suppress the inrush current during hot - plugging of the device and prevent instantaneous overload.

[0004] However, after a short - circuit event occurs in an ordinary load switch, it can only rely on static protection to enter the constant - current mode, and cannot make a reasonable protection response to the transient impact of capacitive load hot - plugging, nor can it provide a reasonable, safe, and reliable current protection response for the capacitive load application of the power switch. Summary of the Invention

[0005] The purpose of the present invention is to provide a dual - current protection circuit for a USB current - limiting switch, aiming to improve the problem that the conventional protection circuit cannot make a reasonable protection response to the transient impact of capacitive load hot - plugging and cannot provide a reasonable, safe, and reliable current protection response for the capacitive load application of the power switch.

[0006] To achieve the above purpose, the present invention adopts the following technical solutions: A dual - current protection circuit for a USB current - limiting switch, comprising a current biasing module, a boost clamping unit, an initialization module, an over - current protection module, a short - circuit protection module, a control module, an output power MOS transistor PowerFET, an output current sensing MOS transistor SenseFET, a sensing current detection resistor Rsense, a load resistor RL, and a load capacitor CL; The external power supply VIN is electrically connected to the drain of the output power MOS transistor PowerFET, one end of the sense current detection resistor Rsense, the current bias module, the boost clamping unit, the initialization module, the overcurrent protection module, and the short-circuit protection module; The other end of the sense current detection resistor Rsense is electrically connected to the drain of the output current sensing MOS transistor SenseFET, the first input terminal of the overcurrent protection module, and the first input terminal of the short-circuit protection module. The current bias module outputs a bias current to the first input terminal of the initialization module, the second input terminal of the overcurrent protection module, and the second input terminal of the short-circuit protection module. The output terminal of the initialization module is electrically connected to the overcurrent protection module. The output terminal of the overcurrent protection module is electrically connected to the first input terminal of the control module. The output terminal of the short-circuit protection module is electrically connected to the third input terminal of the overcurrent protection module, the second input terminal of the initialization module, and the second input terminal of the control module. The output terminals of the control module and the boost clamping unit are both electrically connected to the gates of the output power MOS transistor PowerFET and the output current sensing MOS transistor SenseFET. The source of the output power MOS transistor PowerFET and the source of the output current sensing MOS transistor SenseFET are respectively electrically connected to one end of the load resistor RL and one end of the load capacitor CL, and Vout is output to the external load; The substrates of the output power MOS transistor PowerFET, the output current sensing MOS transistor SenseFET, the other end of the load resistor RL, and the other end of the load capacitor CL are all grounded.

[0007] Further, the current bias module includes an operational amplifier OP101, MOS transistors P101, P102, P103, N101, N102, N103, N104, N105, and resistors R101, R102; The external power supply VIN is electrically connected to the sources and substrates of the MOS transistors P101, P102, and P103. The gate and drain of the MOS transistor P101 are both electrically connected to the gates of the MOS transistors P102, P103, and the drain of the MOS transistor N101; The external reference voltage VREF is electrically connected to the inverting input terminal of the operational amplifier OP101. The output terminal of the operational amplifier OP101 is electrically connected to the gate of the MOS transistor N101. The source of the MOS transistor N101 is electrically connected to one end of the resistor R101 and the non-inverting input terminal of the operational amplifier OP101. The other end of the resistor R101 is electrically connected to one end of the resistor R102; The drain of the MOS transistor P102 outputs a bias current I bias1 to the overcurrent protection module and the short-circuit protection module; The drain of the MOS transistor P103 is electrically connected to the gates and drains of the MOS transistors N102 and N104. The source of the MOS transistor N102 is electrically connected to the gates and drains of the MOS transistors N103 and N105. The drain of the MOS transistor N104 outputs a bias current I bias2 to the initialization module; The other end of the resistor R102, the substrates of the MOS transistors N101, N102, N103, N104, and N105, and the sources and substrates of the MOS transistors N103, N104, and N105 are all grounded.

[0008] Furthermore, the following conditions are satisfied (W / L) P101 :(W / L) P102 :(W / L) P103 =2:1:1; (W / L) P102 :(W / L) P104 =1:1; (W / L) P103 :(W / L) P105 =1:1; wherein, (W / L) Pn is the aspect ratio of the MOS transistor Pn, that is, (W / L) P101 is the aspect ratio of the MOS transistor P101; (W / L) P102 is the aspect ratio of the MOS transistor P102; (W / L) P103 is the aspect ratio of the MOS transistor P103; (W / L) P104 is the aspect ratio of the MOS transistor P104; (W / L) P105 is the aspect ratio of the MOS transistor P105.

[0009] Furthermore, the boost clamping unit includes a charge pump boost module and a clamping module The external power supply VIN is electrically connected to the power input terminal of the charge pump boost module; The output terminal of the charge pump boost module outputs a V gate voltage to the input terminal of the clamping module, the gate of the output power MOS transistor PowerFET, and the gate of the output current sensing MOS transistor SenseFET. The output terminal of the clamping module is electrically connected to the load.

[0010] Further, the charge pump boost module includes MOS transistor P201 and resistor R201, and at least includes transistor Q201, transistor Q202, transistor Q203, transistor Q204, transistor Q205, transistor Q206, transistor Q207, capacitor C201, capacitor C202, capacitor C203, capacitor C204, capacitor C205 and inverters INV200, INV201, INV202, INV203, INV204, INV205; The external power supply VIN is electrically connected to the source and substrate of MOS transistor P201, the external enable signal EN is electrically connected to the gate of MOS transistor P201, and the external clock signal CLK is electrically connected to the positive terminal of inverter INV200; The drain of MOS transistor P201 is electrically connected to the collector, base and one end of capacitor C201 of transistor Q201. The negative terminal of inverter INV200 is electrically connected to the positive terminal of inverter INV201. The negative terminal of inverter INV201 is electrically connected to the other end of capacitor C201 and the positive terminal of inverter INV202. The negative terminal of inverter INV202 is electrically connected to one end of capacitor C202 and the positive terminal of inverter INV203. The negative terminal of inverter INV203 is electrically connected to one end of capacitor C203 and the positive terminal of inverter INV204. The negative terminal of inverter INV204 is electrically connected to one end of capacitor C204 and the positive terminal of inverter INV205. The negative terminal of inverter INV205 is electrically connected to one end of capacitor C205; The emitter of transistor Q201 is electrically connected to the collector, base and the other end of capacitor C202 of transistor Q202. The emitter of transistor Q202 is electrically connected to the collector, base and the other end of capacitor C203 of transistor Q203. The emitter of transistor Q203 is electrically connected to the collector, base and the other end of capacitor C204 of transistor Q204. The emitter of transistor Q204 is electrically connected to the collector, base and the other end of capacitor C205 of transistor Q205. The emitter of transistor Q205 is electrically connected to the collector, base of transistor Q206. The emitter of transistor Q206 is electrically connected to the collector, base of transistor Q207. The emitter of transistor Q207 is electrically connected to one end of resistor R201, and the other end of resistor R201 outputs V gate voltage to the input terminal of the clamping module, the gate of the output power MOS transistor PowerFET and the gate of the output current sensing MOS transistor SenseFET.

[0011] Further, the clamping module includes a triode Q208, and at least includes MOS transistors P202, P203, P204, P205, P206, and P207; The external power supply VIN is electrically connected to the substrates of the MOS transistors P202, P203, P204, P205, P206, and P207; The collector and base of the triode Q208 are both electrically connected to the output terminal of the charge pump boost module; The emitter of the triode Q208 is electrically connected to the source of the MOS transistor P202, and the gate and drain of the MOS transistor P202 are both electrically connected to the source of the MOS transistor P203; the gate and drain of the MOS transistor P203 are both electrically connected to the source of the MOS transistor P204; the gate and drain of the MOS transistor P204 are both electrically connected to the source of the MOS transistor P205; the gate and drain of the MOS transistor P205 are both electrically connected to the source of the MOS transistor P206; the gate and drain of the MOS transistor P206 are both electrically connected to the source of the MOS transistor P207; the gate and drain of the MOS transistor P207 are both connected to the load.

[0012] Further, the initialization module includes inverters INV309, INV310, INV311, MOS transistors P310, P311, P312, P313, P314, P315, P316, P317, P318, P319, P320, MOS transistors N316, N317, N318, N319, N320, N321, N322, N323, N324, N325, N326, a triode Q301, and a capacitor C301; The external power supply VIN is electrically connected to the sources, substrates of the MOS transistors P310, P311, P312, P313, the substrate of the MOS transistor P314, the sources, substrates of the MOS transistors P315, P316, P317, P318, P319, P320; The current bias module outputs a bias current to the gates, drains of MOS transistor P310, the gate of MOS transistor P311, and the gate of MOS transistor P315; the drain of MOS transistor P311 is electrically connected to the drain, gate of MOS transistor N316, and the gate of MOS transistor N22; the external enable signal EN is electrically connected to the gates of MOS transistor P312, MOS transistor P313, MOS transistor N317, and MOS transistor N318; the drain of MOS transistor P312 is electrically connected to the drain of MOS transistor N317, the gate of MOS transistor P319, and the gate of MOS transistor N326; The drain of MOS transistor P313 is electrically connected to the source of MOS transistor P314, and the output terminal of the short - circuit protection module is electrically connected to the gate of MOS transistor P314 and the gate of MOS transistor P319; the drain of MOS transistor P314 is electrically connected to the drain of MOS transistor N318, the drain of MOS transistor N319, and the positive terminal of inverter INV309; The drain of MOS transistor P315 is electrically connected to the drain of MOS transistor N320, one end of capacitor C301, the collector of transistor Q301, and the gate of MOS transistor P316; the negative terminal of inverter INV309 is electrically connected to the gates of MOS transistor N320 and MOS transistor N321, and the drain of MOS transistor N321 is electrically connected to the other end of capacitor C301 and the base of transistor Q301; The drain of MOS transistor P316 is electrically connected to the positive terminal of inverter INV310 and the drain of MOS transistor N322, the negative terminal of inverter INV310 is electrically connected to the positive terminal of inverter INV311, and the negative terminal of inverter INV is electrically connected to the gates of MOS transistor P318 and MOS transistor N323; The drain of MOS transistor P317 is electrically connected to the drains of MOS transistor P318, MOS transistor N323, the gate of MOS transistor P320, and the gate of MOS transistor N325, and the source of MOS transistor N323 is electrically connected to the drain of MOS transistor N324; The drain of MOS transistor P320 is electrically connected to the drains of MOS transistor P319, MOS transistor N325, the gate of MOS transistor P317, and the gate of MOS transistor N324, and outputs the initialization signal INIT to the over - current protection module and the short - circuit protection module; the source of MOS transistor N325 is electrically connected to the drain of MOS transistor N326; The source and substrate of MOS transistor N316, the source and substrate of MOS transistor N317, the source and substrate of MOS transistor N318, the source and substrate of MOS transistor N319, the source and substrate of MOS transistor N320, the source and substrate of MOS transistor N321, the source and substrate of MOS transistor N322, the source and substrate of MOS transistor N323, the substrate of MOS transistor N324, the source and substrate of MOS transistor N325, the substrate of MOS transistor N326, and the emitter of transistor Q301 are all grounded.

[0013] Furthermore, it further includes a reference module, which includes MOS transistors N301, N302, N303, N304, P301, and at least includes resistors R300, R301, R302, and fuses Fuse301, Fuse302; The short - circuit protection module includes MOS transistors P302, P303, P304, N305, N306, Ndep301, and inverters INV301, INV302, INV303, INV304; The over - current protection module includes MOS transistors P305, P306, P307, P308, N307, N308, N309, N310, N311, inverters INV305, INV306, INV307, INV308, and resistor R303; The control module includes MOS transistors P309, N312, N313, and N315; The external power supply VIN is electrically connected to the substrate of MOS transistor P301, the substrate of MOS transistor P302, the substrate of MOS transistor P303, the source and substrate of MOS transistor P304, the substrate of MOS transistor P305, the source and substrate of MOS transistor P306, the source and substrate of MOS transistor P307, the source and substrate of MOS transistor P308, the substrate of MOS transistor P309, and the source and substrate; The current bias module outputs a bias current to the gates and drains of MOS transistor N301, the gates and drains of MOS transistor N303, the gates and drains of MOS transistor N305, and the gate of MOS transistor N307; the source of MOS transistor N301 is electrically connected to the gates and drains of MOS transistor N302, the gates of MOS transistor N304, the gates of MOS transistor N306, the gates of MOS transistor N308, and the gate of MOS transistor N309; the source of MOS transistor N303 is electrically connected to the drain of MOS transistor N304, and the drain of MOS transistor N303 is electrically connected to the gates and drains of MOS transistor P301, the gate of MOS transistor P302, and the gate of MOS transistor P305; the resistors R300, R301, and R302 are connected in series between the source of MOS transistor P301 and the external power supply VIN, both ends of the fuse Fuse301 are electrically connected to both ends of the resistor R301, and both ends of the fuse Fuse302 are electrically connected to both ends of the resistor R302; The other end of the sense current detection resistor Rsense is electrically connected to the source of MOS transistor P302 and one end of the resistor R303; the drain of MOS transistor P302 is electrically connected to the source of MOS transistor P303 and the gate of MOS transistor P304; the gate of MOS transistor P303 is electrically connected to the drain of MOS transistor P304 and the positive pole of the inverter INV301; the drain of MOS transistor P303 is electrically connected to the drain of MOS transistor N305; the source of MOS transistor N305 is electrically connected to the drain of MOS transistor N306; the drain of MOS transistor P304 is electrically connected to the drain of MOS transistor Ndep301; The negative pole of the inverter INV301 is electrically connected to the positive pole of the inverter INV302; the negative pole of the inverter INV302 is electrically connected to the positive pole of the inverter INV303; the negative pole of the inverter INV303 is electrically connected to the positive pole of the inverter INV304; the negative pole of the inverter INV304 outputs a short - circuit protection signal SCP to the gates of MOS transistor N310 and MOS transistor N315; The other end of the resistor R303 is electrically connected to the source of MOS transistor P305; the drain of MOS transistor P305 is electrically connected to the gates of MOS transistor P306, MOS transistor P307, the drain of MOS transistor N307, and the gate of MOS transistor P309; the source of MOS transistor N307 is electrically connected to the drain of MOS transistor N308; the drain of MOS transistor P306 is electrically connected to the drains of MOS transistor N309, MOS transistor P308, the drain of MOS transistor N310, the drain of MOS transistor N311, and the positive pole of the inverter INV305; The drain of the MOS transistor P307 is electrically connected to the source of the MOS transistor P308. The gate of the MOS transistor P308 is electrically connected to the negative pole of the inverter INV305 and the positive pole of the inverter INV306. The negative pole of the inverter INV306 is electrically connected to the positive pole of the inverter INV307. The negative pole of the inverter INV307 is electrically connected to the positive pole of the inverter INV308. The negative pole of the inverter INV308 outputs an overcurrent protection signal OCP to the gate of the MOS transistor N313. The output terminal of the initialization module is electrically connected to the gate of the MOS transistor N311; The drain of the MOS transistor P309 is electrically connected to the gate and drain of the MOS transistor N312 and the gate of the MOS transistor N314. The source of the MOS transistor N313 is electrically connected to the drain of the MOS transistor N314. The drains of the MOS transistor N313 and the MOS transistor N315 are both electrically connected to the gate of the output power MOS transistor PowerFET and the gate of the output current sensing MOS transistor SenseFET; The substrates of the MOS transistors N301, the sources and substrates of the MOS transistors N302, the substrates of the MOS transistors N303, the sources and substrates of the MOS transistors N304, the substrates of the MOS transistors N305, the sources and substrates of the MOS transistors N306, the gates, sources and substrates of the MOS transistor Ndep, the substrates of the MOS transistors N307, the sources and substrates of the MOS transistors N308, the sources and substrates of the MOS transistors N309, the sources and substrates of the MOS transistors N310, the sources and substrates of the MOS transistors N311, the sources and substrates of the MOS transistors N312, the substrates of the MOS transistors N313, the sources and substrates of the MOS transistors N314, and the sources and substrates of the MOS transistors N315 are all grounded.

[0014] Furthermore, the following conditions are satisfied. (W / L) P310 : (W / L) P311 : (W / L) P315 = 10:1:1; Wherein, (W / L) Pn is the aspect ratio of the MOS transistor Pn, that is, (W / L) P310 is the aspect ratio of the MOS transistor P310; (W / L) P311 is the aspect ratio of the MOS transistor P311; (W / L) P315 is the aspect ratio of the MOS transistor P315.

[0015] Furthermore, the following conditions are satisfied. (W / L) N301 : (W / L) N303 : (W / L) N305 : (W / L) N307= 1:2:4:2; (W / L) N302 :(W / L) N304 :(W / L) N306 :(W / L) N308 :(W / L) N309 = 1:2:4:2:n; (W / L) P301 :(W / L) P302 :(W / L) P305 = 4:8:4; Among them, (W / L) Pn is the width-to-length ratio of MOS transistor Pn, that is, (W / L) P301 is the width-to-length ratio of MOS transistor P301; (W / L) P302 is the width-to-length ratio of MOS transistor P302; (W / L) P305 is the width-to-length ratio of MOS transistor P305; (W / L) Nn is the width-to-length ratio of MOS transistor Nn, that is, (W / L) N301 is the width-to-length ratio of MOS transistor N301; (W / L) N302 is the width-to-length ratio of MOS transistor N302; (W / L) N303 is the width-to-length ratio of MOS transistor N303; (W / L) N304 is the width-to-length ratio of MOS transistor N304; (W / L) N305 is the width-to-length ratio of MOS transistor N305; (W / L) N306 is the width-to-length ratio of MOS transistor N306; (W / L) N307 is the width-to-length ratio of MOS transistor N307; (W / L) N308 is the width-to-length ratio of MOS transistor N308; (W / L) N309 is the width-to-length ratio of MOS transistor N309, and n is a proportionality coefficient greater than zero.

[0016] After adopting the above technical solution, compared with the background technology, the present invention has the following advantages: 1. When a capacitive load hot plug event occurs in the load, the output power MOS transistor PowerFET quickly responds to reduce Vout to the voltage of the load capacitor CL and limit the peak current, and enters the current limiting mode until the load capacitor CL is fully charged; when a short circuit event occurs in the load, the output power MOS transistor PowerFET quickly responds to limit the peak current and automatically retry; when the load slowly increases and causes an overcurrent event in the output, the output power MOS transistor PowerFET enters the current limiting mode until the external load reduces the output current below the current limiting value, realizing a reasonable protection response to the transient impact of capacitive load hot plug and providing a reasonable, safe and reliable current protection response.

[0017] 2. The output terminal of the initialization module is electrically connected to the overcurrent protection module and the short-circuit protection module. When the load switch starts the device, the overcurrent protection module is disabled by the initialization module for a period of time to prevent the inrush current from causing the overcurrent protection module to be mis-triggered and resulting in startup failure. In this case, the short-circuit protection module provides protection under extreme conditions to prevent the load from being damaged and enhance the robustness of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is the circuit block diagram of the dual current protection circuit of the USB current limiting switch described in the present invention; Figure 2 It is the circuit diagram of the current biasing module of the dual current protection circuit of the USB current limiting switch described in the present invention; Figure 3 It is the circuit diagram of the boost clamping unit of the dual current protection circuit of the USB current limiting switch described in the present invention; Figure 4 It is the circuit diagram of the initialization module of the dual current protection circuit of the USB current limiting switch described in the present invention; Figure 5 It is the circuit diagram of the overcurrent protection module, short-circuit protection module and control module of the dual current protection circuit of the USB current limiting switch described in the present invention; Figure 6 It is the simulation diagram of the overcurrent threshold IOCP and short-circuit threshold ISCP of the dual current protection circuit of the USB current limiting switch described in the present invention based on Condition 1; Figure 7 It is the manifestation of the overcurrent threshold IOCP and short-circuit threshold ISCP on the output current sensing MOSFET SenseFET of the dual current protection circuit of the USB current limiting switch described in the present invention based on Condition 1; Figure 8 It is the manifestation of the overcurrent threshold IOCP and short-circuit threshold ISCP on the output current sensing MOSFET SenseFET of the dual current protection circuit of the USB current limiting switch described in the present invention based on Condition 2; Figure 9 It is the simulation diagram of the hot plugging of a 100 mF capacitor with an initial voltage of 0 V by the dual current protection circuit of the USB current limiting switch described in the present invention; Figure 10 It is the simulation diagram of the hot plugging of a 10 mF capacitor with an initial voltage of 2.5 V by the dual current protection circuit of the USB current limiting switch described in the present invention; Figure 11 It is the simulation diagram of the current limiting value IOS of the dual current protection circuit of the USB current limiting switch described in the present invention based on Condition 1; Figure 12The simulation curve of the current limiting value IOS when the fuse sets the resistor R300 to 11R on the basis of Condition 1 for the dual current protection circuit of the USB current limiting switch described in the present invention; Figure 13 For the dual current protection circuit I of the USB current limiting switch described in the present invention BIAS1 When it is a low temperature drift current, it is the simulation curve of the current limiting value IOS. Specific embodiments

[0019] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0020] In addition, it should be noted that: the terms "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are all based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element of the present invention must have a specific orientation, so it cannot be understood as a limitation to the present invention.

[0021] When an element is referred to as being "fixed to" or "disposed on" or "provided on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0022] Unless otherwise clearly defined and limited, the terms "installation", "connection", and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the invention can be understood according to specific circumstances. Embodiment

[0023] Please refer to Figures 1-13 As shown, this embodiment provides a dual current protection circuit for a USB current limiting switch. Please refer to Figure 1 As shown, it includes a current bias module, a boost clamping unit, an initialization module, an overcurrent protection module, a short circuit protection module, a control module, an output power MOS transistor PowerFET, an output current sensing MOS transistor SenseFET, and a sensing current detection resistor Rsense.

[0024] The external power supply VIN is electrically connected to the drain of the output power MOS tube PowerFET, one end of the inductive current detection resistor Rsense, the current bias module, the boost clamping unit, the initialization module, the overcurrent protection module, and the short-circuit protection module. The other end of the inductive current detection resistor Rsense is electrically connected to the drain of the output current sensing MOS tube SenseFET, the first input end of the overcurrent protection module, and the first input end of the short-circuit protection module. The current bias module outputs the bias current to the first input end of the initialization module, the second input end of the overcurrent protection module, and the second input end of the short-circuit protection module. The output end of the initialization module is electrically connected to the overcurrent protection module. The output end of the overcurrent protection module is electrically connected to the first input end of the control module, the output end of the short-circuit protection module is electrically connected to the third input end of the overcurrent protection module, the second input end of the initialization module, and the second input end of the control module, and the output end of the control module and the output end of the boost clamping unit are both electrically connected to the gate of the output power MOS tube PowerFET and the gate of the output current sensing MOS tube SenseFET. The source of the output power MOS tube PowerFET and the source of the output current sensing MOS tube SenseFET are electrically connected to one end of the load resistor RL and one end of the load capacitor CL respectively, and output Vout to the external load; the substrate of the output power MOS tube PowerFET, the substrate of the output current sensing MOS tube SenseFET, the other end of the load resistor RL and the other end of the load capacitor CL are all grounded. The output current sensing MOS tube SenseFET and the sensing current detection resistor Rsense constitute an output current detection circuit to sample the output current and output it to the overcurrent protection module and the short-circuit protection module to determine whether there is an overcurrent or short-circuit situation.

[0025] When a capacitive load hot-plug event occurs, the output power MOS tube PowerFET responds quickly to reduce Vout to the load capacitor CL voltage and limit the peak current, and enters the current limiting mode until the load capacitor CL is fully charged; when a short circuit event occurs in the load, the output power MOS tube PowerFET responds quickly to limit the peak current and automatically retries; that is, when the short circuit protection is triggered, it automatically restarts and tries to recover. If the short circuit state is removed, normal operation is restored. If the short circuit state still exists, the output power MOS tube PowerFET enters the current limiting working state. When the load increases slowly and an overcurrent event occurs at the output, the output power MOS tube PowerFET enters the current limiting mode until the external load causes the output current to drop below the current limiting value, so as to make a reasonable protection response to the transient impact of capacitive load hot plugging, and provide a reasonable, safe and reliable current protection response.

[0026] Further, the output terminal of the initialization module is electrically connected to the overcurrent protection module and the short-circuit protection module. When the load switch starts the device, the overcurrent protection module is disabled by the initialization module for a period of time to prevent the inrush current from causing the overcurrent protection module to be mis-triggered and resulting in startup failure. During this period, the short-circuit protection module provides protection in extreme cases to avoid load damage and enhance the robustness of the system.

[0027] Please refer to Figure 2 As shown, specifically, the current bias module includes operational amplifier OP101, MOS transistor P101, MOS transistor P102, MOS transistor P103, MOS transistor N101, MOS transistor N102, MOS transistor N103, MOS transistor N104, MOS transistor N105, and resistors R101 and R102.

[0028] The external power supply VIN is electrically connected to the source and substrate of MOS transistor P101, the source and substrate of MOS transistor P102, and the source and substrate of MOS transistor P103. The gate and drain of MOS transistor P101 are both electrically connected to the gate of MOS transistor P102, the gate of MOS transistor P103, and the drain of MOS transistor N101.

[0029] The external reference voltage VREF is electrically connected to the inverting input terminal of operational amplifier OP101. The output terminal of operational amplifier OP101 is electrically connected to the gate of MOS transistor N101. The source of MOS transistor N101 is electrically connected to one end of resistor R101 and the non-inverting input terminal of operational amplifier OP101. The other end of resistor R101 is electrically connected to one end of resistor R102. The drain of MOS transistor P102 outputs the bias current I bias1 to the overcurrent protection module and the short-circuit protection module. The drain of MOS transistor P103 is electrically connected to the gate, drain of MOS transistor N102, and the gate of MOS transistor N104. The source of MOS transistor N102 is electrically connected to the gate, drain of MOS transistor N103, and the gate of MOS transistor N105. The drain of MOS transistor N104 outputs the bias current I bias2 to the initialization module. The other end of resistor R102, the substrate of MOS transistor N101, the substrate of MOS transistor N102, the source and substrate of MOS transistor N103, the substrate of MOS transistor N104, and the source and substrate of MOS transistor N105 are all grounded.

[0030] The operational amplifier OP101, MOS transistor P101, MOS transistor N101, and resistors R101 and R102 form a low-dropout linear regulator to provide a stable voltage for the subsequent circuit.

[0031] Further, and satisfy the following conditions, (W / L) P101 :(W / L) P102:(W / L) P103 =2:1:1; (W / L) P102 (W / L) P104 =1:1; (W / L) P103 (W / L) P105 =1:1; Among them, (W / L) Pn is the width-to-length ratio of MOS transistor Pn, that is, (W / L) P101 is the width-to-length ratio of MOS transistor P101; (W / L) P102 is the width-to-length ratio of MOS transistor P102; (W / L) P103 is the width-to-length ratio of MOS transistor P103; (W / L) P104 is the width-to-length ratio of MOS transistor P104; (W / L) P105 is the width-to-length ratio of MOS transistor P105. And in this embodiment, resistor R101 and resistor R102 are negative temperature coefficient resistor and positive temperature coefficient resistor respectively.

[0032] Using the negative feedback of operational amplifier OP101 makes VFB1 virtually short to reference voltage VREF, so that VFB1 = VREF. It can be obtained that the bias current generated by the current bias module is I P101 =I N101 =VFB1 / (R101 + R102); Setting appropriate ratios for resistor R101 and resistor R102 can obtain a current with a smaller temperature coefficient; where I pn is the current magnitude of MOS transistor Pn, I Nn is the current magnitude of MOS transistor Nn, that is, I P101 is the current magnitude of MOS transistor P101, I N101 is the current magnitude of MOS transistor N101.

[0033] In this embodiment, (W / L) P101 (W / L) P102 (W / L) P103 =2:1:1; Then according to the MOS transistor saturation region current formula, the current ratios of these MOS transistors are I P101 :I P102 :I P103 =2:1:1. In this embodiment, (W / L) P102 (W / L) P104 =1:1; (W / L) P103 (W / L) P105 =1:1; Since I N102 =I N103 =I P103 So similarly, I N102 :IN103 : I N104 : I N105 = 1:1:1:1.

[0034] Thus, it can be obtained that I BIAS1 = I BIAS2 = 0.5 * VFB1 / (R101 + R102); wherein R101 and R102 are the resistance values of resistor R101 and resistor R102 respectively.

[0035] Please refer to Figure 3 as shown. Further, the boost clamping unit includes a charge pump boost module and a clamping module. The external power supply VIN is electrically connected to the power input terminal of the charge pump boost module. The output terminal of the charge pump boost module outputs V gate voltage to the input terminal of the clamping module, the gate of the output power MOS transistor PowerFET, and the gate of the output current sensing MOS transistor SenseFET. The output terminal of the clamping module is electrically connected to the load.

[0036] Specifically, the charge pump boost module includes MOS transistor P201 and resistor R201, and at least includes transistor Q201, transistor Q202, transistor Q203, transistor Q204, transistor Q205, transistor Q206, transistor Q207, capacitor C201, capacitor C202, capacitor C203, capacitor C204, capacitor C205, and inverters INV200, INV201, INV202, INV203, INV204, INV205.

[0037] The external power supply VIN is electrically connected to the source and substrate of MOS transistor P201. The external enable signal EN is electrically connected to the gate of MOS transistor P201. The external clock signal CLK is electrically connected to the positive electrode of inverter INV200.

[0038] The drain of MOS transistor P201 is electrically connected to the collector, base of transistor Q201, and one end of capacitor C201. The negative terminal of inverter INV200 is electrically connected to the positive terminal of inverter INV201. The negative terminal of inverter INV201 is electrically connected to the other end of capacitor C201 and the positive terminal of inverter INV202. The negative terminal of inverter INV202 is electrically connected to one end of capacitor C202 and the positive terminal of inverter INV203. The negative terminal of inverter INV203 is electrically connected to one end of capacitor C203 and the positive terminal of inverter INV204. The negative terminal of inverter INV204 is electrically connected to one end of capacitor C204 and the positive terminal of inverter INV205. The negative terminal of inverter INV205 is electrically connected to one end of capacitor C205. Further, in this embodiment, the charge pump boost module further includes transistor Qy, capacitor Cy, and inverter INVy, where y is an integer greater than 208.

[0039] And the emitter of transistor Qy is electrically connected to the base and collector of transistor Q206. The base and collector of transistor Qy are electrically connected to one end of capacitor Cy and the emitter of transistor Q(y - 1). The other end of capacitor Cy is electrically connected to the negative terminal of inverter INVy. The positive terminal of inverter INVy is electrically connected to the negative terminal of inverter INV(y - 1) and one end of capacitor C(y - 1).

[0040] The emitter of transistor Q201 is electrically connected to the collector, base of transistor Q202, and the other end of capacitor C202. The emitter of transistor Q202 is electrically connected to the collector, base of transistor Q203, and the other end of capacitor C203. The emitter of transistor Q203 is electrically connected to the collector, base of transistor Q204, and the other end of capacitor C204. The emitter of transistor Q204 is electrically connected to the collector, base of transistor Q205, and the other end of capacitor C205. The emitter of transistor Q205 is electrically connected to the collector, base of transistor Q206. The emitter of transistor Q206 is electrically connected to the collector, base of transistor Q207. The emitter of transistor Q207 is electrically connected to one end of resistor R201, and the other end of resistor R201 outputs V gate voltage to the input terminal of the clamping module, the gate of the output power MOS transistor PowerFET, and the gate of the output current sensing MOS transistor SenseFET.

[0041] Specifically, the clamping module includes transistor Q208 and at least includes MOS transistors P202, P203, P204, P205, P206, P207.

[0042] The external power supply VIN is electrically connected to the substrates of MOS transistors P202, P203, P204, P205, P206, and P207. The collector and base of transistor Q208 are both electrically connected to the output terminal of the charge pump boost module, that is, the collector and base of transistor Q208 are both electrically connected to the other end of resistor R201.

[0043] The emitter of transistor Q208 is electrically connected to the source of MOS transistor P202, and the gate and drain of MOS transistor P202 are both electrically connected to the source of MOS transistor P203; the gate and drain of MOS transistor P203 are both electrically connected to the source of MOS transistor P204; the gate and drain of MOS transistor P204 are both electrically connected to the source of MOS transistor P205; the gate and drain of MOS transistor P205 are both electrically connected to the source of MOS transistor P206; the gate and drain of MOS transistor P206 are both electrically connected to the source of MOS transistor P207; the gate and drain of MOS transistor P207 are both connected to the load. Further, in this embodiment, the clamping module further includes MOS transistor Px, where x is an integer greater than 207. And, the substrate of MOS transistor Px is connected to the external power supply VIN, the base and drain of MOS transistor Px are connected to the external load, and the source of MOS transistor Px is electrically connected to the base and drain of MOS transistor P(x - 1).

[0044] After the external enable signal EN is enabled, MOS transistor P201 is turned on. When the inverter connected to the capacitor outputs a logic zero, these capacitors are charged by the charge sent by the power supply or the previous stage pump. When the inverter outputs a logic high, these capacitors pump charge to the subsequent stage through the rectifier transistor. Finally, the charge accumulates to the gate of the output power MOS transistor PowerFET through resistor R201 to make V gate rise; When the gate voltage of the output power MOS transistor PowerFET rises to exceed the set V gate0 later: V gate0 =V out +V BE208 +V THP202 +V THP203 +V THP204 +V THP205 +V THP206 +V THP207 +V THPx ; Among them, V BEn is the threshold voltage of transistor Qn, that is, V BE208 is the threshold voltage of transistor Q208; V THPn is the threshold voltage of MOS transistor Pn, that is, V THP202is the threshold voltage of MOS transistor P202, V THP203 is the threshold voltage of MOS transistor P203, V THP204 is the threshold voltage of MOS transistor P204, V THP205 is the threshold voltage of MOS transistor P205, V THP206 is the threshold voltage of MOS transistor P206, V THP207 is the threshold voltage of MOS transistor P207, V THPx is the threshold voltage of MOS transistor Px.

[0045] The gate charge of the output power MOS transistor PowerFET will be discharged to the VOUT terminal through the clamping module, so that the gate voltage of the output power MOS transistor PowerFET is stabilized at Vgate0. Finally, the output power MOS transistor PowerFET operates in the linear region to supply power to the load, that is V gate0 -V out >V in -V out .

[0046] Please refer to Figure 4 As shown, specifically, the initialization module includes inverter INV309, inverter INV310, inverter INV311, MOS transistor P310, MOS transistor P311, MOS transistor P312, MOS transistor P313, MOS transistor P314, MOS transistor P315, MOS transistor P316, MOS transistor P317, MOS transistor P318, MOS transistor P319, MOS transistor P320, MOS transistor N316, MOS transistor N317, MOS transistor N318, MOS transistor N319, MOS transistor N320, MOS transistor N321, MOS transistor N322, MOS transistor N323, MOS transistor N324, MOS transistor N325, MOS transistor N326, triode Q301 and capacitor C301.

[0047] The external power supply VIN is electrically connected to the source and substrate of MOS transistor P310, the source and substrate of MOS transistor P311, the source and substrate of MOS transistor P312, the source and substrate of MOS transistor P313, the substrate of MOS transistor P314, the source and substrate of MOS transistor P315, the source and substrate of MOS transistor P316, the source and substrate of MOS transistor P317, the source and substrate of MOS transistor P318, the source and substrate of MOS transistor P319, the source and substrate of MOS transistor P320.

[0048] The current bias module outputs a bias current to the gate and drain of MOS transistor P310, the gate of MOS transistor P311 and the gate of MOS transistor P315; that is, the drain of MOS transistor N104 outputs a bias current I bias2To the gates of MOS transistor P310, the drain of MOS transistor P310, the gate of MOS transistor P311, and the gate of MOS transistor P315. The drain of MOS transistor P311 is electrically connected to the drain, gate of MOS transistor N316, and the gate of MOS transistor N22. The external enable signal EN is electrically connected to the gates of MOS transistor P312, MOS transistor P313, MOS transistor N317, and MOS transistor N318; the drain of MOS transistor P312 is electrically connected to the drain of MOS transistor N317, the gate of MOS transistor P319, and the gate of MOS transistor N326.

[0049] The drain of MOS transistor P313 is electrically connected to the source of MOS transistor P314, and the output terminal of the short - circuit protection module is electrically connected to the gates of MOS transistor P314 and MOS transistor P319; the drain of MOS transistor P314 is electrically connected to the drain of MOS transistor N318, the drain of MOS transistor N319, and the positive electrode of inverter INV309.

[0050] The drain of MOS transistor P315 is electrically connected to the drain of MOS transistor N320, one end of capacitor C301, the collector of triode Q301, and the gate of MOS transistor P316; the negative electrode of inverter INV309 is electrically connected to the gates of MOS transistor N320 and MOS transistor N321, and the drain of MOS transistor N321 is electrically connected to the other end of capacitor C301 and the base of triode Q301.

[0051] The drain of MOS transistor P316 is electrically connected to the positive electrode of inverter INV310 and the drain of MOS transistor N322, the negative electrode of inverter INV310 is electrically connected to the positive electrode of inverter INV311, and the negative electrode of inverter INV is electrically connected to the gates of MOS transistor P318 and MOS transistor N323.

[0052] The drain of MOS transistor P317 is electrically connected to the drains of MOS transistor P318, MOS transistor N323, the gate of MOS transistor P320, and the gate of MOS transistor N325. The source of MOS transistor N323 is electrically connected to the drain of MOS transistor N324.

[0053] The drain of MOS transistor P320 is electrically connected to the drains of MOS transistor P319, MOS transistor N325, the gate of MOS transistor P317, and the gate of MOS transistor N324, and outputs the initialization signal INIT to the over - current protection module and the short - circuit protection module; the source of MOS transistor N325 is electrically connected to the drain of MOS transistor N326.

[0054] The sources and substrates of MOS transistor N316, the sources and substrates of MOS transistor N317, the sources and substrates of MOS transistor N318, the sources and substrates of MOS transistor N319, the sources and substrates of MOS transistor N320, the sources and substrates of MOS transistor N321, the sources and substrates of MOS transistor N322, the sources and substrates of MOS transistor N323, the sources and substrates of MOS transistor N324, the sources and substrates of MOS transistor N325, the sources and substrates of MOS transistor N326, and the emitter of triode Q301 are all grounded.

[0055] Please refer to Figure 5 As shown, further, it further includes a reference module, and the reference module includes MOS transistor N301, MOS transistor N302, MOS transistor N303, MOS transistor N304, MOS transistor P301, and at least includes resistor R300, resistor R301, resistor R302, and fuses Fuse301 and Fuse302.

[0056] The short - circuit protection module includes MOS transistor P302, MOS transistor P303, MOS transistor P304, MOS transistor N305, MOS transistor N306, MOS transistor Ndep301, and inverters INV301, INV302, INV303, and INV304.

[0057] The over - current protection module includes MOS transistor P305, MOS transistor P306, MOS transistor P307, MOS transistor P308, MOS transistor N307, MOS transistor N308, MOS transistor N309, MOS transistor N310, MOS transistor N311, inverters INV305, INV306, INV307, INV308, and resistor R303.

[0058] The control module includes MOS transistor P309, MOS transistor N312, MOS transistor N313, and MOS transistor N315.

[0059] The external power supply VIN is electrically connected to the substrates of MOS transistor P301, the substrates of MOS transistor P302, the substrates of MOS transistor P303, the sources and substrates of MOS transistor P304, the substrates of MOS transistor P305, the sources and substrates of MOS transistor P306, the sources and substrates of MOS transistor P307, the substrates of MOS transistor P308, and the sources and substrates of MOS transistor P309.

[0060] The current bias module outputs a bias current to the gates and drains of MOS transistor N301, the gates and drains of MOS transistor N303, the gates and drains of MOS transistor N305, the gates of MOS transistor N307; that is, the drain of MOS transistor P102 outputs a bias current I bias1To the gates, drains of MOS transistor N301, the gates, drains of MOS transistor N303, the gates, drains of MOS transistor N305, and the gate of MOS transistor N307. The source of MOS transistor N301 is electrically connected to the gates, drains of MOS transistor N302, the gates of MOS transistor N304, the gates of MOS transistor N306, the gates of MOS transistor N308, and the gate of MOS transistor N309. The source of MOS transistor N303 is electrically connected to the drain of MOS transistor N304, and the drain of MOS transistor N303 is electrically connected to the gates, drains of MOS transistor P301, the gate of MOS transistor P302, and the gate of MOS transistor P305. Resistors R300, R301, and R302 are connected in series between the source of MOS transistor P301 and the external power supply VIN in sequence. Both ends of fuse Fuse301 are electrically connected to both ends of resistor R301, and both ends of fuse Fuse302 are electrically connected to both ends of resistor R302.

[0061] Furthermore, in this embodiment, the reference module further includes resistor Rq and fuse Fuseq, where q is an integer greater than 302. Specifically, resistors R300, R301, R302,..., resistor R(q - 1), and resistor Rq are connected in series between the source of MOS transistor P301 and the external power supply VIN in sequence. Both ends of fuse Fuse(q - 1) and both ends of fuse Fuseq are electrically connected to both ends of resistor R(q - 1) and resistor Rq respectively. By adjusting the number of fuses Fuseq, the number and resistance values of resistors Rq in the reference module, the ISCP short - circuit threshold, the IOCP over - current threshold, and the IOS current - limiting value are adjusted.

[0062] The other end of the inductive current detection resistor Rsense is electrically connected to the source of MOS transistor P302 and one end of resistor R303. The drain of MOS transistor P302 is electrically connected to the source of MOS transistor P303 and the gate of MOS transistor P304. The gate of MOS transistor P303 is electrically connected to the drain of MOS transistor P304 and the positive terminal of inverter INV301. The drain of MOS transistor P303 is electrically connected to the drain of MOS transistor N305. The source of MOS transistor N305 is electrically connected to the drain of MOS transistor N306. The drain of MOS transistor P304 is electrically connected to the drain of MOS transistor Ndep301. In this embodiment, MOS transistor Ndep301 is a depletion - type NMOS transistor.

[0063] The negative electrode of inverter INV301 is electrically connected to the positive electrode of inverter INV302, the negative electrode of inverter INV302 is electrically connected to the positive electrode of inverter INV303, the negative electrode of inverter INV303 is electrically connected to the positive electrode of inverter INV304, and the negative electrode of inverter INV304 outputs a short-circuit protection signal SCP to the gates of MOS transistor N310, MOS transistor P314, MOS transistor N315, and MOS transistor P319.

[0064] The other end of resistor R303 is electrically connected to the source electrode of MOS transistor P305, and the drain electrode of MOS transistor P305 is electrically connected to the gates of MOS transistor P306, MOS transistor P307, the drain electrode of MOS transistor N307, and the gate of MOS transistor P309; the source electrode of MOS transistor N307 is electrically connected to the drain electrode of MOS transistor N308; the drain electrode of MOS transistor P306 is electrically connected to the drain electrodes of MOS transistor N309, MOS transistor P308, MOS transistor N310, MOS transistor N311, and the positive electrode of inverter INV305.

[0065] The drain electrode of MOS transistor P307 is electrically connected to the source electrode of MOS transistor P308, the gate of MOS transistor P308 is electrically connected to the negative electrode of inverter INV305 and the positive electrode of inverter INV306, the negative electrode of inverter INV306 is electrically connected to the positive electrode of inverter INV307, the negative electrode of inverter INV307 is electrically connected to the positive electrode of inverter INV308, and the negative electrode of inverter INV308 outputs an over-current protection signal OCP to the gate of MOS transistor N313. The output end of the initialization module is electrically connected to the gate of MOS transistor N311; that is, the drain electrode of MOS transistor P320 outputs an initialization signal INIT to the gate of MOS transistor N311.

[0066] The drain electrode of MOS transistor P309 is electrically connected to the gate, drain electrode of MOS transistor N312, and the gate of MOS transistor N314, the source electrode of MOS transistor N313 is electrically connected to the drain electrode of MOS transistor N314, and the drain electrodes of MOS transistor N313 and MOS transistor N315 are both electrically connected to the gates of the output power MOS transistor PowerFET and the output current sensing MOS transistor SenseFET.

[0067] The substrates of MOS transistor N301, the sources and substrates of MOS transistor N302, the substrate of MOS transistor N303, the sources and substrates of MOS transistor N304, the substrate of MOS transistor N305, the sources and substrates of MOS transistor N306, the gate, source and substrate of MOS transistor Ndep, the substrate of MOS transistor N307, the sources and substrates of MOS transistor N308, the sources and substrates of MOS transistor N309, the sources and substrates of MOS transistor N310, the sources and substrates of MOS transistor N311, the sources and substrates of MOS transistor N312, the substrate of MOS transistor N313, the sources and substrates of MOS transistor N314, and the sources and substrates of MOS transistor N315 are all grounded.

[0068] The NAND gate (nand1) formed by MOS transistors P317, P318, N323 and N324 and the NAND gate (nand2) formed by P319, P320, N325 and N326 constitute a latch; MOS transistors N301, N302, N303, N304, N305, N306, N307, N308, N309 constitute a current mirror circuit.

[0069] The initialization module satisfies the following conditions, (W / L) P310 :(W / L) P311 :(W / L) P315 = 10:1:1; Among them, (W / L) Pn is the aspect ratio of MOS transistor Pn, that is, (W / L) P310 is the aspect ratio of MOS transistor P310; (W / L) P311 is the aspect ratio of MOS transistor P311; (W / L) P315 is the aspect ratio of MOS transistor P315. According to the MOS transistor saturation region current formula, it can be obtained that I P310 : I P311 : I P315 = 10:1:1, That is I P315 = I N322 = I BIAS2 / 10 = 0.5 * VFB1 / 10 * (R101 + R102); When the external enable signal EN inputs a logic high, that is, when the chip is not enabled, the RESET terminal of the latch is at logic zero, so the initialization signal INIT outputs a logic high to turn on MOS transistor N311 to disable the overcurrent protection module.

[0070] When the external enable signal EN inputs a logic zero, that is, when the chip is enabled, since the short-circuit protection signal SCP outputs a logic zero when the short-circuit protection is not triggered, MOS transistor P314 is turned on and MOS transistor N319 is turned off. Therefore, the inverter INV309 outputs a logic zero, that is, MOS transistors N320 and N321 are turned off. MOS transistor P315 charges capacitor C301, and the charging current is the magnitude of the base current of transistor Q301. When the voltage of the upper plate of capacitor C301 can make the current generated by MOS transistor P316 less than I N322 When, the SET signal flips from logic high to logic zero, causing the initialization signal INIT to output a logic zero to turn off MOS transistor N311, and the initialization is completed, enabling the overcurrent protection module.

[0071] According to the capacitor charging formula ΔT = ΔV / I, the initialization duration can be obtained as: T INIT =(VIN - VTHP - VBE)*C301 / IQ301_B IQ301_B≈I P301 / β_Q301 Where, VTHP is the threshold voltage of the PMOS transistor, VBE is the voltage difference between the base and emitter of the transistor, IQ301_B is the base current of transistor Q301, β_Q301 is the DC current gain of transistor Q301, and β≈Ic / Ib.

[0072] Since the latch has the function of latching the output signal, after the initialization is completed, even if the signal at the SET terminal changes, the latch output still maintains the previous state, unless the external enable signal EN flips the signal at the RESET terminal of the latch to logic zero to reset the latch output INIT signal to logic high.

[0073] Furthermore, the short-circuit protection module and the overcurrent protection module satisfy the following conditions, (W / L) N301 :(W / L) N303 :(W / L) N305 :(W / L) N307 =1:2:4:2; (W / L) N302 :(W / L) N304 :(W / L) N306 :(W / L) N308 :(W / L) N309 =1:2:4:2:n; (W / L) P301 :(W / L) P302 :(W / L) P305 =4:8:4; Where, (W / L)Pn is the aspect ratio of MOS transistor Pn, i.e., (W / L) P301 is the aspect ratio of MOS transistor P301; (W / L) P302 is the aspect ratio of MOS transistor P302; (W / L) P305 is the aspect ratio of MOS transistor P305.

[0074] (W / L) Nn is the aspect ratio of MOS transistor Nn, i.e., (W / L) N301 is the aspect ratio of MOS transistor N301; (W / L) N302 is the aspect ratio of MOS transistor N302; (W / L) N303 is the aspect ratio of MOS transistor N303; (W / L) N304 is the aspect ratio of MOS transistor N304; (W / L) N305 is the aspect ratio of MOS transistor N305; (W / L) N306 is the aspect ratio of MOS transistor N306; (W / L) N307 is the aspect ratio of MOS transistor N307; (W / L) N308 is the aspect ratio of MOS transistor N308; (W / L) N309 is the aspect ratio of MOS transistor N309, where n is a proportionality coefficient greater than zero.

[0075] According to the MOS transistor saturation region current formula, the current ratios of MOS transistors N301, N303, N305, and N307 are I N301 : I N303 : I N305 : I N307 = 1:2:4:2.

[0076] The current ratios of MOS transistors N302, N304, N306, N308, and N309 are I N302 : I N304 : I N306 : I N308 : I N309 = 1:2:4:2:n.

[0077] And I N301 = I N302 = I BIAS1 , Then I N303 = I N304 = 2*I BIAS1 ; I N305 = I N306 = 4*I BIAS1; I N307 = I N308 = 2 * I BIAS1 ; I N309 = n * I BIAS1 。

[0078] In this embodiment, the size ratio of the output power MOS transistor PowerFET to the output current sensing MOS transistor SenseFET is: (W / L)powerFET:(W / L)senseFET = 938:1.

[0079] The MOS transistor P301 is connected in the form of a diode, and the current in this branch is 2 * I BAS1 , and V SET = VIN - R300 * 2 * I BIAS1 , where V SET is the voltage of the SET point. The MOS transistor P301, the MOS transistor P302, and the MOS transistor P305 form a current mirror. According to the MOS transistor saturation region current formula, we can get Id = 0.5 * Cox * μp * (W / L) * (VSG - VTHP) 2 ; where Id is the current in the MOS transistor carrier channel, that is, the current between the MOS source and drain. The current magnitude is the electric charge passing through the cross-section of the conductor per unit time; Cox is the gate oxide capacitance per unit area; μp is the electron mobility of the PMOS transistor, VSG is the MOS transistor gate-source voltage, and VTHP is the threshold voltage of the PMOS transistor.

[0080] As can be seen from the above, when the VSG of the MOS transistors P301, P302, and P305 are equal, the replicated current is I P302 = 4 * I BIAS1 = I N305 = I N306 ; I P305 = 2 * I BIAS1 = I N307 = I N308 。

[0081] The output current of the output power MOS transistor PowerFET is Iout, and the output current sensing MOS transistor SenseFET samples the current Isense. When Isense flows through the sense current detection resistor Rsense, the voltage of the output current sensing MOS transistor SenseFET is Vsense = VIN - Rsense * Isense ≈ VIN - Rsense * Iout / 938, Where Rsense is the resistance value of the sense current detection resistor Rsense.

[0082] When different currents flow through the VOUT terminal for Vsense and VFB3, corresponding voltages will be generated. Then the VSGs of MOS transistors P302 and P305 are respectively VSG_P302 = Vsense - VG_P301 = VIN - Rsense * IOUT / 938 - VG_P301; VSG_P305 = Vsense - VR303 - VG_P301 = VIN - Rsense * IOUT / 938 - R303 * 2 * I BIAS1 - VG_P301; Where, VG_P301 is the gate voltage of MOS transistor P301, VR303 is the voltage value of resistor R303, and Vsense is the voltage difference between the power supply voltage minus the current Isense induced by the output current sensing MOS transistor SenseFET and loaded on the sense current detection resistor Rsense.

[0083] When Vsense > V SET According to the MOS transistor current formula, we can get I P302 > I N305 .

[0084] Then MOS transistor P302 enters the linear region. At this time, the voltage of node A is approximately equal to the Vsense voltage, MOS transistor P304 is cut off, and the short - circuit protection signal SCP outputs a low level. When I OUT increases to make Vsense = V SET , according to the MOS transistor current formula, we know that I P302 = I P301 = 2 * I BIAS1 , At this time, the voltage VA of node A is equal to the voltage VC of node C. Since VC ≥ VTHP, MOS transistor P304 conducts and induces a current. This current I P304 flows through MOS transistor Ndep301. The current formula when the depletion - type transistor is saturated is: INdep301 = 0.5 * Cox * μdep * (W / L)dep301 * (0 - VTHdep) 2 ; Where, μdep is the electron mobility of the depletion - type transistor; (W / L)dep301 is the width - to - length ratio of MOS transistor Ndep301, and VTHdep is the threshold voltage of the depletion - type MOS transistor.

[0085] Combined with the saturation condition formula of the depletion-type MOS transistor VGS - VTHdep > 0V, it can be known that When I P304 The induced current is exactly equal to I Ndep301 At this time, the drain voltage of the MOS transistor Ndep301 is exactly equal to (-VTHdep) = 0.6V.

[0086] When I P304 Continues to increase, then the drain voltage of the MOS transistor Ndep301 will also continue to increase, and the MOS transistor P303 feeds back this change from the gate to the source to node A. Therefore, the voltage of node A and the drain voltage of the MOS transistor Ndep301 will finally stabilize due to this negative feedback loop. By setting the loop condition and the threshold of the inverter INV301, signal inversion can be achieved before this loop stabilizes.

[0087] The overcurrent protection principle is the same as the above. Among them, when the B node voltage VB of the MOS transistor P305 is equal to the C node voltage VC of the MOS transistor P301, VFB3 needs to subtract the voltage of V R303 That is, VFB3 = Vsense - VR303 = V SET .

[0088] Please refer to Figures 6-8 As shown, conduct experimental simulation based on condition 1. Among them, condition 1 is that the resistance R300 = 10R, the resistance R303 = 5R, the induced current detection resistance Rsense = 0.02R, and I BIAS1 = 1.75uA.

[0089] Among them, Figure 6 Is the simulation diagram of the overcurrent threshold IOCP and the short-circuit threshold ISCP based on condition 1. It can be seen from Figure 6 That under the conditions of this circuit setting, IOCP ≈ 1.6A and ISCP ≈ 3.2A.

[0090] The short-circuit threshold ISCP and the overcurrent threshold IOCP can be adjusted by the fuse. Specifically, Assume that the current induced by the MOS transistor P304 is exactly I Ndep301 When it is large, the short-circuit protection is triggered, then I P304 = I Ndep301 = C = 0.5 * Cox * μp * (W / L) P304 *(VAa - VTHP) 2 .

[0091] It can be seen from this that when the protection is triggered at node A with VAa, at this time VAa = VCa, and it can be obtained that at this time V sensea = VSETa ; When increasing R300a to R300b through a fuse, assuming the change amount ΔR300 before and after R300 is very small, V SET From V SETa = VIN - R300a * 2I BIAS1 Decreases to V SETb = VIN - R300b * 2I BIAIS1 .

[0092] If the MOS transistor P304 wants to induce the same magnitude of current, the voltage at node A also needs to reach the previous VAa. Under condition B, I P302 and I N305 When balanced again, VA will decrease by 2I BIAIS1 *ΔR300 on the basis of VAa. For convenience of calculation, ignoring the influence of this part on VA, then the voltage at node A at this time VAb≈VAa = VCa, where a and b are stage coefficients, that is, when the voltage at node A is VAa, the protection is triggered, and VAa = VCa, which is the a stage. When increasing R300a to R300b through a fuse, it is the b stage. Then I P302 = I N305 , Therefore, only when V senseb = V SETb can we have VAb = VAa = VCa, and V senseb = VIN - Rsense * I sense_scpb , where, I sense_scpb is the induced current magnitude of the current sensing MOS transistor SenseFET that can make V senseb reach the trigger condition in the b stage.

[0093] From this, we can get: V senseb = VIN - Rsense * I sense_scpb = V SETb = VIN - R300b * 2I BIAIS1 .

[0094] The I out at this time is: I sense_scpb =(R300b * 2I BIAIS1 ) / Rsense; Since R300b > R300a, when the protection is triggered, the corresponding I sense_scpb also increases, and the specific increased value is: ΔI sense =(ΔR300 * 2I BIAIS1 ) / Rsense Similarly, the over - current threshold is as follows: Before trimming, VFB3a = V SETa , that is VIN - Rsense * I sense_ocpa - R303 * 2 IBIAIS1 = VIN - R300a * 2 IBIAIS1 ; I sense_ocpa =[(R300a - R303) * 2 IBIAIS1 / Rsense.

[0095] Among them, I sense_scpa is the induced current magnitude of the current - sensing MOSFET SenseFET that can make V senseb reach the trigger condition in stage a.

[0096] After trimming, VFB3b = V SETb , that is VIN - Rsense * I sense_ocpb - R303 * 2I BIAIS1 = VIN - R300b * 2I BIAIS1 ; I sense_ocpb =[(R300b - R303) * 2I BIAIS1 / Rsense.

[0097] Combining I sense_ocpa and I sense_ocpb , we can get ΔI sense_ocp =(ΔR300 * 2I BIAIS1 ) / Rsense And the I out at this time is: I out ≈938 * Rsense.

[0098] Based on condition two, experimental simulations are carried out. Among them, R300 is trimmed to R300 = 11R, R303 = 5R, Rsense = 0.02R, IBIAS1 = 1.75uA by fusing the fuse. Please refer to Appendix Figure 7 , where Appendix Figure 7 is the manifestation of the over - current threshold IOCP and the short - circuit threshold ISCP on the output current - sensing MOSFET SenseFET based on condition one. Under condition one, IOCP = 1.6A, ISCP = 3.2A, corresponding to I sense_cop = 1.465mA, I sense_scp= 2.94 mA.

[0099] Please refer to the attached Figure 8 , the attached Figure 8 is the manifestation of the overcurrent threshold IOCP and the short - circuit threshold ISCP on the output - current - sensing MOSFET SenseFET based on Condition 2.

[0100] Substitute the adjusted parameters into: ΔI sense =(ΔR300 * 2I BIAIS1 ) / Rsense =(11R - 10R) * 2 * 1.75 μA / 0.02R = 0.175 mA From Figure 8 it can be obtained that ΔI sense_ocp = 0.169 mA, ΔI sense_scp = 0.181 mA; the simulation and calculation data are basically the same.

[0101] After the short - circuit protection module is triggered, the short - circuit protection signal SCP outputs a logic high, turning on the MOSFET N315. The MOSFET N315 quickly releases the charge on the Vgate voltage with an extremely low on - resistance, and the Vgate voltage rapidly decreases, causing the I OUT current to become smaller. This enables the short - circuit protection module to recover immediately. During this period, the short - circuit current will exist briefly for a certain time, that is, there is a t IOS time. After that, if the short - circuit event is still not resolved, the load switch will enter the current - limiting mode to limit the output current to IOS, where IOS is the saturation current of the output - power MOSFET PowerFET in the constant - current state.

[0102] For the short - circuit response to the hot - plugging event of capacitive loads, please refer to Figures 9-13 as shown, where the attached Figure 9 is the simulation diagram of hot - plugging a 100 - mF capacitor with an initial voltage of 0 V, and the attached Figure 10 is the simulation diagram of hot - plugging a 10 - mF capacitor with an initial voltage of 2.5 V.

[0103] From the attached Figure 9 and the attached Figure 10 it can be seen that when a capacitive load is connected instantaneously, the load switch will reduce the VOUT voltage to the capacitor voltage. This response causes the output current to short - circuit, triggering the fast - acting short - circuit protection. After the short - circuit current exists briefly for the Tios time, the load switch enters the current - limiting mode to charge the capacitor until the charging is complete.

[0104] After the over - current protection is triggered, the over - current protection signal OCP outputs a logic high, turning on the MOSFET N313, causing the charge on the Vgate to be discharged at I N314The current magnitude is released, the Vgate voltage decreases, thereby reducing IOUT, and this protection has a hysteresis amount through the MOS transistor N306. Therefore, when I OUT decreases, the overcurrent protection module does not release immediately like the short-circuit protection module. At this time, when I OUT decreases, it drives I sense to decrease. Through the sense current detection resistor Rsense, this change is transmitted to the source of the MOS transistor P305, causing the voltage VFB3 to increase. Through the common-gate MOS transistor P305, this change is amplified to the B node, the gate voltage of the MOS transistor P307 increases, and the current induced by the MOS transistor P307 decreases, that is, the discharge current I N314 of Vgate decreases. And Vgate is constantly charged by the charge pump boost module. Eventually, the charging speed of the charge pump boost module balances with the discharging speed of the MOS transistor N314 to make Vgate stable. The stabilized Vgate voltage makes the output power MOS transistor PowerFET in the saturation region, providing a constant current IOS for the load.

[0105] Under ideal conditions, let the balance point of the current-limiting negative feedback loop be V SET = VFB3; 2 * I BIAS1 * R300 = 2 * I BIAS1 * R303 + I sense * Rsense.

[0106] That is: 2 * I BIAS1 * R300 = 2 * I BIAS1 * R303 + I out * Rsense / 938 That is: I out = [(2 * I BIAS1 * R300 - 2 * I BIAS1 * R303) / Rsense] * 938 It can be seen from this that IOS is only related to the resistance quantization ratio.

[0107] Among them, the V gate voltage determines the currents of the output power MOS transistor PowerFET and the output current sensing MOS transistor SenseFET. The Isense current determines the magnitude of the Vsense voltage; the Vsense voltage is transmitted to the B node through the resistor R303 and the MOS transistor P305. The voltage of the B node is transmitted to the drain of the MOS transistor N312 through the MOS transistor P309. The drain voltage of the MOS transistor N312 is transmitted back to the V gate voltage through the MOS transistors N314 and N313, forming the above-mentioned current-limiting negative feedback loop, that is, Vgate The voltage change affects the currents of the output power MOSFET (PowerFET) and the output current sensing MOSFET (SenseFET). The above balance means that the Vsense voltage feedback makes MOSFET N314 and MOSFET N313 pair for V gate The speed at which the voltage discharges the charge is equal to the speed at which the boost clamping unit supplies the charge.

[0108] For the actual circuit, there will be a certain deviation in the specific value of IOS according to the loop settings, because it is impossible to ensure that VFB3 = V SET When MOSFET P307 senses the discharge speed exactly equal to the charging speed of the charge pump boost module at, so the deviation can only be minimized as much as possible.

[0109] Please refer to Appendix Figure 11 , Appendix Figure 11 is the simulation diagram of the current limiting value IOS on the basis of Condition 1. As can be seen from Appendix Figure 11 it is known that substituting I BIAS1 = 1.75uA, resistor R300 = 10R, resistor R303 = 5R, Rsense = 0.02R into the formula of IOS, we can get IOS = [(2 * 1.75uA * 10 * R - 2 * 1.75uA * 5 * R) / 0.02 * R] * 938 = 0.82075A, The simulation example diagram shows that when the load switch VOUT is short-circuited, IOS ≈ 0.824A, which is basically consistent with the calculation.

[0110] Please refer to Appendix Figure 12 , Appendix Figure 12 is the simulation curve diagram of the current limiting value IOS when the resistor R300 is set to 11R through a fuse on the basis of Condition 1. As can be seen from Appendix Figure 12 it is known that substituting I BIAS1 = 1.75uA, resistor R300 = 11R, resistor R303 = 5R, Rsense = 0.02R into the formula of IOS, we can get IOS = [(2 * 1.75uA * 11 * R - 2 * 1.75uA * 5 * R) / 0.02 * R] * 938 = 0.9849A, The simulation example diagram shows that when the load switch VOUT is short-circuited, IOS ≈ 0.979A, which is basically consistent with the calculation.

[0111] Please refer to Appendix Figure 13 , Appendix Figure 13 is for I BIAS1 When it is a low-temperature drift current, it is the simulation curve diagram of the current limiting value IOS. As can be seen from the formula, when I BIAS1 is a low-temperature drift current, IOS also has the characteristic of being less affected by temperature, which is consistent with Appendix Figure 13The simulation results are in agreement.

[0112] As described above, the above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A dual current protection circuit for a USB current limiting switch, characterized in that, It includes a current bias module, a boost clamping unit, an initialization module, an overcurrent protection module, a short-circuit protection module, a control module, an output power MOS transistor PowerFET, an output current sensing MOS transistor SenseFET, a sensing current detection resistor Rsense, a load resistor RL, and a load capacitor CL; The external power supply VIN is electrically connected to the drain of the output power MOS transistor PowerFET, one end of the sensing current detection resistor Rsense, the current bias module, the boost clamping unit, the initialization module, the overcurrent protection module, and the short-circuit protection module; The other end of the sensing current detection resistor Rsense is electrically connected to the drain of the output current sensing MOS transistor SenseFET, the first input terminal of the overcurrent protection module, and the first input terminal of the short-circuit protection module. The current bias module outputs a bias current to the first input terminal of the initialization module, the second input terminal of the overcurrent protection module, and the second input terminal of the short-circuit protection module. The output terminal of the initialization module is electrically connected to the overcurrent protection module. The output terminal of the overcurrent protection module is electrically connected to the first input terminal of the control module. The output terminal of the short-circuit protection module is electrically connected to the third input terminal of the overcurrent protection module, the second input terminal of the initialization module, and the second input terminal of the control module. The output terminals of the control module and the boost clamping unit are both electrically connected to the gates of the output power MOS transistor PowerFET and the output current sensing MOS transistor SenseFET. The sources of the output power MOS transistor PowerFET and the output current sensing MOS transistor SenseFET are respectively electrically connected to one end of the load resistor RL and one end of the load capacitor CL, and Vout is output to an external load; The substrates of the output power MOS transistor PowerFET, the output current sensing MOS transistor SenseFET, the other end of the load resistor RL, and the other end of the load capacitor CL are all grounded.

2. The dual current protection circuit of the USB current limiting switch according to claim 1, characterized in that: The current bias module includes an operational amplifier OP101, MOS transistors P101, P102, P103, N101, N102, N103, N104, N105, and resistors R101, R102; The external power supply VIN is electrically connected to the sources and substrates of MOS transistors P101, P102, and P103. The gate and drain of MOS transistor P101 are both electrically connected to the gates of MOS transistors P102, P103, and the drain of MOS transistor N101; The external reference voltage VREF is electrically connected to the inverting input terminal of the operational amplifier OP101. The output terminal of the operational amplifier OP101 is electrically connected to the gate of MOS transistor N101. The source of MOS transistor N101 is electrically connected to one end of resistor R101 and the non-inverting input terminal of the operational amplifier OP101. The other end of resistor R101 is electrically connected to one end of resistor R102; The drain output bias current I of MOS transistor P102 bias1 is sent to the overcurrent protection module and the short-circuit protection module; The drain of MOS transistor P103 is electrically connected to the gates and drains of MOS transistor N102 and the gate of MOS transistor N104. The source of MOS transistor N102 is electrically connected to the gates and drains of MOS transistor N103 and the gate of MOS transistor N105. The drain of MOS transistor N104 outputs a bias current I bias2 to the initialization module; The other end of resistor R102, the substrates of MOS transistors N101, N102, N103, N104, and N105, and the sources and substrates of MOS transistors N103, N104, and N105 are all grounded.

3. The dual current protection circuit of the USB current limiting switch according to claim 2, characterized in that: And the following conditions are satisfied. (W / L) P101 :(W / L) P102 :(W / L) P103 =2:1:1; (W / L) P102 :(W / L) P104 = 1:1; (W / L) P103 :(W / L) P105 = 1:1; Among them, (W / L) Pn is the width-to-length ratio of MOS transistor Pn, that is, (W / L) P101 is the width-to-length ratio of MOS transistor P101; (W / L) P102 is the width-to-length ratio of MOS transistor P102; (W / L) P103 is the width-to-length ratio of MOS transistor P103; (W / L) P104 is the width-to-length ratio of MOS transistor P104; (W / L) P105 is the width-to-length ratio of MOS transistor P105.

4. The dual current protection circuit of the USB current limiting switch according to claim 1, characterized in that: The boost clamping unit includes a charge pump boost module and a clamping module. The external power supply VIN is electrically connected to the power input terminal of the charge pump boost module. The output terminal of the charge pump boost module outputs V gate voltage to the input terminal of the clamping module, the gate of the output power MOS transistor PowerFET, and the gate of the output current sensing MOS transistor SenseFET, and the output terminal of the clamping module is electrically connected to the load.

5. The dual current protection circuit of the USB current limiting switch according to claim 4, characterized in that: The charge pump boost module includes MOS transistor P201 and resistor R201, and at least includes transistors Q201, Q202, Q203, Q204, Q205, Q206, Q207, capacitors C201, C202, C203, C204, C205, and inverters INV200, INV201, INV202, INV203, INV204, INV205. The external power supply VIN is electrically connected to the source and substrate of MOS transistor P201, the external enable signal EN is electrically connected to the gate of MOS transistor P201, and the external clock signal CLK is electrically connected to the positive terminal of inverter INV200. The drain of MOS transistor P201 is electrically connected to the collector, base of transistor Q201, and one end of capacitor C201. The negative terminal of inverter INV200 is electrically connected to the positive terminal of inverter INV201. The negative terminal of inverter INV201 is electrically connected to the other end of capacitor C201 and the positive terminal of inverter INV202. The negative terminal of inverter INV202 is electrically connected to one end of capacitor C202 and the positive terminal of inverter INV203. The negative terminal of inverter INV203 is electrically connected to one end of capacitor C203 and the positive terminal of inverter INV204. The negative terminal of inverter INV204 is electrically connected to one end of capacitor C204 and the positive terminal of inverter INV205. The negative terminal of inverter INV205 is electrically connected to one end of capacitor C205. The emitter of transistor Q201 is electrically connected to the collector, base of transistor Q202 and the other end of capacitor C202; the emitter of transistor Q202 is electrically connected to the collector, base of transistor Q203 and the other end of capacitor C203; the emitter of transistor Q203 is electrically connected to the collector, base of transistor Q204 and the other end of capacitor C204; the emitter of transistor Q204 is electrically connected to the collector, base of transistor Q205 and the other end of capacitor C205; the emitter of transistor Q205 is electrically connected to the collector, base of transistor Q206; the emitter of transistor Q206 is electrically connected to the collector, base of transistor Q207; the emitter of transistor Q207 is electrically connected to one end of resistor R201, and the other end of resistor R201 outputs V gate voltage to the input end of the clamping module, the gate of the output power MOS transistor PowerFET and the gate of the output current sensing MOS transistor SenseFET.

6. The dual current protection circuit of the USB current limiting switch according to claim 4, characterized in that: The clamping module includes transistor Q208 and at least includes MOS transistors P202, P203, P204, P205, P206, P207. The external power supply VIN is electrically connected to the substrates of MOS transistors P202, P203, P204, P205, P206, P207. The collector and base of transistor Q208 are both electrically connected to the output terminal of the charge pump boost module. The emitter of triode Q208 is electrically connected to the source of MOS transistor P202, and the gate and drain of MOS transistor P202 are both electrically connected to the source of MOS transistor P203; the gate and drain of MOS transistor P203 are both electrically connected to the source of MOS transistor P204; the gate and drain of MOS transistor P204 are both electrically connected to the source of MOS transistor P205; the gate and drain of MOS transistor P205 are both electrically connected to the source of MOS transistor P206; the gate and drain of MOS transistor P206 are both electrically connected to the source of MOS transistor P207; the gate and drain of MOS transistor P207 are both connected to the load.

7. The dual current protection circuit of the USB current limiting switch according to claim 1, characterized in that: The initialization module includes inverter INV309, inverter INV310, inverter INV311, MOS transistors P310, P311, P312, P313, P314, P315, P316, P317, P318, P319, P320, MOS transistors N316, N317, N318, N319, N320, N321, N322, N323, N324, N325, N326, triode Q301 and capacitor C301; The external power supply VIN is electrically connected to the source, substrate of MOS transistor P310, the source, substrate of MOS transistor P311, the source, substrate of MOS transistor P312, the source, substrate of MOS transistor P313, the substrate of MOS transistor P314, the source, substrate of MOS transistor P315, the source, substrate of MOS transistor P316, the source, substrate of MOS transistor P317, the source, substrate of MOS transistor P318, the source, substrate of MOS transistor P319, the source, substrate of MOS transistor P320; The current bias module outputs a bias current to the gate and drain of MOS transistor P310, the gate of MOS transistor P311 and the gate of MOS transistor P315; the drain of MOS transistor P311 is electrically connected to the drain, gate of MOS transistor N316 and the gate of MOS transistor N22; the external enable signal EN is electrically connected to the gate of MOS transistor P312, the gate of MOS transistor P313, the gate of MOS transistor N317 and the gate of MOS transistor N318; the drain of MOS transistor P312 is electrically connected to the drain of MOS transistor N317, the gate of MOS transistor P319 and the gate of MOS transistor N326; The drain of MOS transistor P313 is electrically connected to the source of MOS transistor P314, and the output terminal of the short-circuit protection module is electrically connected to the gate of MOS transistor P314 and the gate of MOS transistor P319; the drain of MOS transistor P314 is electrically connected to the drain of MOS transistor N318, the drain of MOS transistor N319 and the positive electrode of inverter INV309; The drain of MOS transistor P315 is electrically connected to the drain of MOS transistor N320, one end of capacitor C301, the collector of transistor Q301, and the gate of MOS transistor P316; the negative pole of inverter INV309 is electrically connected to the gates of MOS transistor N320 and MOS transistor N321, and the drain of MOS transistor N321 is electrically connected to the other end of capacitor C301 and the base of transistor Q301; The drain of MOS transistor P316 is electrically connected to the positive pole of inverter INV310 and the drain of MOS transistor N322, the negative pole of inverter INV310 is electrically connected to the positive pole of inverter INV311, and the negative pole of inverter INV is electrically connected to the gates of MOS transistor P318 and MOS transistor N323; The drain of MOS transistor P317 is electrically connected to the drains of MOS transistor P318, MOS transistor N323, the gate of MOS transistor P320, and the gate of MOS transistor N325, and the source of MOS transistor N323 is electrically connected to the drain of MOS transistor N324; The drain of MOS transistor P320 is electrically connected to the drains of MOS transistor P319, MOS transistor N325, the gate of MOS transistor P317, and the gate of MOS transistor N324, and outputs the INIT signal to the overcurrent protection module and the short-circuit protection module; the source of MOS transistor N325 is electrically connected to the drain of MOS transistor N326; The sources and substrates of MOS transistors N316, N317, N318, N319, N320, N321, N322, the substrate of MOS transistor N323, the sources and substrates of MOS transistors N324, N325, N326, and the emitter of transistor Q301 are all grounded.

8. The dual current protection circuit of the USB current limiting switch according to claim 1, characterized in that: It further includes a reference module, which includes MOS transistors N301, N302, N303, N304, P301, and at least includes resistors R300, R301, R302, and fuses Fuse301, Fuse302; The short-circuit protection module includes MOS transistors P302, P303, P304, N305, N306, Ndep301, and inverters INV301, INV302, INV303, INV304; The overcurrent protection module includes MOS transistors P305, P306, P307, P308, N307, N308, N309, N310, N311, inverters INV305, INV306, INV307, INV308, and resistor R303; The control module includes MOS transistor P309, MOS transistor N312, MOS transistor N313, and MOS transistor N315; The external power supply VIN is electrically connected to the substrates of MOS transistor P301, MOS transistor P302, MOS transistor P303, the source and substrate of MOS transistor P304, the substrate of MOS transistor P305, the source and substrate of MOS transistor P306, the source and substrate of MOS transistor P307, the substrate of MOS transistor P308, and the source and substrate of MOS transistor P309; The current bias module outputs a bias current to the gates and drains of MOS transistor N301, MOS transistor N303, MOS transistor N305, and MOS transistor N307; The source of MOS transistor N301 is electrically connected to the gates and drains of MOS transistor N302, MOS transistor N304, MOS transistor N306, MOS transistor N308, and MOS transistor N309; The source of MOS transistor N303 is electrically connected to the drain of MOS transistor N304, and the drain of MOS transistor N303 is electrically connected to the gates and drains of MOS transistor P301, MOS transistor P302, and MOS transistor P305; Resistors R300, R301, and R302 are connected in series between the source of MOS transistor P301 and the external power supply VIN, and both ends of fuse Fuse301 are electrically connected to both ends of resistor R301, and both ends of fuse Fuse302 are electrically connected to both ends of resistor R302; The other end of the induction current detection resistor Rsense is electrically connected to the source of MOS transistor P302 and one end of resistor R303. The drain of MOS transistor P302 is electrically connected to the source of MOS transistor P303 and the gate of MOS transistor P304. The gate of MOS transistor P303 is electrically connected to the drain of MOS transistor P304 and the positive pole of inverter INV301. The drain of MOS transistor P303 is electrically connected to the drain of MOS transistor N305. The source of MOS transistor N305 is electrically connected to the drain of MOS transistor N306. The drain of MOS transistor P304 is electrically connected to the drain of MOS transistor Ndep301; The negative pole of inverter INV301 is electrically connected to the positive pole of inverter INV302. The negative pole of inverter INV302 is electrically connected to the positive pole of inverter INV303. The negative pole of inverter INV303 is electrically connected to the positive pole of inverter INV304. The negative pole of inverter INV304 outputs a short-circuit protection signal SCP to the gates of MOS transistor N310 and MOS transistor N315; The other end of resistor R303 is electrically connected to the source of MOS transistor P305. The drain of MOS transistor P305 is electrically connected to the gates of MOS transistors P306, P307, the drain of MOS transistor N307, and the gate of MOS transistor P309. The source of MOS transistor N307 is electrically connected to the drain of MOS transistor N308. The drain of MOS transistor P306 is electrically connected to the drains of MOS transistors N309, P308, N310, N311, and the positive terminal of inverter INV305. The drain of MOS transistor P307 is electrically connected to the source of MOS transistor P308. The gate of MOS transistor P308 is electrically connected to the negative terminal of inverter INV305 and the positive terminal of inverter INV306. The negative terminal of inverter INV306 is electrically connected to the positive terminal of inverter INV307. The negative terminal of inverter INV307 is electrically connected to the positive terminal of inverter INV308. The negative terminal of inverter INV308 outputs an overcurrent protection signal OCP to the gate of MOS transistor N313. The output terminal of the initialization module is electrically connected to the gate of MOS transistor N311. The drain of MOS transistor P309 is electrically connected to the gate and drain of MOS transistor N312 and the gate of MOS transistor N314. The source of MOS transistor N313 is electrically connected to the drain of MOS transistor N314. The drains of MOS transistor N313 and MOS transistor N315 are both electrically connected to the gates of output power MOS transistor PowerFET and output current sensing MOS transistor SenseFET. The substrates of MOS transistors N301, the sources and substrates of MOS transistors N302, N303, the sources and substrates of MOS transistors N304, N305, N306, the gates, sources and substrates of MOS transistor Ndep, the substrates of MOS transistors N307, the sources and substrates of MOS transistors N308, N309, N310, N311, N312, N313, the sources and substrates of MOS transistors N314, and the sources and substrates of MOS transistors N315 are all grounded.

9. The dual current protection circuit of the USB current limiting switch according to claim 7, characterized in that: And satisfy the following conditions, (W / L) P310 :(W / L) P311 :(W / L) P315 = 10:1:1; Among them, (W / L) Pn is the width-to-length ratio of MOS transistor Pn, that is, (W / L) P310 is the width-to-length ratio of MOS transistor P310; (W / L) P311 is the width-to-length ratio of MOS transistor P311; (W / L) P315 is the width-to-length ratio of MOS transistor P315.

10. The dual current protection circuit of the USB current limiting switch according to claim 8, characterized in that: And satisfy the following conditions, (W / L) N301 :(W / L) N303 :(W / L) N305 :(W / L) N307 =1:2:4:2; (W / L) N302 :(W / L) N304 :(W / L) N306 :(W / L) N308 :(W / L) N309 =1:2:4:2:n; (W / L) P301 :(W / L) P302 :(W / L) P305 =4:8:4; Among them, (W / L) Pn is the width-to-length ratio of MOS transistor Pn, that is, (W / L) P301 is the width-to-length ratio of MOS transistor P301; (W / L) P302 is the width-to-length ratio of MOS transistor P302; (W / L) P305 is the width-to-length ratio of MOS transistor P305; (W / L) Nn is the width-to-length ratio of MOS transistor Nn, i.e., (W / L) N301 is the width-to-length ratio of MOS transistor N301; (W / L) N302 is the width-to-length ratio of MOS transistor N302; (W / L) N303 is the width-to-length ratio of MOS transistor N303; (W / L) N304 is the width-to-length ratio of MOS transistor N304; (W / L) N305 is the width-to-length ratio of MOS transistor N305; (W / L) N306 is the width-to-length ratio of MOS transistor N306; (W / L) N307 is the width-to-length ratio of MOS transistor N307; (W / L) N308 is the width-to-length ratio of MOS transistor N308; (W / L) N309 is the width-to-length ratio of MOS transistor N309, and n is a proportionality coefficient greater than zero.

Images