Converter circuit and failure notification method

Abstract

The present disclosure provides a converter circuit and a related fault notification method. The converter circuit includes a plurality of power stage circuits and a control circuit, and the control circuit and a plurality of temperature feedback terminals of the plurality of power stage circuits are coupled to a node and configured to receive a maximum temperature signal via the node. The fault notification method includes: in response to at least one fault event of at least one of the plurality of power level circuits, controlling the highest temperature signal to have a preset voltage level through the at least one of the plurality of power level circuits; and outputting at least one fault code signal to the control circuit through at least one of the plurality of power level circuits via at least one corresponding one of the plurality of current feedback ends of the plurality of power level circuits. The power stage circuit which detects the fault event outputs the fault code signal to the control circuit through the current feedback end of the power stage circuit, and the converter circuit can clearly record which power stage circuit detects the fault event and the type of the fault event, so that the debugging time of a user on the converter circuit is remarkably shortened.

Description

Technical Field

[0001] The present disclosure relates to a circuit and a method, and more particularly to a converter circuit and a fault notification method. Background Art

[0002] In the related art of multi-phase power converters, a multi-phase power converter may experience a fault event in at least one of its phases due to some non-ideal factors. When a fault occurs, the existing architectures of multi-phase power converters usually only let the user know that a fault event has occurred, but cannot directly inform the user which phase circuits have experienced fault events and what type of fault events have occurred. Therefore, the user needs to spend a lot of time debugging the existing multi-phase power converters, which is quite inconvenient for the user. Summary of the Invention

[0003] One aspect of the present disclosure is a converter circuit. The converter circuit includes a plurality of power stage circuits and a control circuit. The plurality of power stage circuits include a plurality of current feedback terminals and a plurality of temperature feedback terminals. The control circuit is coupled to the plurality of current feedback terminals, and is coupled to the plurality of temperature feedback terminals at a node, and is configured to receive a maximum temperature signal via the node to obtain a maximum temperature value of the plurality of power stage circuits according to the maximum temperature signal. Wherein in response to at least one fault event in at least one of the plurality of power stage circuits, the at least one of the plurality of power stage circuits controls the maximum temperature signal to have a preset voltage level, and outputs at least one fault code signal to the control circuit via at least one corresponding one of the plurality of current feedback terminals.

[0004] In some embodiments, the plurality of power stage circuits are configured to output a plurality of current feedback signals to the control circuit via the plurality of current feedback terminals, and at least one corresponding one of the plurality of current feedback signals output by the at least one corresponding one of the plurality of current feedback terminals includes the at least one fault code signal. When the maximum temperature signal has the preset voltage level, the at least one of the plurality of power stage circuits generates the at least one fault code signal by adjusting a voltage level of at least one corresponding one of the plurality of current feedback signals.

[0005] In some embodiments, the at least one of the plurality of power stage circuits adjusts at least one corresponding one of the plurality of current feedback signals to have a corresponding pulse count according to the at least one fault event, as the at least one fault code signal.

[0006] In some embodiments, the at least one of the plurality of power stage circuits adjusts at least one corresponding one of the plurality of current feedback signals to have a corresponding data code according to the at least one fault event, as the at least one fault code signal.

[0007] In some embodiments, the plurality of power stage circuits are configured to output a plurality of current feedback signals to the control circuit via the plurality of current feedback terminals, and at least one corresponding one of the plurality of current feedback signals output by at least one corresponding one of the plurality of current feedback terminals includes the at least one fault code signal. After at least one of the plurality of power stage circuits completes time synchronization with the control circuit, the at least one fault code signal is output to the control circuit via at least one corresponding one of the plurality of current feedback terminals.

[0008] In some embodiments, when the highest temperature signal has the preset voltage level, at least one of the plurality of power stage circuits and the control circuit simultaneously delay the clock signal for a preset time to complete the time synchronization. During the time synchronization between at least one of the plurality of power stage circuits and the control circuit, the voltage level of at least one corresponding one of the plurality of current feedback signals becomes another preset voltage level different from the preset voltage level.

[0009] One aspect of the present disclosure is a fault notification method. The fault notification method is applicable to a converter circuit. The converter circuit includes a plurality of power stage circuits and a control circuit, and the control circuit is coupled to a plurality of temperature feedback terminals of the plurality of power stage circuits at a node and is configured to receive a highest temperature signal via the node. The fault notification method includes: in response to at least one fault event of at least one of the plurality of power stage circuits, controlling, by at least one of the plurality of power stage circuits, the highest temperature signal to have a preset voltage level; and outputting, by at least one of the plurality of power stage circuits, at least one fault code signal to the control circuit via at least one corresponding one of the plurality of current feedback terminals of the plurality of power stage circuits.

[0010] In some embodiments, the fault notification method further includes: outputting, by the plurality of power stage circuits, a plurality of current feedback signals to the control circuit via the plurality of current feedback terminals, wherein at least one corresponding one of the plurality of current feedback signals output by at least one corresponding one of the plurality of current feedback terminals includes the at least one fault code signal; and generating, by at least one of the plurality of power stage circuits, the at least one fault code signal by adjusting the voltage level of at least one corresponding one of the plurality of current feedback signals.

[0011] In some embodiments, the fault notification method further includes: outputting, by the plurality of power stage circuits, a plurality of current feedback signals to the control circuit via the plurality of current feedback terminals, wherein at least one corresponding one of the plurality of current feedback signals output by at least one corresponding one of the plurality of current feedback terminals includes the at least one fault code signal; and performing, by at least one of the plurality of power stage circuits, time synchronization with the control circuit when the highest temperature signal has the preset voltage level.

[0012] In some embodiments, the fault notification method further includes: decoding the at least one fault code signal through the control circuit to obtain and store the type of the at least one fault event.

[0013] In summary, through the power stage circuit that detects a fault event outputting a fault code signal to the control circuit via its current feedback terminal, the converter circuit of the present disclosure can clearly record which power stage circuit detects the fault event and the type of the fault event. In this way, the time for the user to debug the converter circuit can be significantly reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A block diagram of a converter circuit illustrated according to some embodiments of the present disclosure.

[0015] Figure 2 A block diagram of a power stage circuit illustrated according to some embodiments of the present disclosure.

[0016] Figure 3 A flowchart of a fault notification method illustrated according to some embodiments of the present disclosure.

[0017] Figure 4 An adjustment schematic diagram of a maximum temperature signal and a current feedback signal illustrated according to some embodiments of the present disclosure.

[0018] Figure 5 An adjustment schematic diagram of a maximum temperature signal and a current feedback signal illustrated according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0019] The following examples are described in detail in conjunction with the accompanying drawings. However, the specific examples described are only used to explain the present case and do not limit the present case. The description of the structure and operation is not used to limit the execution order. Any structure recombined by elements and the resulting device with equivalent functions are all within the scope covered by the present disclosure.

[0020] The terms used throughout the specification and claims, unless otherwise specified, generally have their ordinary meanings as used in this field, in the context of the present disclosure, and in the specific context.

[0021] Regarding the use of "coupled" or "connected" herein, it can refer to two or more elements making direct physical or electrical contact with each other, or making indirect physical or electrical contact with each other. It can also refer to two or more elements operating or acting on each other.

[0022] For clarity and convenience of description, in some of the accompanying drawings herein, reference numerals [1] to [4] are used to respectively denote individual elements or signals, but this is not intended to limit the number of elements or signals to a specific number. In addition, if only an element or signal symbol is used without specifying the reference numeral of the element or signal symbol, it means that the element or signal symbol refers to any one of the unspecified elements or signals in the group of elements or signals to which it belongs. For example, the power stage circuit 10 refers to any one of the plurality of power stage circuits 10[1] to 10[4] that is unspecified.

[0023] Please refer to Figure 1 , Figure 1 which is a block diagram of a converter circuit 100 illustrated according to some embodiments of the present disclosure. In some embodiments, as Figure 1 shown, the converter circuit 100 includes a plurality of power stage circuits 10[1] to 10[4] and a control circuit 12. Specifically, the converter circuit 100 can be implemented by a DC / DC converter such as a multi-phase buck converter, but the present disclosure is not limited thereto.

[0024] In some embodiments, a plurality of current output terminals 101[1] to 101[4] of the plurality of power stage circuits 10[1] to 10[4] are respectively electrically coupled to a plurality of load circuits, wherein each of the plurality of load circuits may include an inductor L and a capacitor C electrically connected between the current output terminal 101 of the power stage circuit 10 and the ground terminal. For example, as Figure 1 shown, the inductor L[1] and the capacitor C[1] are connected between the current output terminal 101[1] of the power stage circuit 10[1] and the ground terminal. The inductor L[2] and the capacitor C[2] are connected between the current output terminal 101[2] of the power stage circuit 10[2] and the ground terminal. The inductor L[3] and the capacitor C[3] are connected between the current output terminal 101[3] of the power stage circuit 10[3] and the ground terminal. Also, the inductor L[4] and the capacitor C[4] are connected between the current output terminal 101[4] of the power stage circuit 10[4] and the ground terminal.

[0025] In some embodiments, the control circuit 12 is electrically coupled to the plurality of power stage circuits 10[1] to 10[4]. For example, as Figure 1 shown, the control circuit 12 is coupled to a plurality of current feedback terminals 102[1] to 102[4] of the plurality of power stage circuits 10[1] to 10[4]. Also, the control circuit 12 is further coupled to a plurality of temperature feedback terminals 103[1] to 103[4] of the plurality of power stage circuits 10[1] to 10[4] at a node N1. From the description of these embodiments, it can be seen that the plurality of temperature feedback terminals 103[1] to 103[4] of the plurality of power stage circuits 10[1] to 10[4] are coupled to each other and are coupled to the control circuit 12.

[0026] In some embodiments, the converter circuit 100 is used to supply power. During the period when the converter circuit 100 supplies power, the control circuit 12 respectively outputs a plurality of control signals PWM[1] to PWM[4] to a plurality of power stage circuits 10[1] to 10[4]. The plurality of power stage circuits 10[1] to 10[4] respectively output a plurality of output currents IL[1] to IL[4] according to the plurality of control signals PWM[1] to PWM[4]. As Figure 1 shown, the output current IL[1] of the power stage circuit 10[1] is output to the inductor L[1] and the capacitor C[1] via the current output terminal 101[1]. The output current IL[2] of the power stage circuit 10[2] is output to the inductor L[2] and the capacitor C[2] via the current output terminal 101[2]. The output current IL[3] of the power stage circuit 10[3] is output to the inductor L[3] and the capacitor C[3] via the current output terminal 101[3]. Also, the output current IL[4] of the power stage circuit 10[4] is output to the inductor L[4] and the capacitor C[4] via the current output terminal 101[4]. Specifically, in these embodiments, the control signal PWM can be implemented by a Pulse Width Modulation (PWM) signal.

[0027] In some embodiments, the plurality of power stage circuits 10[1] to 10[4] are used to respectively sense the plurality of output currents IL[1] to IL[4], and output a plurality of current feedback signals Isen[1] to Isen[4] to the control circuit 12 via the plurality of current feedback terminals 102[1] to 102[4]. The control circuit 12 can know a plurality of current sensing values corresponding to the plurality of output currents IL[1] to IL[4] according to the plurality of current feedback signals Isen[1] to Isen[4]. Thereafter, the control circuit 12 can adjust the plurality of control signals PWM[1] to PWM[4] according to the plurality of current sensing values, so that the plurality of power stage circuits 10[1] to 10[4] achieve current balance (that is, the plurality of output currents IL[1] to IL[4] are substantially the same, or the difference is within a predetermined range).

[0028] In some embodiments, in a circuit architecture where the control circuit 12 and the multiple temperature feedback terminals 103[1] to 103[4] of the multiple power stage circuits 10[1] to 10[4] are coupled to the node N1, the highest temperature signal Thest will be generated outside the multiple power stage circuits 10[1] to 10[4] and transmitted to the multiple power stage circuits 10[1] to 10[4] and the control circuit 12 through the node N1. The highest temperature signal Thest has a voltage level corresponding to the highest temperature value of the multiple power stage circuits 10[1] to 10[4]. Specifically, the highest temperature value is the temperature value of the power stage circuit with the highest temperature among the multiple power stage circuits 10[1] to 10[4]. The generation method of the highest temperature signal Thest will be described in detail in the following paragraphs in conjunction with Figure 2 detailed description.

[0029] Please refer to Figure 2 , Figure 2 FIG. 9 is a block diagram of a power stage circuit 10 illustrated according to some embodiments of the present disclosure. In some embodiments, the power stage circuit 10 includes a power circuit 21, a current sensing circuit 22, and a temperature sensing circuit 23. Specifically, the power circuit 21 is electrically coupled to the current output terminal 101 of the power stage circuit 10. The current sensing circuit 22 is electrically coupled to the power circuit 21 and the current feedback terminal 102. The temperature sensing circuit 23 is coupled to the temperature feedback terminal 103.

[0030] In some embodiments, the power circuit 21 includes a high-side switch T1, a low-side switch T2, and a driving circuit D1. The high-side switch T1 is coupled between the input voltage VIN and the current output terminal 101, and the low-side switch T2 is coupled between the current output terminal 101 and the ground voltage GND. In other words, the high-side switch T1 and the low-side switch T2 are serially connected between the input voltage VIN and the ground voltage GND. The driving circuit D1 is coupled to the control terminal of the high-side switch T1, the control terminal of the low-side switch T2, and the control signal PWM, and drives the high-side switch T1 and the low-side switch T2 to conduct alternately according to the duty ratio of the control signal PWM, so that the output current IL is output through the current output terminal 101. The operation of the power circuit 21 is well known to those skilled in the art to which the present disclosure pertains, so only a brief description is provided here. Specifically, the high-side switch T1 and the low-side switch T2 can each be implemented by a transistor (e.g., a metal oxide semiconductor (MOS) transistor), and the driving circuit D1 can be implemented by a gate driver. That is, the driving circuit D1 can respectively output driving signals (not shown in the figure) to the gate (i.e., the control terminal) of the high-side switch T1 and the gate (i.e., the control terminal) of the low-side switch T2. It should be understood that the present disclosure is not limited thereto.

[0031] In some embodiments, the current sensing circuit 22 is configured to sense the output current IL, and generate a current feedback signal Isen according to the sensing result, so as to output the current feedback signal Isen via the current feedback terminal 102. For example, the current sensing circuit 22 may allow the output current IL to flow through a resistor, and generate the current feedback signal Isen according to the voltage difference across the resistor. As another example, the current sensing circuit 22 may utilize the Hall effect to convert the magnetic field around the output current IL into a voltage, and generate the current feedback signal Isen according to the conversion result. Specifically, the current feedback signal Isen is a voltage signal (but the present disclosure is not limited thereto), and has a voltage level corresponding to the magnitude of the output current IL.

[0032] In some embodiments, the temperature sensing circuit 23 is configured to sense the temperature of the power stage circuit 10, and generate a temperature feedback signal Tsen according to the sensing result to the temperature feedback terminal 103. Specifically, the temperature feedback signal Tsen has a voltage level corresponding to the temperature of the power stage circuit 10. In particular, the voltage level of the temperature feedback signal Tsen is positively correlated with the temperature of the power stage circuit 10.

[0033] From the description of the temperature sensing circuit 23, Figure 1 the multiple power stage circuits 10[1] to 10[4] therein will generate multiple temperature feedback signals Tsen, and output them at the multiple temperature feedback terminals 103[1] to 103[4], and the voltage levels of the corresponding ones among the multiple temperature feedback signals Tsen will correspond to the temperatures of the corresponding ones among the multiple power stage circuits 10[1] to 10[4]. In the circuit architecture where the control circuit 12 is coupled to the multiple temperature feedback terminals 103[1] to 103[4] of the multiple power stage circuits 10[1] to 10[4] at the node N1, the one with the maximum voltage level among the multiple temperature feedback signals Tsen (i.e., the temperature feedback signal Tsen generated by the power stage circuit with the highest temperature among the multiple power stage circuits 10[1] to 10[4]) will determine the voltage level of the temperature feedback signal Tsen finally received by the control circuit 12 outside the multiple power stage circuits 10[1] to 10[4], and serve as the highest temperature signal Thest. Also, the highest temperature signal Thest will be transmitted to the control circuit 12 via the node N1, so that the control circuit 12 can obtain the temperature of the power stage circuit with the highest temperature among the multiple power stage circuits 10[1] to 10[4] (i.e., the aforementioned highest temperature value) according to the voltage level of the highest temperature signal Thest. Note that although the highest temperature signal Thest finally received by the control circuit 12 is related to the power stage circuit with the highest temperature among the multiple power stage circuits 10[1] to 10[4], it is impossible to know which one of the multiple power stage circuits 10[1] to 10[4] has the highest temperature, and only the highest temperature value of the multiple power stage circuits 10[1] to 10[4] can be known according to the voltage level of the highest temperature signal Thest.

[0034] In some embodiments, the power stage circuit 10 is used to detect fault events caused by some non-ideal factors. Specifically, the fault events may be under voltage faults, over voltage faults, over current faults, over power faults, over temperature faults, short circuit faults, or any combination thereof. The above-mentioned under voltage faults, over voltage faults, over current faults, over power faults, over temperature faults, and short circuit faults are well-known to those skilled in the art of the present disclosure, so their descriptions are omitted herein.

[0035] Next, the operation of the converter circuit 100 after the power stage circuit 10 detects a fault event will be described in detail with the Figure 3 illustrated fault reporting method 300. Please refer to Figure 3 , Figure 3 which is a flowchart of the fault reporting method 300 illustrated according to some embodiments of the present disclosure. In some embodiments, as Figure 3 illustrated, the fault reporting method 300 includes operations S301 to S302. Operations S301 to S302 will be described in detail with the Figure 1 , Figure 4 and Figure 5 converter circuit 100, where Figure 4 and Figure 5 are respectively schematic diagrams of the adjustment of the maximum temperature signal Thest and the current feedback signal Isen illustrated according to some embodiments of the present disclosure.

[0036] In some embodiments, at least one of the multiple power stage circuits 10[1] to 10[4] detects at least one fault event, so operation S301 is executed. In operation S301, at least one of the multiple power stage circuits 10[1] to 10[4] (i.e., the power stage circuit 10 that detects the fault event), in response to at least one fault event of at least one of the multiple power stage circuits 10[1] to 10[4], controls the maximum temperature signal Thest to have a preset voltage level VH as shown in Figure 4 or Figure 5 illustrated. In Figure 4 or Figure 5In an embodiment, the preset voltage level VH can be the highest voltage level that the system of the converter circuit 100 can reach (e.g., 3.3 volts), and serves as the high logic level. In practice, the temperature feedback signal Tsen generated by the power stage circuit with the highest temperature among the plurality of power stage circuits 10[1] to 10[4] will not reach the preset voltage level VH under normal operating conditions. Therefore, when the control circuit 12 receives the highest temperature signal Thest with the preset voltage level VH via the node N1, the control circuit 12 will know that at least one of the plurality of power stage circuits 10[1] to 10[4] has detected at least one fault event.

[0037] In Figure 4 and Figure 5 , for ease of explanation, it is assumed that the voltage level of the highest temperature signal Thest changes from another preset voltage level VL to the preset voltage level VH, where the preset voltage level VL can be the lowest voltage level that the system of the converter circuit 100 can reach (e.g., 0 volts), and the preset voltage levels VH and VL are used to represent opposite logics on the signal. However, the present disclosure is not limited thereto. In some embodiments, before changing to the preset voltage level VH due to the detection of at least one fault event, the voltage level of the highest temperature signal Thest can change with the temperature of the power stage circuit with the highest temperature among the plurality of power stage circuits 10[1] to 10[4], rather than necessarily remaining at the preset voltage level VL.

[0038] Next, the operation S301 will be further described by taking the power stage circuit 10[1] detecting a fault event as an example. In the case where the power stage circuit 10[1] detects a fault event, the power stage circuit 10[1] will control the internal temperature sensing circuit 23 (as Figure 2 shown) to output a temperature feedback signal Tsen with the preset voltage level VH via the temperature feedback terminal 103[1]. Continuing with the foregoing description, since the temperature feedback signal Tsen generated by the power stage circuit with the highest temperature among the plurality of power stage circuits 10[1] to 10[4] usually does not reach the preset voltage level VH under normal operating conditions of the power stage circuit 10 (i.e., the voltage level of the current highest temperature signal Thest is usually lower than the preset voltage level VH), after the temperature feedback signal Tsen with the preset voltage level VH is output to the outside of the power stage circuit 10[1] (e.g., the node N1), the temperature feedback signal Tsen with the preset voltage level VH will replace the current highest temperature signal Thest as the new highest temperature signal Thest. This new highest temperature signal Thest has the preset voltage level VH.

[0039] In operation S302, at least one of the multiple power stage circuits 10[1] to 10[4] outputs at least one fault code signal CF to the control circuit 12 via at least one corresponding one of the multiple current feedback terminals 102[1] to 102[4]. Continuing with the example where the power stage circuit 10[1] detects a fault event, the power stage circuit 10[1] is used to adjust the voltage level of the current feedback signal Isen[1] according to the fault event to generate the fault code signal CF, and thus output the fault code signal CF to the control circuit 12 via the current feedback terminal 102[1].

[0040] In some further embodiments, the above various fault events (i.e., undervoltage fault, overvoltage fault, overcurrent fault, overpower fault, overtemperature fault, short - circuit fault, etc.) are each preset to correspond to a preset pulse count. For example, an undervoltage fault corresponds to one pulse count. Another example is that an overvoltage fault corresponds to two pulse counts. Accordingly, the power stage circuit 10 that detects a fault event can control the current sensing circuit 22 to adjust the voltage level of the current feedback signal Isen according to the pulse count (i.e., the preset pulse count) corresponding to a certain fault event (such as: overcurrent fault), so that it generates the corresponding number of pulse counts. As Figure 4 shown, according to a specific fault event, three pulses P[1] to P[3] are generated at the voltage level of the current feedback signal Isen as the fault code signal CF[1], that is, the pulse count is equal to 3. Different pulse counts can be used to represent different fault events, such as undervoltage fault, overvoltage fault, overcurrent fault, overpower fault, overtemperature fault, short - circuit fault, etc.

[0041] In some other further embodiments, the above various fault events (i.e., undervoltage fault, overvoltage fault, overcurrent fault, overpower fault, overtemperature fault, short - circuit fault, etc.) are each preset to correspond to a data code DATA. Specifically, the data code DATA can be implemented by serial data defined by the Inter - Integrated Circuit (I2C) Protocol. Accordingly, as Figure 5 shown, the power stage circuit 10 that detects a fault event can adjust the voltage level of the current feedback signal Isen according to the data code DATA corresponding to the fault event to generate the fault code signal CF[2] with the data code DATA.

[0042] In some embodiments, after the control circuit 12 receives the fault code signal CF from the power stage circuit 10 that detects a fault event (i.e., after operation S302), it can decode the fault code signal CF via the internal decoding circuit 121 to obtain and store the type of the fault event. Specifically, the control circuit 12 can pass through the internal memory circuit 123 (such as Figure 1stores the type of the storage fault event, the decoded data corresponding to the type of the fault event, and the time and location at which the fault event occurs (i.e., which one of the power stage circuits 10[1] to 10[4] has a fault).

[0043] In some further embodiments, the control circuit 12 can use the clock signal CLKC stored in the memory circuit 123 to decode the fault code signal CF, so as to obtain the preset pulse count or data code DATA carried by the fault code signal CF. For example, the control circuit 12 is triggered by each periodic pulse in the clock signal CLKC to convert Figure 5 the voltage level of the fault code signal CF[2] in it into serial data to obtain the data code DATA, where the fault code signal CF[2] can be a 4-bit or 8-bit signal, but the present disclosure is not limited thereto.

[0044] In some embodiments, as Figure 4 and Figure 5 shown, the power stage circuit 10 that detects the fault event performs and completes time synchronization with the control circuit 12 during the period TD. In Figure 4 and Figure 5 , the period TD approximately starts at the time when the voltage level of the highest temperature signal Thest changes from the preset voltage level VL to the preset voltage level VH, and approximately ends before the time when the fault code signal CF is generated. From these descriptions, it can be seen that after the power stage circuit 10 that detects the fault event completes time synchronization with the control circuit 12, the power stage circuit 10 that detects the fault event outputs the fault code signal CF to the control circuit 12 via its current feedback terminal 102 to ensure that the control circuit 12 can correctly decode.

[0045] In some further embodiments, when the highest temperature signal Thest has the preset voltage level VH, the power stage circuit 10 that detects the fault event and the control circuit 12 simultaneously delay their respective internal clock signals by a preset time to complete time synchronization. That is to say, the power stage circuit 10 that detects the fault event delays its internal clock signal (not shown in the figure) by a preset time, and the control circuit 12 also delays its internal clock signal CLKC (as Figure 5 shown) by a preset time. It should be understood that the preset time may not be longer than the period TD.

[0046] Specifically, delaying the clock signal CLKC inside the control circuit 12 (or the clock signal inside the power stage circuit 10) can be expressed as delaying the generation of the pulse after the current cycle of the clock signal CLKC. That is to say, after the delay, the pulses generated by the clock signal inside the power stage circuit 10 in each cycle and the pulses generated by the clock signal CLKC inside the control circuit 12 in each cycle will be synchronized in time. In this way, since the power stage circuit 10 that detects a fault event essentially generates a fault code signal CF with a preset pulse count or data code DATA through the triggering of each cycle pulse in the internal clock signal, the control circuit 12 can accurately decode the fault code signal CF through the clock signal CLKC that is synchronized in time with the clock signal inside the power stage circuit 10.

[0047] In summary, the current feedback signal Isen and the temperature feedback signal Tsen (or the highest temperature signal Thest) are not simply used to indicate the occurrence of a fault event. The current feedback signal Isen is further used to carry the fault code signal CF to indicate the type, occurrence time, and location of the fault event, while the temperature feedback signal Tsen is further used to achieve time synchronization between the power stage circuit 10 and the control circuit 12.

[0048] In some embodiments, such as Figure 4 and Figure 5 as shown, during the time period TD when the power stage circuit 10 that detects a fault event is synchronized with the control circuit 12, the voltage level of the current feedback signal Isen of the power stage circuit 10 that detects a fault event becomes a preset voltage level VL.

[0049] Similar to Figure 4 and Figure 5 the description of the highest temperature signal Thest, in Figure 4 and Figure 5 for the sake of convenience of description, the current feedback signal Isen is illustrated to have a preset voltage level VL before the time period TD. However, the present disclosure is not limited thereto. In some embodiments, before the time period TD, the voltage level of the current feedback signal Isen can vary with the output current IL of the power stage circuit 10, rather than necessarily being maintained at the preset voltage level VL.

[0050] In some further embodiments, when the highest temperature signal Thest has a preset voltage level VH, the control circuit 12 controls the voltage level of the current feedback signal Isen to become the preset voltage level VL during the time period TD through the disable control signal PWM. Specifically, the disable control signal PWM indicates maintaining the control signal PWM whose voltage level originally varies according to the duty cycle at the disable level. Figure 2The power circuit 21 will not output the output current IL of the power stage circuit 10 via the current output terminal 101 according to the control signal PWM of the disable level (or the output current IL of the power stage circuit 10 becomes zero). Therefore, the current feedback signal Isen of the power stage circuit 10 will have a preset voltage level VL. In Figure 1 In the embodiment of, during the period TD, the output currents IL[1] to IL[4] of the plurality of power stage circuits 10[1] to 10[4] can become zero simultaneously, so that the plurality of current feedback signals Isen[1] to Isen[4] simultaneously have the preset voltage level VL. After the period TD, only the power stage circuit 10 that detects a fault event will output a fault code signal CF to the control circuit 12 via the current feedback terminal 102. In this way, the control circuit 12 can clearly know which one of the plurality of power stage circuits 10[1] to 10[4] detects a fault event.

[0051] In the above embodiment, after the control circuit 12 stores the type, occurrence time, and location of the fault event (i.e., the power stage circuit 10 that detects the fault event) via the internal memory circuit 123, the control circuit 12 can then perform a shutdown operation to stop the converter circuit 100 from supplying power. The shutdown operation is well known to those skilled in the art of the present disclosure, so its description is omitted.

[0052] As can be seen from the above embodiments of the present disclosure, by the power stage circuit 10 that detects a fault event outputting a fault code signal to the control circuit 12 via its current feedback terminal 102, the converter circuit 100 of the present disclosure can clearly record which power stage circuit 10 detects a fault event and the type of the fault event. In other words, the user of the converter circuit 100 can directly know which power stage circuit 10 detects a fault event and the type of the fault event by accessing the internal memory circuit 123 of the control circuit 12 in the converter circuit 100. In this way, the time for the user to debug the converter circuit 100 can be significantly reduced.

[0053] Whether for a single-phase power supply scheme or a multi-phase power supply scheme, the present invention can achieve fault identification of the power stage circuit 10 through the control circuit 12. Specifically, in some embodiments, for example Figure 1 In the multi-phase power supply scheme shown, the current feedback signals Isen[1] to Isen[4] of each power stage circuit 10[1] to 10[4] are respectively coupled to a current feedback terminal on the control circuit 12, and the temperature feedback signal Tsen (or the highest temperature signal Thest) is transmitted to the control circuit 12 through the node N1 after being connected in multiple phases. Therefore, by cooperating with detecting the state changes of the current feedback signals Isen[1] to Isen[4] and the temperature feedback signal Tsen, the present disclosure can achieve the fault alarm function for each phase of the power supply.

[0054] As used herein, the terms "about", "approximately" or "substantially" generally refer to an error or range of within twenty percent, preferably within ten percent, and more preferably within five percent of a numerical value. Unless otherwise specified in the text, the numerical values mentioned therein are regarded as approximate values, i.e., the error or range indicated by "about", "approximately" or "substantially about".

[0055] Although the present disclosure has been disclosed above in embodiments, it is not intended to limit the present disclosure. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be determined by the appended claims.

[0056]

Symbol Description

[0057] 10: Power stage circuit

[0058] 12: Control circuit

[0059] 21: Power circuit

[0060] 22: Current sensing circuit

[0061] 23: Temperature sensing circuit

[0062] 100: Converter circuit

[0063] 101: Current output terminal

[0064] 102: Current feedback terminal

[0065] 103: Temperature feedback terminal

[0066] 121: Decoding circuit

[0067] 123: Memory circuit

[0068] 300: Fault notification method

[0069] C: Capacitor

[0070] CF: Fault code signal

[0071] CLKC: Clock signal

[0072] D1: Driver circuit

[0073] DATA: Data code

[0074] GND: Ground voltage

[0075] IL: Output current

[0076] Isen: Current feedback signal

[0077] L: Inductance

[0078] N1: Node

[0079] P: Pulse

[0080] PWM: Control Signal

[0081] S301~S302: Operations

[0082] T1: High-Side Switch

[0083] T2: Low-Side Switch

[0084] TD: Period

[0085] Thest: Maximum Temperature Signal

[0086] Tsen: Temperature Feedback Signal

[0087] VH, VL: Preset Voltage Levels

[0088] VIN: Input Voltage.

Claims

1. A converter circuit, characterized in that, Comprising: A plurality of power stage circuits, including a plurality of current feedback terminals and a plurality of temperature feedback terminals; And A control circuit, coupled to the plurality of current feedback terminals, and coupled to the plurality of temperature feedback terminals at a node, and configured to receive a maximum temperature signal via the node to obtain a maximum temperature value of the plurality of power stage circuits according to the maximum temperature signal; Wherein in response to at least one fault event of at least one of the plurality of power stage circuits, the at least one of the plurality of power stage circuits controls the maximum temperature signal to have a preset voltage level and outputs at least one fault code signal to the control circuit via at least one corresponding one of the plurality of current feedback terminals.

2. The converter circuit according to claim 1, wherein The plurality of power stage circuits are configured to output a plurality of current feedback signals to the control circuit via the plurality of current feedback terminals, and at least one corresponding one of the plurality of current feedback signals output by the at least one corresponding one of the plurality of current feedback terminals includes the at least one fault code signal; Wherein when the maximum temperature signal has the preset voltage level, the at least one of the plurality of power stage circuits generates the at least one fault code signal by adjusting a voltage level of at least one corresponding one of the plurality of current feedback signals.

3. The converter circuit according to claim 2, wherein The at least one of the plurality of power stage circuits adjusts at least one corresponding one of the plurality of current feedback signals to have a corresponding pulse count according to the at least one fault event, as the at least one fault code signal.

4. The converter circuit according to claim 2, characterized in that, The at least one of the plurality of power stage circuits adjusts at least one corresponding one of the plurality of current feedback signals to have a corresponding data code according to the at least one fault event, as the at least one fault code signal.

5. The converter circuit according to claim 1, wherein The plurality of power stage circuits are configured to output a plurality of current feedback signals to the control circuit via the plurality of current feedback terminals, and at least one corresponding one of the plurality of current feedback signals output by the at least one corresponding one of the plurality of current feedback terminals includes the at least one fault code signal; Wherein after the at least one of the plurality of power stage circuits completes time synchronization with the control circuit, the at least one fault code signal is output to the control circuit via at least one corresponding one of the plurality of current feedback terminals.

6. The converter circuit according to claim 5, characterized in that, When the maximum temperature signal has the preset voltage level, the at least one of the plurality of power stage circuits and the control circuit simultaneously delay a clock signal for a preset time to complete the time synchronization; Wherein during the time synchronization between the at least one of the plurality of power stage circuits and the control circuit, a voltage level of at least one corresponding one of the plurality of current feedback signals becomes another preset voltage level different from the preset voltage level.

7. A fault notification method, characterized in that, Applicable to a converter circuit, wherein the converter circuit includes a plurality of power stage circuits and a control circuit, the control circuit is coupled to a plurality of temperature feedback terminals of the plurality of power stage circuits at a node, and is configured to receive a maximum temperature signal via the node, and the fault notification method includes: In response to at least one fault event of at least one of the plurality of power stage circuits, the at least one of the plurality of power stage circuits controls the maximum temperature signal to have a preset voltage level; And Via at least one of the multiple power stage circuits, at least one fault code signal is output to the control circuit via at least one corresponding one of the multiple current feedback terminals of the multiple power stage circuits.

8. The fault notification method according to claim 7, wherein Further comprising: Via the multiple power stage circuits, multiple current feedback signals are output to the control circuit via the multiple current feedback terminals, wherein at least one corresponding one of the multiple current feedback signals output by at least one corresponding one of the multiple current feedback terminals includes the at least one fault code signal; And Via at least one of the multiple power stage circuits, the voltage level of at least one corresponding one of the multiple current feedback signals is adjusted to generate the at least one fault code signal.

9. The fault notification method according to claim 7, characterized in that, Further comprising: Via the multiple power stage circuits, multiple current feedback signals are output to the control circuit via the multiple current feedback terminals, wherein at least one corresponding one of the multiple current feedback signals output by at least one corresponding one of the multiple current feedback terminals includes the at least one fault code signal; And When the highest temperature signal has the preset voltage level, time synchronization is performed with the control circuit via at least one of the multiple power stage circuits.

10. The fault notification method according to claim 7, wherein, Further comprising: Via the control circuit, the at least one fault code signal is decoded to obtain and store the type of the at least one fault event.

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