Resonant power switching circuit and control method thereof

Abstract

The invention provides a resonant power conversion circuit and a control method thereof, and the resonant power conversion circuit comprises a resonant capacitor, a transformer, an upper bridge transistor, a lower bridge transistor, a first current detection circuit, an integrator, and a full-wave rectification device. The resonant capacitor is coupled between the resonant node and a ground terminal. The transformer includes a primary coil coupled between the switching node and the resonant node. The upper bridge transistor supplies an input voltage to the switching node based on an upper bridge driving signal. The lower bridge transistor couples the switching node to a ground terminal based on a lower bridge driving signal. The first current detection circuit generates a current detection signal based on the voltage of the resonant node. The integrator generates an integral signal based on the current detection signal. The full-wave rectification device performs full-wave rectification on the integral signal to generate a rectification signal.

Description

Technical Field

[0001] The present invention relates to a resonant power conversion circuit and a control method thereof, and particularly to a resonant power conversion circuit and a control method thereof that compare a rectification signal generated by comparing signals related to full-wave rectification and the voltage across a resonant capacitor, and a feedback voltage to control an upper-bridge transistor and a lower-bridge transistor. Background Art

[0002] With the continuous development of portable electronic devices, the development trend of power conversion circuits, like most power products, is towards high efficiency, high power density, high reliability, and low cost. Since resonant power conversion circuits (including LLC resonant power conversion circuits, etc.) have advantages such as achieving zero-voltage switching (ZVS) on the primary side and zero-current switching (ZCS) of the secondary-side rectifier diode within the full load range, using frequency control to make the duty cycles of the upper-bridge transistor and the lower-bridge transistor both 50%, not requiring an output inductor, and the secondary side can use transistors with lower voltages to reduce costs and improve efficiency, they have been increasingly applied to DC voltage converters in recent years.

[0003] However, in practice, the duty cycles of the upper-bridge transistor and the lower-bridge transistor do not each account for 50%, resulting in uneven current transferred to the secondary side and thus reducing the conversion efficiency. Therefore, it is necessary to improve the balance of the duty cycles of the upper-bridge transistor and the lower-bridge transistor. Summary of the Invention

[0004] The present invention proposes a resonant power conversion circuit and a control method thereof. A rectification signal is generated by full-wave rectifying a current detection signal related to the current flowing through a resonant capacitor, a compensation signal is generated based on a feedback voltage, and the rectification signal is compared with the compensation signal, so that the enable period of the upper-bridge transistor can approach the enable period of the lower-bridge transistor, thereby improving the conversion efficiency of the resonant power conversion circuit. In addition, the resonant power conversion circuit and the control method of the present invention further detect the time point when the current flowing through the resonant capacitor is zero, and turn on the lower-bridge transistor at this time point to reduce the power loss generated by the switching of the switch, thereby further improving the conversion efficiency of the resonant power conversion circuit.

[0005] In view of this, the present invention provides a resonant power conversion circuit, which includes a resonant capacitor, a transformer, an upper bridge transistor, a lower bridge transistor, a first current detection circuit, an integrator, a full-wave rectifier, a control circuit, a rectifier circuit, and a feedback circuit. The above-mentioned resonant capacitor is coupled between a resonant node and a ground terminal. The above-mentioned transformer includes a primary coil and a secondary coil, wherein the above-mentioned primary coil is coupled between a switching node and the above-mentioned resonant node. The above-mentioned upper bridge transistor provides an input voltage to the above-mentioned switching node based on an upper bridge driving signal. The above-mentioned lower bridge transistor couples the above-mentioned switching node to the above-mentioned ground terminal based on a lower bridge driving signal. The above-mentioned first current detection circuit generates a current detection signal based on the voltage of the above-mentioned resonant node. The above-mentioned integrator generates an integration signal based on the above-mentioned current detection signal. The above-mentioned full-wave rectifier full-wave rectifies the above-mentioned integration signal generated by the above-mentioned integrator to generate a rectification signal. The above-mentioned control circuit generates the above-mentioned upper bridge driving signal and the above-mentioned lower bridge driving signal based on the above-mentioned rectification signal and a feedback voltage. The above-mentioned rectifier circuit is coupled to the above-mentioned secondary coil and converts the current flowing through the above-mentioned secondary coil into an output voltage. The above-mentioned feedback circuit generates the above-mentioned feedback voltage based on the above-mentioned output voltage.

[0006] According to an embodiment of the present invention, the above-mentioned first current detection circuit includes a first capacitor and a first resistor. The above-mentioned first capacitor is coupled between the above-mentioned resonant node and a first detection node. The above-mentioned first resistor is coupled between the above-mentioned first detection node and the above-mentioned ground terminal. The above-mentioned first current detection circuit generates the above-mentioned current detection signal at the above-mentioned first detection node.

[0007] According to an embodiment of the present invention, the above-mentioned integrator includes an integration amplifier, a second capacitor, a second resistor, a third resistor, and a third capacitor. The above-mentioned integration amplifier includes an integration positive input terminal, an integration negative input terminal, and an integration output terminal, wherein the above-mentioned integration positive input terminal receives a reference voltage, and the above-mentioned integration output terminal generates the above-mentioned integration signal. The above-mentioned second capacitor is coupled between the above-mentioned first detection node and a second detection node. The above-mentioned second resistor is coupled between the above-mentioned second detection node and the above-mentioned integration negative input terminal, and the above-mentioned third resistor is coupled between the above-mentioned integration negative input terminal and the above-mentioned integration output terminal. The above-mentioned third capacitor is coupled between the above-mentioned integration negative input terminal and the above-mentioned integration output terminal.

[0008] According to an embodiment of the present invention, the above-mentioned full-wave rectifier uses a base voltage as a DC level to full-wave rectify the above-mentioned integration signal to generate the above-mentioned rectification signal. The above-mentioned base voltage is equal to the sum of the above-mentioned reference voltage and an offset voltage. The above-mentioned full-wave rectifier further compares the above-mentioned rectification signal with a first critical voltage to generate a cross signal. The above-mentioned first critical voltage is slightly greater than the above-mentioned base voltage.

[0009] According to an embodiment of the present invention, the control circuit includes a digital circuit, a first amplifier, a second amplifier, a second resistor, an N-type transistor, a current mirror, and a summing circuit. The digital circuit gradually increases a soft start voltage to the feedback voltage within a predetermined time. The first amplifier includes a first positive input terminal, a first negative input terminal, and a first output terminal, wherein the first positive input terminal receives the soft start voltage, and the first negative input terminal is coupled to the first output terminal. The second amplifier includes a second positive input terminal, a second negative input terminal, and a second output terminal, wherein the second positive input terminal receives a feedback critical voltage, and the second output terminal generates a compensation voltage. The second resistor is coupled between the second negative input terminal and the first output terminal and generates a differential current. The N-type transistor includes a gate terminal, a drain terminal, and a source terminal, wherein the gate terminal is coupled to the second output terminal, and the source terminal is coupled to the second negative input terminal. The current mirror maps the differential current into at least one mirrored current. The summing circuit subtracts a sawtooth wave from the compensation voltage to generate a compensation signal. When the soft start voltage is less than the feedback critical voltage, the compensation voltage is equal to the feedback critical voltage. When the soft start voltage is not less than the feedback critical voltage, the compensation voltage is equal to the soft start voltage.

[0010] According to an embodiment of the present invention, when the rectification signal is less than the first critical voltage, the full-wave rectification device sets the cross signal to a disabled state. When the rectification signal exceeds the first critical voltage, the full-wave rectification device sets the cross signal to an enabled state. In response to the cross signal changing from the disabled state to the enabled state, the control circuit sets a phase signal to the enabled state. In response to the rectification signal exceeding the compensation signal, the control circuit sets the phase signal to the disabled state based on an upper bridge dead time signal or a lower bridge dead time signal. The upper bridge dead time signal controls an upper bridge dead time of the upper bridge drive signal. The lower bridge dead time signal controls a lower bridge dead time of the lower bridge drive signal.

[0011] According to an embodiment of the present invention, when the upper bridge driving signal turns on the upper bridge transistor and the phase signal is in the enabled state, the control circuit disables the upper bridge driving signal in response to the rectified signal exceeding the compensation signal. When the upper bridge signal does not turn on the upper bridge transistor, the control circuit enables the lower bridge driving signal after the lower bridge dead time to turn on the lower bridge transistor. When the lower bridge driving signal turns on the lower bridge transistor and the phase signal is in the enabled state, the control circuit disables the lower bridge driving signal in response to the rectified signal exceeding the compensation signal. When the lower bridge driving signal does not turn on the lower bridge transistor, the control circuit enables the upper bridge driving signal after the upper bridge dead time to turn on the upper bridge transistor.

[0012] According to an embodiment of the present invention, the control circuit further limits the enable period of the upper bridge driving signal and the enable period of the lower bridge driving signal to be not greater than a maximum enable period.

[0013] According to an embodiment of the present invention, the offset voltage is determined based on the difference between the enable period of the upper bridge driving signal and the enable period of the lower bridge driving signal. The offset voltage is used to adjust the enable period of the upper bridge driving signal and the enable period of the lower bridge driving signal, so that the enable period of the upper bridge driving signal is close to the enable period of the lower bridge driving signal.

[0014] According to an embodiment of the present invention, the full-wave rectifier device includes a fourth resistor, a first current source, and an automatic adjustment circuit. The fourth resistor is coupled between the reference voltage and the base voltage, and the voltage across the fourth resistor generates the offset voltage. The first current source provides a first current flowing to the base voltage. The automatic adjustment circuit extracts an adjustment current from the base voltage based on the upper bridge driving signal, the lower bridge driving signal, the upper bridge dead time signal, and the lower bridge dead time signal.

[0015] According to an embodiment of the present invention, in response to the first current being greater than the adjustment current, the offset voltage is positive, and the base voltage is greater than the reference voltage. In response to the first current being less than the adjustment current, the offset voltage is negative, and the base voltage is less than the reference voltage. In response to the first current being equal to the adjustment current, the base voltage is equal to the reference voltage.

[0016] According to an embodiment of the present invention, the above-mentioned automatic adjustment circuit includes a time-voltage conversion circuit. The time-voltage conversion circuit is used to convert the enable period of the above-mentioned upper-bridge drive signal and the enable period of the above-mentioned lower-bridge drive signal into an upper-bridge enable period voltage and a lower-bridge enable period voltage respectively. The time-voltage conversion circuit includes a second current source, a first switch, a second switch, a fourth capacitor, a fifth capacitor, a sixth capacitor, a third switch, and a fourth switch. The second current source provides a second current. The first switch provides the second current to a charging node based on the enabled above-mentioned upper-bridge drive signal or the enabled above-mentioned lower-bridge drive signal. During the above-mentioned upper-bridge dead time and the above-mentioned lower-bridge dead time, the second switch couples the charging node to the ground terminal. The fourth capacitor is coupled between the charging node and the ground terminal. The fifth capacitor is coupled between an upper-bridge enable period voltage and the ground terminal. The sixth capacitor is coupled between a lower-bridge enable period voltage and the ground terminal. The third switch couples the charging node to the upper-bridge enable period voltage based on the enabled above-mentioned upper-bridge drive signal. The fourth switch couples the charging node to the lower-bridge enable period voltage based on the enabled above-mentioned lower-bridge drive signal. The above-mentioned upper-bridge enable period voltage represents the enable period of the above-mentioned upper-bridge drive signal, and the above-mentioned lower-bridge enable period voltage represents the enable period of the above-mentioned lower-bridge drive signal.

[0017] According to an embodiment of the present invention, the above-mentioned automatic adjustment circuit further includes a first comparison circuit, a plurality of registers, a counter, and a digital-to-analog converter. The first comparison circuit compares the above-mentioned upper-bridge enable period voltage and the above-mentioned lower-bridge enable period voltage, and generates an upper count signal and a lower count signal. The registers are used to latch the above-mentioned upper count signal and the above-mentioned lower count signal during the above-mentioned upper-bridge dead time and the above-mentioned lower-bridge dead time. The counter increments a digital code based on the enabled above-mentioned upper count signal and decrements the digital code based on the enabled above-mentioned lower count signal. The digital-to-analog converter generates the above-mentioned adjustment current based on the digital code. When the above-mentioned upper-bridge enable period voltage is greater than the above-mentioned lower-bridge enable period voltage, the first comparison circuit enables the above-mentioned upper count signal and disables the above-mentioned lower count signal. When the above-mentioned upper-bridge enable period voltage is not greater than the above-mentioned lower-bridge enable period voltage, the first comparison circuit disables the above-mentioned upper count signal and enables the above-mentioned lower count signal.

[0018] According to an embodiment of the present invention, in response to the increase in the output voltage, the feedback voltage decreases. In response to the feedback voltage being lower than a low-power critical voltage, a lower-bridge dead-time signal enables a burst signal, such that the control circuit operates in a burst mode based on the enabled burst signal. When the control circuit operates in the burst mode, neither the upper-bridge transistor nor the lower-bridge transistor conducts. A duration of the burst mode increases as the output power of the output voltage decreases. The duration is determined by the mapped current.

[0019] According to an embodiment of the present invention, the resonant power conversion circuit further includes a second current detection circuit. The second current detection circuit generates an over-current signal and a zero-current signal based on the current detection signal. When the current flowing through the resonant capacitor exceeds a preset value, the over-current signal is in a reset state, and the control circuit disables the upper-bridge drive signal and the lower-bridge drive signal based on the over-current signal in the reset state. When the current flowing through the resonant capacitor is approximately zero, the zero-current signal is in the enabled state, such that the control circuit enables the lower-bridge drive signal based on the zero-current signal in the enabled state.

[0020] According to an embodiment of the present invention, the control circuit further operates in the burst mode based on the burst signal in the enabled state and the zero-current signal in the enabled state. The burst mode starts when the upper-bridge drive signal is in the disabled state and ends when the lower-bridge drive signal is in the enabled state.

[0021] According to an embodiment of the present invention, the second current detection circuit includes a fifth resistor, a third current source, a second comparison circuit, and a third comparison circuit. The fifth resistor is coupled between the first detection node and a third detection node. The third current source provides a third current to the third detection node, such that the third current flows through the fifth resistor and the first resistor, and a current detection voltage is generated at the third detection node. The second comparison circuit compares the current detection voltage with a first upper critical voltage and a first lower critical voltage to generate the overcurrent signal. The third comparison circuit compares the current detection voltage with a zero current critical voltage to generate the zero current signal. When the current detection voltage is greater than the first upper critical voltage or the current detection voltage is less than the first lower critical voltage, the second comparison circuit sets the overcurrent signal to the reset state. When the current detection voltage exceeds the zero current critical voltage, the third comparison circuit sets the zero current signal to the enable state. The third current flows through the fifth resistor and the first resistor to generate a DC voltage. The zero current critical voltage is slightly greater than the DC voltage.

[0022] According to another embodiment of the present invention, the second current detection circuit includes a second comparison circuit and a third comparison circuit. The second comparison circuit compares the voltage of the second detection node with a second upper critical voltage and a second lower critical voltage to generate the overcurrent signal. The third comparison circuit compares the voltage of the second detection node with a zero current critical voltage to generate the zero current signal. When the voltage of the second detection node is greater than the second upper critical voltage or the voltage of the second detection node is less than the second lower critical voltage, the second comparison circuit sets the overcurrent signal to the reset state. When the voltage of the second detection node exceeds the zero current critical voltage, the third comparison circuit sets the zero current signal to the enable state. The zero current critical voltage is slightly greater than zero.

[0023] The present invention further provides a control method for controlling a resonant power conversion circuit. The above-mentioned resonant power conversion circuit includes a resonant capacitor coupled between a resonant node and a ground terminal, a transformer including a primary coil and a secondary coil, an upper bridge transistor for providing an input voltage to a switching node, a lower bridge transistor for coupling the switching node to the ground terminal, a rectifying circuit for converting the current flowing through the secondary coil into an output voltage, and a feedback circuit for generating a feedback voltage based on the output voltage. The primary coil is coupled between the switching node and the resonant node. The control method includes: detecting the current flowing through the resonant capacitor by a first current detection circuit to generate a current detection signal; integrating the current detection signal based on a reference voltage to generate an integration signal; full-wave rectifying the integration signal to generate a rectifying signal; and driving the upper bridge transistor and the lower bridge transistor based on the rectifying signal and a feedback voltage. The first current detection circuit includes a first capacitor and a first resistor. The first capacitor is coupled between the resonant node and a first detection node, and the first resistor is coupled between the first detection node and the ground terminal. The current detection signal is generated at the first detection node.

[0024] According to an embodiment of the present invention, the control method further includes: using a base voltage as a DC level to full-wave rectify the integration signal to generate the rectifying signal; and comparing the rectifying signal with a first critical voltage to generate a cross signal. The base voltage is equal to the sum of the reference voltage and an offset voltage. The first critical voltage is slightly greater than the base voltage.

[0025] According to an embodiment of the present invention, the control method further includes: gradually increasing a soft start voltage to the feedback voltage within a predetermined time; converting the soft start voltage into a compensation voltage; and subtracting a sawtooth wave from the compensation voltage to generate a compensation signal. When the soft start voltage is less than the feedback critical voltage, the compensation voltage is equal to the feedback critical voltage. When the soft start voltage is not less than the feedback critical voltage, the compensation voltage is equal to the soft start voltage.

[0026] According to an embodiment of the present invention, the above control method further includes: when the rectification signal is less than the first critical voltage, setting the cross signal to a disabled state; when the rectification signal exceeds the first critical voltage, setting the cross signal to an enabled state; in response to the cross signal changing from the disabled state to the enabled state, setting a phase signal to the enabled state; and in response to the rectification signal exceeding the compensation signal, setting the phase signal to the disabled state during an upper bridge dead time or a lower bridge dead time. The lower bridge dead time is the time after the upper bridge transistor is turned off and before the lower bridge transistor is turned on. The upper bridge dead time is the time after the lower bridge transistor is turned off and before the upper bridge transistor is turned on.

[0027] According to an embodiment of the present invention, the above control method further includes: when the upper bridge transistor is turned on and the phase signal is in the enabled state, not turning on the upper bridge transistor in response to the rectification signal exceeding the compensation signal; when the lower bridge transistor is turned on and the phase signal is in the enabled state, not turning on the lower bridge transistor in response to the rectification signal exceeding the compensation signal; and when the lower bridge transistor is turned off, turning on the upper bridge transistor after the upper bridge dead time. When the upper bridge transistor is turned off, turning on the lower bridge transistor after the lower bridge dead time.

[0028] According to an embodiment of the present invention, the above control method further includes: limiting the on-time of the upper bridge transistor and the on-time of the lower bridge transistor to be not greater than a maximum enable period.

[0029] According to an embodiment of the present invention, the above control method further includes: determining the offset voltage based on the difference between the on-time of the upper bridge transistor and the on-time of the lower bridge transistor. The offset voltage is used to adjust the on-time of the upper bridge transistor and the on-time of the lower bridge transistor so that the on-time of the upper bridge transistor is close to the on-time of the lower bridge transistor.

[0030] According to an embodiment of the present invention, the control method further includes: generating the offset voltage by using the voltage across a first resistor, wherein the first resistor is coupled between the reference voltage and the base voltage; providing a first current flowing to the base voltage; using an automatic adjustment circuit to extract an adjustment current from the base voltage based on conduction and non-conduction of the upper bridge transistor and the lower bridge transistor, the upper bridge dead time, and the lower bridge dead time; in response to the first current being greater than the adjustment current, the offset voltage is positive, and the base voltage is greater than the reference voltage; in response to the first current being less than the adjustment current, the offset voltage is negative, and the base voltage is less than the reference voltage; and in response to the first current being equal to the adjustment current, the base voltage is equal to the reference voltage.

[0031] According to an embodiment of the present invention, the control method further includes: operating in a burst mode in response to the feedback voltage being lower than a low-power critical voltage, wherein in response to an increase in the output voltage, the feedback voltage decreases; in the burst mode, simultaneously turning off the upper bridge transistor and the lower bridge transistor; and in response to a decrease in the output power of the output voltage, increasing a duration of the burst mode.

[0032] According to an embodiment of the present invention, the control method further includes: when the current flowing through the resonant capacitor exceeds a preset value, simultaneously turning off the upper bridge transistor and the lower bridge transistor; and when the current flowing through the resonant capacitor is approximately zero, turning on the lower bridge transistor. The burst mode starts with the upper bridge transistor being off and ends with the upper bridge transistor being off. Description of the Drawings

[0033] Figure 1 is a block diagram showing a resonant power conversion circuit according to an embodiment of the present invention;

[0034] Figure 2 is a block diagram showing a full-wave rectifying device according to an embodiment of the present invention;

[0035] Figure 3 is a waveform diagram showing a rectified signal and an integrated signal according to an embodiment of the present invention;

[0036] Figure 4 is a block diagram showing a compensation circuit according to an embodiment of the present invention;

[0037] Figure 5 is a block diagram showing a control circuit according to an embodiment of the present invention;

[0038] Figure 6is a waveform diagram showing a control circuit according to an embodiment of the present invention;

[0039] Figure 7 is a circuit diagram showing a delay time generator according to an embodiment of the present invention;

[0040] Figure 8 is a schematic diagram showing a time-voltage conversion circuit according to an embodiment of the present invention;

[0041] Figure 9 is a schematic diagram showing an automatic adjustment circuit according to an embodiment of the present invention;

[0042] Figure 10 is a block diagram showing an output voltage detection circuit according to an embodiment of the present invention;

[0043] Figure 11 is a waveform diagram showing a resonant power conversion circuit operating at a light load according to an embodiment of the present invention;

[0044] Figure 12 is a block diagram showing a second current detection circuit according to an embodiment of the present invention;

[0045] Figure 13 is a waveform diagram showing a resonant power conversion circuit according to an embodiment of the present invention;

[0046] Figure 14 is a block diagram showing a resonant power conversion circuit according to another embodiment of the present invention;

[0047] Figure 15 is a block diagram showing a second current detection circuit according to another embodiment of the present invention; and

[0048] Figure 16 is a flowchart showing a control method for controlling a resonant power conversion circuit according to an embodiment of the present invention.

[0049] Reference Numerals

[0050] 100, 1400: Resonant Power Conversion Circuit

[0051] 111: Upper Bridge Transistor

[0052] 112: Lower Bridge Transistor

[0053] 120: First Current Detection Circuit

[0054] 130: Integrator

[0055] 131: Integrating Amplifier

[0056] 140,200: Full-wave rectifier device

[0057] 150,1200,1500: Second current detection circuit

[0058] 160,500: Control circuit

[0059] 170: Shift register circuit

[0060] 180: Rectification circuit

[0061] 190: Feedback circuit

[0062] TM: Transformer

[0063] LR: Resonant inductor

[0064] CR: Resonant capacitor

[0065] HSD: Upper bridge drive circuit

[0066] LSD: Lower bridge drive circuit

[0067] PS: Primary coil

[0068] SS: Secondary coil

[0069] NR: Resonant node

[0070] SW: Switching node

[0071] HSG: Upper bridge gate drive signal

[0072] LSG: Lower bridge gate drive signal

[0073] VIN: Input voltage

[0074] C1: First capacitor

[0075] C2: Second capacitor

[0076] C3: Third capacitor

[0077] R1: First resistor

[0078] R2: Second resistor

[0079] R3: Third resistor

[0080] R4: Fourth resistor

[0081] R5: Fifth resistor

[0082] R6: Sixth resistor

[0083] R7: Seventh resistor

[0084] R8: Eighth resistor

[0085] FW: Rectified Signal

[0086] FB: Feedback Voltage

[0087] SZ: Cross Signal

[0088] COUT: Output Capacitor

[0089] HS: High-Bridge Drive Signal

[0090] LS: Low-Bridge Drive Signal

[0091] D1: First Rectifying Element

[0092] D2: Second Rectifying Element

[0093] VOUT: Output Voltage

[0094] DR: Voltage Regulating Element

[0095] VD1: First Dividing Voltage

[0096] PD: Opto-Coupler Element

[0097] LED: Diode

[0098] Q: Transistor

[0099] VCC: Supply Voltage

[0100] VCS: Current Detection Voltage

[0101] CS: Current Detection Signal

[0102] INT: Integral Signal

[0103] OCP: Over-Current Signal

[0104] ZCD: Zero-Current Signal

[0105] ND1: First Detection Node

[0106] ND2: Second Detection Node

[0107] ND3: Third Detection Node

[0108] VREF: Reference Voltage

[0109] 210: Full-Wave Rectifier

[0110] 220: Bias Circuit

[0111] 221: Automatic Adjustment Circuit

[0112] CMP1: First Comparator

[0113] R9: Ninth Resistor

[0114] R10: Tenth resistor

[0115] R11: Eleventh resistor

[0116] R12: Twelfth resistor

[0117] R13: Thirteenth resistor

[0118] AMP1: First amplifier

[0119] AMP2: Second amplifier

[0120] D3: Third diode

[0121] D4: Fourth diode

[0122] CMP1: First comparator

[0123] VT1: First critical voltage

[0124] AMP3: Third amplifier

[0125] CS1: First current source

[0126] R14: Fourteenth resistor

[0127] I1: First current

[0128] VBS: Base voltage

[0129] CK_H: Upper bridge dead time signal

[0130] CK_L: Lower bridge dead time signal

[0131] ID: Adjustment current

[0132] VOS: Offset voltage

[0133] DC: DC level

[0134] 400: Compensation circuit

[0135] 410: Digital circuit

[0136] 411: First counter

[0137] 412: First digital-to-analog converter

[0138] 420: Summing circuit

[0139] SFT: Soft start voltage

[0140] AMP4: Fourth amplifier

[0141] AMP5: Fifth amplifier

[0142] R15: The fifteenth resistor

[0143] MN1: The first N-type transistor

[0144] CM1: The first current mirror

[0145] VTC: Feedback critical voltage

[0146] INP4: The fourth positive input terminal

[0147] INN4: The fourth negative input terminal

[0148] O4: The fourth output terminal

[0149] INP5: The fifth positive input terminal

[0150] INN5: The fifth negative input terminal

[0151] O5: The fifth output terminal

[0152] IDIFF: Differential current

[0153] IB1: The first mapped current

[0154] IB2: The second mapped current

[0155] IB3: The third mapped current

[0156] G: Gate terminal

[0157] D: Drain terminal

[0158] S: Source terminal

[0159] VCOMP: Compensation voltage

[0160] COMP: Compensation signal

[0161] RAMP: Sawtooth wave

[0162] FF1 The first flip-flop

[0163] AND1: The first AND gate

[0164] SE: Phase signal

[0165] CMP2: The second comparator

[0166] AND2: The second AND gate

[0167] OR1: The first OR gate

[0168] OR2: The second OR gate

[0169] DT1: The first dead time generator

[0170] DT2: The second dead time generator

[0171] FF2 Second flip-flop

[0172] FF3: Third flip-flop

[0173] AND3: Third AND gate

[0174] AND4: Fourth AND gate

[0175] AND5: Fifth AND gate

[0176] AND6: Sixth AND gate

[0177] dHS: Delayed high-bridge drive signal

[0178] HIS: Initial high-bridge drive signal

[0179] dLS: Delayed low-bridge drive signal

[0180] ILS: Initial low-bridge drive signal

[0181] IX: First regulated current

[0182] IY: Second regulated current

[0183] INV1: First inverter

[0184] INV2: Second inverter

[0185] 501: First cycle limit circuit

[0186] 502: Second cycle limit circuit

[0187] 600: Waveform diagram

[0188] T1: First time

[0189] T2: Second time

[0190] T3: Third time

[0191] T4: Fourth time

[0192] 700: Delay time generator

[0193] INV3: Third inverter

[0194] MN2: Second N-type transistor

[0195] C3: Third capacitor

[0196] CS2: Second current source

[0197] CS3: Third current source

[0198] CM2: Second current mirror

[0199] CMP3: The third comparator

[0200] IN: Input signal

[0201] VCAP1: The first capacitor voltage

[0202] I2: The second current

[0203] I3: The third current

[0204] I4: The fourth current

[0205] I5: The fifth current

[0206] I6: The sixth current

[0207] I7: The seventh current

[0208] VT2: The second critical voltage

[0209] OUT: Output signal

[0210] IA: Input current

[0211] 800: Time-voltage conversion circuit

[0212] CS4: The fourth current source

[0213] OR3: The third OR gate

[0214] SW1: The first switch

[0215] SW2: The second switch

[0216] SW3: The third switch

[0217] SW4: The fourth switch

[0218] NAND1: The first NAND gate

[0219] C4: The fourth capacitor

[0220] C5: The fifth capacitor

[0221] C6: The sixth capacitor

[0222] I4: The fourth current

[0223] VDH: Upper bridge enable periodic voltage

[0224] VDL: Lower bridge enable periodic voltage

[0225] 900: Automatic adjustment circuit

[0226] 910: Comparison circuit

[0227] 920: Signal generation circuit

[0228] FF4: Fourth flip-flop

[0229] FF5: Fifth flip-flop

[0230] 930: Second counter

[0231] 940: Second digital-to-analog converter

[0232] UP: Up-count signal

[0233] DWN: Down-count signal

[0234] LTH: Latch signal

[0235] CLK: Clock signal

[0236] B: Digital code

[0237] CMP4: Fourth comparator

[0238] CMP5: Fifth comparator

[0239] INV4: Fourth inverter

[0240] INV5: Fifth inverter

[0241] INV6: Sixth inverter

[0242] AND7: Seventh AND gate

[0243] AND8: Eighth AND gate

[0244] AND9: Ninth AND gate

[0245] AND10: Tenth AND gate

[0246] AND11: Eleventh AND gate

[0247] AND12: Twelfth AND gate

[0248] LUP: Latch up-count signal

[0249] LDWN: Latch down-count signal

[0250] CS5: Fifth current source

[0251] C7: Seventh capacitor

[0252] VCAP2: Second capacitor voltage

[0253] MN3: Third N-type transistor

[0254] 1000: Output voltage detection circuit

[0255] 1010: Delay circuit

[0256] CMP6: The sixth comparator

[0257] FF6: The sixth flip-flop

[0258] FF7: The seventh flip-flop

[0259] INV7: The seventh inverter

[0260] INV8: The eighth inverter

[0261] INV9: The ninth inverter

[0262] VTLP: Low-power critical voltage

[0263] CP: Comparison signal

[0264] PSR: Preamble burst signal

[0265] PSB: Inverted preamble burst signal

[0266] BST: Burst signal

[0267] ST: Reset signal

[0268] MN4: The fourth N-type transistor

[0269] CS6: The sixth current source

[0270] C8: The eighth capacitor

[0271] I8: The eighth current

[0272] NOR1: The first NOR gate

[0273] OR4: The fourth OR gate

[0274] AND13: The thirteenth AND gate

[0275] VCAP3: The third capacitor voltage

[0276] S1: The first signal

[0277] S1B: The first inverted signal

[0278] S2: The second signal

[0279] CS7: The seventh current source

[0280] 1210: The first comparison circuit

[0281] 1220: The second comparison circuit

[0282] I9: The ninth current

[0283] VB: Bias voltage

[0284] VTH1: First upper critical voltage

[0285] VTL1: First lower critical voltage

[0286] VTZ1: First zero-current critical voltage

[0287] CMP7: Seventh comparator

[0288] CMP8: Eighth comparator

[0289] OR5: Fifth OR gate

[0290] 1211: Delay circuit

[0291] CMP9: Ninth comparator

[0292] CS8: Eighth current source

[0293] C9: Ninth capacitor

[0294] MN5: Fifth N-type transistor

[0295] NOR2: Second NOR gate

[0296] I10: Tenth current

[0297] VCAP4: Fourth capacitor voltage

[0298] CRE: Comparison result

[0299] 1410: Package

[0300] 1600: Control method

[0301] S1610~S1640: Step flow Detailed implementation manner

[0302] The following description is for the embodiments of the present disclosure. Its purpose is to illustrate the general principles of the present disclosure by way of examples and should not be regarded as a limitation of the present disclosure. The scope of the present disclosure shall be defined by the scope of the patent application.

[0303] It should be noted that the content disclosed below can provide multiple embodiments or examples for practicing different features of the present disclosure. The specific component examples and arrangements described below are only used to briefly elaborate the spirit of the present disclosure and are not used to limit the scope of the present disclosure. In addition, the following specification may reuse the same component symbols or words in multiple examples. However, the purpose of reuse is only to provide a simplified and clear description and is not used to limit the relationship between the multiple embodiments and / or configurations discussed below.

[0304] In addition, the descriptions such as one feature being connected to, coupled to, and / or formed on top of another feature described in the following specification may actually include multiple different embodiments, including the direct contact of such features, or other additional features being formed between such features, etc., such that the features are not in direct contact.

[0305] In addition, relative terms such as "lower" or "bottom" and "higher" or "top" may be used in the embodiments to describe the relative relationship of one element of the figure to another element. It can be understood that if the device in the figure is flipped upside down, the element described on the "lower" side will become the element on the "higher" side.

[0306] It can be understood that although terms such as "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms, and these terms are only used to distinguish different elements, components, regions, layers, and / or parts. Therefore, a first element, component, region, layer, and / or part discussed below may be referred to as a second element, component, region, layer, and / or part without departing from the teachings of some embodiments of the present disclosure.

[0307] Some embodiments of the present disclosure can be understood in conjunction with the figures, and the figures of the embodiments of the present disclosure are also regarded as a part of the description of the embodiments of the present disclosure. It should be understood that the figures of the embodiments of the present disclosure are not drawn to the scale of actual devices and elements. The shapes and thicknesses of the embodiments may be exaggerated in the figures for the purpose of clearly showing the features of the embodiments of the present disclosure. In addition, the structures and devices in the figures are shown in a schematic manner for the purpose of clearly showing the features of the embodiments of the present disclosure.

[0308] Herein, the terms "about", "approximately", and "substantially" generally mean within 20% of a given value or range, preferably within 10%, more preferably within 5%, or 3%, or 2%, or 1%, or 0.5%. The quantity given herein is an approximate quantity, that is, the meaning of "about", "approximately", and "substantially" may still be implied even without specifically stating "about", "approximately", and "substantially".

[0309] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this disclosure belongs. It can be understood that these terms, such as those defined in a commonly used dictionary, should be interpreted to have a meaning consistent with the relevant technology and the background or context of the present disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of the present disclosure.

[0310] In some embodiments of the present disclosure, terms related to joining and connecting, such as "connect" and "interconnect", unless otherwise specifically defined, may mean that two structures are in direct contact, or may also mean that two structures are not in direct contact, with other structures disposed therebetween. And these terms related to joining and connecting may also include cases where both structures are movable, or both structures are fixed.

[0311] In the drawings, similar elements and / or features may have the same element symbols. Various elements of the same type may be distinguished by adding a letter or number after the element symbol to distinguish similar elements and / or similar features.

[0312] Figure 1 is a block diagram showing a resonant power conversion circuit according to an embodiment of the present invention. As Figure 1 shown, the resonant power conversion circuit 100 includes a transformer TM, a resonant inductor LR, a resonant capacitor CR, an upper bridge transistor 111, a lower bridge transistor 112, a first current detection circuit 120, an integrator 130, a full-wave rectifier 140, a fourth resistor R4, a second current detection circuit 150, a control circuit 160, a shift register circuit 170, an upper bridge drive circuit HSD, a lower bridge drive circuit LSD, a rectifier circuit 180, and a feedback circuit 190.

[0313] The transformer TM includes a primary coil PS and a secondary coil SS, wherein the primary coil PS is coupled to the resonant node NR. The resonant inductor LR is coupled between the switching node SW and the primary coil PS, and the resonant capacitor CR is coupled between the resonant node NR and the ground terminal. According to an embodiment of the present invention, the resonant inductor LR can be replaced by the leakage inductance of the primary coil PS of the transformer TM. In other words, the primary coil PS can be coupled between the switching node SW and the resonant node NR.

[0314] The upper bridge gate drive signal HSG drives the upper bridge transistor 111 to conduct and non-conduct, and supplies the input voltage VIN to the switching node SW. The lower bridge gate drive signal LSG drives the lower bridge transistor 112 to conduct and non-conduct, and couples the switching node SW to the ground terminal. The first current detection circuit 120 includes a first capacitor C1 and a first resistor R1, wherein the first capacitor C1 is coupled between the resonant node NR and the first detection node ND1, and the first resistor R1 is coupled between the first detection node ND1 and the ground terminal. According to an embodiment of the present invention, the first current detection circuit 120 generates a current detection signal CS at the first detection node ND1.

[0315] The integrator 130 is used to integrate the current detection signal CS at the first detection node ND1 to generate an integration signal INT. As Figure 1As shown, the integrator 130 includes a second capacitor C2, a second resistor R2, an integrating amplifier 131, a third resistor R3, and a third capacitor C3. The second capacitor C2 is coupled between a first detection node ND1 and a second detection node ND2. The second resistor R2 is coupled between the second detection node ND2 and the negative input terminal of the integrating amplifier 131. The positive input terminal of the integrating amplifier 131 receives a reference voltage VREF, and the third resistor R3 and the third capacitor C3 are connected in parallel between the output terminal and the negative input terminal of the integrating amplifier 131.

[0316] The full-wave rectifying device 140 full-wave rectifies the integration signal INT to generate a rectifying signal FW and a cross signal SZ. A fourth resistor R4 is coupled between the first detection node ND1 and a third detection node ND3. The second current detection circuit 150 is coupled to the third detection node ND3 and generates an overcurrent signal OCP and a zero-current signal ZCD according to the current detection voltage VCS of the third detection node ND3. In other words, the second current detection circuit 150 receives the current detection signal CS through the fourth resistor R4 and generates the overcurrent signal OCP and the zero-current signal ZCD.

[0317] The control circuit 160 generates an upper bridge driving signal HS and a lower bridge driving signal LS based on the rectifying signal FW, the feedback voltage FB, the overcurrent signal OCP, and the zero-current signal ZCD. The shift circuit 170 is configured to convert the upper bridge driving signal HS to the voltage level of the input voltage VIN and generate an upper bridge gate driving signal HSG through the upper bridge driving circuit HSD to drive the upper bridge transistor 111. The lower bridge driving circuit LSD generates a lower bridge gate driving signal LSG based on the lower bridge driving signal LS to drive the lower bridge transistor 112.

[0318] The rectifying circuit 180 is coupled to the secondary coil SS and is configured to convert the current flowing through the secondary coil SS into an output voltage VOUT. As Figure 1 shown, the rectifying circuit 180 includes a first rectifying element D1, a second rectifying element D2, and an output capacitor COUT. The first rectifying element D1 and the second rectifying element D2 are configured to more efficiently charge the output capacitor COUT with the current flowing through the secondary coil SS, thereby generating the output voltage VOUT. According to other embodiments of the present invention, the first rectifying element D1 and the second rectifying element D2 can be replaced with electronic elements having a low on-resistance to further improve the conversion efficiency.

[0319] The feedback circuit 190 generates a feedback voltage FB based on the output voltage VOUT. As Figure 1As shown, the feedback circuit 190 includes a fifth resistor R5, a sixth resistor R6, a voltage regulator element DR, an optocoupler element PD, a seventh resistor R7, and an eighth resistor R8. The fifth resistor R5 and the sixth resistor R6 are used to divide the output voltage VOUT, thereby generating a first divided voltage VD1. The voltage regulator element DR generates a current flowing through the diode LED of the optocoupler element PD based on the first divided voltage VD1, causing the diode LED to emit light, and turning on the transistor Q of the optocoupler element PD through optical coupling.

[0320] The seventh resistor R7 is used to limit the current flowing through the diode LED. The supply voltage VCC generates a feedback voltage FB through the eighth resistor R8 and the turned-on transistor Q. According to an embodiment of the present invention, the voltage regulator element DR can be TL431. According to some embodiments of the present invention, when the output voltage VOUT increases, the feedback voltage FB decreases accordingly. According to some other embodiments of the present invention, when the output voltage VOUT decreases, the feedback voltage FB increases accordingly. The control method of the resonant power conversion circuit 100 will be described in detail below.

[0321] Figure 2 is a block diagram showing a full-wave rectifier device according to an embodiment of the present invention. According to an embodiment of the present invention, Figure 2 The full-wave rectifier device 200 corresponds to Figure 1 The full-wave rectifier device 140. As Figure 2 shown, the full-wave rectifier device 200 includes a full-wave rectifier 210, a first comparator CMP1, and a bias circuit 220. The full-wave rectifier 210 includes a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a first amplifier AMP1, a twelfth resistor R12, a thirteenth resistor R13, a third diode D3, a fourth diode D4, and a second amplifier AMP2. The full-wave rectifier 210 uses the base voltage VBS as a DC level to perform full-wave rectification on the integration signal INT generated by the integrator 130, thereby generating a rectified signal FW.

[0322] The first comparator CMP1 compares the rectified signal FW with a first critical voltage VT1, thereby generating a cross signal SZ. According to an embodiment of the present invention, the first critical voltage VT1 is slightly greater than the base voltage VBS. According to an embodiment of the present invention, when the rectified signal FW is less than the first critical voltage VT1, the first comparator CMP1 sets the cross signal SZ to the disabled state. According to another embodiment of the present invention, when the rectified signal FW exceeds the first critical voltage VT1, the first comparator CMP1 sets the cross signal SZ to the enabled state.

[0323] The bias circuit 220 includes a third amplifier AMP3, a first current source CS1, a fourteenth resistor R14, and an automatic adjustment circuit 221. As Figure 2As shown, the positive input terminal of the third amplifier AMP3 receives a reference voltage VREF, and the third amplifier AMP3 is coupled in the form of a unity-gain buffer such that the voltage at the output terminal of the third amplifier AMP3 is equal to the reference voltage VREF. The first current source CS1 supplies a first current I1 to the base voltage VBS, and the fourteenth resistor R14 is coupled between the base voltage VBS and the output terminal of the third amplifier AMP3.

[0324] The automatic adjustment circuit 221 extracts an adjustment current ID from the base voltage VBS based on the upper-bridge driving signal HS, the lower-bridge driving signal LS, the upper-bridge dead-time signal CK_H, and the lower-bridge dead-time signal CK_L. The automatic adjustment circuit 221, the upper-bridge dead-time signal CK_H, and the lower-bridge dead-time signal CK_L will be described in detail below. According to an embodiment of the present invention, the base voltage VBS is equal to the sum of the reference voltage VREF and the offset voltage VOS.

[0325] According to an embodiment of the present invention, in response to the first current I1 being greater than the adjustment current ID, the offset voltage VOS is positive, and the base voltage VBS is greater than the reference voltage VREF. According to another embodiment of the present invention, in response to the first current I1 being less than the adjustment current ID, the offset voltage VOS is negative, and the base voltage VBS is less than the reference voltage VREF. According to another embodiment of the present invention, in response to the first current I1 being equal to the adjustment current ID, the base voltage VBS is equal to the reference voltage VREF. According to another embodiment of the present invention, in response to the first current I1 being equal to the adjustment current ID, the offset voltage VOS is zero, and the base voltage VBS is equal to the reference voltage VREF.

[0326] Figure 3 is a waveform diagram showing a rectified signal and an integrated signal according to an embodiment of the present invention. As Figure 3 shown, the divided voltage signal SD has a DC level DC. The full-wave rectifier 210 uses the base voltage VBS as the DC level to perform full-wave rectification on the integrated signal INT to generate a rectified signal FW. Then, the first comparator CMP1 compares the rectified signal FW and the first critical voltage VT1 to generate a cross signal SZ. As Figure 3 shown, when the rectified signal FW is less than the first critical voltage VT1, the first comparator CMP1 disables the cross signal SZ. When the rectified signal FW is not less than the first critical voltage VT1, the cross signal SZ remains in the enabled state.

[0327] Figure 4 is a block diagram showing a compensation circuit according to an embodiment of the present invention. According to an embodiment of the present invention, Figure 1 the control circuit 160 of Figure 4As shown, the compensation circuit 400 includes a digital circuit 410, a fourth amplifier AMP4, a fifth amplifier AMP5, a fifteenth resistor R15, a first N-type transistor MN1, a first current mirror CM1, and a summing circuit 420.

[0328] The compensation circuit 400 is configured to generate a compensation voltage VCOMP based on the feedback voltage FB, and limit the compensation voltage VCOMP to be not less than the feedback threshold voltage VTC. In other words, the compensation voltage VCOMP generated by the compensation circuit 400 is equal to the feedback voltage FB, and the minimum value of the compensation voltage VCOMP is limited to the feedback threshold voltage VTC. In addition, the compensation circuit 400 further subtracts the sawtooth wave RAMP from the compensation voltage VCOMP to generate a compensation signal COMP.

[0329] When the resonant power conversion circuit 100 starts to operate initially, the digital circuit 410 is configured to gradually increase the soft start voltage SFT to the feedback voltage FB within a predetermined time. As Figure 4 shown, the digital circuit 410 includes a first counter 411 and a first digital-to-analog converter 412. The first counter 411 counts from 0 to a maximum value according to the clock signal CLK, and the first digital-to-analog converter 412 generates the soft start voltage SFT according to the counting value of the first counter 411 and the feedback voltage FB.

[0330] For example, the first counter 411 counts from 0 to 1024 according to the clock signal CLK, and the maximum value of the feedback voltage FB is 5V. Therefore, every time a cycle of the clock signal CLK passes, the soft start voltage SFT increases by approximately 5mV until the soft start voltage SFT is equal to the feedback voltage FB. Since the soft start voltage SFT slowly climbs to the correct voltage value of the feedback voltage FB, the Figure 1 resonant power conversion circuit 100 can gradually establish the output voltage VOUT.

[0331] The fourth amplifier AMP4 includes a fourth positive input terminal INP4, a fourth negative input terminal INN4, and a fourth output terminal O4, where the fourth positive input terminal INP4 receives the soft start voltage SFT, and the fourth negative input terminal INN4 is coupled to the fourth output terminal O4. The fifth amplifier AMP5 includes a fifth positive input terminal INP5, a fifth negative input terminal INN5, and a fifth output terminal O5, where the fifth positive input terminal INP5 receives the feedback threshold voltage VTC. According to an embodiment of the present invention, the fourth amplifier AMP4 is coupled as a unity gain amplifier, so the voltage at the fourth output terminal O4 is equal to the soft start voltage SFT.

[0332] The fifteenth resistor R15 is coupled between the fifth negative input terminal INN5 and the fourth output terminal O4, and generates a differential current IDIFF. The first N-type transistor MN1 includes a gate terminal G, a drain terminal D, and a source terminal S, wherein the gate terminal G is coupled to the fifth output terminal O5, and the source terminal S is coupled to the fifth negative input terminal INN5 and generates a compensation voltage VCOMP. The summing circuit 420 is configured to subtract the ramp signal RAMP from the compensation voltage VCOMP to generate a compensation signal COMP.

[0333] The first current mirror CM1 is coupled to the drain terminal D, and maps the differential current IDIFF to a first mapped current IB1, a second mapped current IB2, and a third mapped current IB3. According to some embodiments of the present invention, the first mapped current IB1, the second mapped current IB2, and the third mapped current IB3 are N, M, and P times the differential current IDIFF respectively, where N, M, and P are the magnification factors mapped by the first current mirror CM1, and N, M, and P may be the same or different.

[0334] According to an embodiment of the present invention, when the soft start voltage SFT is less than the feedback critical voltage VTC, the difference between the feedback critical voltage VTC and the soft start voltage SFT and the resistance value of the fifteenth resistor R15 generate a differential current IDIFF. The first current mirror CM1 generates a first mapped current IB1, a second mapped current IB2, and a third mapped current IB3, and the compensation voltage VCOMP is equal to the feedback critical voltage VTC. According to another embodiment of the present invention, when the soft start voltage SFT is greater than or equal to the feedback critical voltage VTC, the fifth amplifier AMP5 does not turn on the first N-type transistor MN1, so that the first current mirror CM1 does not generate a first mapped current IB1, a second mapped current IB2, and a third mapped current IB3, and the compensation voltage VCOMP is equal to the soft start voltage SFT.

[0335] In other words, when the soft start voltage SFT is less than the feedback critical voltage VTC, the compensation voltage VCOMP is equal to the feedback critical voltage VTC, and the first mapped current IB1, the second mapped current IB2, and the third mapped current IB3 are correspondingly generated. When the soft start voltage SFT is not less than the feedback critical voltage VTC, the compensation voltage VCOMP is equal to the soft start voltage SFT, and the first mapped current IB1, the second mapped current IB2, and the third mapped current IB3 are not generated. The functions of the first mapped current IB1, the second mapped current IB2, and the third mapped current IB3 will be described in detail below.

[0336] Figure 5 is a block diagram showing a control circuit according to an embodiment of the present invention. As Figure 5As shown, the control circuit 500 includes a first flip-flop FF1 and a first AND gate AND1. The first flip-flop FF1 outputs the supply voltage VCC as a phase signal SE (i.e., sets the phase signal SE to the enabled state) based on the positive signal edge of the cross signal SZ (i.e., the cross signal SZ changes from the disabled state to the enabled state). According to some embodiments of the present invention, the cross signal SZ is in the disabled state at a low logic level and in the enabled state at a high logic level. In other words, as Figure 2 shown, when the rectified signal FW increases and exceeds the first critical voltage VT1, the phase signal SE is enabled.

[0337] The first flip-flop FF1 also sets the phase signal SE to the disabled state based on the upper bridge dead time signal CK_H or the lower bridge dead time signal CK_L being in the disabled state (i.e., a low logic level). In other words, during the upper bridge dead time and the lower bridge dead time, the phase signal SE is in the disabled state. As Figure 5 shown, the control circuit 500 further includes a second comparator CMP2, a second AND gate AND2, a first OR gate OR1, a first dead time generator DT1, a second flip-flop FF2, and a third AND gate AND3.

[0338] When the rectified signal FW exceeds the compensation signal COMP generated by the compensation circuit 400, the delayed upper bridge drive signal dHS is in the enabled state, and the phase signal SE is in the enabled state, a negative pulse is generated on the lower bridge dead time signal CK_L by triggering the first dead time generator DT1 through the second AND gate AND2 and the first OR gate OR1, and the upper bridge drive signal HS is set to the disabled state through the third AND gate AND3, thereby turning off Figure 1 the upper bridge transistor 111.

[0339] In addition, the negative pulse of the lower bridge dead time signal CK_L resets the second flip-flop FF2, so that the delayed upper bridge drive signal dHS is reset to the disabled state. According to an embodiment of the present invention, the width of the negative pulse of the lower bridge dead time signal CK_L is used to determine the lower bridge dead time of the lower bridge transistor 112. According to an embodiment of the present invention, the first adjustment current IX is used to adjust the length of the lower bridge dead time.

[0340] As Figure 5 shown, the control circuit 500 further includes a first inverter INV1, a fourth AND gate AND4, a third flip-flop FF3, a fifth AND gate AND5, a second OR gate OR2, a second dead time generator DT2, and a sixth AND gate AND6. The first inverter INV1 inverts the delayed upper bridge drive signal dHS that is in the disabled state, and sets the initial upper bridge drive signal IHS to the enabled state. When the lower bridge dead time signal CK_L changes from the disabled state (negative pulse) to the enabled state and the burst signal BST is in the disabled state (at Figure 5In an embodiment, when the high logic bit is present, the third flip-flop FF3 outputs the initial upper bridge drive signal IHS in an enabled state as a delayed lower bridge drive signal dLS (i.e., in an enabled state).

[0341] Next, when the delayed lower bridge drive signal dLS is in an enabled state, the rectification signal FW exceeds the compensation signal COMP, and the phase signal SE is in an enabled state, the second dead time generator DT2 is enabled through the fifth AND gate AND5 and the second OR gate OR2 to generate a negative pulse in the upper bridge dead time signal CK_H, and the lower bridge drive signal LS is set to a disabled state through the sixth AND gate AND6, thereby not conducting Figure 1 the lower bridge transistor 112. In addition, the negative pulse of the upper bridge dead time signal CK_H resets the third flip-flop FF3, making the delayed lower bridge drive signal dLS in a disabled state. According to an embodiment of the present invention, the width of the negative pulse of the upper bridge dead time signal CK_H is used to determine the upper bridge dead time of the upper bridge transistor 111. According to an embodiment of the present invention, the second adjustment current IY is used to adjust the length of the upper bridge dead time.

[0342] As Figure 5 shown, the control circuit 500 further includes a first cycle limit circuit 501, a second cycle limit circuit 502, and a second inverter INV2. When the enable cycle of the upper bridge drive signal HS exceeds the maximum enable cycle, the first cycle limit circuit 501 issues an enable signal based on the first mapped current IB1 generated by the compensation circuit 400 to trigger the first dead time generator DT1 to generate a negative pulse to reset (or disable) the delayed upper bridge drive signal dHS, thereby disabling the upper bridge drive signal HS. According to an embodiment of the present invention, during the enable cycle of the upper bridge drive signal HS, the upper bridge transistor 111 is conducting; during the enable cycle of the lower bridge drive signal LS, the lower bridge transistor 112 is conducting.

[0343] When the enable cycle of the lower bridge drive signal LS exceeds the maximum enable cycle, the second cycle limit circuit 502 issues an enable signal based on the second mapped current IB2 generated by the compensation circuit 400 to trigger the second dead time generator DT2 to generate a negative pulse to reset or disable the delayed lower bridge drive signal dLS, thereby disabling the lower bridge drive signal LS. The second inverter INV2 is used to invert the delayed lower bridge drive signal dLS to generate an initial lower bridge drive signal ILS.

[0344] As Figure 5As shown, the control circuit 500 further includes a seventh AND gate AND7 and an eighth AND gate AND8. The seventh AND gate AND7 is used to perform a logical AND operation on the lower-bridge dead-time signal CK_L and the over-current signal OCP, and reset the second flip-flop FF2. Specifically, when the lower-bridge dead-time signal CK_L is at a low logic level (i.e., a negative pulse) or the over-current signal OCP is at a low logic level (i.e., a negative pulse), the delayed upper-bridge drive signal dHS is reset to a disabled state.

[0345] The eighth AND gate AND8 is used to perform a logical AND operation on the upper-bridge dead-time signal CK_H and the over-current signal OCP, and reset the third flip-flop FF3. Specifically, when the upper-bridge dead-time signal CK_H is in a negative pulse state or the over-current signal OCP is in a negative pulse state, the delayed lower-bridge drive signal dLS is reset to a disabled state.

[0346] Figure 6 is a waveform diagram showing the control circuit according to an embodiment of the present invention. The following will be combined with Figure 5 the control circuit 500 and Figure 6 the waveform diagram 600 for a detailed explanation.

[0347] At Figure 6 the first time T1, the lower-bridge drive signal LS is in an enabled state and the rectification signal FW continuously increases and just exceeds the compensation signal COMP. As Figure 5 shown, since the rectification signal FW exceeds the compensation signal COMP, the output of the second comparator CMP2 triggers the second dead-time generator DT2 to generate a negative pulse on the upper-bridge dead-time signal CK_H through the fifth AND gate AND5 and the second OR gate OR2, and the negative pulse of the upper-bridge dead-time signal CK_H resets the first flip-flop FF1 and disables the phase signal SE. In addition, the negative pulse of the upper-bridge dead-time signal CK_H simultaneously disables the lower-bridge drive signal LS through the sixth AND gate AND6.

[0348] According to an embodiment of the present invention, when the upper-bridge dead-time signal CK_H is in a disabled state, that is, between the first time T1 and the second time T2, the third flip-flop FF3 is reset and the delayed lower-bridge drive signal dLS is disabled. And the disabled delayed lower-bridge drive signal dLS stops the second dead-time generator DT2 from continuously disabling the upper-bridge dead-time signal CK_H through the fifth AND gate AND5 and the second OR gate OR2, and ends the upper-bridge dead-time and reaches the second time T2.

[0349] At Figure 6At the second time T2, the upper bridge dead time signal CK_H returns from a negative pulse to the enabled state, that is, the upper bridge dead time signal CK_H generates a positive signal edge at the second time T2, causing the second flip-flop FF2 to output the initially enabled lower bridge drive signal ILS as a delayed upper bridge drive signal dHS, and setting the upper bridge drive signal HS to the enabled state through the third AND gate AND3.

[0350] At Figure 6 the third time T3, the upper bridge drive signal HS remains in the enabled state, and the rectification signal FW continues to increase and just exceeds the compensation signal COMP. As Figure 5 shown, since the rectification signal FW increases and exceeds the compensation signal COMP, the output of the second comparator CMP2 triggers the first dead time generator DT1 to generate a negative pulse on the lower bridge dead time signal CK_L through the second AND gate AND2 and the first OR gate OR1, and the negative pulse of the lower bridge dead time signal CK_L resets the first flip-flop FF1 to disable the phase signal SE. In addition, the negative pulse of the lower bridge dead time signal CK_L simultaneously disables the upper bridge drive signal HS through the third AND gate AND3.

[0351] According to an embodiment of the present invention, when the lower bridge dead time signal CK_L is in the disabled state, the second flip-flop FF2 is reset to disable the delayed upper bridge drive signal dHS, and the disabled delayed upper bridge drive signal dHS stops the first dead time generator DT1 from continuously disabling the lower bridge dead time signal CK_L through the second AND gate AND2 and the first OR gate OR1, causing the lower bridge dead time signal CK_L to return to the enabled state.

[0352] At Figure 6 the fourth time T4, the lower bridge dead time signal CK_L returns from a negative pulse to the enabled state, that is, the lower bridge dead time signal CK_L generates a positive signal edge at the fourth time T4, and with the burst signal BST being in the disabled state (i.e., high logic level), causing the third flip-flop FF3 to output the initially enabled upper bridge drive signal IHS as a delayed lower bridge drive signal dLS, and setting the lower bridge drive signal LS to the enabled state through the sixth AND gate AND6.

[0353] Figure 7 FIG. is a circuit diagram showing a delay time generator according to an embodiment of the present invention. According to an embodiment of the present invention, Figure 7 the delay time generator 700 corresponds to Figure 5 the first dead time generator DT1 and the second dead time generator DT2 of

[0354] As Figure 7As shown, the delay time generator 700 includes a third inverter INV3, a second N-type transistor MN2, a third capacitor C3, a second current source CS2, a second current mirror CM2, a third current source CS3, and a third comparator CMP3.

[0355] When the input signal IN received by the third inverter INV3 is in a disabled state, the second N-type transistor MN2 is turned on, and the first capacitor voltage VCAP1 generated by the third capacitor C3 is coupled to the ground terminal. When the third inverter INV3 then receives an input signal IN in an enabled state, the second N-type transistor MN2 is turned off, and the second current mirror CM2 maps the second current I2 generated by the second current source CS2 to a fourth current I4. With the addition of the third current I3 generated by the third current source CS3 connected in parallel to the second current mirror CM2, the third capacitor C3 is charged by a fifth current I5 to generate the first capacitor voltage VCAP1. According to an embodiment of the present invention, the fifth current I5 is the sum of the third current I3 and the fourth current I4.

[0356] When the first capacitor voltage VCAP1 exceeds the second critical voltage VT2, the third comparator CMP3 generates an output signal OUT in a disabled state. When the input signal IN returns to the disabled state again, the second N-type transistor MN2 is turned on to discharge the first capacitor voltage VCAP1 to the ground terminal, causing the output signal OUT generated by the third comparator CMP3 to return to the enabled state again. According to an embodiment of the present invention, the fifth current I5 determines the length of the charging time based on the capacitance value of the third capacitor C3.

[0357] According to an embodiment of the present invention, when an additional input current IA is provided to the second current source CS2, the magnitude of the fourth current I4 is reduced, thereby reducing the fifth current I5 for charging the third capacitor C3, so that the time for the output signal OUT to remain in the disabled state can be extended. In other words, by increasing the magnitude of the input current IA, the time of the negative pulse of the output signal OUT can be adjusted. According to some embodiments of the present invention, Figure 7 the input current IA corresponds to Figure 5 the first adjustment current IX and the second adjustment current IY.

[0358] Figure 8 is a schematic diagram showing a time-voltage conversion circuit according to an embodiment of the present invention. According to an embodiment of the present invention, Figure 2 the automatic adjustment circuit 221 of Figure 8As shown, the time-voltage conversion circuit 800 includes a fourth current source CS4, a third OR gate OR3, a first switch SW1, a first NAND gate NAND1, a second switch SW2, a fourth capacitor C4, a third switch SW3, a fifth capacitor C5, a fourth switch SW4, and a sixth capacitor C6.

[0359] The fourth current source CS4 generates a fourth current I4. The third OR gate OR3 performs a logical OR operation on the upper-bridge drive signal HS and the lower-bridge drive signal LS to turn on the first switch SW1, so that a sixth current I6 charges the fourth capacitor C4. The first NAND gate NAND1 performs a logical NAND operation on the upper-bridge dead-time signal CK_H and the lower-bridge dead-time signal CK_L to turn on the second switch SW2, so that the fourth capacitor C4 discharges to the ground terminal.

[0360] The upper-bridge drive signal HS controls the third switch SW3, so that the sixth current I6 can charge the fifth capacitor C5 to generate an upper-bridge enable-period voltage VDH. The lower-bridge drive signal LS controls the fourth switch SW4, so that the sixth current I6 can charge the sixth capacitor C6 to generate a lower-bridge enable-period voltage VDL.

[0361] In other words, when the upper-bridge drive signal HS is in an enabled state, the sixth current I6 charges the fourth capacitor C4 and the fifth capacitor C5. When the lower-bridge drive signal LS is in an enabled state, the sixth current I6 charges the fourth capacitor C4 and the sixth capacitor C6. During the upper-bridge dead time and the lower-bridge dead time, the fourth capacitor C4 is discharged to clear the charge stored in the fourth capacitor C4. Therefore, the upper-bridge enable-period voltage VDH represents the enable period of the upper-bridge drive signal HS, and the lower-bridge enable-period voltage VDL represents the enable period of the lower-bridge drive signal LS.

[0362] Figure 9 is a schematic diagram showing an automatic adjustment circuit according to an embodiment of the present invention. According to an embodiment of the present invention, the automatic adjustment circuit 900 corresponds to Figure 2 the automatic adjustment circuit 221.

[0363] As Figure 9 shown, the automatic adjustment circuit 900 includes a comparison circuit 910, a signal generation circuit 920, a fourth flip-flop FF4, a fifth flip-flop FF5, a second counter 930, and a second digital-to-analog converter 940. The comparison circuit 910 is used to compare the upper-bridge enable-period voltage VDH and the lower-bridge enable-period voltage VDL to generate an up signal UP and a down signal DWN.

[0364] The signal generation circuit 920 generates a clock signal CLK and a latch signal LTH based on the upper bridge dead time signal CK_H and the lower bridge dead time signal CK_L. The fourth flip-flop FF4 latches the up-count signal UP into the latched up-count signal LUP based on the latch signal LTH. The fifth flip-flop FF5 latches the down-count signal DWN into the latched down-count signal LDWN based on the latch signal LTH. The second counter 930 counts the digital code B based on the clock signal CLK. When the latched up-count signal LUP is in the enabled state and the latched down-count signal LDWN is in the disabled state, the second counter 930 counts up the digital code B. When the latched up-count signal LUP is in the disabled state and the latched down-count signal LDWN is in the enabled state, the second counter 930 counts down the digital code B.

[0365] As Figure 9 shown, the comparison circuit 910 includes a fourth comparator CMP4, a fifth comparator CMP5, a fourth inverter INV4, a fifth inverter INV5, a ninth AND gate AND9, and a tenth AND gate AND10. When the upper bridge enable period voltage VDH exceeds the lower bridge enable period voltage VDL, the output of the fourth comparator CMP4 is in the enabled state and the output of the fifth comparator CMP5 is in the disabled state. When the upper bridge enable period voltage VDH does not exceed the lower bridge enable period voltage VDL, the output of the fourth comparator CMP4 is in the disabled state and the output of the fifth comparator CMP5 is in the enabled state. Then, the up-count signal UP and the down-count signal DWN are generated through the fourth inverter INV4, the fifth inverter INV5, the ninth AND gate AND9, and the tenth AND gate AND10.

[0366] In other words, when the upper bridge enable period voltage VDH exceeds the lower bridge enable period voltage VDL, the up-count signal UP is in the enabled state and the down-count signal DWN is in the disabled state. When the upper bridge enable period voltage VDH does not exceed the lower bridge enable period voltage VDL, the up-count signal UP is in the disabled state and the down-count signal DWN is in the enabled state. That is, when the enable period of the upper bridge drive signal HS exceeds the enable period of the lower bridge drive signal LS, the second counter 930 counts up the digital code B to cause the second digital-to-analog converter 940 to increase the adjustment current ID. When the enable period of the upper bridge drive signal HS does not exceed the enable period of the lower bridge drive signal LS, the second counter 930 counts down the digital code B to cause the second digital-to-analog converter 940 to decrease the adjustment current ID.

[0367] The signal generation circuit 920 includes an eleventh AND gate AND11, a fifth current source CS5, a third N-type transistor MN3, a seventh capacitor C7, a sixth inverter INV6, and a twelfth AND gate AND12. The eleventh AND gate AND11 performs a logical AND operation on the upper bridge dead time signal CK_H and the lower bridge dead time signal CK_L to generate a clock signal CLK. When either the upper bridge dead time signal CK_H or the lower bridge dead time signal CK_L is in a negative pulse, the clock signal CLK is in a disabled state, and the seventh current I7 of the fifth current source CS5 charges the seventh capacitor C7 to generate a second capacitor voltage VCAP2, and the sixth inverter INV6 inverts the clock signal CLK, so that the latch signal LTH output by the twelfth AND gate AND12 generates a positive signal edge, thereby triggering the fourth flip-flop FF4 and the fifth flip-flop FF5 to latch the up-count signal UP and the down-count signal DWN respectively.

[0368] According to an embodiment of the present invention, when the enable period of the upper bridge drive signal HS exceeds the enable period of the lower bridge drive signal LS, the adjustment current ID is increased to increase the offset voltage VOS and the base voltage VBS, thereby shortening the enable period of the upper bridge drive signal HS and extending the enable period of the lower bridge drive signal LS. According to another embodiment of the present invention, when the enable period of the upper bridge drive signal HS does not exceed the enable period of the lower bridge drive signal LS, the adjustment current ID is decreased to decrease the offset voltage VOS and the base voltage VBS, thereby extending the enable period of the upper bridge drive signal HS and shortening the enable period of the lower bridge drive signal LS. In other words, by adjusting the base voltage VBS, the enable period of the upper bridge drive signal HS is made close to the enable period of the lower bridge drive signal LS.

[0369] Figure 10 is a block diagram showing an output voltage detection circuit according to an embodiment of the present invention. According to an embodiment of the present invention, Figure 1 the control circuit 160 further includes an output voltage detection circuit 1000. As Figure 10 shown, the output voltage detection circuit 1000 includes a sixth comparator CMP6, a sixth flip-flop FF6, a seventh inverter INV7, an eighth inverter INV8, and a delay circuit 1010.

[0370] The sixth comparator CMP6 compares the feedback voltage FB and the low-power critical voltage VTLP to generate a comparison signal CP. According to an embodiment of the present invention, when Figure 1 the output voltage VOUT increases, the feedback voltage FB decreases, and the increase in the output voltage VOUT represents a decrease in the output power. In other words, when Figure 10 the comparison signal CP of is a high logic level, it represents that the output power is too low.

[0371] The seventh inverter INV7 inverts the lower-bridge dead-time signal CK_L, triggering the sixth flip-flop FF6 to output the comparison signal CP as the pre-burst signal PSR, and generating the inverted pre-burst signal PSB via the eighth inverter INV8. The sixth flip-flop FF6 outputs the comparison signal CP as the pre-burst signal PSR according to the positive signal edge of the output signal of the seventh inverter INV7. In addition, when the over-current signal OCP is at a low logic level, the pre-burst signal PSR is set to the enabled state; when the reset signal ST is at a low logic level, the pre-burst signal PSR is set to the disabled state.

[0372] After receiving the inverted pre-burst signal PSB at a high logic level, the delay circuit 1010 delays for a delay time to generate the reset signal ST to reset the pre-burst signal PSR, and Figure 4 the third mapped current IB3 is used to adjust the delay time of the delay circuit 1010. According to an embodiment of the present invention, the delay circuit 1010 can be implemented by Figure 7 the delay time generator 700, where the pre-burst signal PSR corresponds to Figure 7 the input signal IN, and the reset signal ST corresponds to Figure 7 the output signal OUT, and the detailed operation will not be repeated here.

[0373] As Figure 10 shown, the output voltage detection circuit 1000 further includes a fourth N-type transistor MN4, a sixth current source CS6, an eighth capacitor C8, a first NOR gate NOR1, a seventh flip-flop FF7, a ninth inverter INV9, a fourth OR gate OR4, and a thirteenth AND gate AND13.

[0374] The fourth N-type transistor MN4 is controlled by the zero-current signal ZCD to discharge the third capacitor voltage VCAP3 to the ground terminal, and the eighth capacitor C8 is coupled between the third capacitor voltage VCAP3 and the ground terminal. The sixth current source CS6 provides the eighth current I8 to charge the eighth capacitor C8 to generate the third capacitor voltage VCAP3. The seventh flip-flop FF7 enables the first signal S1 (i.e., a high logic level) based on the positive signal edge of the pre-burst signal PSR. The ninth inverter INV9 inverts the first signal S1 to generate the first inverted signal S1B. The first NOR gate NOR1 performs a NOR operation on the third capacitor voltage VCAP3 and the lower-bridge drive signal LS to reset the first signal S1.

[0375] The fourth OR gate OR4 performs a logical OR operation on the first inverted signal S1B and the zero current signal ZCD to generate a second signal S2. The thirteenth AND gate AND13 performs a logical AND operation on the inverted pre-burst signal PSB and the second signal S2 to generate a burst signal BST. According to an embodiment of the present invention, when the resonant power conversion circuit 100 returns from the burst mode to the normal operation mode (i.e., the burst signal BST transitions from a low logic level to a high logic level), the rising edge of the burst signal BST aligns with the rising edge of the zero current signal ZCD. In other words, the resonant power conversion circuit 100 returns from the burst mode to the normal operation mode only when the current flowing through the resonant capacitor CR approaches zero.

[0376] Figure 11 is a waveform diagram showing the operation of the resonant power conversion circuit according to an embodiment of the present invention under a light load. As Figure 11 shown, when the burst signal BST is at a high logic level (i.e., the disabled state), Figure 1 the resonant power conversion circuit 100 operates in the normal operation mode. Therefore, the high-side drive signal HS and the low-side drive signal LS are interleaved to turn on the high-side transistor 111 and the low-side transistor 112, respectively.

[0377] When the output voltage VOUT continuously rises and causes the burst signal BST to transition to a low logic level (i.e., the enabled state), the resonant power conversion circuit 100 operates in the burst mode, such that both the high-side drive signal HS and the low-side drive signal LS are maintained in the disabled state and the high-side transistor 111 and the low-side transistor 112 are not turned on simultaneously. In addition, the falling edge of the burst signal BST aligns with the falling edge of the high-side drive signal HS, and the rising edge of the burst signal BST aligns with the rising edge of the low-side drive signal LS.

[0378] Figure 12 is a block diagram showing the second current detection circuit according to an embodiment of the present invention. As Figure 12 shown, the second current detection circuit 1200 corresponds to Figure 1 the second current detection circuit 150, and includes a seventh current source CS7, a first comparison circuit 1210, and a second comparison circuit 1220.

[0379] The seventh current source CS7 provides a ninth current I9 flowing to the third detection node ND3, where the ninth current I9 flows through Figure 1 the fourth resistor R4 and the first resistor R1 to generate a DC bias voltage VB. As Figure 1As shown, the AC signal of the resonant node NR is coupled to the first detection node ND1 and the third detection node ND3 through the first capacitor C1. Therefore, the AC signal of the resonant node NR combines with the DC bias voltage VB of the third detection node ND3 to generate the current detection voltage VCS of the third detection node ND3.

[0380] When the current detection voltage VCS exceeds the first upper critical voltage VTH1 or the current detection voltage VCS is less than the first lower critical voltage VTL1, the first comparison circuit 1210 is used to generate a negative pulse on the overcurrent signal OCP. When the current detection voltage VCS exceeds the first upper critical voltage VTH1 or is lower than the first lower critical voltage VTL1, it represents an overcurrent state (i.e., the current flowing through the resonant capacitor CR exceeds a preset value). When the current detection voltage VCS is less than the first zero-current critical voltage VTZ1, the second comparison circuit 1220 is used to generate a negative pulse on the zero-current signal ZCD. In other words, when the zero-current signal ZCD is at a low logic level, it represents that the current flowing through the resonant capacitor CR is close to zero. According to an embodiment of the present invention, the first zero-current critical voltage VTZ1 is slightly greater than the bias voltage VB.

[0381] Specifically, the first comparison circuit 1210 includes a seventh comparator CMP7, an eighth comparator CMP8, a fifth OR gate OR5, and a delay circuit 1211. The seventh comparator CMP7 is used to compare the current detection voltage VCS with the first upper critical voltage VTH1, and the eighth comparator CMP8 is used to compare the current detection voltage VCS with the first lower critical voltage VTL1. When the current detection voltage VCS exceeds the first upper critical voltage VTH1 or is lower than the first lower critical voltage VTL1, the output signals of the seventh comparator CMP7 and the eighth comparator CMP8 trigger the delay circuit 1211 to generate a negative pulse on the overcurrent signal OCP through the fifth OR gate OR5. According to an embodiment of the present invention, the delay circuit 1211 can be implemented by Figure 7 the delay time generator 700, where the output signal of the fifth OR gate OR5 corresponds to Figure 7 the input signal IN, and the overcurrent signal OCP corresponds to Figure 7 the output signal OUT. The detailed operation will not be repeated here.

[0382] The second comparison circuit 1220 includes a ninth comparator CMP9, an eighth current source CS8, a ninth capacitor C9, a fifth N-type transistor MN5, and a second NOR gate NOR2. The ninth comparator CMP9 compares the current detection voltage VCS with a first zero-current threshold voltage VTZ1 to generate a comparison result CRE. The eighth current source CS8 provides a tenth current I10 to the fourth capacitor voltage VCAP4 to charge the ninth capacitor C9. The fifth N-type transistor MN5 couples the fourth capacitor voltage VCAP4 to the ground terminal according to the comparison result CRE. The second NOR gate NOR2 performs a logical NOR operation on the fourth capacitor voltage VCAP4 and the comparison result CRE to generate a zero-current signal ZCD.

[0383] According to an embodiment of the present invention, when the comparison result CRE changes from a high logic level to a low logic level, that is, when the current detection voltage VCS drops below the first zero-current threshold voltage VTZ1, the fifth N-type transistor MN5 is turned off and the ninth capacitor C9 starts to charge, thereby generating a positive pulse on the zero-current signal ZCD.

[0384] Figure 13 is a waveform diagram showing a resonant power conversion circuit according to an embodiment of the present invention. The following description of Figure 13 the waveform diagram will be accompanied by Figure 1 and Figure 12 for detailed illustration.

[0385] As Figure 1 and Figure 13 shown, when the resonant power conversion circuit 100 operates, a signal similar to a sine wave exists on the switching node SW. As Figure 1 shown, since the signal of the resonant node NR is coupled to the current detection voltage VCS through the first capacitor C1, and as Figure 12 shown, the ninth current I9, the fourth resistor R4, and the first resistor R1 generate a DC bias voltage VB, the signal of the resonant node NR is superimposed on the bias voltage VB to generate the current detection voltage VCS.

[0386] As Figure 12 and Figure 13 shown, since the first zero-current threshold voltage VTZ1 is slightly greater than the bias voltage VB, when the current detection voltage VCS exceeds the first zero-current threshold voltage VTZ1 (which can be regarded as the current detection voltage VCS exceeding the bias voltage VB), the comparison result CRE is at a high logic level. When the current detection voltage VCS gradually decreases and is lower than the first zero-current threshold voltage VTZ1, the comparison result CRE generates a falling edge, causing a positive pulse to be generated on the zero-current signal ZCD. In addition, the positive pulse of the zero-current signal ZCD exactly occurs at the trough position of the signal on the switching node SW.

[0387] As Figure 10 shown, the burst signal BST is a high logic level based on the zero current signal ZCD being a high logic level. As Figure 11 shown, when the burst signal BST is a high logic level (i.e., the disabled state), the resonant power conversion circuit 100 enters the normal operation mode, and when the resonant power conversion circuit 100 enters the normal operation mode, the lower bridge drive signal LS first enters the enabled state. That is, when the resonant power conversion circuit 100 switches from the burst mode to the normal operation mode, the lower bridge transistor 112 conducts first, and the lower bridge transistor 112 conducts at the lowest point of the signal at the switching node SW.

[0388] In other words, when the resonant power conversion circuit 100 switches from the burst mode to the normal operation mode, the lower bridge transistor 112 conducts at the trough of the signal at the switching node SW, which helps to reduce the power loss caused by the switch switching.

[0389] Figure 14 is a block diagram showing a resonant power conversion circuit according to another embodiment of the present invention. Comparing the resonant power conversion circuit 1400 with the Figure 1 resonant power conversion circuit 100, Figure 1 the fourth resistor R4 of the

[0390] As Figure 14 shown, the resonant power conversion circuit 1400 includes a package 1410. The package 1410 is used to integrate the second resistor R2, the third resistor R3, the third capacitor C3, the integrating amplifier 131, the full-wave rectifying device 140, the second current detection circuit 1411, the control circuit 160, the shift register circuit 170, the upper bridge drive circuit HSD, and the lower bridge drive circuit LSD in the same package. According to another embodiment of the present invention, when the resonant power conversion circuit 1400 is applied to a non-isolated occasion, the package 1410 may further include a feedback circuit 190.

[0391] Figure 15 is a block diagram showing a second current detection circuit according to another embodiment of the present invention. According to an embodiment of the present invention, the second current detection circuit 1500 corresponds to the Figure 14 second current detection circuit 1411 of the Figure 12 Comparing the second current detection circuit 1500 with the Figure 12 second current detection circuit 1200 of the

[0392] As Figure 15 shown, the second current detection circuit 1500 includes a first comparison circuit 1210 and a second comparison circuit 1220. Compared with the second current detection circuit 1200 of Figure 12 , the first comparison circuit 1210 uses a second upper critical voltage VTH2 and a second lower critical voltage VTL2 as comparison references, and the second comparison circuit 1220 uses a second zero-current critical voltage VTZ2 as a comparison reference.

[0393] In addition, since the current detection voltage VCS of the second current detection circuit 1500 does not have the Figure 12 bias voltage VB, therefore Figure 15 the second upper critical voltage VTH2 and the second lower critical voltage VTL2 are different from the first upper critical voltage VTH1 and the first lower critical voltage VTL1 respectively, and the second zero-current critical voltage VTZ2 is also different from the first zero-current critical voltage VTZ1. According to some embodiments of the present invention, the second zero-current critical voltage VTZ2 is slightly greater than zero.

[0394] Figure 16 is a flowchart showing a control method for controlling a resonant power conversion circuit according to an embodiment of the present invention. The following description of the control method 1600 of Figure 16 will be described in conjunction with the resonant power conversion circuit 100 of Figure 1 for detailed illustration.

[0395] First, the first current detection circuit 120 of Figure 1 is used to detect the current flowing through the resonant capacitor CR, and a current detection signal CS is generated (step S1610). As Figure 1 shown, the first current detection circuit 120 detects the voltage of the resonant node NR, and a current detection signal CS is generated at the first detection node ND1.

[0396] Next, the integrator 130 integrates the current detection signal CS based on the reference voltage VREF to generate an integration signal INT (step S1620). The full-wave rectifier 140 full-wave rectifies the integration signal INT to generate a rectified signal FW (step S1630). Subsequently, the control circuit 160 drives the upper bridge transistor 111 and the lower bridge transistor 112 based on the rectified signal FW and the feedback voltage FB (step S1640).

[0397] According to an embodiment of the present invention, Figure 2 the full-wave rectifier 200 of Figure 4 full-wave rectifies the integration signal INT to generate a rectified signal FW and a cross signal SZ, Figure 5The control circuit 500 generates an upper-bridge drive signal HS and a lower-bridge drive signal LS by comparing a compensation signal COMP and a rectification signal FW and based on a cross signal SZ. In addition, the upper-bridge drive signal HS and the lower-bridge drive signal LS are respectively used to drive an upper-bridge transistor 111 and a lower-bridge transistor 112.

[0398] The present invention provides a resonant power conversion circuit and a control method thereof. A rectification signal is generated by full-wave rectifying a current detection signal related to the current flowing through a resonant capacitor, a compensation signal is generated based on a feedback voltage, and the rectification signal is compared with the compensation signal, so that the enable period of the upper-bridge transistor can approach the enable period of the lower-bridge transistor, thereby improving the conversion efficiency of the resonant power conversion circuit. In addition, the resonant power conversion circuit and the control method thereof of the present invention further detect the time point when the current flowing through the resonant capacitor is zero, and turn on the lower-bridge transistor at this time point to reduce the power loss generated by the switching of the switch, thereby further improving the conversion efficiency of the resonant power conversion circuit.

[0399] Although the embodiments of the present disclosure and their advantages have been disclosed above, it should be understood that any person skilled in the art can make changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure. In addition, the protection scope of the present disclosure is not limited to the processes, machines, manufactures, compositions of matter, devices, methods, and steps in the specific embodiments described in the specification. Any person skilled in the art can understand the processes, machines, manufactures, compositions of matter, devices, methods, and steps developed currently or in the future from the disclosure content of some embodiments of the present disclosure. As long as they can perform substantially the same functions or obtain substantially the same results in the embodiments described herein, they can be used according to some embodiments of the present disclosure. Therefore, the protection scope of the present disclosure includes the above-mentioned processes, machines, manufactures, compositions of matter, devices, methods, and steps. In addition, each claim constitutes an individual embodiment, and the protection scope of the present disclosure also includes the combination of each claim and the embodiment.

Claims

1. A resonant power conversion circuit, characterized in that: include: A resonant capacitor coupled between a resonant node and a ground terminal; A transformer, comprising a primary coil and a secondary coil, wherein the primary coil is coupled between a switching node and the resonant node; an upper bridge transistor, providing an input voltage to the switching node based on an upper bridge driving signal; a lower bridge transistor, coupling the switching node to the ground terminal based on a lower bridge driving signal; a first current detection circuit, generating a current detection signal based on the voltage of the resonant node; an integrator, generating an integrated signal based on the current detection signal; a full-wave rectifier for full-wave rectifying the integrated signal generated by the integrator to generate a rectified signal; a control circuit, generating the upper bridge driving signal and the lower bridge driving signal based on the rectified signal and a feedback voltage; a rectifier circuit coupled to the secondary coil and converting the current flowing through the secondary coil into an output voltage; and A feedback circuit generates the feedback voltage based on the output voltage.

2. The resonant power conversion circuit according to claim 1, wherein: The first current detection circuit comprises: a first capacitor coupled between the resonant node and a first detection node; and A first resistor coupled between the first detection node and the ground terminal; The first current detection circuit generates the current detection signal at the first detection node.

3. The resonant power conversion circuit according to claim 2, wherein: The above integrator includes: An integrating amplifier, comprising an integrating positive input terminal, an integrating negative input terminal and an integrating output terminal, wherein the integrating positive input terminal receives a reference voltage, and the integrating output terminal generates the integrating signal; a second capacitor coupled between the first detection node and a second detection node; A second resistor coupled between the second detection node and the integral negative input terminal; a third resistor coupled between the above-mentioned integral negative input terminal and the above-mentioned integral output terminal; and A third capacitor is coupled between the above-mentioned integral negative input terminal and the above-mentioned integral output terminal.

4. The resonant power conversion circuit according to claim 3, wherein: The full-wave rectifier uses a basic voltage as a DC potential to perform full-wave rectification on the integrated signal to generate the rectified signal; The base voltage is equal to the sum of the reference voltage and an offset voltage. The full-wave rectifier device further compares the rectified signal with a first critical voltage to generate a crossover signal; The first critical voltage is slightly greater than the basic voltage.

5. The resonant power conversion circuit as claimed in claim 4, characterized in that: The control circuit comprises: A digital circuit gradually increases a soft start voltage to the feedback voltage within a predetermined time; a first amplifier, comprising a first positive input terminal, a first negative input terminal and a first output terminal, wherein the first positive input terminal receives the soft start voltage, and the first negative input terminal is coupled to the first output terminal; A second amplifier, comprising a second positive input terminal, a second negative input terminal and a second output terminal, wherein the second positive input terminal receives a feedback threshold voltage, and the second output terminal generates a compensation voltage; a second resistor, coupled between the second negative input terminal and the first output terminal, and generating a difference current; An N-type transistor, comprising a gate terminal, a drain terminal and a source terminal, wherein the gate terminal is coupled to the second output terminal, and the source terminal is coupled to the second negative input terminal; a current mirror, mapping the difference current into at least one mapping current; and a summing circuit, subtracting a sawtooth wave from the compensation voltage to generate a compensation signal; When the soft-start voltage is less than the feedback critical voltage, the compensation voltage is equal to the feedback critical voltage; When the soft-start voltage is not less than the feedback critical voltage, the compensation voltage is equal to the soft-start voltage.

6. The resonant power conversion circuit as claimed in claim 5, characterized in that: When the rectified signal is less than the first critical voltage, the full-wave rectifier sets the cross signal to a disabled state; When the rectified signal exceeds the first critical voltage, the full-wave rectifier sets the cross signal to an enabled state; wherein in response to the cross signal changing from the disabled state to the enabled state, the control circuit sets a phase signal to the enabled state; In response to the rectified signal exceeding the compensation signal, the control circuit sets the phase signal to the disabled state based on an upper bridge dead time signal or a lower bridge dead time signal; The upper bridge dead time signal controls an upper bridge dead time of the upper bridge driving signal; The lower bridge dead time signal controls a lower bridge dead time of the lower bridge driving signal.

7. The resonant power conversion circuit according to claim 6, wherein: When the upper bridge driving signal turns on the upper bridge transistor and the phase signal is in the enabling state, the control circuit disables the upper bridge driving signal in response to the rectified signal exceeding the compensation signal; When the upper bridge signal does not turn on the upper bridge transistor, the control circuit enables the lower bridge drive signal after the lower bridge dead time to turn on the lower bridge transistor; When the lower bridge driving signal turns on the lower bridge transistor and the phase signal is in the enabling state, the control circuit disables the lower bridge driving signal in response to the rectified signal exceeding the compensation signal; When the lower bridge driving signal does not turn on the lower bridge transistor, the control circuit enables the upper bridge driving signal to turn on the upper bridge transistor after the upper bridge dead time.

8. The resonant power conversion circuit as claimed in claim 6, wherein: The control circuit further limits the enabling period of the upper bridge driving signal and the enabling period of the lower bridge driving signal to be no greater than a maximum enabling period.

9. The resonant power conversion circuit according to claim 6, wherein: The offset voltage is determined based on the difference between the enable period of the upper bridge driving signal and the enable period of the lower bridge driving signal; The offset voltage is used to adjust the enabling period of the upper bridge driving signal and the enabling period of the lower bridge driving signal, so that the enabling period of the upper bridge driving signal is close to the enabling period of the lower bridge driving signal.

10. The resonant power conversion circuit according to claim 6, wherein: The full-wave rectifier comprises: a fourth resistor coupled between the reference voltage and the base voltage, wherein a voltage across the fourth resistor generates the offset voltage; a first current source, providing a first current to flow to the basic voltage; and An automatic adjustment circuit extracts an adjustment current from the basic voltage based on the upper bridge driving signal, the lower bridge driving signal, the upper bridge dead time signal and the lower bridge dead time signal.

11. The resonant power conversion circuit according to claim 10, wherein: In response to the first current being greater than the adjustment current, the offset voltage is positive, and the base voltage is greater than the reference voltage; In response to the first current being smaller than the adjustment current, the offset voltage is a negative value, and the base voltage is smaller than the reference voltage; In response to the first current being equal to the adjustment current, the basic voltage is equal to the reference voltage.

12. The resonant power conversion circuit according to claim 10, wherein: The automatic adjustment circuit comprises: A time-to-voltage conversion circuit, used for converting the enable period of the upper bridge driving signal and the enable period of the lower bridge driving signal into an upper bridge enable period voltage and a lower bridge enable period voltage respectively; The above-mentioned time-to-voltage conversion circuit comprises: a second current source, providing a second current; a first switch, providing the second current to a charging node based on the enabled upper bridge driving signal or the enabled lower bridge driving signal; a second switch, coupling the charging node to the ground terminal during the upper bridge dead time and the lower bridge dead time; a fourth capacitor coupled between the charging node and the ground terminal; a fifth capacitor coupled between an upper bridge enabling period voltage and the ground terminal; A sixth capacitor coupled between a lower bridge enabling period voltage and the ground terminal; a third switch, coupling the charging node to the upper bridge enabling periodic voltage based on the enabled upper bridge driving signal; and a fourth switch, coupling the charging node to the lower bridge enabling periodic voltage based on the enabled lower bridge driving signal; The upper bridge enabling cycle voltage represents the enabling cycle of the upper bridge driving signal, and the lower bridge enabling cycle voltage represents the enabling cycle of the lower bridge driving signal.

13. The resonant power conversion circuit according to claim 12, wherein: The automatic adjustment circuit further comprises: a first comparison circuit, for comparing the upper bridge enabling periodic voltage and the lower bridge enabling periodic voltage to generate an up-counting signal and a down-counting signal; A plurality of registers, used for latching the up-count signal and the down-count signal during the upper bridge dead time and the lower bridge dead time; a counter that counts up a digital code based on the enabled up-count signal and counts down the digital code based on the enabled down-count signal; and a digital-to-analog converter, generating the adjustment current based on the digital code; When the upper bridge enabling period voltage is greater than the lower bridge enabling period voltage, the first comparison circuit enables the up-counting signal and disables the down-counting signal; When the upper bridge enabling period voltage is not greater than the lower bridge enabling period voltage, the first comparison circuit disables the up-counting signal and enables the down-counting signal.

14. The resonant power conversion circuit as claimed in claim 10, wherein: In response to the increase in the output voltage, the feedback voltage decreases; In response to the feedback voltage being lower than a low power critical voltage, a lower bridge dead time signal enables a burst signal, so that the control circuit operates in a burst mode based on the enabled burst signal; When the control circuit operates in the burst mode, both the upper bridge transistor and the lower bridge transistor are not turned on; wherein a duration of the burst mode increases as the output power of the output voltage decreases; The duration is determined by the mapping current.

15. The resonant power conversion circuit according to claim 14, wherein: Also includes: a second current detection circuit, generating an over-current signal and a zero-current signal based on the current detection signal; When the current flowing through the resonant capacitor exceeds a preset value, the overcurrent signal is in a reset state, and the control circuit disables the upper bridge drive signal and the lower bridge drive signal based on the overcurrent signal in the reset state; When the current flowing through the resonant capacitor is approximately zero, the zero current signal is in the enabling state, so that the control circuit enables the lower bridge driving signal based on the zero current signal in the enabling state.

16. The resonant power conversion circuit as claimed in claim 15, characterized in that: The control circuit further operates in the burst mode based on the burst signal in the enable state and the zero current signal in the enable state; The burst mode starts when the upper bridge driving signal is in the disabled state, and ends when the lower bridge driving signal is in the enabled state.

17. The resonant power conversion circuit according to claim 15, wherein: The second current detection circuit comprises: a fifth resistor coupled between the first detection node and a third detection node; a third current source, providing a third current to the third detection node, so that the third current flows through the fifth resistor and the first resistor, wherein a current detection voltage is generated at the third detection node; a second comparison circuit, comparing the current detection voltage with a first upper threshold voltage and a first lower threshold voltage to generate the over-current signal; and a third comparison circuit, comparing the current detection voltage with a zero current threshold voltage to generate the zero current signal; When the current detection voltage is greater than the first upper threshold voltage or the current detection voltage is less than the first lower threshold voltage, the second comparison circuit sets the over-current signal to the reset state; When the current detection voltage exceeds the zero current critical voltage, the third comparison circuit sets the zero current signal to the enable state; The third current flows through the fifth resistor and the first resistor to generate a DC voltage; The above zero current critical voltage is slightly greater than the above DC voltage.

18. The resonant power conversion circuit according to claim 15, wherein: The second current detection circuit comprises: a second comparison circuit, comparing the voltage of the second detection node with a second upper threshold voltage and a second lower threshold voltage to generate the over-current signal; and a third comparison circuit, comparing the voltage of the second detection node with a zero current threshold voltage to generate the zero current signal; When the voltage of the second detection node is greater than the second upper threshold voltage or the voltage of the second detection node is less than the second lower threshold voltage, the second comparison circuit sets the overcurrent signal to the reset state; When the voltage of the second detection node exceeds the zero current critical voltage, the third comparison circuit sets the zero current signal to the enable state; The above zero current critical voltage is slightly greater than zero.

19. A control method for controlling a resonant power conversion circuit, characterized in that: The resonant power conversion circuit includes a resonant capacitor coupled between a resonant node and a ground terminal, a transformer including a primary coil and a secondary coil, an upper bridge transistor providing an input voltage to a switching node, a lower bridge transistor coupling the switching node to the ground terminal, a rectifier circuit converting a current flowing through the secondary coil into an output voltage, and a feedback circuit generating a feedback voltage based on the output voltage, wherein the primary coil is coupled between the switching node and the resonant node, wherein the control method includes: Using a first current detection circuit to detect the current flowing through the resonant capacitor to generate a current detection signal; Integrating the current detection signal based on a reference voltage to generate an integrated signal; Full-wave rectifying the integrated signal to generate a rectified signal; and Based on the rectified signal and a feedback voltage, the upper bridge transistor and the lower bridge transistor are driven; The first current detection circuit includes a first capacitor and a first resistor, wherein the first capacitor is coupled between the resonant node and a first detection node, and the first resistor is coupled between the first detection node and the ground terminal; The current detection signal is generated at the first detection node.

20. The control method according to claim 19, characterized in that: Also includes: Using a basic voltage as a DC potential, full-wave rectifying the integrated signal to generate the rectified signal; and Comparing the rectified signal with a first critical voltage to generate a cross signal; The base voltage is equal to the sum of the reference voltage and an offset voltage. The first critical voltage is slightly greater than the basic voltage.

21. The control method according to claim 20, characterized in that: Also includes: gradually increasing a soft start voltage to the feedback voltage within a predetermined time; Converting the soft start voltage into a compensation voltage; and Subtracting a sawtooth wave from the compensation voltage to generate a compensation signal; When the soft-start voltage is less than the feedback critical voltage, the compensation voltage is equal to the feedback critical voltage; When the soft-start voltage is not less than the feedback critical voltage, the compensation voltage is equal to the soft-start voltage.

22. The control method according to claim 21, characterized in that: Also includes: When the rectified signal is less than the first critical voltage, setting the cross signal to a disabled state; When the rectified signal exceeds the first critical voltage, setting the cross signal to an enabled state; In response to the cross signal changing from the disabled state to the enabled state, setting a phase signal to the enabled state; and In response to the rectified signal exceeding the compensation signal, the phase signal is set to the disabled state during an upper bridge dead time or a lower bridge dead time; The lower bridge dead time is the time from when the upper bridge transistor is turned off to when the lower bridge transistor is turned on. The upper bridge dead time is the time from when the lower bridge transistor is turned off to when the upper bridge transistor is turned on.

23. The control method according to claim 22, characterized in that: Also includes: When the upper bridge transistor is turned on and the phase signal is in the enabled state, the upper bridge transistor is turned off in response to the rectified signal exceeding the compensation signal, wherein when the upper bridge transistor is not turned on, the lower bridge transistor is turned on after the lower bridge dead time; When the lower bridge transistor is turned on and the phase signal is in the enabled state, the lower bridge transistor is turned off in response to the rectified signal exceeding the compensation signal; and When the lower bridge transistor is not conducting, the upper bridge transistor is turned on after the upper bridge dead time.

24. The control method according to claim 22, characterized in that: Also includes: The conduction time of the upper bridge transistor and the conduction time of the lower bridge transistor are limited to be no greater than a maximum enabling period.

25. The control method according to claim 22, characterized in that: Also includes: Determining the offset voltage based on a difference between the on-time of the upper bridge transistor and the on-time of the lower bridge transistor; The offset voltage is used to adjust the on-time of the upper bridge transistor and the on-time of the lower bridge transistor, so that the on-time of the upper bridge transistor is close to the on-time of the lower bridge transistor.

26. The control method according to claim 22, characterized in that: Also includes: The offset voltage is generated by utilizing a voltage across a first resistor, wherein the first resistor is coupled between the reference voltage and the base voltage; Providing a first current to flow to the above-mentioned basic voltage; Using an automatic adjustment circuit, based on the conduction and non-conduction of the upper bridge transistor and the lower bridge transistor, the upper bridge dead time and the lower bridge dead time, an adjustment current is extracted from the basic voltage; In response to the first current being greater than the adjustment current, the offset voltage is positive, and the base voltage is greater than the reference voltage; In response to the first current being smaller than the adjustment current, the offset voltage is a negative value, and the base voltage is smaller than the reference voltage; and In response to the first current being equal to the adjustment current, the basic voltage is equal to the reference voltage.

27. The control method according to claim 26, characterized in that: Also includes: In response to the feedback voltage being lower than a low power threshold voltage, operating in a burst mode, wherein in response to the output voltage increasing, the feedback voltage decreases; In the burst mode, the upper bridge transistor and the lower bridge transistor are not turned on at the same time; and In response to the output power drop of the output voltage, a duration of the burst mode is increased.

28. The control method according to claim 27, characterized in that: Also includes: When the current flowing through the resonant capacitor exceeds a preset value, the upper bridge transistor and the lower bridge transistor are turned off at the same time; as well as When the current flowing through the resonant capacitor is approximately zero, turning on the lower bridge transistor; The burst mode starts when the upper bridge transistor is not conducting, and ends when the upper bridge transistor is not conducting.

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