Universal on-chip oscillator

Abstract

The invention belongs to the technical field of CMOS / BiCMOS high-precision on-chip RC oscillators, and particularly relates to a universal on-chip oscillator. The circuit mainly comprises a reference voltage / current generation module, an analog reference voltage generation module, a switched capacitor charging and discharging device, a three-input amplifier and a dynamic latch. The input end of the reference voltage / current generation module is connected with AVDD, and the analog reference voltage generation module and the switched capacitor charging and discharging device are both connected with the output end of the reference voltage / current generation module; the circuit has the characteristics of high oscillation starting speed, stable period, low power consumption and the like, and in addition, the duty ratio of an output waveform can be adjusted through the specific value of a capacitor. The clock generation circuit is simple in structure, small in area and suitable for a medium / low frequency digital integrated circuit or a digital-analog hybrid integrated circuit.

Description

Technical Field

[0001] The present invention belongs to the technical field of CMOS / BiCMOS high-precision on-chip RC oscillators, and particularly relates to a general-purpose on-chip oscillator. Background Art

[0002] In the field of mixed-signal circuit design, the system requires a crystal oscillator with stable operation, and hopes to output a crystal oscillator / clock signal whose output period is not affected by power supply, temperature, and process drift at a specified oscillation frequency. However, it requires at least two additional input / output nodes and cannot be integrated inside the chip, which not only hinders the high integration of the chip but also increases the device cost; there are also high-precision on-chip RC oscillators on the market. In order to obtain a stable oscillation output, high requirements are put forward for the reference voltage, current, and comparator, and it highly depends on process consistency and trimming design, increasing risks and costs. As a basic IP in mixed-signal circuit design, oscillators are widely used. This design gets rid of the strict requirements of traditional high-precision oscillators for aspects such as reference voltage, bias current, and multi-functional calibration design. The circuit is simple and the process is general, with very high practical value.

[0003] Currently, the technical measures adopted for high-precision RC clock oscillators in existing products or papers are basically to generate analog reference voltages and currents that are not related to temperature, power supply, and process corners. Based on the premise that all control conditions remain constant, a relatively stable charge and discharge cycle is achieved. This design meets the theoretical requirements and is also a commonly used design method, but the disadvantages are also obvious, that is, it is very difficult to obtain analog reference voltages and currents that are basically not related to temperature, power supply, and process corners. For this reason, trimming, high-order temperature compensation, and high power supply rejection design need to be introduced. Even so, the test results often deviate greatly from the design expectations.

[0004] In traditional oscillators, the reference current output by the reference voltage / current generation module has a small relationship with the power supply within a certain range. As the temperature rises, the reference current shows an upward trend. If the reference current remains constant and the process capacitance value fluctuates very little, then at high temperatures, the output frequency of the oscillator will increase proportionally, and at low temperatures, the output frequency will decrease proportionally, resulting in a large difference in the full temperature range. Therefore, the biggest challenge to make the system generate a stable oscillation frequency is to suppress temperature drift. Summary of the Invention

[0005] The present invention provides a general-purpose on-chip oscillator to solve the technical problem in the prior art that the reference current / voltage is greatly affected by temperature and there is temperature drift, resulting in unstable oscillation frequency of the oscillator.

[0006] To achieve the above object, the present invention adopts the following technical solutions: A general-purpose on-chip oscillator includes a reference voltage / current generation module, an analog reference voltage generation module, a switched-capacitor charge / discharger, a three-input amplifier, and a dynamic latch. The input terminal of the reference voltage / current generation module is connected to A VDD , and both the analog reference voltage generation module and the switched-capacitor charge / discharger are connected to the output terminal of the reference voltage / current generation module; The reference voltage / current generation module generates a bias voltage V A and a reference current I PTAT , and the reference current I PTAT is transmitted to the analog reference voltage generation module and the switched-capacitor charge / discharger through the bias voltage V A ; The analog reference voltage generation module includes a resistor, and the resistor generates an analog reference voltage V PTAT after receiving the reference current I COMP ; The switched-capacitor charge / discharger includes a first NMOS transistor and a second NMOS transistor. After the reference current I PTAT is input into the first NMOS transistor, a first voltage signal is output through the node V B . After the reference current I PTAT is input into the second NMOS transistor, a second voltage signal is output through the node V C ; The three-input amplifier is composed of a first NPN transistor, a second NPN transistor, and a third NPN transistor to form three input ports. The output terminal of the three-input amplifier is connected to the input terminal of the dynamic latch, and the output terminal of the dynamic latch is connected to the gates of the first NMOS transistor and the second NMOS transistor; The output terminal of the analog reference voltage generation module is connected to the base of the first NPN transistor; the base of the second NPN transistor is connected to the node V B , and the base of the third NPN transistor is connected to the node V C ; The three-input amplifier receives the analog reference voltage V COMP , the first voltage signal, and the second voltage signal through the first NPN transistor, the second NPN transistor, and the third NPN transistor respectively, and outputs a voltage amplified signal after amplifying and processing them; The dynamic latch adjusts the working states of the first NMOS transistor and the second NMOS transistor according to the amplified voltage signal, thereby changing the first voltage signal, the second voltage signal, and the charge and discharge of the switched-capacitor charge / discharger.

[0007] The output terminal of the reference voltage / current generation module is connected to the gate of the first PMOS transistor. The drain of the first PMOS transistor is connected to one end of the resistor, and the reference current I PTAT is biased and output through the bias voltage V A and applied to the resistor in the analog reference voltage generation module through the first PMOS transistor.

[0008] The reference current I provided by the first PMOS transistor PTAT and the resistance value of the resistor are both positive temperature coefficients.

[0009] The reference current I PTAT is applied to the resistor to obtain an analog reference voltage V COMP that varies linearly with temperature.

[0010] The analog reference voltage generation module further includes a filter capacitor. The filter capacitor is connected in parallel with the resistor. The resistor receives the reference current I through the first PMOS transistor PTAT , and the filter capacitor filters the reference current I PTAT and then outputs the analog reference voltage V COMP .

[0011] The output terminal of the reference voltage / current generation module is also connected to the gates of the second PMOS transistor and the third PMOS transistor. The first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are connected in series. The drain of the second PMOS transistor is connected to the source of the first NMOS transistor in the switched-capacitor charge / discharger through the node V B , and the drain of the third PMOS transistor is connected to the source of the second NMOS transistor in the switched-capacitor charge / discharger through the node V C . The reference current I PTAT is input into the first NMOS transistor through the second PMOS transistor, and the reference current I PTAT is input into the second NMOS transistor through the third PMOS transistor. The drains of the first NMOS transistor and the second NMOS transistor are grounded.

[0012] The switched-capacitor charge / discharger further includes a first capacitor and a second capacitor. The node V B is connected to the positive electrode of the first capacitor, and the node V C is connected to the positive electrode of the second capacitor. The negative electrodes of the first capacitor and the second capacitor are both connected to V SS .

[0013] The output terminal of the reference voltage / current generation module is also connected to a fourth PMOS transistor. The output terminal of the reference voltage / current generation module is serially connected to the gates of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor in sequence. The drain of the fourth PMOS transistor is connected to the source of a third NMOS transistor. The gate of the third NMOS transistor is connected to the gate of a fourth NMOS transistor. The drains of the third NMOS transistor and the fourth NMOS transistor are connected to V SS, the source of the fourth NMOS transistor is connected to the emitters of the first NPN transistor, the second NPN transistor, and the third NPN transistor, and the reference voltage / current generation module provides a voltage source to the first NPN transistor, the second NPN transistor, and the third NPN transistor through the fourth PMOS transistor, the third NMOS transistor, and the fourth NMOS transistor.

[0014] The three-input amplifier further includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor. The collector of the second NPN transistor is connected to the drain and gate of the fifth PMOS transistor and the gate of the seventh PMOS transistor. The collector of the third NPN transistor is connected to the drain and gate of the sixth PMOS transistor and the gate of the eighth PMOS transistor. The drain of the seventh PMOS transistor is connected to the input terminal of the dynamic latch through node V D is connected to the input terminal of the dynamic latch through node V E is connected to the input terminal of the dynamic latch.

[0015] The node V D is connected to the first switch S2 through a transistor in the dynamic latch. The node V E is connected to the second switch S1 through a transistor in the dynamic latch. The dynamic latch adjusts the operating states of the first switch S1 and the second switch S2 according to the input voltage signals of node V E and node V D . The first switch S1 is connected to the gate of the first NMOS transistor. The second switch S2 is connected to the gate of the second NMOS transistor. The dynamic latch adjusts the operating states of the first switch S1 and the second switch S2 according to the input voltage signals of node V E and node V D . Furthermore, it controls the conduction or cutoff of the first NMOS transistor and the second NMOS transistor. When the first NMOS transistor and the second NMOS transistor are conducting, the first NMOS transistor and the second NMOS transistor cross to discharge the first capacitor and the second capacitor; when the first NMOS transistor and the second NMOS transistor are cutoff, the first NMOS transistor and the second NMOS transistor cross to charge the first capacitor and the second capacitor.

[0016] Compared with the prior art, the present invention has the following beneficial effects: The present invention discloses a circuit structure of a general - purpose oscillator, which has the characteristics of fast startup speed, stable period, low power consumption, etc. It does not rely on analog reference voltages and currents that are basically independent of temperature, power supply, and process corners. Through the idea of negative - feedback compensation, it realizes a stable oscillation period output. A simple PTAT current source is used to charge and discharge a capacitor and amplify the differential voltage with a simplified three - terminal input dynamic comparator, so that the output frequency accuracy is not affected by process deviation, temperature drift, and power - supply voltage deviation. In addition, the duty cycle of the output waveform can be adjusted by adjusting the ratio of the first capacitor to the second capacitor. Its structure is simple, the area is small, and it is applicable to clock - generation circuits in medium / low - frequency digital integrated circuits or mixed - signal integrated circuits. It gets rid of the strict requirements of traditional high - precision oscillators for aspects such as reference voltage, bias current, and multi - function calibration design. The circuit is simple and the process is general, with very high practical value. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 : Schematic diagram of the oscillator circuit; Figure 2 : Temperature drift diagram of the on - chip bandgap reference of the oscillator; Figure 3 : Input signal diagram of the three - terminal input amplifier; Figure 4 : Output signal diagram of the three - terminal input amplifier; Figure 5 : Complementary current - voltage diagram that is relatively independent of temperature; Figure 6 : Output diagram of the 1 - MHz oscillation frequency at three temperatures; Figure 7 : Output diagram of the 200 - kHz oscillation frequency at three temperatures. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] To further understand the content of the present invention, the following describes the present invention in detail with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments are only for explaining the present invention and not for limiting it.

[0019] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0020] Refer to Figure 1 , a general - purpose on - chip oscillator, including a reference voltage / current generation module 100, an analog reference voltage generation module 101, a switched - capacitor charge - discharger 102, a three - input amplifier 103, and a dynamic latch 104; the input end of the reference voltage / current generation module 100 is connected to A VDD, the analog reference voltage generation module 101 and the switched-capacitor charge / discharge unit 102 are both connected to the output terminal of the reference voltage / current generation module 100; the output terminal of the reference voltage / current generation module 100 is serially connected to the gates of the first PMOS (P-Metal-Oxide-Semiconductor) transistor 01, the second PMOS transistor 02, the third PMOS transistor 03, and the fourth PMOS transistor 04 in sequence; the analog reference voltage generation module 101 includes a filter capacitor 05 and a resistor 06, the filter capacitor 05 is connected in parallel with the resistor 06, and the drain of the first PMOS transistor 01 is connected to one end of the resistor 06; the switched-capacitor charge / discharge unit 102 includes a first NMOS (N-Metal-Oxide-Semiconductor) transistor 07, a second NMOS transistor 08, a first capacitor 09, and a second capacitor 10, the drain of the second PMOS transistor 02 is connected to the source of the first NMOS transistor 07 in the switched-capacitor charge / discharge unit 102 through a node VB, the drain of the third PMOS transistor 03 is connected to the source of the second NMOS transistor 08 in the switched-capacitor charge / discharge unit 102 through a node VC, the drain of the first NMOS transistor 07 and the drain of the second NMOS transistor 08 are connected to V SS , the node V B is connected to the positive electrode of the first capacitor 09, the node V C is connected to the positive electrode of the second capacitor 10, and the negative electrodes of the first capacitor 09 and the second capacitor 10 are both connected to V SS。The three-input amplifier 103 consists of a first NPN transistor 16, a second NPN transistor 17, and a third NPN transistor 18 to form three input ports. The gate of the first NPN transistor 16 is connected to the output terminal of the analog reference voltage generation module 101. The drain of the fourth PMOS transistor 04 is connected to the source of the third NMOS transistor 11. The gate of the third NMOS transistor 11 is connected to the gate of the fourth NMOS transistor 19. The drains of the third NMOS transistor 11 and the fourth NMOS transistor 19 are connected to VSS. The source of the fourth NMOS transistor 19 is connected to the emitters of the first NPN transistor 16, the second NPN transistor 17, and the third NPN transistor 18. The collector of the second NPN transistor 17 is connected to the drain and gate of the fifth PMOS transistor 12 and the gate of the seventh PMOS transistor 14. The collector of the third NPN transistor 18 is connected to the drain and gate of the sixth PMOS transistor 13 and the gate of the eighth PMOS transistor 15. The drain of the seventh PMOS transistor 14 is connected to the input terminal of the dynamic latch 104 through the node VD. The drain of the eighth PMOS transistor 15 is connected to the input terminal of the dynamic latch 104 through the node VE. The node VD is connected to the gate of the first NMOS transistor 07 through the transistors in the dynamic latch 104. The node VE is connected to the gate of the second NMOS transistor 08 through the transistors in the dynamic latch 104.

[0021] The present invention proposes a general-purpose on-chip oscillator and designs an RC oscillator that is not affected by temperature and power supply voltage. A simple PTAT current source is used to charge and discharge the capacitor and amplify the differential voltage with a simplified three-terminal input dynamic comparator, so that the output frequency accuracy is not affected by process deviation, temperature drift, and power supply voltage deviation. The circuit adopts the domestic commercially mature 0.35μm CMOS mixed-signal manufacturing process, with a working temperature range of -55°C to 125°C, a power supply voltage of 3.3V to 6.5V, the output frequency can cover 10Hz to 10MHz, the relative frequency drift is within 2‰ to 6‰, and at the output frequency of 1MHz, the total power consumption is about 60uA.

[0022] Based on the oscillator circuit diagram as Figure 1 shown, a general-purpose on-chip oscillator of the present invention is a high-precision on-chip RC oscillator including a reference voltage / current generation module 100, an analog reference voltage generation module 101, a switched-capacitor charger 102, a three-input amplifier 103, and a dynamic latch 104.

[0023] First, after the circuit is powered on, the bandgap reference voltage / current source of the reference voltage / current generation module 100 is established. Different from the traditional technology, the present invention uses the bandgap reference voltage V generated by the reference voltage / current generation module 100 BGR, but the reference voltage / current generation module 100 uses the generated bias voltage V A and reference current I PTAT , so in the present invention, the absolute value temperature drift of the bandgap reference voltage V BGR does not affect the core parameter - oscillation frequency. The on-chip bandgap reference temperature drift diagram of the oscillator generated by the bandgap reference voltage V BGR is as shown in Figure 2 . The reference current I PTAT is transmitted to the first PMOS transistor 01, the second PMOS transistor 02, the third PMOS transistor 03, and the fourth PMOS transistor 04 after being biased by the bias voltage V A , and the current value shows a linear upward trend with temperature. The drain of the first PMOS transistor 01 is connected to the positive electrode of the filter capacitor 05 and one end of the resistor 6. The first PMOS transistor 01 applies the reference current I PTAT to the resistor 06. After the filter capacitor 05 filters the reference current I PTAT , the analog reference voltage V COMP is output. The negative electrode of the filter capacitor 05 and the other end of the resistor 06 are grounded. The analog reference voltage V COMP is input into the three-input amplifier 103 through the base of the first NPN transistor 16. The drain of the second PMOS transistor 02 is connected to the source of the first NMOS transistor 07 in the switched-capacitor charge / discharger 102 through the node V B . The drain of the third PMOS transistor 03 is connected to the source of the second NMOS transistor 08 in the switched-capacitor charge / discharger 102 through the node V C . The drains of the first NMOS transistor 07 and the second NMOS transistor 08 are grounded. The reference current I PTAT is input into the first NMOS transistor 07 through the second PMOS transistor 02 and then outputs a first voltage signal through the node V B . The reference current I PTAT is input into the second NMOS transistor 08 through the third PMOS transistor 03 and then outputs a second voltage signal through the node V C . The first voltage signal is input into the three-input amplifier 103 through the base of the second NPN transistor 17. The second voltage signal is input into the three-input amplifier 103 through the third NPN transistor 18. According to the received analog reference voltage V COMP , the first voltage signal, and the second voltage signal, through the current amplification characteristics composed of the fifth PMOS transistor 12, the sixth PMOS transistor 13, the seventh PMOS transistor 14, and the eighth PMOS transistor 15, the three-input amplifier 103 amplifies the analog reference voltage V COMP , the first voltage signal, and the second voltage signal according to the characteristics and outputs a voltage amplification signal. The analog reference voltage V COMP and the first voltage signal are amplified according to the characteristics and then pass through the node V DOutput to the dynamic latch 104, the analog reference voltage V COMP And the second voltage signal characteristic is amplified and output to the dynamic latch 104 through the node V E Output to the dynamic latch 104. The node VD is connected to the first switch S2 through the transistor in the dynamic latch 104, and the node VE is connected to the second switch S1 through the transistor in the dynamic latch 104. The first switch S1 is connected to the gate of the first NMOS transistor 07, and the second switch S2 is connected to the gate of the second NMOS transistor 08. The dynamic latch 104 adjusts the working states of the first switch S1 and the second switch S2 according to the input voltage signals of the node VE and the node VD, and then controls the conduction or cutoff of the first NMOS transistor 07 and the second NMOS transistor 08. When the first NMOS transistor 07 and the second NMOS transistor 08 are conducting, the first NMOS transistor 07 and the second NMOS transistor 08 cross to discharge the first capacitor 09 and the second capacitor 10; when the first NMOS transistor 07 and the second NMOS transistor 08 are cutoff, the first NMOS transistor 07 and the second NMOS transistor 08 cross to charge the first capacitor 09 and the second capacitor 10.

[0024] In the initial working state, the first switch S1 = 0 and the second switch S2 = 1 at the output end of the dynamic latch 104. At this time, the first NMOS transistor 07 is in the cutoff state, and the node V B at the upper plate of the first capacitor 09 is charged by the current bandgap reference through the second PMOS transistor 02. The second NMOS transistor 08 is in the conducting state, and the node V C at the upper plate of the second capacitor 10 forms a discharge loop with the ground through the conducting second NMOS transistor 08. The charge stored in the second capacitor 10 will flow to the ground through this loop, so that the voltage of the upper plate VC of the second capacitor 10 gradually decreases until it reaches a state close to the 0VmV level. The nodes V B , the node V C and the analog reference voltage V COMP The output line graph is as shown in Figure 3 When the dynamic latch 104 makes the first NMOS transistor 07 conduct through the first switch S1, the reference current I PTAT provided by the first PMOS transistor 02 will flow to the first capacitor 09, and the first capacitor 09 starts to charge. The voltage at the node VB of its upper plate gradually increases. When the voltage at the node V B at the upper plate of the first capacitor 09 is charged to V COMP , the working states of the transistors inside the three-input amplifier 103 change, resulting in a change in the voltage state at its output end. The output of the three-input amplifier 103 becomes a high voltage, and the nodes V D and V E The output graph is as shown in Figure 4As shown, at this time, the output of the dynamic latch 104 is S1 = 1 and S2 = 0. The second capacitor 10 is charged by the current bandgap reference source, and at the same time, the voltage on the first capacitor 09 is discharged to 0V (non-absolute value, in the mV range). When the voltage at the point on capacitor 10 is charged to V COMP When this occurs, the output of the three-input amplifier 103 becomes 1. The output of this dynamic latch 104 is S1 = 0 and S2 = 1, and this cycle repeats, causing the RC oscillator to oscillate continuously at a fixed frequency.

[0025] The calculation formula for the output frequency of the RC oscillator is:

[0026] In the above formula, IPTAT is the current flowing through capacitor 09 or 10, that is, the charge and discharge current; C is the capacitance value; V COMP is the analog reference voltage that changes linearly with temperature. When the capacitor is charged to this voltage, the charging stops and the discharging begins. According to the above formula, the output frequency of the RC oscillator can be calculated.

[0027] As Figure 5 shown, for the V COMP and I PTAT output curves of the invention, the slopes of the two curves change consistently with temperature. V COMP changes approximately 2.487 times from low temperature to high temperature, and I PTAT changes approximately 2.488 times from low temperature to high temperature. It can be seen from the above formula that when the slopes of the V COMP and I PTAT output curves are the same, assuming that the process capacitance parameters remain unchanged, then the output frequency can be kept constant. Therefore, only by ensuring that the parasitic capacitance / resistance of the V B and V C nodes are the same can the oscillation frequency be ensured to be stable over the full temperature range.

[0028] When the output frequency of the oscillator is 1 MHz, the oscillation period is 1 μs. As Figure 6 shown, the oscillation period at -55 °C is 1.002 μs, at 25 °C is 0.999 μs, and at 125 °C is 1.000 μs. The oscillation period drift value over the full temperature range is approximately 2‰. The output frequency of the oscillator can be adjusted by configuring capacitor 09, 10 or mirror current transistors 02, 03, and a very stable oscillation period can be achieved. Therefore, a configurable current source / capacitor array can be considered during design. As Figure 7 shown, when the output is adjusted to an oscillation frequency of 200 kHz, the oscillation period is 5 μs. The oscillation period at -55 °C is 4.993 μs, at 25 °C is 4.999 μs, and at 125 °C is 4.992 μs. The oscillation period drift value over the full temperature range is approximately 1.4‰.

[0029] The design verification of the general-purpose on-chip oscillator circuit of the present invention is based on a 0.35μm CMOS mixed-signal design platform. It can achieve high-precision stable clock output within the full temperature range without the need for high-precision low-temperature-drift reference voltages, currents, and complex temperature compensation designs. Within the range of 10Hz to 1MHz of the oscillator output, the duty cycle drift during full temperature operation (-55°C to 125°C) is less than 2‰; within the range of 1MHz to 10MHz of the oscillator output, the duty cycle drift during full temperature operation (-55°C to 125°C) is less than 6‰. It can effectively reduce the dependence of the oscillator on the process and the complexity of the design. The typical power consumption of the oscillator in this design is as low as 60uA.

[0030] This paper designs an extremely simplified low-power on-chip oscillator circuit. In addition, it should be understood that although this specification is described according to embodiments, not every embodiment only contains an independent technical solution. This narrative manner of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art. The above content is only to illustrate the technical idea of the present invention and cannot be used to limit the protection scope of the present invention. Any modification made on the basis of the technical solution according to the technical idea proposed by the present invention falls within the protection scope of the claims of the present invention.

Claims

1. A general-purpose on-chip oscillator, characterized in that: The invention comprises a reference voltage / current generating module (100), an analog reference voltage generating module (101), a switch capacitor charging and discharging device (102), a three-input amplifier (103) and a dynamic latch (104); the input end of the reference voltage / current generating module (100) is connected to A VDD , the analog reference voltage generating module (101) and the switched capacitor charger (102) are both connected to the output end of the reference voltage / current generating module (100); The reference voltage / current generating module (100) generates a bias voltage V A and reference current I PTAT , reference current I PTAT By biasing the voltage V A Transmitted to the analog reference voltage generation module (101) and the switched capacitor charger (102); The analog reference voltage generating module (101) includes a resistor (06) which receives a reference current I PTAT Generate analog reference voltage V COMP ; The switch capacitor charger (102) includes a first NMOS tube (07) and a second NMOS tube (08), and a reference current I PTAT After inputting the first NMOS tube (07), it passes through the node V B Output the first voltage signal, the reference current I PTAT After inputting the second NMOS tube (08), it passes through the node V C outputting a second voltage signal; The three-input amplifier (103) comprises three input ports formed by a first NPN tube (16), a second NPN tube (17) and a third NPN tube (18); the output end of the three-input amplifier (103) is connected to the input end of the dynamic latch (104); the output end of the dynamic latch (104) is connected to the gates of the first NMOS tube (07) and the second NMOS tube (08); The output end of the analog reference voltage generating module (101) is connected to the base of the first NPN tube (16); the base of the second NPN tube (17) is connected to the node V B The base of the third NPN transistor (18) is connected to the node V C The three-input amplifier (103) receives the analog reference voltage V through the first NPN tube (16), the second NPN tube (17) and the third NPN tube (18) respectively. COMP , a first voltage signal and a second voltage signal and amplifies them to output an amplified voltage signal; the dynamic latch (104) adjusts the working state of the first NMOS tube (07) and the second NMOS tube (08) according to the amplified voltage signal, thereby changing the first voltage signal and the second voltage signal and the charging and discharging of the switch capacitor charger (102).

2. A universal on-chip oscillator according to claim 1, characterized in that: The output end of the reference voltage / current generating module (100) is connected to the gate of the first PMOS tube (01), the drain of the first PMOS tube (01) is connected to one end of the resistor (06), and the reference current I PTAT By the bias voltage V A After the bias output, it is applied to the resistor (06) in the analog reference voltage generation module (101) through the first PMOS tube (01).

3. A universal on-chip oscillator according to claim 2, characterized in that: The reference current I provided by the first PMOS tube (01) PTAT The resistance values ​​of resistor (06) are both positive temperature coefficients.

4. A universal on-chip oscillator according to claim 3, characterized in that: The reference current I PTAT The analog reference voltage V applied to resistor (06) COMP Varies linearly with temperature.

5. A universal on-chip oscillator according to claim 2, characterized in that: The analog reference voltage generating module (101) further comprises a filter capacitor (05), the filter capacitor (05) is connected in parallel with a resistor (06), and the resistor (06) receives a reference current I through a first PMOS tube (01). PTAT , the filter capacitor (05) has a significant effect on the reference current I PTAT After filtering, the analog reference voltage V is output COMP .

6. A universal on-chip oscillator according to claim 2, characterized in that: The output end of the reference voltage / current generating module (100) is also connected to the gate of the second PMOS tube (02) and the gate of the third PMOS tube (03), the first PMOS tube (01), the second PMOS tube (02) and the third PMOS tube (03) are connected in series, and the drain of the second PMOS tube (02) is connected via a node V B The source of the first NMOS tube (07) in the switch capacitor charger (102) is connected, and the drain of the third PMOS tube (03) is connected to the node V C is connected to the source of the second NMOS tube (08) in the switched capacitor charger (102), the reference current I PTAT The reference current I PTAT The second NMOS tube (08) is input through the third PMOS tube (03), and the drain of the first NMOS tube (07) and the drain of the second NMOS tube (08) are grounded.

7. A universal on-chip oscillator according to claim 6, characterized in that: The switched capacitor charger (102) also includes a first capacitor (09) and a second capacitor (10), and a node V B Connect the positive electrode of the first capacitor (09), node V C Connect the positive electrode of the second capacitor (10), and the negative electrodes of the first capacitor (09) and the second capacitor (10) are connected to V SS .

8. A universal on-chip oscillator according to claim 2, characterized in that: The output end of the reference voltage / current generating module (100) is also connected to a fourth PMOS tube (04); the output end of the reference voltage / current generating module (100) is connected in series with the gates of the first PMOS tube (01), the second PMOS tube (02), the third PMOS tube (03) and the fourth PMOS tube (04) in sequence; the drain of the fourth PMOS tube (04) is connected to the source of the third NMOS tube (11); the gate of the third NMOS tube (11) is connected to the gate of the fourth NMOS tube (19); the drains of the third NMOS tube (11) and the fourth NMOS tube (19) are connected to V SS The source of the fourth NMOS tube (19) is connected to the emitters of the first NPN tube (16), the second NPN tube (17) and the third NPN tube (18); the reference voltage / current generation module (100) provides a voltage source to the first NPN tube (16), the second NPN tube (17) and the third NPN tube (18) through the fourth PMOS tube (04), the third NMOS tube (11) and the fourth NMOS tube (19).

9. A universal on-chip oscillator according to claim 1, characterized in that: The three-input amplifier (103) further comprises a fifth PMOS tube (12), a sixth PMOS tube (13), a seventh PMOS tube (14) and an eighth PMOS tube (15); the collector of the second NPN tube (17) is connected to the drain and gate of the fifth PMOS tube (12) and the gate of the seventh PMOS tube (14); the collector of the third NPN tube (18) is connected to the drain and gate of the sixth PMOS tube (13) and the gate of the eighth PMOS tube (15); the drain of the seventh PMOS tube (14) is connected to the gate of the seventh PMOS tube (15) via a node V D The input end of the dynamic latch (104) is connected, and the drain of the eighth PMOS tube (15) is connected to the node V E Connected to the input terminal of the dynamic latch (104).

10. A universal on-chip oscillator according to claim 9, characterized in that: The node V D The first switch S2 is connected through the transistor in the dynamic latch (104), and the node V E The second switch S1 is connected via a transistor in the dynamic latch (104), and the dynamic latch (104) is connected according to the node V E and node V D The input voltage signal is used to adjust the working state of the first switch S1 and the second switch S2. The first switch S1 is connected to the gate of the first NMOS tube (07), and the second switch S2 is connected to the gate of the second NMOS tube (08). The dynamic latch (104) is connected according to the node V E and node V D The input voltage signal is used to adjust the working state of the first switch S1 and the second switch S2, thereby controlling the first NMOS tube (07) and the second NMOS tube (08) to be turned on or off. When the first NMOS tube (07) and the second NMOS tube (08) are turned on, the first NMOS tube (07) and the second NMOS tube (08) cross to discharge the first capacitor (09) and the second capacitor (10); when the first NMOS tube (07) and the second NMOS tube (08) are turned off, the first NMOS tube (07) and the second NMOS tube (08) cross to charge the first capacitor (09) and the second capacitor (10).

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