Compensation module and fractional frequency division phase-locked loop circuit
By designing a compensation module including registers, selection output unit and residual unit, the nonlinear and quantization noise problems in the fractional frequency-divided phase-locked loop circuit are solved, and the risk of spurious and loss of lock is achieved, and the performance of the phase-locked loop is improved.
Patent Information
- Application Number
- CN202311817971.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-26
- Publication Date
- 2025-06-27
AI Technical Summary
The decimal frequency-dividing phase-locked loop circuit has nonlinear and quantization noise problems, resulting in stray and loss of locking.
A compensation module is designed, including several registers, select output units and residual units, for compensating for nonlinearity and quantization noise of the fractional frequency-dividing phase-locked loop circuit. The compensation module reduces quantization noise and nonlinear effects by storing the average output data of the phase interpolator and the modulator at different outputs, and subtracting the output data of the time-digital converter using the residual unit.
Effectively compensate for the nonlinearity and quantization noise of the decimal frequency-dividing phase-locked loop circuit, reduce the risk of stray and loss of lock, and improve the performance of the phase-locked loop.
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Figure CN120223067A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and particularly to a compensation module and a fractional-N phase-locked loop circuit. Background Art
[0002] A phase-locked loop is an important part of a radio frequency system. In order to obtain better noise performance and higher frequency resolution, the phase-locked loop is expected to achieve a lower division ratio, a larger filter bandwidth, and fractional-N frequency division with high frequency resolution. Digital phase-locked loops have received increasing attention in deep sub-micron processes due to their good compatibility with digital circuits and adaptability to low supply voltages. Generally, a fractional-N phase-locked loop requires a ΣΔ modulator that outputs a randomly varying integer sequence. The average value of this integer sequence in the time domain is 0.F, where F is the fractional part of the division ratio. This sequence is added to a fixed integer N and then fed to the division control word of the frequency divider, thereby achieving a fractional division ratio of N.F. Since the variation range of the integer sequence output by the ΣΔ modulator is very large, for example, the output integer sequence range of the commonly used MASH 1-1-1 structure ΣΔ modulator is between -3 and 4, which results in a very large variation range of the phase difference input to the phase frequency detector (PFD). This is the quantization noise of fractional-N frequency division. This quantization noise not only deteriorates the phase noise of the phase-locked loop but also easily causes the phase-locked loop to lose lock. To reduce the influence of quantization noise, generally, the filter bandwidth needs to be set very small to filter out the quantization noise, which results in an excessively long lock time of the phase-locked loop and a large noise contribution from the voltage-controlled oscillator (VCO).
[0003] The use of a phase interpolator can effectively reduce quantization noise. The principle is that it can delay the output of the VCO by any phase between 0 and Tvco, where Tvco is the period of the VCO, and the delayed phase is discrete rather than continuous. If the minimum step size of the delayed phase is 360 / N, then the quantization noise can be reduced by N times. In this way, the filter bandwidth can be appropriately increased without worrying about the influence of quantization noise. Figure 1 is a circuit schematic diagram of a phase-locked loop with a phase interpolator in the prior art. Refer to Figure 1, including a Phase Interpolator (PI), a modulator (not shown in the figure), a Time to Digital Invertor (TDC), a Digital Loop Filter (DLF), a Digital Controlled Oscillator (DCO), a divider (DIV), an accumulator (Acc), and a fractional divider digital control module (DIG). The use of the phase interpolator brings a new problem, namely the linearity problem. If the linearity is very poor, although it improves the quantization noise, it will create new spurs.
[0004] Therefore, it is necessary to provide a new type of compensation module and a fractional divider phase-locked loop circuit to solve the above problems existing in the prior art. Summary of the Invention
[0005] The object of the present invention is to provide a compensation module and a fractional divider phase-locked loop circuit to compensate for at least one of the non-linearity and quantization noise of the fractional divider phase-locked loop circuit.
[0006] To achieve the above object, the compensation module of the present invention is applied to a fractional divider phase-locked loop circuit. The compensation module includes a plurality of registers, a selection output unit, and a residual unit. The selection output unit includes a plurality of input ends. The output ends of the plurality of registers are respectively connected to the plurality of input ends of the selection output unit in one-to-one correspondence. The first input end of the residual unit is connected to the input end of the selection output unit. The second input end of the residual unit is used to be connected to the output end of the time digital converter.
[0007] Optionally, the fractional divider phase-locked loop circuit includes a phase interpolator and a time digital converter. The average output of the time digital converter within a target time at different outputs of the phase interpolator is respectively stored in the plurality of registers.
[0008] Optionally, the fractional divider phase-locked loop circuit includes a modulator and a time digital converter. The average output of the time digital converter within a target time at different outputs of the modulator is respectively stored in the plurality of registers.
[0009] Optionally, the fractional divider phase-locked loop circuit includes a phase interpolator, a modulator, and a time digital converter. The average output of the time digital converter within a target time at different outputs of the modulator and the modulator is respectively stored in the plurality of registers.
[0010] Optionally, the fractional-N phase-locked loop circuit includes a phase interpolator, a frequency divider, a modulator, and a time-to-digital converter. In some of the registers, the average output of the time-to-digital converter within a target time when the phase interpolator outputs different values is stored respectively. In the remaining part of the registers, the average output of the time-to-digital converter within the target time when the modulator outputs different values is stored respectively.
[0011] The present invention also provides a fractional-N phase-locked loop circuit, which includes a phase interpolator, a modulator, a time-to-digital converter, a digital filter, a numerically controlled oscillator, a frequency divider, an accumulator, a fractional-N digital control module, and the compensation module. The output end of the time-to-digital converter is connected to the second input end of the residual unit. The output end of the residual unit is connected to the input end of the digital filter. The output end of the digital filter is connected to the input end of the numerically controlled oscillator. The output end of the numerically controlled oscillator is connected to the first input end of the phase interpolator. The output end of the phase interpolator is connected to the first input end of the frequency divider. The output end of the modulator is connected to the second input end of the frequency divider. The output end of the frequency divider is connected to the first input end of the time-to-digital converter, the input end of the fractional-N digital control module, and the first input end of the accumulator. The output end of the fractional-N digital control module is connected to the second input end of the accumulator. The output end of the accumulator is connected to the second input end of the phase interpolator. The second input end of the time-to-digital converter is used to receive a clock signal.
[0012] The beneficial effect of the present invention is that: the compensation module includes a plurality of registers, a selection output unit, and a residual unit. The selection output unit includes a plurality of input ends. The output ends of the plurality of registers are respectively and correspondingly connected to the plurality of input ends of the selection output unit. The first input end of the residual unit is connected to the input end of the selection output unit. The second input end of the residual unit is used to be connected to the output end of the time-to-digital converter. Applying the compensation module to the fractional-N phase-locked loop circuit can compensate for at least one of the non-linearity and quantization noise of the fractional-N phase-locked loop circuit. Description of the Drawings
[0013] Figure 1 is a schematic circuit diagram of a phase-locked loop with a phase interpolator in the prior art;
[0014] Figure 2 is a schematic circuit diagram of the fractional-N phase-locked loop circuit in some embodiments of the present invention.
[0015] Figure 3 is a schematic circuit diagram of the compensation module in some embodiments of the present invention;
[0016] Figure 4Schematic diagram of the compensation module in some other embodiments of the present invention. Detailed implementation manners
[0017] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention. Apparently, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein shall have the ordinary meanings as understood by those of ordinary skill in the art to which the present invention pertains. The words such as "including" used herein are intended to mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items.
[0018] In view of the problems existing in the prior art, embodiments of the present invention provide a fractional-N phase-locked loop circuit. Referring to Figure 2 , the fractional-N phase-locked loop circuit includes a Phase Interpolator (PI), a Sigma Delta Modulator (SDM), a Time to Digital invertor (TDC), a Digital Loop Filter (DLF), a Digital Controlled Oscillator (DCO), a DIVider (DIV), an Accumulator (Acc), a fractional-N Digital Control module (DIG), and a COMPensation module (COMP). The output end of the time digital converter is connected to the second input end of the residual unit, the output end of the residual unit is connected to the input end of the digital filter, the output end of the digital filter is connected to the input end of the digital controlled oscillator, the output end of the digital controlled oscillator is connected to the first input end of the phase interpolator, the output end of the phase interpolator is connected to the first input end of the divider, the output end of the modulator is connected to the second input end of the divider, the output end of the divider is connected to the first input end of the time digital converter, the input end of the fractional-N digital control module, and the first input end of the accumulator. The output end of the fractional-N digital control module is connected to the second input end of the accumulator, the output end of the accumulator is connected to the second input end of the phase interpolator, and the second input end of the time digital converter is used to receive a clock signal.
[0019] In some embodiments, the compensation module includes a plurality of registers, a selection output unit, and a residual unit. The selection output unit includes a plurality of input terminals. The output terminals of the plurality of registers are connected to the plurality of input terminals of the selection output unit in a one-to-one correspondence. A first input terminal of the residual unit is connected to an input terminal of the selection output unit. A second input terminal of the residual unit is configured to be connected to an output terminal of the time-to-digital converter. The residual unit subtracts the data output by the selection output unit from the data output by the time-to-digital converter. An output terminal of the residual unit is connected to an input terminal of the digital filter.
[0020] In some embodiments, the fractional-N phase-locked loop circuit includes a phase interpolator and a time-to-digital converter. The plurality of registers respectively store the average output of the time-to-digital converter within a target time when the phase interpolator outputs different values.
[0021] Figure 3 The figure is a schematic circuit diagram of the compensation module in some embodiments of the present invention. Refer to Figure 3 , when the output range of the phase interpolator is 0 to 255, the compensation module includes 256 registers 100, a selection output unit 200, and a residual unit 300. The output terminals of the 256 registers 100 are connected to the input terminals of the selection output unit 200 in a one-to-one correspondence. A first input terminal of the residual unit 300 is connected to an input terminal of the selection output unit 200. A second input terminal of the residual unit 300 is configured to be connected to an output terminal of the time-to-digital converter. Among them, the first register 100 stores the average output of the time-to-digital converter within a target time when the phase interpolator outputs 0; the second register 100 stores the average output of the time-to-digital converter within a target time when the phase interpolator outputs 1; the third register 100 stores the average output of the time-to-digital converter within a target time when the phase interpolator outputs 2; and so on. The 256th register 100 stores the average output of the time-to-digital converter within a target time when the phase interpolator outputs 255.
[0022] In some embodiments, the plurality of registers respectively store the average output of the time-to-digital converter within a target time when the modulator outputs different values.
[0023] Figure 4 The figure is a schematic circuit diagram of the compensation module in some other embodiments of the present invention. Refer to Figure 4, the output range of the modulator is -3 to 4. The compensation module includes eight registers 100, a selection output unit 200, and a residual unit 300. The output terminals of the eight registers 100 are respectively and correspondingly connected to the input terminal of the selection output unit 200. The first input terminal of the residual unit 300 is connected to the input terminal of the selection output unit 200. The second input terminal of the residual unit 300 is used to be connected to the output terminal of the time-to-digital converter. Among them, the first register 100 stores the average output of the time-to-digital converter within the target time when the output of the modulator is -3; the second register 100 stores the average output of the time-to-digital converter within the target time when the output of the modulator is -2; the third register 100 stores the average output of the time-to-digital converter within the target time when the output of the modulator is -1; and so on. The eighth register 100 stores the average output of the time-to-digital converter within the target time when the output of the modulator is 4.
[0024] In some embodiments, several of the registers respectively store the average output of the time-to-digital converter within the target time when the modulator and the modulator have different outputs.
[0025] In some embodiments, when the output range of the phase interpolator is 0 to 255 and the output range of the modulator is -3 to 4, the compensation module includes 2,048 registers, a selection output unit, and a residual unit. The output terminals of the 2,048 registers are respectively and correspondingly connected to the input terminal of the selection output unit. The first input terminal of the residual unit is connected to the input terminal of the selection output unit. The second input terminal of the residual unit is used to be connected to the output terminal of the time-to-digital converter. Among them, the first register stores the average output of the time-to-digital converter within the target time when the output of the phase interpolator is 0 and the output of the modulator is -3; the second register stores the average output of the time-to-digital converter within the target time when the output of the phase interpolator is 1 and the output of the modulator is -2; the third register stores the average output of the time-to-digital converter within the target time when the output of the phase interpolator is 2 and the output of the modulator is -1; and so on. The 2,048th register stores the average output of the time-to-digital converter within the target time when the output of the phase interpolator is 255 and the output of the modulator is 4.
[0026] In some embodiments, some of the storages respectively store the average output of the time-to-digital converter within the target time when the phase interpolator has different outputs, and the remaining part of the registers respectively store the average output of the time-to-digital converter within the target time when the modulator has different outputs.
[0027] In some embodiments, when the output range of the phase interpolator is 0 to 255, the output range of the modulator is -3 to 4. The compensation module includes 264 registers, a selection output unit, and a residual unit. The output ends of the 264 registers are respectively and correspondingly connected to the input end of the selection output unit. The first input end of the residual unit is connected to the input end of the selection output unit. The second input end of the residual unit is used to be connected to the output end of the time-to-digital converter. Among them, the first register stores the average output of the time-to-digital converter within the target time when the output of the phase interpolator is 0; the second register stores the average output of the time-to-digital converter within the target time when the output of the phase interpolator is 1; the third register stores the average output of the time-to-digital converter within the target time when the output of the phase interpolator is 2; and so on. The 256th register stores the average output of the time-to-digital converter within the target time when the output of the phase interpolator is 255. The 257th register stores the average output of the time-to-digital converter within the target time when the output of the modulator is -3; the 258th register stores the average output of the time-to-digital converter within the target time when the output of the modulator is -2; the 259th register stores the average output of the time-to-digital converter within the target time when the output of the modulator is -1; and so on. The 264th register stores the average output of the time-to-digital converter within the target time when the output of the modulator is 4.
[0028] In some embodiments, the frequency division of the frequency divider is set to an integer multiple of 1 / 256, such as 1 / 256, and the modulator is controlled to stop working. Then, the non-linearity of the phase interpolator is calibrated by the data stored in the first register to the 256th register. Then, the frequency division of the frequency divider is set to the required value, and the modulator starts to work. The non-linearity of the modulator is calibrated by the data stored in the 257th register to the 264th register 100.
[0029] Although the embodiments of the present invention have been described in detail above, it is obvious to those skilled in the art that various modifications and changes can be made to these embodiments. However, it should be understood that such modifications and changes are all within the scope and spirit of the present invention described in the claims. Moreover, the present invention described herein may have other embodiments and can be implemented or realized in various ways.
Claims
1. A compensation module is applied to a fractional-N phase-locked loop circuit, and is characterized in that It includes several registers, a selection output unit, and a residual unit. The selection output unit includes several input terminals. The output terminals of several of the registers are connected to the several input terminals of the selection output unit in a one-to-one correspondence. The first input terminal of the residual unit is connected to the input terminal of the selection output unit. The second input terminal of the residual unit is used to be connected to the output terminal of the time-to-digital converter.
2. The compensation module according to claim 1, wherein The fractional-N phase-locked loop circuit includes a phase interpolator and a time-to-digital converter. The average output of the time-to-digital converter within a target time when the phase interpolator outputs differently is stored in several of the registers respectively.
3. The compensation module according to claim 1, wherein The fractional-N phase-locked loop circuit includes a modulator and a time-to-digital converter. The average output of the time-to-digital converter within a target time when the modulator outputs differently is stored in several of the registers respectively.
4. The compensation module according to claim 1, characterized in that, The fractional-N phase-locked loop circuit includes a phase interpolator, a modulator, and a time-to-digital converter. The average output of the time-to-digital converter within a target time when the modulator and the modulator output differently is stored in several of the registers respectively.
5. The compensation module according to claim 1, characterized in that, The fractional-N phase-locked loop circuit includes a phase interpolator, a frequency divider, a modulator, and a time-to-digital converter. The average output of the time-to-digital converter within a target time when the phase interpolator outputs differently is stored in some of the memories respectively. The average output of the time-to-digital converter within a target time when the modulator outputs differently is stored in the remaining registers respectively.
6. A fractional-N phase-locked loop circuit, characterized in that, It includes a phase interpolator, a modulator, a time-to-digital converter, a digital filter, a numerically controlled oscillator, a frequency divider, an accumulator, a fractional-N digital control module, and a compensation module according to any one of claims 1 to 5. The output terminal of the time-to-digital converter is connected to the second input terminal of the residual unit. The output terminal of the residual unit is connected to the input terminal of the digital filter. The output terminal of the digital filter is connected to the input terminal of the numerically controlled oscillator. The output terminal of the numerically controlled oscillator is connected to the first input terminal of the phase interpolator. The output terminal of the phase interpolator is connected to the first input terminal of the frequency divider. The output terminal of the modulator is connected to the second input terminal of the frequency divider. The output terminal of the frequency divider is connected to the first input terminal of the time-to-digital converter, the input terminal of the fractional-N digital control module, and the first input terminal of the accumulator. The output terminal of the fractional-N digital control module is connected to the second input terminal of the accumulator. The output terminal of the accumulator is connected to the second input terminal of the phase interpolator. The second input terminal of the time-to-digital converter is used to receive a clock signal.