AFC (Automatic Frequency Control) system applied to multi-core PLL (Phase Locked Loop)
By designing an AFC system that includes frequency comparison, lock detection and output control units, the problems of multi-core PLL frequency control and hardware resource waste are solved, and the rapid and accurate frequency control of PLL and the efficient utilization of hardware resources are achieved.
Patent Information
- Application Number
- CN202510274200.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-07
- Publication Date
- 2025-06-27
AI Technical Summary
The existing AFC technology cannot effectively control the frequency of multi-core PLLs, resulting in a degradation of PLL performance. In traditional designs, the AFC module and the lock detection module are separated, resulting in wasting hardware resources.
An AFC automatic frequency control system applied to multi-core PLL is designed, including a frequency comparison unit, a lock detection unit and an output control unit. The target subband is searched through the AFC dichotomy method, and the counter resource is multiplexed with the lock detection module to realize frequency oscillation and lock detection.
It realizes fast and accurate frequency control of multi-core PLLs, meets the PLL wideband output requirements, and reduces hardware resource overhead.
Smart Images
Figure CN120223071A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of network communication technologies, and particularly to an AFC automatic frequency control system applied to a multi-core PLL. Background Art
[0002] In modern communication systems, the phase-locked loop (PLL) serves as a crucial frequency synthesis component and plays a vital role. One of the core components in the PLL is the voltage-controlled oscillator (VCO), whose performance directly affects the output frequency accuracy and stability of the PLL. Generally, the VCO in the PLL is designed with a highly flexible structure, namely, it is composed of multiple variable capacitor arrays (usually referred to as Cbank arrays). These capacitor arrays adjust the oscillation frequency of the VCO by changing the capacitance value, thereby achieving precise control of the output frequency.
[0003] During the PLL startup phase, the system first intelligently selects the Cbank array in the VCO according to the predetermined output frequency requirement. This process involves a complex frequency sub-band search algorithm aimed at quickly finding a sub-band close to the target frequency. Once a suitable frequency sub-band is found, the PLL loop starts to enter the working state, and gradually reduces the frequency error by continuously adjusting the control voltage of the VCO until it finally locks onto the target frequency. This mechanism ensures that the PLL can quickly and stably generate the required output frequency.
[0004] To further expand the output frequency range of the PLL, modern designs often adopt the strategy of using multiple VCO cores. Each VCO core covers a specific frequency range, and by switching different VCO cores, the PLL can meet a wider range of frequency requirements. However, this design also brings new challenges: the automatic frequency control (AFC) module needs to be able to quickly and accurately find the most suitable frequency sub-band when faced with the scenario of multiple VCO cores existing in a single PLL, so as to ensure that the PLL can meet the requirements of wide-frequency output. This requires the AFC algorithm to have a high degree of flexibility and intelligence and be able to adaptively adjust according to the characteristics of different VCO cores.
[0005] In addition, in terms of hardware resource optimization, traditional PLL designs often separate the AFC module and the lock detection module into two independent components. Although these two modules have different functions, they both rely on multi-bit counters to collect frequency information. The separate design not only increases the complexity of the hardware design but also leads to a waste of hardware resources. To improve resource utilization, modern PLL designs have begun to explore the possibility of multiplexing the AFC module and the lock detection module, and effectively reduce the overall hardware overhead by sharing key hardware resources such as counters.
[0006] However, the prior art has certain limitations in the face of these challenges. First, the traditional AFC algorithm is mainly designed for the capacitor array scenario of a single VCO. When applied to multiple VCO cores, it often fails to accurately lock to the most suitable VCO core, resulting in a decline in PLL performance. Second, the traditional AFC module and the lock detection module are designed separately. Although their respective functions are clear, it causes redundancy and waste of hardware resources. These problems limit the performance of PLL in terms of wideband output and hardware resource optimization, and new technical solutions are urgently needed to overcome them. Summary of the Invention
[0007] The present application provides an AFC automatic frequency control system applied to a multi-core PLL to solve the problem that the existing AFC technology cannot perform frequency control on a multi-core PLL.
[0008] The control system includes an AFC module provided in the multi-core PLL, and the multi-core PLL includes a plurality of capacitor arrays;
[0009] The AFC module includes:
[0010] A frequency comparison unit configured to generate an expected sub-band according to all the capacitor arrays in the multi-core PLL; generate a target sub-band or a lock failure result according to the expected sub-band and the lock detection result; the expected sub-band is obtained through a first sub-band search, and the first sub-band search is based on the AFC dichotomy method;
[0011] A lock detection unit configured to generate a lock detection result according to the expected sub-band;
[0012] An output control unit configured to send the target sub-band or the lock failure result to the multi-core PLL;
[0013] The multi-core PLL is configured to perform frequency oscillation according to the target sub-band.
[0014] Preferably, the lock detection unit is further configured to:
[0015] Obtain a preset sub-band distribution interval;
[0016] Judge whether the multi-core PLL is locked according to a first frequency difference, and generate the lock detection result according to the preset sub-band distribution interval and the expected sub-band; the first frequency difference is obtained by the multi-core PLL performing frequency oscillation according to the expected sub-band.
[0017] Preferably, the multi-core PLL further includes a feedback clock, a reference clock, and a frequency counter. The feedback clock is used to represent the frequency value when the multi-core PLL performs frequency oscillation according to the desired sub-band. The reference clock is used to represent the frequency reference value of the feedback clock. The frequency counter is configured to generate a first frequency difference used to represent the numerical difference between the reference clock and the feedback clock.
[0018] The lock detection unit is further configured to:
[0019] Determine whether the first frequency difference is greater than a preset frequency;
[0020] If so, generate a lock detection result indicating that the multi-core PLL fails to lock;
[0021] If not, generate a lock detection result indicating that the multi-core PLL locks successfully.
[0022] Preferably, the preset sub-band distribution interval is constructed based on a high-frequency interval, a low-frequency interval, and / or a vacant frequency interval;
[0023] The lock detection unit is further configured to:
[0024] Generate interval belonging information of the desired sub-band in the high-frequency interval, the low-frequency interval, and / or the vacant frequency interval according to the desired sub-band and the preset sub-band distribution interval;
[0025] Generate the lock detection result according to the interval belonging information and the lock information of the multi-core PLL.
[0026] Preferably, the interval belonging information includes first information, second information, third information, fourth information, fifth information, and sixth information;
[0027] The first information is used to represent that the desired sub-band is located in the interval below the low-frequency interval;
[0028] The second information is used to represent that the desired sub-band is located in the low-frequency interval;
[0029] The third information is used to represent that the desired sub-band is located in the interval above the high-frequency interval;
[0030] The fourth information is used to represent that the desired sub-band is located in the interval between the low-frequency interval and the high-frequency interval;
[0031] The fifth information is used to represent that the desired sub-band is located in the high-frequency interval;
[0032] The sixth piece of information is used to characterize that the desired sub-band is located in the vacant frequency interval, and the vacant frequency interval is a frequency blank interval between the low frequency interval and the high frequency interval.
[0033] Preferably, the frequency comparison unit is further configured to:
[0034] Generate a corresponding sub-band search strategy or a lock failure result according to the lock detection result;
[0035] Perform a second sub-band search according to the sub-band search strategy and the desired sub-band to obtain the target sub-band.
[0036] Preferably, the frequency comparison unit is further configured to:
[0037] When the interval to which the desired sub-band belongs conforms to the first piece of information and the multi-core PLL fails to lock, generate a lock failure result;
[0038] When the interval to which the desired sub-band belongs conforms to the second piece of information and the multi-core PLL locks successfully, set the desired sub-band as the target sub-band;
[0039] When the interval to which the desired sub-band belongs conforms to the third piece of information, the fifth piece of information or the sixth piece of information and the multi-core PLL fails to lock, generate the sub-band search strategy;
[0040] When the interval to which the desired sub-band belongs conforms to the fourth piece of information and the multi-core PLL locks successfully, generate the sub-band search strategy.
[0041] Preferably, the multi-core PLL further includes the VCO selector, and the VCO selector is configured to select a frequency search direction for sub-band search. The frequency search direction includes a sub-band search direction from the low frequency interval to the high frequency interval and a sub-band search direction from the high frequency interval to the low frequency interval;
[0042] The sub-band search strategy includes performing a second sub-band search in a direction opposite to the first sub-band search; the multi-core PLL is further configured to perform frequency oscillation according to the sub-band obtained from the second sub-band search;
[0043] The lock detection unit is further configured to:
[0044] Obtain the lock information when the multi-core PLL performs frequency oscillation according to the sub-band obtained from the second sub-band search;
[0045] The frequency comparison unit is further configured to:
[0046] Generate the target sub-band or the lock failure result according to the lock information and the sub-band obtained from the second sub-band search.
[0047] Preferably, the control system further includes a result storage unit configured to store the minimum difference value calculated by the frequency counter.
[0048] The output control unit is further configured to send the target sub-band corresponding to the first frequency difference with the value closest to the minimum difference value to the multi-core PLL.
[0049] Preferably, the frequency comparison unit and the lock detection unit share the same frequency counter.
[0050] As can be seen from the above, the present application provides an AFC automatic frequency control system applied to a multi-core PLL. The control system includes an AFC module provided in the multi-core PLL, and the multi-core PLL includes a plurality of capacitor arrays; the AFC module includes a frequency comparison unit configured to generate an expected sub-band according to all the capacitor arrays in the multi-core PLL; generate a target sub-band or a lock failure result according to the expected sub-band and the lock detection result; the expected sub-band is obtained through a first sub-band search, and the first sub-band search is based on the AFC dichotomy method; a lock detection unit configured to generate a lock detection result according to the expected sub-band; an output control unit configured to send the target sub-band or the lock failure result to the multi-core PLL; the multi-core PLL is configured to perform frequency oscillation according to the target sub-band. The present application solves the problem that the existing AFC technology cannot perform frequency control on the multi-core PLL through the above control system. BRIEF DESCRIPTION OF THE DRAWINGS
[0051] In order to more clearly illustrate the technical solutions of the present application, the drawings required for the embodiments will be briefly introduced below. Obviously, for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.
[0052] Figure 1 It is a schematic diagram of an AFC automatic frequency control system applied to a multi-core PLL of the present application;
[0053] Figure 2 It is a schematic diagram of the relationship between the VCO sub-band and the capacitor array;
[0054] Figure 3 It is a circuit diagram of the AFC technology in the PLL;
[0055] Figure 4 It is a schematic diagram of the AFC dichotomy method;
[0056] Figure 5It is the logic flowchart of AFC;
[0057] Figure 6 It is the schematic diagram of the interval belonging information in an AFC automatic frequency control system applied to a multi-core PLL in this application. Specific implementation manners
[0058] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of the present invention.
[0059] It should be noted that the brief description of the terms in this application is only for the convenience of understanding the subsequent described implementation manners, rather than intending to limit the implementation manners of this application. Unless otherwise specified, these terms should be understood in their ordinary and common meanings.
[0060] It should be noted that in this application, words such as "exemplary" or "for example" are used to represent examples, illustrations or explanations. Any embodiment or design solution described as "exemplary" or "for example" in this application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Exactly speaking, using words such as "exemplary" or "for example" aims to present relevant concepts in a specific manner.
[0061] Usually, the oscillator in the PLL is composed of multiple variable capacitor arrays. When the PLL starts up, the Cbank array in the VCO will be selected first according to the required output frequency. After finding a suitable frequency sub-band, the PLL loop starts to work and finally locks. In order to increase the output frequency range, the PLL adopts multiple VCO cores. Therefore, the AFC needs to be able to quickly and accurately find the sub-band in the scenario where there are multiple VCOs in a PLL to meet the output requirements of the PLL with wide frequency. At the same time, it multiplexes the counting module with the lock detection to reduce the hardware resource overhead.
[0062] AFC (Automatic Frequency Control technology) is applied in the process of PLL initialization. First, the discrete coarse tuning method of the VCO in the PLL is to control the access of the capacitor through the switch in the Cbnak. Usually, the VCO is designed as a multi-bit switch array. To make the VCO oscillate at a suitable operating frequency, it is necessary to select the capacitor array of the VCO during the PLL initialization. This process is also called sub-band search. The schematic diagram of the relationship between the sub-band of the VCO and the capacitor array is as Figure 2 shown: In order to quickly find the sub-band, an initialization algorithm usually needs to be used for search. The algorithm commonly used in the industry is the binary search method to find the sub-band.
[0063] Before the AFC starts to work, the PLL loop is disconnected, the fine tuning of the VCO frequency is turned off, and only the AFC controls the Cbank for coarse tuning. The output of the VCO is divided by a frequency divider to obtain the feedback clock. The AFC compares the reference clock and the feedback clock, and then gives the control word for the Cbank (i.e., determines the sub-band). After the AFC sub-band search is completed, the fine tuning of the VCO frequency is turned on, the coarse tuning branch is disconnected, and the overall loop starts to work, and the PLL starts to lock normally. This AFC technology acts on the coarse tuning stage of the PLL. The above process is as Figure 3 shown.
[0064] AFC mainly consists of several modules: a lock detector, a frequency comparator, and an output controller... For a single-core VCO, the sub-band search method can be implemented using a simple binary search method. The specific search process is as follows:
[0065] Step 1: The output controller selects the sub-band in the middle. The feedback clock after the VCO is divided by a frequency divider and the reference clock are input into the frequency comparator together. The frequency comparator is actually composed of two multi-bit counters. Each time a clock edge arrives, the value of the counter decreases by 1 until the value of one of the counters decreases to 0, and the value of the other counter at this time represents the frequency difference.
[0066] Step 2: The frequency comparator gives the result to the output controller. The output controller makes a judgment. If the frequency of the feedback clock is greater than the reference clock, it will increase the control word of the sub-band (select a higher-frequency sub-band), otherwise it will decrease the control word of the sub-band. The output controller will select the sub-band in the middle position of the remaining sub-bands (binary search method), and the specific performance is Figure 4 .
[0067] Step 3: The frequency comparator is reset and starts counting again. Then this process is looped until all the sub-bands of all Bit positions.
[0068] Step 4: The frequency detector starts to work. When the PLL is locked, it outputs a high level; if the PLL is unlocked, it outputs a low level.
[0069] Through the above operations, the AFC process of the PLL is realized. For the specific process, please refer to Figure 5 .
[0070] However, the existing AFC algorithms have the following problems:
[0071] (1) The application scenarios of the general AFC algorithm are applied to the capacitor array of a single VCO; in the application scenarios of multiple VCOs, it cannot lock to a suitable VCO.
[0072] (2) Usually, the AFC module and the lock detection module are separated into two independent modules, but both use a multi-bit counter to collect frequency information. Separating the design of the two modules will cause waste of hardware resources.
[0073] Based on the above problems, the present application provides the following implementation manners.
[0074] Figure 1 It is a schematic diagram of an AFC automatic frequency control system applied to a multi-core PLL of the present application.
[0075] See Figure 1 It can be seen that the present embodiment provides an AFC automatic frequency control system applied to a multi-core PLL. The control system includes an AFC module provided in the multi-core PLL. The multi-core PLL includes several capacitor arrays. Specifically, in the present embodiment, the capacitor arrays in the multi-core PLL can refer to Figure 2 the capacitor arrays in
[0076] The AFC module includes:
[0077] A frequency comparison unit configured to generate an expected sub-band according to all the capacitor arrays in the multi-core PLL; generate a target sub-band or a lock failure result according to the expected sub-band and the lock detection result; the expected sub-band is obtained through a first sub-band search, and the first sub-band search is based on the AFC dichotomy method.
[0078] Specifically, in the present embodiment, the frequency comparison unit is used to perform a sub-band search for the capacitor arrays and thereby obtain a search target sub-band.
[0079] Among them, the frequency comparison unit performs a sub-band search through the AFC dichotomy method, and the AFC dichotomy method can refer to 4.
[0080] The AFC module further includes:
[0081] A lock detection unit configured to generate a lock detection result according to the expected sub-band.
[0082] Specifically, in the present embodiment, the lock detection unit is used to detect the locking condition of the multi-core PLL in real time during the operation of the AFC module and generate the relevant lock detection result.
[0083] Among them, the relationship between the frequency comparison unit and the lock detection unit can be understood as a "circular closed loop", that is, the sub-bands are searched through the frequency comparison unit, the multi-core PLL performs frequency oscillation according to the sub-bands, the lock detection unit obtains the lock information of the multi-core PLL, and transmits the lock information to the frequency comparison unit, and the frequency comparison unit decides whether to perform further sub-band search according to the lock information.
[0084] The AFC module further includes:
[0085] An output control unit configured to send the target sub-band or the lock failure result to the multi-core PLL.
[0086] Specifically, in this embodiment, the output control unit is used to send the target sub-band or the lock failure result calculated by the frequency comparison unit to the multi-core PLL. The output control unit can be understood as the data output end of the AFC module. Through the output control unit, relevant data is conveyed to the multi-core PLL, and the multi-core PLL performs frequency oscillation according to the target sub-band and generates relevant data.
[0087] Further, in some embodiments, the lock detection unit is further configured to:
[0088] Obtain a preset sub-band distribution interval;
[0089] Judge whether the multi-core PLL is locked according to the first frequency difference, and generate the lock detection result according to the preset sub-band distribution interval and the expected sub-band; the first frequency difference is obtained by the multi-core PLL performing frequency oscillation according to the expected sub-band.
[0090] Specifically, in this embodiment, different cases of locking are classified by setting the preset sub-band distribution interval, where the preset sub-band distribution interval is referred to Figure 6 , which can be understood as classifying the distribution of sub-bands in high frequency and low frequency, and performing different processing on the locking cases corresponding to sub-bands in different intervals. The processing method is to generate the corresponding lock detection result through the lock detection unit, and the frequency comparison unit decides whether to perform further sub-band search or directly disconnect the AFC module according to different lock detection results.
[0091] Further, in some embodiments, the multi-core PLL further includes a feedback clock, a reference clock, and a frequency counter. The feedback clock is used to represent the frequency value when the multi-core PLL performs frequency oscillation according to the expected sub-band, and the reference clock is used to represent the frequency reference value of the feedback clock; the frequency counter is configured to generate a first frequency difference used to represent the numerical difference between the reference clock and the feedback clock.
[0092] The lock detection unit is further configured to:
[0093] Determine whether the first frequency difference is greater than a preset frequency;
[0094] If so, generate a lock detection result indicating that the multi-core PLL fails to lock;
[0095] If not, generate a lock detection result indicating that the multi-core PLL locks successfully.
[0096] Specifically, in this embodiment, the lock detection unit obtains the values of the feedback clock and the reference clock in the multi-core PLL, and uses the frequency counter to perform a difference operation on these values to obtain the first frequency difference. By determining the value of the first frequency difference, the locking situation of the multi-core PLL can be obtained.
[0097] It should be noted that the preset frequency needs to be determined according to the actual situation. Therefore, the determination condition for the multi-core PLL to lock changes according to the actual situation.
[0098] Further, in some embodiments, the preset sub-band distribution interval is constructed based on a high-frequency interval, a low-frequency interval, and / or a vacant frequency interval;
[0099] The lock detection unit is further configured to:
[0100] Generate interval belonging information of the expected sub-band in the high-frequency interval, the low-frequency interval, and / or the vacant frequency interval according to the expected sub-band and the preset sub-band distribution interval;
[0101] Generate the lock detection result according to the interval belonging information and the lock information of the multi-core PLL.
[0102] Specifically, in this embodiment, the lock detection unit generates the lock detection result through the expected sub-band and the belonging information of the expected sub-band in the preset sub-band distribution interval, so as to accurately reflect the locking situation of the multi-core PLL when performing frequency oscillation according to different sub-bands.
[0103] Among them, the interval belonging information includes first information, second information, third information, fourth information, fifth information, and sixth information;
[0104] The first information is used to represent that the desired sub-band is located in the lower interval of the low-frequency interval;
[0105] The second information is used to represent that the desired sub-band is located in the low-frequency interval;
[0106] The third information is used to represent that the desired sub-band is located in the upper interval of the high-frequency interval;
[0107] The fourth information is used to represent that the desired sub-band is located in the interval between the low-frequency interval and the high-frequency interval;
[0108] The fifth information is used to represent that the desired sub-band is located in the high-frequency interval;
[0109] The sixth information is used to represent that the desired sub-band is located in the vacant frequency interval, and the vacant frequency interval is the frequency blank interval between the low-frequency interval and the high-frequency interval.
[0110] Among them, the first information, second information, third information, fourth information, fifth information, and sixth information can be referred to Figure 6 , where Figure 6 In the first row of the attached drawings in [], from left to right are the first information, the second information, and the third information respectively, Figure 6 In the second row of the attached drawings in [], from left to right are the fourth information, the fifth information, and the sixth information respectively.
[0111] Further, in some embodiments, the frequency comparison unit is further configured to:
[0112] Generate a corresponding sub-band search strategy or a lock failure result according to the lock detection result;
[0113] Perform a second sub-band search according to the sub-band search strategy and the desired sub-band to obtain the target sub-band.
[0114] Specifically, in this embodiment, since different sub-bands have different effects on the locking situation, it is necessary to perform different sub-band search strategies or output lock failure results for the locking situations corresponding to different sub-bands.
[0115] Further, in some embodiments, the frequency comparison unit is further configured to:
[0116] When the interval belonging of the desired sub-band conforms to the first information and the multi-core PLL lock fails, generate a lock failure result;
[0117] When the interval to which the desired sub-band belongs conforms to the second information and the multi-core PLL is successfully locked, set the desired sub-band as the target sub-band;
[0118] When the interval to which the desired sub-band belongs conforms to the third information, the fifth information or the sixth information and the multi-core PLL fails to lock, generate the sub-band search strategy;
[0119] When the interval to which the desired sub-band belongs conforms to the fourth information and the multi-core PLL is successfully locked, generate the sub-band search strategy.
[0120] Specifically, in this embodiment, the frequency comparison unit determines whether the multi-core PLL can perform further sub-band search or directly determines that it cannot be locked based on the locking status of the multi-core PLL and the interval to which the corresponding desired sub-band belongs.
[0121] Among them, mainly for the search of the desired sub-band conforming to the third information or the fourth information to perform further sub-band search.
[0122] Further, in some embodiments, the multi-core PLL further includes the VCO selector, and the VCO selector is configured to select the frequency search direction for sub-band search, and the frequency search direction includes the sub-band search direction from the low-frequency interval to the high-frequency interval and the sub-band search direction from the high-frequency interval to the low-frequency interval;
[0123] The sub-band search strategy includes performing a second sub-band search in the opposite direction to the first sub-band search; the multi-core PLL is further configured to perform frequency oscillation according to the sub-band obtained by the second sub-band search;
[0124] The locking detection unit is further configured to:
[0125] Obtain the locking information of the multi-core PLL when performing frequency oscillation according to the sub-band obtained by the second sub-band search;
[0126] The frequency comparison unit is further configured to:
[0127] Generate the target sub-band or the locking failure result according to the locking information and the sub-band obtained by the second sub-band search.
[0128] Specifically, in this embodiment, by using the VCO selector to select the search direction for starting sub-band search, it can be understood that the initial search direction is set as the sub-band search direction from the low-frequency interval to the high-frequency interval, then the search direction of the sub-band search performed according to the sub-band search strategy is the sub-band search direction from the high-frequency interval to the low-frequency interval.
[0129] A more accurate target sub - band can be retrieved through bidirectional sub - band retrieval, which can reduce the occurrence of problems caused by unstable locking due to the sub - band being at the edge of the interval.
[0130] Exemplarily, the AFC logic in this embodiment is as follows:
[0131] Step 1: The AFC technology of the multi - core PLL adds a VCO selector. First, before starting the binary search for the sub - band, the selector first selects the low - frequency sub - band.
[0132] Step 2: Perform the AFC binary - search algorithm to search for the sub - band. At this time, judge according to the result of the searched sub - band and the detection result of the lock detector, and it is divided into Figure 6 6 cases for discussion.
[0133] (1) Corresponding to Figure 6 the first piece of information in, if the result of the 5 - Bit capacitor array is 5b’11111, and at the same time the result obtained by the lock detector is that the clock frequency fed back by the VCO is higher than the reference clock frequency and cannot be locked, it means that even if the VCO selects the L - VCO and uses the lowest sub - band, it cannot be lower than the reference frequency, indicating that the required frequency falls outside the range of all sub - bands. At this time, there is no Cbank control word that can meet the working conditions. Then the lock detector detects a loss of lock, and the PLL no longer performs the VCO switching operation.
[0134] (2) Corresponding to Figure 6 the second piece of information in, if the result of the 5 - Bit capacitor array is between 5b’11110 and 5b’00001, and at the same time it can be locked, it means that the current sub - band can meet the locking conditions. The lock detector detects a lock, and the PLL no longer performs the VCO switching operation.
[0135] (3) Corresponding to Figure 6 the third, fifth, and sixth pieces of information in, if the result of the 5 - Bit capacitor array is 5b’00000, and at the same time the lock detector detects a loss of lock, it means that under the current reference - frequency condition, the PLL needs a higher VCO frequency. Therefore, the AFC controls the PLL to perform the VCO switching operation.
[0136] (4) Corresponding to Figure 6 the fourth piece of information in, if the result of the 5 - Bit capacitor array is 5b’00000, and at the same time the lock detector detects a lock, it means that even though the sub - band of the current VCO can be locked, it is the outermost sub - band, and there is still a risk of losing lock in the face of environmental changes such as PVT. Therefore, the AFC still controls the PLL to perform the VCO switching operation. Usually, there is an overlapping part between two VCO sub - bands. If in the higher - frequency VCO core, it may not lock into the more - outermost sub - band.
[0137] Step 3: According to the classification logic in step 2, in case (3) or (4), the VCO selector selects a higher frequency VCO for hopping. The hopping operation is performed after the AFC process in step 2 is completed and the lock detector has a detection result. At this time, the entire PLL re-performs the AFC process in step 2 to search for the sub-band. According to the search results, the following cases are discussed:
[0138] (1) If the 5-bit capacitor array result is 5b'00000, the lock detector is unlocked, indicating that the desired frequency is higher than all sub-bands of the high-frequency VCO. In any case, the PLL cannot be locked at this time, so the AFC process is stopped.
[0139] (2) If the 5-bit capacitor array result is between 5b'11110 and 5b'00001, the lock detector is locked. The sub-band is found and the AFC process is stopped.
[0140] (3) If the 5-bit capacitor array result is 5b'11111, the lock detector is locked. The sub-band is found and the AFC process stops.
[0141] (4) If the result of the 5-bit capacitor array is 5b'11111, the lock detector is unlocked. This means that the high-frequency VCO does not meet the conditional sub-band. If the AFC result of the low-frequency VCO does not achieve lock, that is, the situation (3) in step 2, the high-frequency VCO and the low-frequency VCO do not achieve overlap, and the expected frequency falls in between. At this time, the PLL cannot be locked anyway, so the AFC process is stopped. If the AFC result of the low-frequency VCO is locked, that is, (4) in step 2, the low-frequency VCOAFC process is re-executed to achieve lock.
[0142] The bit number 5b'11111 can be understood as that all five capacitors in the capacitor array are turned on, and if it is 5b'00000, it can be understood as that all five capacitors in the capacitor array are turned off.
[0143] The above classification includes all possible sub-band situations of the multi-core VCO, and according to the above steps, the AFC process of the multi-core VCO is implemented in the fastest way.
[0144] Further, in some embodiments, the control system further comprises a result storage unit, wherein the result storage unit is configured to store the minimum difference value calculated by the frequency counter;
[0145] The output control unit is further configured to send the target sub-band corresponding to the first frequency difference value whose value is closest to the minimum difference value to the multi-core PLL.
[0146] Specifically, in this embodiment, during each bisection search for sub-bands, if the decision is solely based on the output of the frequency comparison unit, it may lead to a non-optimal result in the final decision. Suppose the expected frequency is ultimately closer to the sub-band of 5b'00100. When the bisection method determines that the middle bit is 1, since the expected frequency is higher, the bisection method will obtain 5b'00010. Due to the lower expected frequency, the next step will result in 5b'00011. In fact, the expected frequency is closer to 5b'00100, but according to the above locking logic, it will ultimately be locked to 5b'00011.
[0147] Therefore, a result register unit is added after each Bit frequency comparison unit to store the frequency difference and the current control word. The result register unit stores the value with the smallest frequency difference and the corresponding control word. After the control word of the last Bit is determined, it is compared with the previous results, and the final output control unit will output the result with the smallest frequency difference. In the above example, 5b'00100 will be closer to the expected frequency than 5b'00011, and finally 5b'00100 will be output.
[0148] Furthermore, in some embodiments, the frequency comparison unit and the locking detection unit share the same frequency counter.
[0149] Specifically, in this embodiment, the locking detection unit and the AFC bisection logic are used. Both of them require the frequency counter to count for frequency comparison. However, since the frequency counters of the locking detection unit and the frequency comparison unit work in different stages, they can share the same counter without conflict.
[0150] This embodiment has the following advantages:
[0151] It realizes the ability to quickly and accurately find the sub-band even in the scenario where there are multiple VCOs in a PLL, meets the output requirements of the PLL wideband, and at the same time reduces the hardware resource overhead.
[0152] For the sake of convenience in explanation, the above description has been made in conjunction with specific embodiments. However, the above discussion in some embodiments is not intended to be exhaustive or to limit the embodiments to the specific forms disclosed above. According to the above teachings, various modifications and variations can be obtained. The selection and description of the above embodiments are for better explaining the content of the present disclosure, so that those skilled in the art can better use the embodiments.
Claims
1. An AFC automatic frequency control system applied to a multi-core PLL, characterized in that: The control system includes an AFC module arranged in a multi-core PLL, wherein the multi-core PLL includes a plurality of capacitor arrays; The AFC module includes: A frequency comparison unit, the frequency comparison unit is configured to generate an expected sub-band according to all the capacitor arrays in the multi-core PLL; generate a target sub-band or a lock failure result according to the expected sub-band and a lock detection result; the expected sub-band is obtained through a first sub-band search, and the first sub-band search is performed based on an AFC dichotomy method; a lock detection unit, the lock detection unit being configured to generate a lock detection result according to the desired sub-band; an output control unit, the output control unit being configured to send the target subband or the locking failure result to the multi-core PLL; The multi-core PLL is configured to perform frequency oscillation according to the target sub-band.
2. The AFC automatic frequency control system applied to a multi-core PLL according to claim 1, characterized in that: The lock detection unit is further configured to: Obtaining a preset sub-band distribution interval; Whether the multi-core PLL is locked is determined according to a first frequency difference, and the lock detection result is generated according to the preset sub-band distribution interval and the expected sub-band; the first frequency difference is obtained by the multi-core PLL performing frequency oscillation according to the expected sub-band.
3. The AFC automatic frequency control system applied to a multi-core PLL according to claim 2, characterized in that: The multi-core PLL further includes a feedback clock, a reference clock and a frequency counter, wherein the feedback clock is used to represent the frequency value of the multi-core PLL when the multi-core PLL performs frequency oscillation according to the expected sub-band, and the reference clock is used to represent the frequency reference value of the feedback clock; the frequency counter is configured to generate a first frequency difference value for representing the difference between the reference clock and the feedback clock; The lock detection unit is further configured to: Determining whether the first frequency difference is greater than a preset frequency; If yes, generating a lock detection result indicating that the multi-core PLL has failed to lock; If not, a lock detection result is generated indicating that the multi-core PLL is locked successfully.
4. The AFC automatic frequency control system applied to a multi-core PLL according to claim 2, characterized in that: The preset sub-band distribution interval is constructed based on a high frequency interval, a low frequency interval and / or an empty frequency interval; The lock detection unit is further configured to: Generate interval belonging information of the expected subband in the high frequency interval, the low frequency interval and / or the vacant frequency interval according to the expected subband and the preset subband distribution interval; The lock detection result is generated according to the interval belonging information and the lock information of the multi-core PLL.
5. The AFC automatic frequency control system applied to a multi-core PLL according to claim 4, characterized in that: The interval belonging information includes first information, second information, third information, fourth information, fifth information and sixth information; The first information is used to indicate that the desired subband is located in a lower interval of the low frequency interval; The second information is used to indicate that the desired subband is located in the low frequency interval; The third information is used to indicate that the desired subband is located in an upper interval of the high frequency interval; The fourth information is used to indicate that the desired subband is located between the low frequency interval and the high frequency interval; The fifth information is used to indicate that the desired subband is located in the high frequency interval; The sixth information is used to indicate that the desired subband is located in the vacant frequency interval, and the vacant frequency interval is a frequency blank interval between the low frequency interval and the high frequency interval.
6. The AFC automatic frequency control system applied to a multi-core PLL according to claim 5, characterized in that: The frequency comparison unit is further configured to: Generate a corresponding sub-band search strategy or a locking failure result according to the locking detection result; A second subband search is performed according to the subband search strategy and the desired subband to obtain the target subband.
7. The AFC automatic frequency control system applied to a multi-core PLL according to claim 6, characterized in that: The frequency comparison unit is further configured to: When the interval of the expected sub-band matches the first information and the multi-core PLL fails to lock, generating a locking failure result; When the interval of the desired sub-band is consistent with the second information and the multi-core PLL is locked successfully, setting the desired sub-band as the target sub-band; When the interval of the desired sub-band matches the third information, the fifth information or the sixth information, and the multi-core PLL fails to lock, generating the sub-band search strategy; When the interval of the desired sub-band matches the fourth information and the multi-core PLL is locked successfully, the sub-band search strategy is generated.
8. The AFC automatic frequency control system applied to a multi-core PLL according to claim 7, characterized in that: The multi-core PLL further comprises the VCO selector, wherein the VCO selector is configured to select a frequency search direction of a sub-band search, wherein the frequency search direction comprises a sub-band search direction from a low frequency interval to a high frequency interval and a sub-band search direction from a high frequency interval to a low frequency interval; The sub-band search strategy includes performing a second sub-band search in the opposite direction to the first sub-band search; the multi-core PLL is further configured to perform frequency oscillation according to the sub-band obtained by the second sub-band search; The lock detection unit is further configured to: Acquire locking information of the multi-core PLL when frequency oscillates according to the sub-band obtained by searching the second sub-band; The frequency comparison unit is further configured to: The target subband or the locking failure result is generated according to the locking information and the subband obtained by the second subband search.
9. The AFC automatic frequency control system applied to a multi-core PLL according to claim 8, characterized in that: The control system further comprises a result storage unit, wherein the result storage unit is configured to store the minimum difference value calculated by the frequency counter; The output control unit is further configured to send the target sub-band corresponding to the first frequency difference value whose value is closest to the minimum difference value to the multi-core PLL.
10. The AFC automatic frequency control system applied to multi-core PLL according to claim 9, characterized in that: The frequency comparison unit and the lock detection unit share the same frequency counter.