ADC circuit and control method thereof

Abstract

The invention provides an ADC circuit and a control method thereof. The ADC circuit comprises a multi-stage SAR analog-to-digital converter and a multi-stage residual error processing circuit. Each stage of residual error processing circuit is located between two adjacent stages of SAR analog-to-digital converters and comprises a residual error sampling circuit and a residual error amplifying circuit, the residual error sampling circuit and the residual error amplifying circuit are both single-channel circuits, the residual error sampling circuit is realized by adopting a passive charge sharing mode, and the residual error amplifying circuit is realized by adopting an active operational amplifier. In each sampling conversion period of the ADC circuit, the residual error sampling circuit and the residual error amplification circuit carry out residual error sampling and residual error amplification on residual error signals output by the previous-stage SAR analog-to-digital converter, and when the residual error amplification circuit amplifies the residual error signals output by the previous-stage SAR analog-to-digital converter and the next-stage SAR analog-to-digital converter carries out sampling, the residual error signals output by the next-stage SAR analog-to-digital converter are amplified by the residual error amplification circuit. And the previous stage of SAR analog-to-digital converter is used for carrying out next sampling. According to the invention, the ADC conversion rate can be improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular, to an ADC circuit and its control method. Background Art

[0002] A SAR ADC (Successive Approximation Register Analog to Digital Converter) is a circuit that converts an analog signal into a digital signal. It obtains N bits of data corresponding to the analog signal based on a binary search algorithm. Generally, for an N-bit SAR ADC, at least N comparisons are required to obtain a complete digital output. Therefore, the conversion speed of the SAR ADC is limited by its successive approximation algorithm and is not suitable for high-speed applications. However, the SAR ADC has the advantages of low power consumption, simple algorithm, and small size. In order to achieve a higher speed, one implementation solution is to combine the structural characteristics of the SAR ADC with those of the Pipeline ADC to form a Pipeline SAR ADC (pipelined successive approximation register analog-to-digital converter), which can achieve high speed and high precision while maintaining the advantages of low power consumption, simple algorithm, and small size. Since the Pipeline SAR ADC replaces the flash-type sub-ADC in the Pipeline ADC with a SAR ADC, and the SAR ADC used can have a higher number of bits, the number of cascaded stages is much less than that of the Pipeline ADC, usually two to four stages.

[0003] However, since the Pipeline SAR ADC requires an inter-stage operational amplifier, in the existing Pipeline SAR ADC, the first-stage SAR ADC must wait for the residue amplification and the sampling stage of the second-stage SAR ADC to be completed before it can sample the next input signal. Therefore, the conversion rate of the Pipeline SAR ADC is limited and its conversion rate is slow. Summary of the Invention

[0004] The purpose of this application is to provide an ADC circuit and its control method that can solve at least one of the technical problems mentioned in the above prior art.

[0005] One aspect of the present application provides an ADC circuit. The ADC circuit includes a multi-stage SAR analog-to-digital converter and a multi-stage residue processing circuit. Among them, each stage of the residue processing circuit is located between two adjacent stages of the SAR analog-to-digital converter; each stage of the residue processing circuit includes a residue sampling circuit and a residue amplification circuit connected to the output end of the residue sampling circuit. Both the residue sampling circuit and the residue amplification circuit are single-channel circuits. The residue sampling circuit is implemented by a passive charge sharing method, and the residue amplification circuit is implemented by an active operational amplifier. In each sampling conversion cycle of the ADC circuit, the residue sampling circuit and the residue amplification circuit perform residue sampling and residue amplification on the residue signal output by the previous stage of the SAR analog-to-digital converter. During the period when the residue amplification circuit amplifies the residue signal output by the previous stage of the SAR analog-to-digital converter and the next stage of the SAR analog-to-digital converter performs sampling, the previous stage of the SAR analog-to-digital converter is used to perform the next sampling.

[0006] Further, the residue sampling circuit includes a first sampling capacitor and a second sampling capacitor. The residue signal includes a positive residue signal and a negative residue signal. Among them, in the residue sampling stage, the first plate and the second plate of the first sampling capacitor are respectively connected to the positive residue signal and the negative residue signal; the first plate and the second plate of the second sampling capacitor are also respectively connected to the positive residue signal and the negative residue signal.

[0007] Further, the residue sampling circuit includes a first positive terminal switch, a second positive terminal switch, a first negative terminal switch, and a second negative terminal switch. Among them, the first plate of the first sampling capacitor is connected to the positive residue signal through the first positive terminal switch; the second plate of the first sampling capacitor is connected to the negative residue signal through the second positive terminal switch; the first plate of the second sampling capacitor is connected to the positive residue signal through the first negative terminal switch; the second plate of the second sampling capacitor is connected to the negative residue signal through the second negative terminal switch.

[0008] Further, when entering the residue sampling stage, the first positive terminal switch, the second positive terminal switch, the first negative terminal switch, and the second negative terminal switch are switched from the open state to the closed state; after the charge sharing process is completed, the first positive terminal switch, the second positive terminal switch, the first negative terminal switch, and the second negative terminal switch are switched from the closed state to the open state.

[0009] Further, the residual error sampling circuit further includes a third positive terminal switch, a fourth positive terminal switch, a fifth positive terminal switch, a third negative terminal switch, a fourth negative terminal switch, and a fifth negative terminal switch. Among them, the first terminal of the third positive terminal switch is connected to a reference voltage, and the second terminal of the third positive terminal switch is connected to the second electrode plate of the first sampling capacitor and is connected to the first electrode plate of the first sampling capacitor through the fifth positive terminal switch; both ends of the fourth positive terminal switch are respectively connected to the first electrode plate of the first sampling capacitor and the positive output terminal of the residual error sampling circuit; the first terminal of the third negative terminal switch is connected to the reference voltage, and the second terminal of the third negative terminal switch is connected to the first electrode plate of the second sampling capacitor and is connected to the second electrode plate of the second sampling capacitor through the fifth negative terminal switch; both ends of the fourth negative terminal switch are respectively connected to the second electrode plate of the second sampling capacitor and the negative output terminal of the residual error sampling circuit.

[0010] Further, when entering the residual error sampling stage, the fifth positive terminal switch and the fifth negative terminal switch are switched from the closed state to the open state.

[0011] Further, the residual error amplification circuit includes an operational amplifier, a first feedback capacitor, a second feedback capacitor, a sixth positive terminal switch, and a sixth negative terminal switch. Among them, the operational amplifier has a positive input terminal, a negative input terminal, a positive amplification output terminal, and a negative amplification output terminal. The positive input terminal of the operational amplifier is connected to the positive output terminal of the residual error sampling circuit, and the negative input terminal of the operational amplifier is connected to the negative output terminal of the residual error sampling circuit; the first feedback capacitor and the sixth positive terminal switch are both connected in parallel between the positive input terminal and the negative amplification output terminal of the operational amplifier; the second feedback capacitor and the sixth negative terminal switch are both connected in parallel between the negative input terminal and the positive amplification output terminal of the operational amplifier.

[0012] Further, when entering the residual error amplification stage, the third positive terminal switch, the fourth positive terminal switch, the third negative terminal switch, and the fourth negative terminal switch are switched from the open state to the closed state, and the sixth positive terminal switch and the sixth negative terminal switch are switched from the closed state to the open state.

[0013] Further, when the next-stage SAR analog-to-digital converter completes sampling of the residual error amplified signal, the third positive terminal switch, the fourth positive terminal switch, the third negative terminal switch, and the fourth negative terminal switch are turned off, and moreover, the fifth positive terminal switch, the fifth negative terminal switch, the sixth positive terminal switch, and the sixth negative terminal switch are switched from the open state to the closed state.

[0014] Further, each stage of the SAR analog-to-digital converter includes a positive terminal switch array, a negative terminal switch array, a positive terminal capacitor array, a negative terminal capacitor array, a positive terminal upper plate switch, a negative terminal upper plate switch, a comparator, and an SAR control module. Among them, the first plate of the positive terminal capacitor array is connected to the positive input terminal of the comparator and accesses the reference voltage through the positive terminal upper plate switch; the second plate of the positive terminal capacitor array selectively accesses the positive differential input signal, the reference voltage, the positive reference voltage, and the negative reference voltage through the positive terminal switch array; the first plate of the negative terminal capacitor array is connected to the negative input terminal of the comparator and accesses the reference voltage through the negative terminal upper plate switch; the second plate of the negative terminal capacitor array selectively accesses the negative differential input signal, the reference voltage, the positive reference voltage, and the negative reference voltage through the negative terminal switch array; the output terminal of the comparator is connected to the SAR control module; the SAR control module is used to control the positive terminal switch array and the negative terminal switch array, and output a conversion end signal and the digital code of the corresponding stage.

[0015] Further, when a certain stage of the SAR analog-to-digital converter enters the sampling stage, the positive terminal upper plate switch and the negative terminal upper plate switch in this stage of the SAR analog-to-digital converter are closed. At the same time, the second plate of the positive terminal capacitor array in this stage of the SAR analog-to-digital converter accesses the positive input signal through the positive terminal switch array in this stage of the SAR analog-to-digital converter, and the second plate of the negative terminal capacitor array in this stage of the SAR analog-to-digital converter accesses the negative input signal through the negative terminal switch array in this stage of the SAR analog-to-digital converter. Among them, for the first stage of the SAR analog-to-digital converter, the positive input signal includes the positive differential input signal, and the negative input signal includes the negative differential input signal; for the other stages of the SAR analog-to-digital converter except the first stage, the positive input signal includes the positive residual difference amplification signal output by the previous stage of the residual difference amplification circuit, and the negative input signal includes the negative residual difference amplification signal output by the previous stage of the residual difference amplification circuit; after a predetermined sampling stabilization time, the positive terminal upper plate switch and the negative terminal upper plate switch in this stage of the SAR analog-to-digital converter are switched from the closed state to the open state, and the second plate of the positive terminal capacitor array in this stage of the SAR analog-to-digital converter accesses the reference voltage through the positive terminal switch array in this stage of the SAR analog-to-digital converter, and the second plate of the negative terminal capacitor array in this stage of the SAR analog-to-digital converter accesses the reference voltage through the negative terminal switch array in this stage of the SAR analog-to-digital converter.

[0016] Further, the ADC circuit further includes a redundant calibration and data processing circuit. The output terminal of each stage of the SAR analog-to-digital converter is connected to the redundant calibration and data processing circuit, and the redundant calibration and data processing circuit is used to finally output the digital code of the ADC circuit.

[0017] Another aspect of the present application provides a control method for an ADC circuit. The ADC circuit includes multiple stages of SAR analog-to-digital converters and multiple stages of residue processing circuits. Each stage of the residue processing circuit is located between two adjacent stages of the SAR analog-to-digital converters. Each stage of the residue processing circuit includes a residue sampling circuit and a residue amplification circuit connected to the output terminal of the residue sampling circuit. Both the residue sampling circuit and the residue amplification circuit are single-channel circuits. The method includes: in each sampling conversion cycle of the ADC circuit, controlling the residue sampling circuit and the residue amplification circuit to respectively perform residue sampling and residue amplification on the residue signal output by the previous stage of the SAR analog-to-digital converter; during the period when the residue amplification circuit amplifies the residue signal output by the previous stage of the SAR analog-to-digital converter and the next stage of the SAR analog-to-digital converter performs sampling, controlling the previous stage of the SAR analog-to-digital converter to perform the next sampling.

[0018] Further, the residue sampling circuit includes a first sampling capacitor and a second sampling capacitor. The residue signal includes a positive residue signal and a negative residue signal. The method further includes: in entering the residue sampling stage, controlling to connect the first electrode plate and the second electrode plate of the first sampling capacitor to the positive residue signal and the negative residue signal output by the previous stage of the SAR analog-to-digital converter respectively; and connecting the first electrode plate and the second electrode plate of the second sampling capacitor to the positive residue signal and the negative residue signal output by the previous stage of the SAR analog-to-digital converter respectively.

[0019] Further, the residue amplification circuit includes an operational amplifier, a first feedback capacitor, and a second feedback capacitor. The method further includes: in entering the residue amplification stage, controlling to connect the second electrode plate of the first sampling capacitor and the first electrode plate of the second sampling capacitor to the reference voltage; connecting the first electrode plate of the first sampling capacitor and the second electrode plate of the second sampling capacitor to the positive input terminal and the negative input terminal of the operational amplifier respectively; and controlling to connect the positive input terminal of the operational amplifier to the negative amplified output terminal of the operational amplifier through the first feedback capacitor; connecting the negative input terminal of the operational amplifier to the positive amplified output terminal of the operational amplifier through the second feedback capacitor.

[0020] Further, the method further includes: when the next-stage SAR analog-to-digital converter completes sampling of the residual difference amplified signal output by the residual difference amplification circuit, controlling to short-circuit both ends of the first sampling capacitor, both ends of the second sampling capacitor, both ends of the first feedback capacitor, and both ends of the second feedback capacitor.

[0021] Further, each stage of the SAR analog-to-digital converter includes a positive terminal switch array, a negative terminal switch array, a positive terminal capacitor array, and a negative terminal capacitor array. The method further includes: when a certain stage of the SAR analog-to-digital converter enters the sampling stage, by controlling the positive terminal switch array and the negative terminal switch array in this stage of the SAR analog-to-digital converter, connecting the positive input signal and the negative input signal to the second plates of the positive terminal capacitor array and the negative terminal capacitor array in this stage of the SAR analog-to-digital converter respectively; and controlling the first plates of the positive terminal capacitor array and the negative terminal capacitor array in this stage of the SAR analog-to-digital converter to access the reference voltage. Wherein, for the first stage of the SAR analog-to-digital converter, the positive input signal includes a positive differential input signal, and the negative input signal includes a negative differential input signal; for other stages of the SAR analog-to-digital converter except the first stage, the positive input signal includes the positive residual difference amplified signal output by the previous-stage residual difference amplification circuit, and the negative input signal includes the negative residual difference amplified signal output by the previous-stage residual difference amplification circuit; after a predetermined sampling stabilization time, controlling the first plates of the positive terminal capacitor array and the negative terminal capacitor array in this stage of the SAR analog-to-digital converter to disconnect from the reference voltage; and controlling the positive input signal and the negative input signal to disconnect from the second plates of the positive terminal capacitor array and the negative terminal capacitor array in this stage of the SAR analog-to-digital converter, and connecting the second plates of the positive terminal capacitor array and the negative terminal capacitor array in this stage of the SAR analog-to-digital converter to the reference voltage.

[0022] The ADC circuit and its control method according to one or more embodiments of the present application can, by introducing a residual difference sampling circuit, realize the next sampling of the input signal by the previous-stage SAR ADC while performing residual difference amplification and the sampling stage of the subsequent-stage SAR ADC, make more full use of the advantages of pipelined operation, and greatly improve the conversion rate of the ADC circuit. For the same conversion rate requirement, by adopting the structure of the ADC circuit of the present application, the time of the residual difference amplification and sampling stage can be appropriately increased, thereby reducing the requirements for the switch size and the bandwidth of the operational amplifier in the circuit, thus reducing the design difficulty and cost.

[0023] In addition, in the ADC circuit and its control method according to one or more embodiments of the present application, by introducing a residue sampling circuit, the input common-mode voltage of the operational amplifier is always equal to the reference voltage during residue amplification, and does not depend on the residue signal output by the previous-stage SAR ADC. Therefore, the previous-stage SAR ADC can flexibly adopt other timing architectures. Even if it does not adopt the VCM-Based timing architecture, such as a monotonic timing architecture with a smaller area and lower power consumption, it can still ensure that the common-mode input voltage input to the operational amplifier in the residue amplification circuit is constantly the reference voltage, thereby reducing the design difficulty of the operational amplifier and improving the flexibility of circuit design. Description of the Drawings

[0024] Figure 1 FIG. is a general structural block diagram of a two-stage Pipeline SAR ADC in the related art.

[0025] Figure 2 is Figure 1 a schematic implementation circuit diagram of the two-stage Pipeline SAR ADC shown in FIG.

[0026] Figure 3 is Figure 2 a working timing diagram of the two-stage Pipeline SAR ADC shown in FIG.

[0027] Figure 4 FIG. is a general structural block diagram of a two-stage Pipeline SAR ADC according to an embodiment of the present application.

[0028] Figure 5 is Figure 4 a schematic implementation circuit diagram of the two-stage Pipeline SAR ADC shown in FIG.

[0029] Figure 6 is Figure 5 a working timing diagram of the two-stage Pipeline SAR ADC shown in FIG.

[0030] Figure 7 FIG. is a flowchart of a control method for an ADC circuit according to an embodiment of the present application. Detailed Embodiments

[0031] Here, exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices consistent with some aspects of the present application as detailed in the appended claims.

[0032] Figure 1 Reveals the overall structural block diagram of a two-stage Pipeline SAR ADC 100 in the related art. As Figure 1 shown, the two-stage Pipeline SAR ADC 100 includes a first-stage M-bit (bit) SAR ADC (referred to as the first-stage SAR ADC 111), a residue amplifier circuit 130, a second-stage L-bit (bit) SAR ADC (referred to as the second-stage SAR ADC 112), and a redundant calibration and data processing circuit 140. Among them, the first-stage M-bit SAR ADC samples and quantifies the input signal (VINP - VINN) to generate the M-bit digital code D1 of the first stage <m-1:0>and the residue signal VP1-VN1. The residue amplifier circuit 130 amplifies the residue signal (VP1-VN1) output by the first-stage M-bit SAR ADC to generate an amplified signal, i.e., the residue amplified signal (VOP-VON). The second-stage L-bit SAR ADC samples and quantizes the residue amplified signal (VOP-VON) output by the residue amplifier circuit 130 to generate the second-stage L-bit digital code D2 <l-1:0>Finally, through the redundancy calibration and data processing circuit 140, the final N-bit quantization data Dout is generated. <n-1:0>. Usually, 1-bit redundancy is required in the design, i.e., M + L = N + 1, and the amplification factor of the residual error amplification circuit 130 is designed. . For example, for a 14-bit two-stage Pipeline SAR ADC 100, the first-stage SAR ADC 111 can be designed as 7 bits, and the second-stage SAR ADC 112 can be designed as 8 bits. And the amplification factor of the residual error amplification circuit 130 is .

[0033] Figure 2 Reveals Figure 1 An implementation circuit diagram of the two-stage Pipeline SAR ADC 100 shown, where the first-stage and the second-stage SAR ADC 112 both adopt the VCM-Based timing architecture as an example is shown; Figure 3 Reveals Figure 2 The working timing diagram of the two-stage Pipeline SAR ADC 100 shown. Next, it will be combined with Figure 2 And Figure 3 And taking the fully differential form as an example to illustrate the working principle of the two-stage Pipeline SAR ADC 100 in detail.

[0034] Sampling stage of the first-stage SAR ADC 111 (duration t1): By controlling the first-stage positive terminal (P-terminal) switch array and the first-stage negative terminal (N-terminal) switch array, the positive differential input signal VINP and the negative differential input signal VINN are respectively connected to the second plates of the first-stage positive terminal capacitor array CDAC1_P and the first-stage negative terminal capacitor array CDAC1_N. At the same time, the first plates of the first-stage positive terminal capacitor array CDAC1_P and the first-stage negative terminal capacitor array CDAC1_N are connected to the reference voltage VCM through controlling the first-stage positive terminal upper plate switch SW1P and the first-stage negative terminal upper plate switch SW1N, so as to sample the input signal. After a certain sampling stabilization time, control the first-stage positive terminal upper plate switch SW1P and the first-stage negative terminal upper plate switch SW1N to disconnect, and disconnect the positive differential input signal VINP and the negative differential input signal VINN from the second plates of the first-stage positive terminal capacitor array CDAC1_P and the first-stage negative terminal capacitor array CDAC1_N respectively. At this time, the sampling of the input signal is completed (the information of the input signal V1 is sampled into the first-stage positive terminal capacitor array CDAC1_P and the first-stage negative terminal capacitor array CDAC1_N).

[0035] First-stage SAR ADC 111 conversion phase (duration t2): The conversion end signal EOC_1 output by the first-stage SAR control (SAR CTRL1) module changes from high to low, indicating that the first-stage SAR ADC 111 enters the conversion phase. According to the binary search algorithm, the switching of the first-stage positive terminal switch array and the first-stage negative terminal switch array is controlled by the SAR CTRL1 module, and the signals connected to the second plates of the first-stage positive terminal switch array CDAC1_P and the first-stage negative terminal switch array CDAC1_N are controlled to gradually approximate the quantization of the sampled signal. Finally, the conversion end signal EOC_1 changes from low to high, indicating that the conversion of the first-stage SAR ADC 111 is completed. At this time, a residue signal (VP1 - VN1) is generated, and at the same time, the digital code D1_1 of the first stage is generated and output <m-1:0>。

[0036] Residual error amplification and second-stage SAR ADC 112 sampling phase (duration t3): By controlling the closing of the first positive terminal switch SW11P and the first negative terminal switch SW11N, and the opening of the sixth positive terminal switch SW41P and the sixth negative terminal switch SW41N, the operational amplifier AMP is used to amplify the residual error signal (VP1 - VN1) to generate a residual error amplified signal (VOP - VON). At the same time, by controlling the second-stage positive terminal switch array and the second-stage negative terminal switch array, the positive residual error amplified signal VOP and the negative residual error amplified signal VON are respectively connected to the second plates of the second-stage positive terminal capacitor array CDAC2_P and the second-stage negative terminal capacitor array CDAC2_N. The first plates of the second-stage positive terminal capacitor array CDAC2_P and the second-stage negative terminal capacitor array CDAC2_N are connected to the reference voltage VCM by controlling the second-stage positive terminal upper plate switch SW2P and the second-stage negative terminal upper plate switch SW2N, thereby realizing the sampling of the residual error amplified signal (VOP - VON) by the second-stage SAR ADC 112. After a certain amplification stabilization and sampling stabilization time, control the second-stage positive terminal upper plate switch SW2P, the second-stage negative terminal upper plate switch SW2N, the first positive terminal switch SW11P, and the first negative terminal switch SW11N to open, and disconnect the positive residual error amplified signal VOP and the negative residual error amplified signal VON from the second plates of the second-stage positive terminal capacitor array CDAC2_P and the second-stage negative terminal capacitor array CDAC2_N respectively. At this time, the residual error amplification and the second-stage SAR ADC 112 complete the sampling of the residual error amplified signal.

[0037] Second-stage SAR ADC 112 conversion phase (duration t4): The conversion end signal EOC_2 output by the second-stage SAR control (SAR CTRL2) module changes from high to low, indicating that the second-stage SAR ADC 112 enters the conversion phase. According to the binary search algorithm, the second-stage SAR ADC 112, through the SAR CTRL2 module, controls the switching of the second-stage positive terminal switch array and the second-stage negative terminal switch array to gradually approximate and realize the quantization of the sampled signal. Finally, the conversion end signal EOC_2 changes from low to high, indicating that the second-stage SAR ADC 112 conversion is completed. At this time, the digital code D2_1 of the second stage is generated and output. <l-1:0>。

[0038] N-bit quantized data Dout <n-1:0>Generation stage: The redundancy calibration and data processing circuit 140 processes the digital code D1_1 of the first stage <m-1:0>and the digital code D2_1 of the second level <l-1:0>After performing alignment addition and correcting the fixed offset, the final N-bit quantized data (i.e., N-bit digital code) Dout1 is output <n-1:0>, this N-bit quantized data corresponds to the input signal V1.

[0039] From Figure 3 From the timing diagram, it can also be seen that while the second-stage SAR ADC 112 conversion stage described above is in progress, the first-stage SAR ADC 111 can perform the next sampling of the input signal (sampling the input signal V2), demonstrating the characteristics of pipelined operation. Figure 3 The digital code Dout2 in <n-1:0>It is through the digital code D1_2 of the first level <m-1:0>and the digital code D2_2 of the second level <l-1:0>The N-bit quantization data corresponding to the input signal V2, obtained after alignment addition and correction of the fixed offset.

[0040] Normally, the number of bits of the first-stage SAR ADC 111 and the second-stage SAR ADC 112 will be designed to be approximately equal. For example, for a 14-bit two-stage Pipeline SAR ADC 100, the first-stage SAR ADC 111 can be designed to have 7 bits and the second-stage SAR ADC 112 to have 8 bits. Therefore, Figure 3 the time t2 in [[ ]] is approximately equal to the time t4; at the same time, since the residue amplification needs to amplify small signals through an active operational amplifier AMP, a relatively long time is required to achieve the required accuracy. Therefore, Figure 3 the time t3 in [[ ]] is much larger than the time t1. Based on the above analysis, it can be seen that the maximum conversion rate of this two-stage Pipeline SAR ADC 100 (i.e., Dout <n-1:0>The speed of data update , see Figure 3 In Figure 3 , Tconv is determined by the time t1 + t3 + t4, .

[0041] The two-stage Pipeline SAR ADC 100 of the above related technologies mainly has the following two disadvantages: First, the first-stage SAR ADC 111 must wait for the residue amplification and the sampling stage of the second-stage SAR ADC 112 to be completed before it can sample the next input signal. As Figure 3 shown, when the first-stage SAR ADC 111 samples the input voltage V2, it must wait for the operational amplifier AMP to complete the amplification of the previous residue signal (the residue signal generated after quantifying the input voltage V1). This is because the amplification of the operational amplifier AMP requires the charges stored on the first-stage positive capacitor array CDAC1_P and the first-stage negative capacitor array CDAC1_N (including the residue voltage VP1 - VN1). Only when the amplification is completed and the sampling stage of the second-stage SAR ADC 112 is completed, the first-stage positive capacitor array CDAC1_P and the first-stage negative capacitor array CDAC1_N of the first-stage SAR ADC 111 can be released for sampling the new input signal. This will cause the problem of limited conversion rate in the two-stage Pipeline SAR ADC 100 of the related technologies. The maximum conversion rate , is determined by the time t1 + t3 + t4, where t1 is the sampling stage time of the first-stage SAR ADC 111, t3 is the residue amplification and the sampling stage time of the second-stage SAR ADC 112, and t4 is the conversion stage time of the second-stage SAR ADC 112. When a certain conversion rate needs to be achieved, the above three times must be compressed, resulting in a larger switch size and a higher bandwidth requirement for the operational amplifier AMP in the circuit, thus increasing the design difficulty and cost.

[0042] Second, when performing residual error amplification, by closing the first positive terminal switch SW11P and the first negative terminal switch SW11N, and opening the sixth positive terminal switch SW41P and the sixth negative terminal switch SW41N, the operational amplifier AMP is used to amplify the residual error signal (VP1 - VN1) to generate a residual error amplified signal (VOP - VON). At this time, the positive residual error signal VP1 and the negative residual error signal VN1 are respectively connected to the positive input terminal and the negative input terminal of the operational amplifier AMP. This requires a relatively high common-mode input voltage range for the operational amplifier AMP. When the first-stage SAR ADC 111 does not adopt the VCM - Based timing architecture, for example, when adopting a monotonic timing architecture with a smaller area and lower power consumption, the common-mode voltage of the positive residual error signal VP1 and the negative residual error signal VN1 will change from VCM to 0V, thereby increasing the design difficulty of the operational amplifier AMP.

[0043] In view of this, the present application proposes an improved ADC circuit that can solve at least one of the technical problems mentioned in the above related technologies.

[0044] Next, the ADC circuit and its control method of the present application will be described in detail with reference to the accompanying drawings. Without conflict, the features in the following embodiments and implementation manners can be combined with each other.

[0045] The present application provides an ADC circuit. The ADC circuit includes multiple stages of SAR analog-to-digital converters (SAR ADCs) and multiple stages of residual error processing circuits. Each stage of the residual error processing circuit is located between two adjacent stages of SAR analog-to-digital converters; each stage of the residual error processing circuit includes a residual error sampling circuit 220 and a residual error amplification circuit 230 connected to the output terminal of the residual error sampling circuit 220. Both the residual error sampling circuit 220 and the residual error amplification circuit 230 are single-channel circuits. Among them, the residual error sampling circuit 220 is implemented by a passive charge sharing method, and the residual error amplification circuit 230 is implemented by an active operational amplifier. In each sampling conversion cycle of the ADC circuit, the single-channel residual error sampling circuit 220 and the single-channel residual error amplification circuit 230 perform residual error sampling and residual error amplification on the residual error signal output by the previous-stage SAR analog-to-digital converter.

[0046] In some embodiments, the ADC circuit of the present application further includes a redundant calibration and data processing circuit 240. Among them, the output terminal of each stage of the SAR analog-to-digital converter is connected to the redundant calibration and data processing circuit 240, and the redundant calibration and data processing circuit 240 is used to finally output the digital code of the ADC circuit.

[0047] Hereinafter, it will be described by taking the ADC circuit of the present application including two-stage Pipeline SAR ADC 200 and in a fully differential form as an example.

[0048] Figure 4 Reveals the overall structural block diagram of the two-stage Pipeline SAR ADC 200 according to an embodiment of the present application. As Figure 4 shown, the two-stage Pipeline SAR ADC 200 according to an embodiment of the present application includes a first-stage M-bit SAR ADC (referred to as the first-stage SAR ADC 211), a residue sampling circuit 220, a residue amplification circuit 230, a second-stage L-bit SAR ADC (referred to as the second-stage SAR ADC 212), and a redundant calibration and data processing circuit 240. Among them, the first-stage M-bit SAR ADC samples and quantifies the differential input signal (VINP - VINN) to generate the M-bit digital code D1 of the first stage <m-1:0>and the residual difference signal VP1 - VN1. The residual difference sampling circuit 220 samples the residual difference signal VP1 - VN1 and stores the information in the sampling capacitor. The residual difference amplification circuit 230 amplifies the residual difference signal stored in the sampling capacitor to generate a residual difference amplified signal (VOP - VON). The second - stage L - bit SAR ADC samples and quantizes the residual difference amplified signal (VOP - VON) output by the residual difference amplification circuit 230 to generate the second - stage L - bit digital code D2 <l-1:0>Finally, through the redundant calibration and data processing circuit 240, the final N-bit quantization data Dout is generated <n-1:0>。

[0049] Figure 5 discloses Figure 4 An implementation circuit diagram of the two-stage Pipeline SAR ADC 200 shown, where the first-stage SAR ADC 211 and the second-stage SAR ADC 212 both adopt a VCM-Based timing architecture as an example. Of course, it can be understood that, in fact, the first-stage SAR ADC 211 and the second-stage SAR ADC 212 of the present application can also be implemented using other SAR ADC architectures, such as a monotonic timing architecture with a smaller area and lower power consumption, etc. The present application does not limit this.

[0050] As Figure 5 shown, the residue sampling circuit 220 of the present application includes a first sampling capacitor CSP and a second sampling capacitor CSN, and the residue signals include a positive residue signal VP1 and a negative residue signal VN1.

[0051] In the residue sampling stage, the first plate and the second plate of the first sampling capacitor CSP are respectively connected to the positive residue signal VP1 and the negative residue signal VN1; the first plate and the second plate of the second sampling capacitor CSN are also respectively connected to the positive residue signal VP1 and the negative residue signal VN1.

[0052] In some embodiments, the residue sampling circuit 220 of the present application includes a first positive terminal switch S11P, a second positive terminal switch S12P, a first negative terminal switch S11N, and a second negative terminal switch S12N. Among them, the first plate of the first sampling capacitor CSP is connected to the positive residue signal VP1 through the first positive terminal switch S11P; the second plate of the first sampling capacitor CSP is connected to the negative residue signal VN1 through the second positive terminal switch S12P; the first plate of the second sampling capacitor CSN is connected to the positive residue signal VP1 through the first negative terminal switch S11N; the second plate of the second sampling capacitor CSN is connected to the negative residue signal VN1 through the second negative terminal switch S12N.

[0053] When entering the residue sampling stage, the first positive terminal switch S11P, the second positive terminal switch S12P, the first negative terminal switch S11N, and the second negative terminal switch S12N are switched from the open state to the closed state; after the charge sharing process is completed, the first positive terminal switch S11P, the second positive terminal switch S12P, the first negative terminal switch S11N, and the second negative terminal switch S12N are switched from the closed state to the open state.

[0054] In some embodiments, the residual difference sampling circuit 220 of the present application further includes a third positive terminal switch S21P, a fourth positive terminal switch S22P, a fifth positive terminal switch R31P, a third negative terminal switch S21N, a fourth negative terminal switch S22N, and a fifth negative terminal switch R31N. Among them, the first terminal of the third positive terminal switch S21P is connected to the reference voltage VCM, the second terminal of the third positive terminal switch S21P is connected to the second electrode plate of the first sampling capacitor CSP and is connected to the first electrode plate of the first sampling capacitor CSP through the fifth positive terminal switch R31P; both ends of the fourth positive terminal switch S22P are respectively connected to the first electrode plate of the first sampling capacitor CSP and the positive output terminal of the residual difference sampling circuit 220; the first terminal of the third negative terminal switch S21N is connected to the reference voltage VCM, the second terminal of the third negative terminal switch S21N is connected to the first electrode plate of the second sampling capacitor CSN and is connected to the second electrode plate of the second sampling capacitor CSN through the fifth negative terminal switch R31N; both ends of the fourth negative terminal switch S22N are respectively connected to the second electrode plate of the second sampling capacitor CSN and the negative output terminal of the residual difference sampling circuit 220.

[0055] When entering the residual difference sampling stage, the fifth positive terminal switch R31P and the fifth negative terminal switch R31N are switched from the closed state to the open state.

[0056] In some embodiments, the residual difference amplification circuit 230 of the present application includes an operational amplifier AMP, a first feedback capacitor CFP, a second feedback capacitor CFN, a sixth positive terminal switch SW41P, and a sixth negative terminal switch SW41N. Among them, the operational amplifier AMP has a positive input terminal, a negative input terminal, a positive amplification output terminal, and a negative amplification output terminal. The positive input terminal of the operational amplifier AMP is connected to the positive output terminal of the residual difference sampling circuit 220, and the negative input terminal of the operational amplifier AMP is connected to the negative output terminal of the residual difference sampling circuit 220; the first feedback capacitor CFP and the sixth positive terminal switch SW41P are both connected in parallel between the positive input terminal and the negative amplification output terminal of the operational amplifier AMP; the second feedback capacitor CFN and the sixth negative terminal switch SW41N are both connected in parallel between the negative input terminal and the positive amplification output terminal of the operational amplifier AMP.

[0057] When entering the residual difference amplification stage, the third positive terminal switch S21P, the fourth positive terminal switch S22P, the third negative terminal switch S21N, and the fourth negative terminal switch S22N are switched from the open state to the closed state, and the sixth positive terminal switch SW41P and the sixth negative terminal switch SW41N are switched from the closed state to the open state.

[0058] When the next-stage SAR analog-to-digital converter completes the sampling of the residual difference amplified signal, the third positive terminal switch S21P, the fourth positive terminal switch S22P, the third negative terminal switch S21N, and the fourth negative terminal switch S22N are turned off, and the fifth positive terminal switch R31P, the fifth negative terminal switch R31N, the sixth positive terminal switch SW41P, and the sixth negative terminal switch SW41N are switched from the off state to the on state.

[0059] In some embodiments, each stage of the SAR analog-to-digital converter (SAR ADC) includes a positive terminal switch array, a negative terminal switch array, a positive terminal capacitor array, a negative terminal capacitor array, a positive terminal upper plate switch, a negative terminal upper plate switch, a comparator, and an SAR control module. Among them, the first plate of the positive terminal capacitor array is connected to the positive input terminal of the comparator and accesses the reference voltage VCM through the positive terminal upper plate switch; the second plate of the positive terminal capacitor array selectively accesses the positive differential input signal, the reference voltage VCM, the positive reference voltage VREF, and the negative reference voltage VSS through the positive terminal switch array. Usually, the reference voltage VCM is equal to half of the sum of the positive reference voltage VREF and the negative reference voltage VSS, that is ; the first plate of the negative terminal capacitor array is connected to the negative input terminal of the comparator and accesses the reference voltage VCM through the negative terminal upper plate switch; the second plate of the negative terminal capacitor array selectively accesses the negative differential input signal VINN, the reference voltage VCM, the positive reference voltage VREF, and the negative reference voltage VSS through the negative terminal switch array; the output terminal of the comparator is connected to the SAR control module; the SAR control module is used to control the positive terminal switch array and the negative terminal switch array, and output a conversion end signal and the digital code of the corresponding stage.

[0060] For example, for the first-stage SAR ADC, the first plate of the first-stage positive terminal capacitor array CDAC1_P is connected to the positive input terminal of the first-stage comparator COMP1 and accesses the reference voltage VCM through the first-stage positive terminal upper plate switch; the second plate of the first-stage positive terminal capacitor array CDAC1_P selectively accesses the positive differential input signal VINP, the reference voltage VCM, the positive reference voltage VREF, and the negative reference voltage VSS through the first-stage positive terminal switch array; the first plate of the first-stage negative terminal capacitor array CDAC1_N is connected to the negative input terminal of the first-stage comparator COMP1 and accesses the reference voltage VCM through the first-stage negative terminal upper plate switch; the second plate of the first-stage negative terminal capacitor array CDAC1_N selectively accesses the negative differential input signal VINN, the reference voltage VCM, the positive reference voltage VREF, and the negative reference voltage VSS through the first-stage negative terminal switch array; the output terminal of the first-stage comparator COMP1 is connected to the first-stage SAR control (SAR CTRL1) module; the first-stage SAR control (SAR CTRL1) module is used to control the first-stage positive terminal switch array and the first-stage negative terminal switch array, and outputs the conversion end signal EOC_1 and the digital code D1_1 of the first stage <m-1:0>。

[0061] For the second-stage SAR ADC, the first plate of the second-stage positive terminal capacitor array CDAC2_P is connected to the positive input terminal of the second-stage comparator COMP2 and is connected to the reference voltage VCM through the second-stage positive terminal upper plate switch; the second plate of the second-stage positive terminal capacitor array CDAC2_P is selectively connected to the positive differential input signal VINP, the reference voltage VCM, the positive reference voltage VREF, and the negative reference voltage VSS through the second-stage positive terminal switch array; the first plate of the second-stage negative terminal capacitor array CDAC2_N is connected to the negative input terminal of the second-stage comparator COMP2 and is connected to the reference voltage VCM through the second-stage negative terminal upper plate switch; the second plate of the second-stage negative terminal capacitor array CDAC2_N is selectively connected to the negative differential input signal VINN, the reference voltage VCM, the positive reference voltage VREF, and the negative reference voltage VSS through the second-stage negative terminal switch array; the output terminal of the second-stage comparator COMP2 is connected to the second-stage SAR control (SAR CTRL2) module; the second-stage SAR control (SAR CTRL2) module is used to control the second-stage positive terminal switch array and the second-stage negative terminal switch array, and outputs the conversion end signal EOC_2 and the digital code D2_1 of the second stage <m-1:0>When a certain - stage SAR analog - to - digital converter enters the sampling stage, the positive - terminal upper - plate switch and the negative - terminal upper - plate switch in this stage of the SAR analog - to - digital converter are closed. At the same time, the second plates of the positive - terminal capacitor array of this stage are connected to the positive - input signal through the positive - terminal switch array of this stage, and the second plates of the negative - terminal capacitor array of this stage are connected to the negative - input signal through the negative - terminal switch array of this stage. Among them, for the first - stage SAR analog - to - digital converter, the positive - input signal includes the positive - differential input signal VINP, and the negative - input signal includes the negative - differential input signal VINN; for the other stages of the SAR analog - to - digital converter except the first stage, the positive - input signal includes the positive residual - amplified signal VOP output by the previous - stage residual - difference amplifier circuit, and the negative - input signal includes the negative residual - amplified signal VON output by the previous - stage residual - difference amplifier circuit. After a predetermined sampling - stabilization time, the positive - terminal upper - plate switch and the negative - terminal upper - plate switch in this stage of the SAR analog - to - digital converter are switched from the closed state to the open state, and the second plates of the positive - terminal capacitor array of this stage are connected to the reference voltage VCM through the positive - terminal switch array of this stage, and the second plates of the negative - terminal capacitor array of this stage are connected to the reference voltage VCM through the negative - terminal switch array of this stage.

[0062] Figure 6 discloses Figure 5 the operating timing diagram of the two - stage Pipeline SAR ADC 200 shown below. Next, in combination with Figure 5 and Figure 6 , taking the two - stage Pipeline SAR ADC 200 as an example, the working principle of the ADC circuit of the present application will be described.

[0063] Sampling stage of the first - stage SAR ADC 211 (duration t1): By controlling the first - stage positive - terminal (P - terminal) switch array and the first - stage negative - terminal (N - terminal) switch array, the positive - differential input signal VINP and the negative - differential input signal VINN are respectively connected to the second plates of the first - stage positive - terminal capacitor array CDAC1_P and the first - stage negative - terminal capacitor array CDAC1_N. At the same time, the first plates of the first - stage positive - terminal capacitor array CDAC1_P and the first - stage negative - terminal capacitor array CDAC1_N are connected to the reference voltage VCM by controlling the first - stage positive - terminal upper - plate switch SW1P and the first - stage negative - terminal upper - plate switch SW1N, so as to sample the input signal. After a certain sampling - stabilization time, control the first - stage positive - terminal upper - plate switch SW1P and the first - stage negative - terminal upper - plate switch SW1N to disconnect, and disconnect the positive - differential input signal VINP and the negative - differential input signal VINN from the second plates of the first - stage positive - terminal capacitor array CDAC1_P and the first - stage negative - terminal capacitor array CDAC1_N. At this time, the sampling of the input signal is completed (the information of the input signal V1 is sampled into the first - stage positive - terminal capacitor array CDAC1_P and the first - stage negative - terminal capacitor array CDAC1_N).

[0064] The first-stage SAR ADC 211 conversion phase (duration t2): The conversion end signal EOC_1 output by the first-stage SAR control (SAR CTRL1) module changes from high to low, indicating that the first-stage SAR ADC 211 enters the conversion phase. According to the binary search algorithm, the switching of the first-stage positive terminal switch array and the first-stage negative terminal switch array is controlled by the SAR CTRL1 module, and the signals connected to the second plates of the first-stage positive terminal capacitor array CDAC1_P and the first-stage negative terminal capacitor array CDAC1_N are controlled to gradually approximate the quantization of the sampled signal. Finally, the conversion end signal EOC_1 changes from low to high, indicating that the conversion of the first-stage SAR ADC 211 is completed. At this time, a residue signal (VP1 - VN1) is generated, and the digital code D1_1 of the first stage is output simultaneously. <m-1:0>。

[0065] Residual difference sampling stage (duration ts): The residual difference sampling circuit 220 samples the residual difference signal as follows: The fifth positive terminal switch R31P and the fifth negative terminal switch R31N are switched from the closed state to the open state, and the first positive terminal switch S11P, the second positive terminal switch S12P, the first negative terminal switch S11N, and the second negative terminal switch S12N are switched from the open state to the closed state, so as to connect the first plates and the second plates of the first sampling capacitor CSP and the second sampling capacitor CSN to the positive residual difference signal VP1 and the negative residual difference signal VN1 respectively. After a duration ts, the charge sharing process is completed, and the first positive terminal switch S11P, the second positive terminal switch S12P, the first negative terminal switch S11N, and the first negative terminal switch S12N are switched from the closed state to the open state. At this time, the sampling of the residual difference signal is completed and the charge information is stored on the first sampling capacitor CSP and the second sampling capacitor CSN.

[0066] Residual error amplification and sampling phase (duration t3) of the second-stage SAR ADC 212: By controlling the third positive terminal switch S21P, the fourth positive terminal switch S22P, the third negative terminal switch S21N, and the fourth negative terminal switch S22N to switch from the open state to the closed state, and at the same time, the sixth positive terminal switch SW41P and the sixth negative terminal switch SW41N to switch from the closed state to the open state, residual error amplification is achieved, generating a residual error amplification signal (VOP - VON). At the same time, by controlling the second-stage positive terminal switch array CDAC2_P and the second-stage negative terminal switch array CDAC2_N, the positive residual error amplification signal VOP and the negative residual error amplification signal VON are respectively connected to the second plates of the second-stage positive terminal switch array CDAC2_P and the second-stage negative terminal switch array CDAC2_N. The first plates of the second-stage positive terminal switch array CDAC2_P and the second-stage negative terminal switch array CDAC2_N are connected to the reference voltage VCM by controlling the second-stage positive terminal upper plate switch SW2P and the second-stage negative terminal upper plate switch SW2N, thereby realizing the sampling of the residual error amplification signal (VOP - VON) by the second-stage SAR ADC 212. After a certain amplification stabilization and sampling stabilization time, control the second-stage positive terminal upper plate switch SW2P, the second-stage negative terminal upper plate switch SW2N, the third positive terminal switch S21P, the fourth positive terminal switch S22P, the third negative terminal switch S21N, and the fourth negative terminal switch S22N to disconnect, and disconnect the positive residual error amplification signal VOP and the negative residual error amplification VON from the second plates of the second-stage positive terminal switch array CDAC2_P and the second-stage negative terminal switch array CDAC2_N. At this time, the sampling of the residual error amplification signal by the second-stage SAR ADC 212 is completed. At this time, it is also necessary to switch the fifth positive terminal switch R31P, the fifth negative terminal switch R31N, the sixth positive terminal switch SW41P, and the sixth negative terminal switch SW41N from the open state to the closed state to achieve the charge zero reset of the first sampling capacitor CSP, the second sampling capacitor CSN, the first feedback capacitor CFP, and the second feedback capacitor CFN for the next sampling and amplification process.

[0067] Conversion phase (duration t4) of the second-stage SAR ADC 212: The conversion end signal EOC_2 output by the second-stage SAR control (SAR CTRL2) module changes from high to low, indicating that the second-stage SAR ADC 212 enters the conversion phase. According to the binary search algorithm, the second-stage SAR ADC 212, according to the binary search algorithm, controls the switching of the second-stage positive terminal switch array and the second-stage negative terminal switch array through the SAR CTRL2 module to gradually approximate and realize the quantization of the sampling signal. Finally, the conversion end signal EOC_2 changes from low to high, indicating that the conversion of the second-stage SAR ADC 212 is completed. At this time, the digital code D2_1 of the second stage is generated. <l-1:0>。

[0068] N-bit quantized data Dout <n-1:0>Generation stage: The redundancy calibration and data processing circuit 240 processes the digital code D1_1 of the first stage <m-1:0>and the digital code D2_1 of the second level <l-1:0>After performing alignment addition and correcting the fixed offset, the final N-bit quantization data (i.e., N-bit digital code) Dout1 is output <n-1:0>, this N-bit quantized data corresponds to the input signal V1.

[0069] From Figure 6 From the timing diagram, it can also be seen that while the residual error amplification and the sampling phase of the second-stage SAR ADC 212 described above are taking place, the first-stage SAR ADC 211 can perform the next sampling of the input signal (sampling the input voltage V2). This is mainly because the positive residual error signal VP1 and the negative residual error signal VN1 are no longer needed during this stage. The first-stage positive terminal capacitor array CDAC1_P and the first-stage negative terminal capacitor array CDAC1_N can be used to sample the new input signal, making more full use of the advantages of pipelined operation. Figure 6 The digital code Dout2 in <n-1:0>is by means of the digital code D1_2 of the first level <m-1:0>and the digital code D2_2 of the second level <l-1:0>The N-bit quantization data corresponding to the input signal V2, obtained after alignment addition and correction of the fixed offset.

[0070] Based on the above analysis, it can be seen that for the two-stage Pipeline SAR ADC 200 of the present application, although a residue sampling stage (with a duration of ts) is introduced, the time ts is much shorter than that of other stages. Because the residue sampling stage is actually a process of charge sharing and transfer between capacitors, and such a passive sharing and transfer process can be completed very quickly. Since in the residue sampling stage, the residue signals (VP1 - VN1) on the first-stage positive capacitor array CDAC1_P and the first-stage negative capacitor array CDAC1_N have been sampled and stored in the first sampling capacitor CSP and the second sampling capacitor CSN, therefore, during the subsequent residue amplification and the sampling stage of the second-stage SAR ADC 212, the first-stage SAR ADC 211 can perform the next sampling of the input signal. As Figure 6 shown, the maximum conversion rate of the two-stage Pipeline SAR ADC 200 of the present application (i.e., the digital code Dout <n-1:0>The speed of data update , compared with the above related technologies , there is a significant rate improvement

[0071] In addition, during the residue amplification and the sampling stage of the second-stage SAR ADC 212, by controlling the third positive terminal switch S21P, the fourth positive terminal switch S22P, the third negative terminal switch S21N, and the fourth negative terminal switch S22N to switch from the open state to the closed state, and at the same time, the sixth positive terminal switch SW41P and the sixth negative terminal switch SW41N switch from the closed state to the open state, residue amplification is achieved, and a residue amplification signal (VOP - VON) is generated. At this time, the reference voltage VCM is respectively connected to the second electrode plate of the first sampling capacitor CSP and the first electrode plate of the second sampling capacitor CSN through the third positive terminal switch S21P and the third negative terminal switch S21N. And after the residue sampling stage ends, the charges stored on the first sampling capacitor CSP and the second sampling capacitor CSN are the same. Therefore, it can be seen that the common-mode levels of the positive signal VISP and the negative signal VISN output by the residue sampling circuit 220 are always VCM at this time. And at this time, the positive input terminal and the negative input terminal of the operational amplifier AMP are respectively connected to the positive signal VISP and the negative signal VISN output by the residue sampling circuit 220. It can be seen that it ensures that the common-mode input voltage of the operational amplifier AMP is always the reference voltage VCM, and does not depend on the positive residue signal VP1 and the negative residue signal VN1 output by the first-stage SAR ADC 211, greatly simplifying the design difficulty of the operational amplifier AMP and improving the flexibility of circuit design

[0072] The two-stage Pipeline SAR ADC 200 of the present application can, by introducing the residue sampling circuit 220, realize that while performing residue amplification and the sampling stage of the second-stage SAR ADC 212, the first-stage SAR ADC 211 performs the next sampling of the input signal, making more full use of the advantages of pipelined operation. The maximum conversion rate of the ADC circuit is increased from to , greatly improving the conversion rate of the ADC circuit. For the same conversion rate requirement, by adopting the circuit structure of the two-stage Pipeline SAR ADC 200 of the present application, the time of the residue amplification and sampling stage can be appropriately increased, thereby reducing the requirements for the switch size and the bandwidth of the operational amplifier AMP in the circuit, thus reducing the design difficulty and cost

[0073] In addition, by introducing the residue sampling circuit 220 in the two-stage Pipeline SAR ADC 200 of the present application, the input common-mode voltage of the operational amplifier AMP during residue amplification is always equal to the reference voltage VCM, and does not depend on the positive residue signal VP1 and the negative residue signal VN1 output by the first-stage SAR ADC 211. Therefore, the first-stage SAR ADC 211 can flexibly adopt other timing architectures. Even if it does not adopt the VCM-Based timing architecture, such as a monotonic timing architecture with a smaller area and lower power consumption, it can still ensure that the common-mode input voltage input to the operational amplifier AMP in the residue amplification circuit 230 is constantly the reference voltage VCM, thereby reducing the design difficulty of the operational amplifier AMP and improving the flexibility of circuit design.

[0074] The above takes the two-stage Pipeline SAR ADC 200 as an example to illustrate the composition, working principle, and beneficial effects that can be achieved by the ADC circuit of the present application. It can be similarly extended to more-stage Pipeline SAR ADCs, and will not be elaborated here.

[0075] The present application also provides a control method for an ADC circuit. The ADC circuit includes multiple-stage SAR analog-to-digital converters and multiple-stage residue processing circuits, and each stage of the residue processing circuit is located between two adjacent stages of SAR analog-to-digital converters. Each stage of the residue processing circuit includes a residue sampling circuit 220 and a residue amplification circuit 230 connected to the output end of the residue sampling circuit 220. Both the residue sampling circuit 220 and the residue amplification circuit 230 are single-channel circuits.

[0076] Figure 7 Disclosed is a flowchart of a control method for an ADC circuit according to an embodiment of the present application. As Figure 7 and in combination with Figure 5 shown, the control method for an ADC circuit according to an embodiment of the present application may include step S71 and step S72.

[0077] In step S71, in each sampling conversion period of the ADC circuit, control the residue sampling circuit 220 and the residue amplification circuit 230 to respectively perform residue sampling and residue amplification on the residue signal output by the previous-stage SAR analog-to-digital converter.

[0078] In step S72, during the period when the residue amplification circuit 230 amplifies the residue signal output by the previous-stage SAR analog-to-digital converter and the next-stage SAR analog-to-digital converter samples, control the previous-stage SAR analog-to-digital converter to perform the next sampling.

[0079] The above steps S71 and S72 can be controlled to be executed by one or more controllers.

[0080] The residue sampling circuit 220 includes a first sampling capacitor CSP and a second sampling capacitor CSN, and the residue signal includes a positive residue signal VP1 and a negative residue signal VN1. In some embodiments, the control method of the ADC circuit of the present application may further include step S73.

[0081] In step S73, when entering the residue sampling stage, control is performed to connect the first plate and the second plate of the first sampling capacitor CSP to the positive residue signal VP1 and the negative residue signal VN1 output by the previous-stage SAR analog-to-digital converter respectively; and connect the first plate and the second plate of the second sampling capacitor CSN to the positive residue signal VP1 and the negative residue signal VN1 output by the previous-stage SAR analog-to-digital converter respectively.

[0082] The residue amplification circuit 230 includes an operational amplifier AMP, a first feedback capacitor CFP and a second feedback capacitor CFN. In some embodiments, the control method of the ADC circuit of the present application may further include step S74.

[0083] In step S74, when entering the residue amplification stage, control is performed to connect the second plate of the first sampling capacitor CSP and the first plate of the second sampling capacitor CSN to the reference voltage VCM; connect the first plate of the first sampling capacitor CSP and the second plate of the second sampling capacitor CSN to the positive input terminal and the negative input terminal of the operational amplifier AMP respectively; and control to connect the positive input terminal of the operational amplifier AMP to the negative amplification output terminal of the operational amplifier AMP through the first feedback capacitor CFP; connect the negative input terminal of the operational amplifier AMP to the positive amplification output terminal of the operational amplifier AMP through the second feedback capacitor CFN.

[0084] In some embodiments, the control method of the ADC circuit of the present application may further include step S75.

[0085] In step S75, when the next-stage SAR analog-to-digital converter completes sampling of the residue amplification signal output by the residue amplification circuit 230, control is performed to short-circuit both ends of the first sampling capacitor CSP, both ends of the second sampling capacitor CSN, both ends of the first feedback capacitor CFP and both ends of the second feedback capacitor CFN.

[0086] Each stage of the SAR analog-to-digital converter includes a positive terminal switch array, a negative terminal switch array, a positive terminal capacitor array and a negative terminal capacitor array. In some embodiments, the control method of the ADC circuit of the present application may further include step S76 and step S77.

[0087] In step S76, when a certain - stage SAR analog - to - digital converter enters the sampling phase, by controlling the positive - terminal switch array and the negative - terminal switch array of this stage, the positive - input signal and the negative - input signal are respectively connected to the second plates of the positive - terminal capacitor array and the negative - terminal capacitor array of this stage; and control the first plates of the positive - terminal capacitor array and the negative - terminal capacitor array of this stage to access the reference voltage VCM. Among them, for the first - stage SAR analog - to - digital converter, the positive - input signal includes the positive differential - input signal VINP, and the negative - input signal includes the negative differential - input signal VINN; for the other - stage SAR analog - to - digital converters except the first stage, the positive - input signal includes the positive residual - amplification signal VOP output by the previous - stage residual - difference amplification circuit, and the negative - input signal includes the negative residual - amplification signal VON output by the previous - stage residual - difference amplification circuit.

[0088] In step S77, after a predetermined sampling - stabilization time, control the first plates of the positive - terminal capacitor array and the negative - terminal capacitor array of this stage to disconnect from the reference voltage VCM; and control the positive - input signal and the negative - input signal to disconnect from the second plates of the positive - terminal capacitor array and the negative - terminal capacitor array of this stage, and connect the second plates of the positive - terminal capacitor array and the negative - terminal capacitor array of this stage to the reference voltage VCM.

[0089] It can be understood that the above - mentioned steps are only distinguished for the convenience of description. In practice, according to the working principle of the ADC circuit, the above - mentioned steps or some operations in each step can be merged with each other or carried out in different steps. These minor changes do not change the basic principle of the control method of the ADC circuit of the present application, and they are all within the protection scope of the present application.

[0090] In the control method of the ADC circuit of the present application, the controller can execute the corresponding steps by controlling the corresponding switch array and / or the corresponding switches.

[0091] The control method of the ADC circuit of the present application has beneficial technical effects similar to those described above for the ADC circuit. Therefore, it will not be elaborated here.

[0092] The above has introduced in detail the ADC circuit and its control method provided by the embodiments of the present application. Specific examples are used in this article to elaborate on the ADC circuit and its control method of the embodiments of the present application. The description of the above - mentioned embodiments is only used to help understand the core idea of the present application and is not used to limit the present application. It should be pointed out that for those of ordinary skill in the art in this technical field, without departing from the spirit and principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications should also fall within the protection scope of the appended claims of the present application.

Claims

1. An ADC circuit, characterized in that, It includes a multi-stage SAR analog-to-digital converter and a multi-stage residue processing circuit. Among them, each stage of the residue processing circuit is located between two adjacent stages of the SAR analog-to-digital converter; each stage of the residue processing circuit includes a residue sampling circuit and a residue amplification circuit connected to the output end of the residue sampling circuit. Both the residue sampling circuit and the residue amplification circuit are single-channel circuits. The residue sampling circuit is implemented by a passive charge sharing method, and the residue amplification circuit is implemented by an active operational amplifier. In each sampling and conversion cycle of the ADC circuit, the residue sampling circuit and the residue amplification circuit perform residue sampling and residue amplification on the residue signal output by the previous stage of the SAR analog-to-digital converter. During the period when the residue amplification circuit amplifies the residue signal output by the previous stage of the SAR analog-to-digital converter and the next stage of the SAR analog-to-digital converter performs sampling, the previous stage of the SAR analog-to-digital converter is used to perform the next sampling.

2. The ADC circuit according to claim 1, characterized in that, The residue sampling circuit includes a first sampling capacitor and a second sampling capacitor. The residue signal includes a positive residue signal and a negative residue signal. Among them, in the residue sampling stage, the first plate and the second plate of the first sampling capacitor are respectively connected to the positive residue signal and the negative residue signal; the first plate and the second plate of the second sampling capacitor are also respectively connected to the positive residue signal and the negative residue signal.

3. The ADC circuit according to claim 2, wherein The residue sampling circuit includes a first positive terminal switch, a second positive terminal switch, a first negative terminal switch, and a second negative terminal switch. Among them, the first plate of the first sampling capacitor is connected to the positive residue signal through the first positive terminal switch; the second plate of the first sampling capacitor is connected to the negative residue signal through the second positive terminal switch; the first plate of the second sampling capacitor is connected to the positive residue signal through the first negative terminal switch; the second plate of the second sampling capacitor is connected to the negative residue signal through the second negative terminal switch.

4. The ADC circuit according to claim 3, wherein When entering the residue sampling stage, the first positive terminal switch, the second positive terminal switch, the first negative terminal switch, and the second negative terminal switch are switched from the open state to the closed state; after the charge sharing process is completed, the first positive terminal switch, the second positive terminal switch, the first negative terminal switch, and the second negative terminal switch are switched from the closed state to the open state.

5. The ADC circuit according to claim 3, wherein The residue sampling circuit further includes a third positive terminal switch, a fourth positive terminal switch, a fifth positive terminal switch, a third negative terminal switch, a fourth negative terminal switch, and a fifth negative terminal switch. Among them, the first end of the third positive terminal switch is connected to a reference voltage, and the second end of the third positive terminal switch is connected to the second plate of the first sampling capacitor and is connected to the first plate of the first sampling capacitor through the fifth positive terminal switch; both ends of the fourth positive terminal switch are respectively connected to the first plate of the first sampling capacitor and the positive output end of the residue sampling circuit; The first terminal of the third negative terminal switch is connected to the reference voltage, and the second terminal of the third negative terminal switch is connected to the first plate of the second sampling capacitor and is connected to the second plate of the second sampling capacitor through the fifth negative terminal switch; Both ends of the fourth negative terminal switch are respectively connected to the second plate of the second sampling capacitor and the negative output terminal of the residual difference sampling circuit.

6. The ADC circuit according to claim 5, wherein When entering the residual difference sampling stage, the fifth positive terminal switch and the fifth negative terminal switch are switched from the closed state to the open state.

7. The ADC circuit according to claim 5, wherein The residual difference amplifier circuit includes an operational amplifier, a first feedback capacitor, a second feedback capacitor, a sixth positive terminal switch, and a sixth negative terminal switch, where The operational amplifier has a positive input terminal, a negative input terminal, a positive amplification output terminal, and a negative amplification output terminal. The positive input terminal of the operational amplifier is connected to the positive output terminal of the residual difference sampling circuit, and the negative input terminal of the operational amplifier is connected to the negative output terminal of the residual difference sampling circuit; The first feedback capacitor and the sixth positive terminal switch are both connected in parallel between the positive input terminal and the negative amplification output terminal of the operational amplifier; The second feedback capacitor and the sixth negative terminal switch are both connected in parallel between the negative input terminal and the positive amplification output terminal of the operational amplifier.

8. The ADC circuit according to claim 7, wherein When entering the residual difference amplification stage, the third positive terminal switch, the fourth positive terminal switch, the third negative terminal switch, and the fourth negative terminal switch are switched from the open state to the closed state, and the sixth positive terminal switch and the sixth negative terminal switch are switched from the closed state to the open state.

9. The ADC circuit according to claim 7, wherein When the next-stage SAR analog-to-digital converter completes sampling of the residual difference amplified signal, the third positive terminal switch, the fourth positive terminal switch, the third negative terminal switch, and the fourth negative terminal switch are turned off, and moreover, the fifth positive terminal switch, the fifth negative terminal switch, the sixth positive terminal switch, and the sixth negative terminal switch are switched from the open state to the closed state.

10. The ADC circuit according to any one of claims 1 to 9, characterized in that, Each stage of the SAR analog-to-digital converter includes a positive terminal switch array, a negative terminal switch array, a positive terminal capacitor array, a negative terminal capacitor array, a positive terminal upper plate switch, a negative terminal upper plate switch, a comparator, and an SAR control module, where The first plate of the positive terminal capacitor array is connected to the positive input terminal of the comparator and is connected to the reference voltage through the positive terminal upper plate switch; the second plate of the positive terminal capacitor array is selectively connected to the positive differential input signal, the reference voltage, the positive reference voltage, and the negative reference voltage through the positive terminal switch array; The first plate of the negative terminal capacitor array is connected to the negative input terminal of the comparator and is connected to the reference voltage through the negative terminal upper plate switch; the second plate of the negative terminal capacitor array is selectively connected to the negative differential input signal, the reference voltage, the positive reference voltage, and the negative reference voltage through the negative terminal switch array; The output terminal of the comparator is connected to the SAR control module; The SAR control module is used to control the positive terminal switch array and the negative terminal switch array, and output a conversion end signal and the digital code of the corresponding stage.

11. The ADC circuit according to claim 10, wherein When a certain - stage SAR analog - to - digital converter enters the sampling stage, the positive - terminal upper - plate switch and the negative - terminal upper - plate switch in this stage of the SAR analog - to - digital converter are closed. At the same time, the second plates of the positive - terminal capacitor array in this stage of the SAR analog - to - digital converter are connected to the positive - input signal through the positive - terminal switch array in this stage of the SAR analog - to - digital converter, and the second plates of the negative - terminal capacitor array in this stage of the SAR analog - to - digital converter are connected to the negative - input signal through the negative - terminal switch array in this stage of the SAR analog - to - digital converter. Among them, for the first - stage SAR analog - to - digital converter, the positive - input signal includes a positive differential - input signal, and the negative - input signal includes a negative differential - input signal; for the other stages of the SAR analog - to - digital converter except the first stage, the positive - input signal includes the positive residual - difference amplification signal output by the previous - stage residual - difference amplification circuit, and the negative - input signal includes the negative residual - difference amplification signal output by the previous - stage residual - difference amplification circuit; after a predetermined sampling - stabilization time, the positive - terminal upper - plate switch and the negative - terminal upper - plate switch in this stage of the SAR analog - to - digital converter are switched from the closed state to the open state, and the second plates of the positive - terminal capacitor array in this stage of the SAR analog - to - digital converter are connected to the reference voltage through the positive - terminal switch array in this stage of the SAR analog - to - digital converter, and the second plates of the negative - terminal capacitor array in this stage of the SAR analog - to - digital converter are connected to the reference voltage through the negative - terminal switch array in this stage of the SAR analog - to - digital converter.

12. The ADC circuit according to claim 10, wherein, It further includes a redundant calibration and data - processing circuit, where the output terminal of each stage of the SAR analog - to - digital converter is connected to the redundant calibration and data - processing circuit, and the redundant calibration and data - processing circuit is used to finally output the digital code of the ADC circuit.

13. A control method for an ADC circuit, the ADC circuit comprising a multi-stage SAR analog-to-digital converter and a multi-stage residue processing circuit, each stage of the residue processing circuit being located between two adjacent stages of the SAR analog-to-digital converter, characterized in that, Each stage of the residual - difference processing circuit includes a residual - difference sampling circuit and a residual - difference amplification circuit connected to the output terminal of the residual - difference sampling circuit. Both the residual - difference sampling circuit and the residual - difference amplification circuit are single - channel circuits. The method includes: In each sampling - conversion period of the ADC circuit, controlling the residual - difference sampling circuit and the residual - difference amplification circuit to respectively perform residual - difference sampling and residual - difference amplification on the residual - difference signal output by the previous - stage SAR analog - to - digital converter; During the period when the residual - difference amplification circuit amplifies the residual - difference signal output by the previous - stage SAR analog - to - digital converter and the next - stage SAR analog - to - digital converter performs sampling, controlling the previous - stage SAR analog - to - digital converter to perform the next sampling.

14. The control method according to claim 13, wherein The residual - difference sampling circuit includes a first sampling capacitor and a second sampling capacitor. The residual - difference signal includes a positive residual - difference signal and a negative residual - difference signal. The method further includes: When entering the residual - difference sampling stage, controlling to connect the first plate and the second plate of the first sampling capacitor to the positive residual - difference signal and the negative residual - difference signal output by the previous - stage SAR analog - to - digital converter respectively; and connecting the first plate and the second plate of the second sampling capacitor to the positive residual - difference signal and the negative residual - difference signal output by the previous - stage SAR analog - to - digital converter respectively.

15. The control method according to claim 14, wherein The residual error amplification circuit includes an operational amplifier, a first feedback capacitor, and a second feedback capacitor. The method further includes: In the residual error amplification stage, controlling to connect the second electrode plate of the first sampling capacitor and the first electrode plate of the second sampling capacitor to a reference voltage; connecting the first electrode plate of the first sampling capacitor and the second electrode plate of the second sampling capacitor to the positive input terminal and the negative input terminal of the operational amplifier respectively; and controlling to connect the positive input terminal of the operational amplifier to the negative amplification output terminal of the operational amplifier through the first feedback capacitor; connecting the negative input terminal of the operational amplifier to the positive amplification output terminal of the operational amplifier through the second feedback capacitor.

16. The control method according to claim 15, characterized in that, It further includes: When the next-stage SAR analog-to-digital converter completes sampling of the residual error amplification signal output by the residual error amplification circuit, controlling to short-circuit both ends of the first sampling capacitor, both ends of the second sampling capacitor, both ends of the first feedback capacitor, and both ends of the second feedback capacitor.

17. The control method according to claim 13, wherein Each stage of the SAR analog-to-digital converter includes a positive terminal switch array, a negative terminal switch array, a positive terminal capacitor array, and a negative terminal capacitor array. The method further includes: When a certain stage of the SAR analog-to-digital converter enters the sampling stage, by controlling the positive terminal switch array and the negative terminal switch array in this stage of the SAR analog-to-digital converter, connecting the positive input signal and the negative input signal to the second electrode plates of the positive terminal capacitor array and the negative terminal capacitor array in this stage of the SAR analog-to-digital converter respectively; and controlling the first electrode plates of the positive terminal capacitor array and the negative terminal capacitor array in this stage of the SAR analog-to-digital converter to be connected to a reference voltage. Among them, for the first stage of the SAR analog-to-digital converter, the positive input signal includes a positive differential input signal, and the negative input signal includes a negative differential input signal; for other stages of the SAR analog-to-digital converter except the first stage, the positive input signal includes the positive residual error amplification signal output by the previous-stage residual error amplification circuit, and the negative input signal includes the negative residual error amplification signal output by the previous-stage residual error amplification circuit; After a predetermined sampling stabilization time, controlling the first electrode plates of the positive terminal capacitor array and the negative terminal capacitor array in this stage of the SAR analog-to-digital converter to be disconnected from the reference voltage; and controlling the positive input signal and the negative input signal to be disconnected from the second electrode plates of the positive terminal capacitor array and the negative terminal capacitor array in this stage of the SAR analog-to-digital converter, and connecting the second electrode plates of the positive terminal capacitor array and the negative terminal capacitor array in this stage of the SAR analog-to-digital converter to the reference voltage.

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