Low-complexity and high-performance LDPC (Low Density Parity Check) soft decoding implementation method and device

Abstract

The invention provides an LDPC soft decoding implementation method and device with low complexity and high performance. The method comprises the following steps: initializing matrix row and column parameters and a variable node information secondary minimum value mapping table according to a decoding matrix; initializing information transmitted from the variable node to the check node, a minimum value of the information, a column number where the minimum value is located and a secondary minimum value estimation parameter of the variable node information; updating of node information is completed; and performing hard decision, updating the speculated code word and checking the code word, and outputting a decoding result when the checking is successful. According to the method, the problem of memory conflict is solved by adopting the decoding design of layering according to columns, and the throughput rate is improved; by adopting the variable node information secondary minimum mapping estimation method, the hardware implementation complexity is effectively reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of error correction in wireless communication systems, and particularly relates to a method and device for implementing low-complexity and high-performance LDPC soft decoding. Background Art

[0002] With the popularization of 5G technology and Wifi6 technology, the information transmission volume and transmission rate in the field of wireless communication have increased significantly, which brings higher requirements for the stability and reliability of information transmission. In the field of wireless communication, a decoder is a device or algorithm that decodes the signal output from an encoder. It is mainly used in digital communication to convert the encoded information back to the original format and is a key link to ensure accurate information transmission. Therefore, it is necessary to conduct in-depth research on the decoding algorithm and the implementation method of the decoder.

[0003] The type and design of the decoder depend on the coding scheme used. Common coding schemes include convolutional coding, Cyclic Redundancy Check (CRC), Hamming code, etc. For different coding schemes, the decoder needs to have corresponding algorithms and hardware support for decoding.

[0004] With the development of communication technology, the design of the decoder has become more complex and diverse. The Low Density Parity Check (LDPC) code has become a widely used channel coding and decoding scheme for general decoders in the communication field due to its good decoding performance, adaptability to various communication standards, and relatively low hardware implementation complexity. Therefore, the research and design of LDPC decoders have become very meaningful.

[0005] LDPC decoding algorithms can be divided into soft decoding algorithms and hard decoding algorithms. The hard decoding algorithm decodes the hard decision information as the original codeword and does not require multiple read operations. Its decoding complexity is low and it is friendly to the hardware implementation of the decoder, but its decoding performance is poor. The LDPC soft decoding algorithm needs to obtain the Log Likelihood Ratio (LLR) of the soft decision probability information, which is expressed by the following formula:

[0006]

[0007] Where p(y = 0 / 1) represents the probability that the bit is 0 or 1. The acquisition of soft decision probability information usually requires multiple read operations, which will increase the resource overhead and power consumption. The commonly used LDPC soft decoding algorithm is the Belief Propagation (BP) algorithm. Since this algorithm has a large number of complex non-linear functions, it is not suitable for hardware implementation. The Normalized Min-Sum (NMS) algorithm simplifies the non-linear functions in the BP algorithm into addition, subtraction, comparison, and exclusive OR operations. Although this sacrifices some decoding performance, it achieves a lower hardware implementation complexity.

[0008] In the decoding process of LDPC codes, the scheduling methods between nodes can be divided into Flooding and Layered. In Flooding decoding, in each iteration, the information from all variable nodes to check nodes is calculated first, then the information from check nodes to variable nodes is calculated, and then the global scale is used for iterative update. In Layered decoding, after updating the information of each check node, the information is immediately used to update the information of variable nodes and is used for the update of check node messages later.

[0009] According to the current communication protocol standard, the Layered decoding framework usually uses Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes as channel coding, and block parallel decoding can be easily implemented by introducing a small amount of hardware resources. Among them, the block parallelism is linearly related to the codeword length. There are 51 values (ranging from 2 to 384) in the 5G standard, which requires reserving 384 computing modules and storing 384 copies of check node information at the same time, resulting in excessive consumption of hardware resources. At the same time, when decoding long codewords, Layered decoding needs to consume multiple clock cycles to complete the update of check node information, which has a great impact on the decoding throughput (the amount of codewords decoded per unit clock cycle).

[0010] In summary, the problems existing in the existing Layered decoding algorithm of LDPC soft decoding are as follows: (1) In order to be compatible with all codewords of the communication protocol, the decoder needs to reserve a large parallelism and store a large amount of check node information, resulting in excessive resource consumption; (2) When decoding long codewords, it takes multiple clock cycles to complete the update of check node information, which greatly limits the decoding throughput. Summary of the Invention

[0011] In order to solve the technical problems that the existing Layered decoding algorithm of LDPC soft decoding requires the decoder to reserve a large parallelism, store a large amount of check node information, resulting in excessive resource consumption, and that when decoding long codewords, it takes multiple clock cycles to complete the update of check node information, which limits the decoding throughput, the present invention provides a method and device for implementing LDPC soft decoding with low complexity and high performance.

[0012] The technical solution proposed by the present invention is as follows: A method for implementing low-complexity and high-performance LDPC soft decoding, specifically a column-layered random estimation and normalized min-sum algorithm decoding method, includes the following steps:

[0013] Step S1. Initialize the matrix row and column parameters and the variable node information second-minimum value mapping table according to the decoding matrix H.

[0014] Step S2. Initialize the minimum value min1 of the information q i,j 、q i,j transmitted from the variable node to the check node, the column number min1_idx where the minimum value is located, and the variable node information second-minimum value estimation parameter es_min2_idx.

[0015] Step S3. The node information update unit performs calculation iterations according to q i,j 、min1 and the variable node information second-minimum value mapping estimated value, completes the update of the node information, and calculates the posterior probability.

[0016] Step S4. Perform a hard decision on the posterior probability result obtained in Step S3, update the speculated codeword to and check the codeword, and output the decoding result when the check is successful.

[0017] The present invention also provides a low-complexity and high-performance LDPC soft decoding device, which can implement the above-mentioned low-complexity and high-performance LDPC soft decoding implementation method, and includes:

[0018] A control state machine, an input / output control module, a node information operation module, a second-minimum value estimation mapping module, and an information storage module;

[0019] The control state machine is used to statically configure decoding parameters such as matrix parameters and the maximum number of iterations;

[0020] The input / output control module is used to control the streaming transmission of the decoding result and the input channel LLR value;

[0021] The node information operation module includes a check node operation unit, a variable node information minimum value update operation unit, and an APP operation unit; the check node operation unit is used to calculate the information from the check node to the variable node, the variable node information minimum value update operation unit is used to update the information from the calculation unit to the check node, and the APP operation unit uses an adder summation operation to obtain the posterior probability

[0022] The second minimum value estimation mapping module is used for estimating the second minimum value of variable nodes, and includes a variable node second minimum value parameter mapping unit and a variable node second minimum value estimation calculation unit; the variable node second minimum value parameter mapping unit is used for mapping and generating a variable node second minimum value estimation parameter es_min2_idx, and the variable node second minimum value estimation calculation unit is used for estimating and calculating the second minimum value of variable node information.

[0023] The information storage module includes an LLR storage RAM, a variable node information storage RAM, a variable node information minimum value storage register, a variable node information minimum value address register, and a check node sign bit RAM.

[0024] Further, the mapping in the second minimum value estimation calculation unit of the device has been block-divided and simplified, and the hardware can be built by combinational logic NAND gates without a data selector.

[0025] Further, the device adopts a column-by-column hierarchical pipelined decoding architecture.

[0026] By adopting the column-by-column hierarchical decoding design, the present invention enables the update of check node information and the update of variable node information to be completed in two clock cycles and can be pipelined during the implementation of the decoder, solving the memory conflict problem and improving the throughput. In addition, by adopting the method of estimating the second minimum value of variable node information by mapping, the storage data scale of the check node row information register is significantly reduced with the addition of a small amount of hardware resources, effectively reducing the hardware implementation complexity. Description of the Drawings

[0027] Figure 1 It is a schematic flow chart of a method for implementing low-complexity and high-performance LDPC soft decoding according to the present invention;

[0028] Figure 2 It is a low-complexity and high-performance LDPC soft decoding device according to the present invention;

[0029] Figure 3 It is a schematic diagram of column-by-column decoding layering according to the present invention;

[0030] Figure 4 It is a schematic flow chart of node information update according to the present invention;

[0031] Figure 5 It is a double-mapping estimation flow chart of second minimum value update according to the present invention. Detailed Embodiments

[0032] To make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention.

[0033] Embodiment 1

[0034] As Figure 1 shown, in an embodiment of the present invention, a method for implementing low-complexity and high-performance LDPC soft decoding is provided. The method includes the following steps:

[0035] Step S1. Initialize the matrix row-column parameters and the variable node information second-minimum value mapping table according to the decoding matrix H, which specifically includes the following steps:

[0036] Initialize the number of rows of the decoding matrix as m, the number of columns of the decoding matrix as n, the maximum number of decoding iterations as iter_max, initialize the second-minimum value estimation mapping table T for check node update, initialize the information q transmitted from the variable node to the check node i,j of the second-minimum value estimation parameter es_min2_idx, and record the iteration number of each iteration as iter.

[0037] Further, the mapping table T in the step S1 can be as shown in Table 1:

[0038]

[0039] Among them, for a 6*22 (QC = 384) matrix, QC is the parallelism, es_min2_idx can be set as a 2-bit mapping parameter flag, sw is the syndrome weight, and a total of five parameters in four ranges, namely sw_min, sw_1, sw_2, sw_3, and sw_max, are selected for mapping. The optional parameters of the typical values of the 6*22 (QC = 384) mapping table T are shown in Table 2:

[0040]

[0041] The above parameters are all pre-optimized through Monte Carlo optimization and then determined in combination with the convenience of hardware implementation.

[0042] Step S2. Initialize the information q transmitted from the variable node to the check node i,j 、qi,j The minimum value min1, the column number min1_idx where the minimum value is located, and the second minimum value estimation parameter es_min2_idx of the variable node information, specifically including the following steps:

[0043] Calculate the LLR value L(y) based on the 0, 1 hard decoding information read multiple times. The formula for L(y) is as follows:

[0044]

[0045] y = (L(y0), L(y1),..., L(y n-1 ))

[0046] y is the codeword received by the decoder. Initialize q i,j , q i,j Assign the LLR value of each codeword to the information transmitted from the variable node to the check node, that is, when the i-th row and the j-th column in the check matrix are valid blocks, q i,j = L(y j ). Initialize the minimum value of the variable node information qi,j as the LLR value of the first column of the matrix, that is, min1 = L(y0), initialize the address column number min1_idx where the minimum value is located as 0, and initialize the second minimum value estimation parameter of the variable node information as 0x03.

[0047] Step S3. The node information update unit performs calculation iterations based on q i,j , min1, and the second minimum value mapping estimation value of the variable node information to complete the update of the node information. The node information includes variable node information and check node information and calculates the posterior probability, specifically including the following steps:

[0048] S31. The matrix uses a quasi-cyclic low-density parity-check code (QC-LDPC), and the decoding is performed layer by layer by column. Each iteration starts from the first column layer until the last column layer, and each column layer is the number of columns of a QC block; update each valid check node in the current column according to min1, γ i,j represents the check node information transmitted from the j-th row check node to the i-th row variable node in the check matrix, and the formula for γ i,j is as follows:

[0049]

[0050]

[0051] Among them, N c(i)\(j\) represents the set of variables connected to the \(i\)-th check node except the \(j\)-th variable node; \(es\_min2(min1, es\_min2\_idx)\) is the estimated value of the second smallest value of the variable node, which is calculated by combinational logic mapping according to the estimated parameter \(es\_min2\_idx\) of the second smallest value of the variable node and \(min1\), and \(sgn(q i,j' ) represents the exclusive OR calculation of the sign bit of the original check node and the sign bit of the variable node, and the sign bit of the variable node is obtained by reading the RAM.

[0052] Used to calculate the check node information \(\gamma i,j The normalization parameter \(\alpha\) used can be obtained by multiplication, addition and shifting through 2-bit information, and the obtained \(\alpha\) can be selected as 0.125, 0.375, 0.875 to reduce resource consumption.

[0053] The estimation process of the estimated value of the second smallest value can be obtained by the linear combination of \(es\_min2\_idx\) and \(min1\), and Table 3 gives the preferred values in the \(6\times22\) parity-check matrix.

[0054]

[0055] S32. According to the check node information \(\gamma\) obtained in S31 i,j For the information \(q\) of each variable node in this column i,j Perform an update, and the formula for \(q i,j is expressed as follows:

[0056]

[0057] S33. Compare the variable node information \(q\) obtained in S32 i,j with \(min1\). If \(|q i,j | \lt min1\), then update \(min1 = |q i,j | and \(min1\_idx = j\).

[0058] After the information is updated in step S33, a cyclic shift is also required, that is, according to the globally configured cyclic shift value, the row information \(min1\), \(min1\_idx\) updated for the entire column layer of the current check node is shifted so that it can be directly used by the next column layer. The globally configured cyclic shift value is globally configured according to the decoding matrix information.

[0059] S34. Calculate the a posteriori probability (APP) of the codeword. The APP of each bit of each codeword is \(Q j , and the formula for \(Q j is expressed as follows:

[0060]

[0061] Step S4. Perform a hard decision on the posterior probability APP obtained in step S34, and update the speculated codeword and check the codeword. When the check is successful, output the decoding result.

[0062] c j is the speculated codeword at the j-th bit position, and the formula for c j is expressed as follows:

[0063]

[0064] In addition, it is also necessary to update the second smallest value estimation parameter es_min2_idx. Specifically, after each iteration is completed, calculate the number of non-zero parity equations in the syndrome of all hard decision results that satisfy the parity check matrix and denote it as the parity check weight sw. According to the size range of sw shown in Table 1, look up the mapping table T to obtain the second smallest value estimation parameter es_min2_idx, and the parameter is used for the next decoding iteration.

[0065] When the parity check weight is 0, that is, when sw = 0, it is regarded as a successful check, and then the speculated codeword is output as the decoding result; if the check fails, then determine whether iter is equal to iter_max. If the maximum decoding iteration number is reached, terminate the decoding and report decoding failure. If the maximum decoding number is not reached, return to step S3 to continue the calculation iteration. The maximum decoding iteration number can be selected as 24.

[0066] Embodiment 2

[0067] Refer to Figure 2 , this embodiment provides a low-complexity and high-performance LDPC soft decoding device, and the device adopts a low-complexity and high-performance LDPC soft decoding implementation method in Embodiment 1.

[0068] The device adopts a column-by-column hierarchical pipelined decoding architecture.

[0069] A control state machine, an input / output control module, a node information operation module, a second smallest value estimation mapping module, and an information storage module.

[0070] The control state machine is used to statically configure decoding parameters such as matrix parameters, maximum iteration number, global loop value, etc. The control state machine provides a handshake signal for flow control of the input / output module under the drive of the check information in the check module, ensuring that the device can cache two codewords simultaneously and perform decoding polling. The information storage module includes an LLR storage RAM, a variable node information storage RAM, a variable node information minimum value storage register, a variable node information minimum value address register, and a parity check node sign bit RAM.

[0071] The minimum value storage register and the minimum value address register of the variable node information are used to store the minimum value of the variable node and the address where the minimum value is located. Initialize the minimum value of the current check node row used for check node update as the LLR value of the first column, that is, min1 = L(y0), and initialize the address column number min1_idx where the minimum value is located to 0.

[0072] Preferably, min1 is stored in a register with a 3-bit width, and min1_idx is stored in a register with a 5-bit width, which reduces the consumption of hardware resources while ensuring the error correction performance. The input / output control module is used to control the streaming transmission of the decoding result and the input channel LLR value. The module includes a handshake mechanism. When both BRAMs in the LLR storage RAM are full and there is no decoding result output, it can autonomously apply backpressure to the upper-level input until a codeword is decoded and then continue to receive external input.

[0073] The node information operation module includes a check node operation unit, a variable node information minimum value update operation unit, and an APP operation unit. The check node operation unit is used to calculate the information from the check node to the variable node, and the variable node information minimum value update operation unit is used to update the calculation unit to the check node information.

[0074] Calculate the information γ from the check node to the variable node using the min1 value stored in the variable node information minimum value storage register, the second smallest value estimated by the second smallest value estimation operation unit, the updated sign bit stored in the check node sign bit RAM, and the normalization parameter α i,j The variable node information minimum value update operation unit is used to compare the information q passed to the check node read from the variable node RAM i,j with the size relationship of min1 in the register, and update min1 and min1_idx based on this. If |q i,j | < min1, then update min1 = |q i,j |, min1_idx = j.

[0075] A cyclic shift module is further provided after the variable node information minimum value update operation unit. The cyclic shift module cyclically shifts the updated min1 and min1_idx according to the global cyclic value of this row and then writes them back to the min1 and min1_idx registers for use by the check node operation of the next valid block in this row. Among them, the global cyclic value is globally statically configured by the control state machine. Preferably, the matrix uses row-fixed offset, and only the static cyclic value of the same matrix row needs to be configured, without a shift register, which can significantly reduce the consumption of hardware resources.

[0076] The APP operation unit uses an adder to sum the information γ from all valid check nodes to variable nodes in the current column layer i,j and the LLR to obtain APP, specifically as follows: Subsequently, Q j subtracts γ from all nodes in this column layer i,j to obtain and writes q i,j into the variable node information RAM for use by min1 to update.

[0077] A check module is further provided after the APP operation unit. The check module extracts the sign bit of Q j calculated by the APP operation unit as a speculative codeword and stores it in the decoding result RAM, and checks the speculative codeword. When the speculative codeword satisfies that is, when all check equations are satisfied, the check module reports the decoding success information of the control status, and waits for the input / output control module to read the decoding result RAM and output the decoding result.

[0078] Preferably, the check module can perform a check after each iteration, or can perform a check when the decoding of each column layer is completed. When the check is successful in a certain column layer, it directly reports decoding success without completing a full iteration process, reducing the number of iterations and improving the hardware throughput rate.

[0079] The second smallest value estimation mapping module includes a variable node second smallest value parameter mapping unit and a variable node second smallest value estimation calculation unit. The variable node second smallest value parameter mapping unit is used to map and generate the variable node second smallest value estimation parameter es_min2_idx. The variable node second smallest value estimation calculation unit is used to estimate and calculate the second smallest value of the variable node information.

[0080] The variable node second smallest value estimation calculation unit estimates the second smallest value according to es_min2_idx and min1 output by the variable node second smallest value parameter mapping unit. Preferably, the estimation method can use the linear mapping estimation shown in Table 3. Since the mapping has been block-divided and simplified, the hardware can be built by combinational logic NAND gates without a data selector. Compared with the method of storing the second smallest value and the address in registers in the traditional normalized min-sum algorithm, the hardware complexity is significantly reduced.

[0081] Embodiment 3

[0082] Based on Embodiments 1 and 2, this embodiment further illustrates the column-layer pipelined decoding architecture of the device and the beneficial effect of this architecture on optimizing the throughput rate.

[0083] See Figure 3, the device completes decoding according to a column-layered decoding architecture. The matrix is layered by n columns, and the execution between layers is serial, while the decoding of m rows within each layer is parallel.

[0084] Preferably, only instantiating the maximum column weight number of decoding engines is required to complete the parallel operation. The maximum column weight represents the number of valid blocks in the column with the most valid blocks among all column layers of the matrix. See Figure 3 As shown, the black part represents valid blocks, and the blank part represents invalid blocks. The maximum column weight in the illustrated matrix is 4, that is, instantiating 4 decoding engines can complete the parallel execution of m rows.

[0085] Figure 3 It also shows the matrix structure distribution in a valid block. The valid block conforms to the quasi-cyclic code characteristic (QC-LDPC), and the information transfer between column layers can be completed through the cyclic shift module.

[0086] Figure 4 It illustrates the timing of the pipelined architecture for column-layer decoding of the device. The decoding of one column layer includes four steps: calculating the information from the check node to the variable node, updating the row minimum value information, calculating the APP and the information from the variable node to the check node, and writing back the variable node information. Since the APP calculation needs to sum up the information of all check nodes in the same column layer and subtract the current check node information to obtain the variable node information and write it back. To reduce the risk of timing convergence, the write-back and calculation are carried out in two clock cycles, and all decoding and information update of one column layer can be completed in three clock cycles. Therefore, if the latest variable node information cannot be obtained in the second clock cycle of the next column layer decoding, there may be a one-cycle delay. After the decoding performance simulation, at the same raw bit error probability (RaW Bit Error Ratio, RBER), the uncorrectable bit error rate only decreases by 0.2%, which can be ignored.

[0087] Preferably, ensuring that the valid blocks in one row of the matrix are not continuous can avoid the impact of one-cycle delay on the decoding performance.

[0088] Through the above analysis, the decoding architecture of column-layer decoding can ensure that under the premise of pipelined operation between column layers, it will not cause an unacceptable impact on the decoding performance. That is to say, for the matrix codeword with n column layers, only n + 2 clock cycles are required to complete the decoding of the entire codeword, which greatly improves the throughput of the decoding device.

[0089] Preferably, based on the pipelined architecture of column-layer decoding, Figure 5 a method for estimating the second smallest value in a double mapping form is provided. By Figure 4It can be seen that the use and comparison update of the second smallest value are completed in two clock cycles respectively. Therefore, two different mapping rules can be adopted for the estimation of the second smallest value. Performance simulation shows that when calculating the parity check information, adopting a simplified mapping form has a minimal impact on the error correction ability, but can save half of the hardware consumption for mapping calculation. Table 4 shows the comparison of hardware resource consumption under different randomized mapping strategies.

[0090]

[0091] In the table, LUT represents the lookup table, BRAM represents the block RAM, and FF represents the flip-flop. The following results can be obtained from the table:

[0092] In a 6*22 (QC = 384) matrix, where QC is the parallelism, under the single-mapping random estimation method, the LUT decreases by 18.1% and the FF decreases by 14%; under the double-mapping random estimation method, the LUT decreases by 28.6% and the FF decreases by 25.1%.

[0093] In summary, the present invention adopts a column-layered decoding design, enabling the update of the parity check node information and the variable node information to be completed in two clock cycles and allowing pipelining during the implementation of the decoder, thus solving the memory conflict problem and improving the throughput. In addition, by adopting the method of estimating the second smallest value of the variable node information, the storage data scale of the parity check node row information register is significantly reduced with the addition of a small amount of hardware resources, effectively reducing the complexity of hardware implementation.

[0094] The above are only the preferred embodiments of the present invention, and do not limit the protection scope of the present invention. Any equivalent structural transformation made using the content of the specification and drawings of the present invention under the concept of the present invention, or directly / indirectly applied to other related technical fields, shall be included within the patent protection scope of the present invention.

Claims

1. A method for implementing low-complexity and high-performance LDPC soft decoding, characterized in that, The method is a column - hierarchical random estimation and normalized min - sum algorithm decoding method, including the following steps: Step S1. Initialize the matrix row - column parameters and the variable - node information second - minimum value mapping table according to the decoding matrix H; Step S2. Initialize the information q transmitted from the variable nodes to the check nodes i,j , q i,j 's minimum value min1, the column number min1_idx where the minimum value is located, and the second smallest value estimation parameter es_min2_idx of the variable node information Step S3. The node information update unit performs iterative calculations based on q i,j , min1, and the estimated value of the second smallest value mapping of the variable node information to complete the update of the node information and calculate the posterior probability; Step S4. Perform a hard decision on the posterior probability result obtained in step S3, and update the hypothesized codeword to and check the codeword. When the check is successful, output the decoding result.

2. The method according to claim 1, characterized in that, The specific steps of Step S3 are as follows: S31. The matrix uses a quasi-cyclic low-density parity-check code, and the decoding is performed in a layered manner column by column. Each iteration starts from the first column layer until the last column layer, and each column layer has the number of columns of a QC block; each valid check node in the current column is updated according to min1, γ i,j represents the check node information transmitted from the check node in the j-th row to the variable node in the i-th row in the check matrix, γ i,j The formula for is expressed as follows: Among them, N c (i)\j represents the set of variables connected to the i-th check node except for the j-th variable node; es_min2(min1, es_min2_idx) is the estimated value of the second smallest value of the variable node, sgn(q i,j' ) represents the exclusive OR calculation of the sign bit of the original check node and the sign bit of the variable node; γ, the check node information obtained according to S31 i,j For the information q of each variable node in this column i,j Perform an update, and the formula for q i,j is expressed as follows: S33. The variable node information q obtained in S32 i,j is compared with min1. If |q i,j | < min1, then update min1 = |q i,j | and min1_idx = j; S34. Calculate the posterior probability of the codewords. The posterior probability of each bit of each codeword is Q j , Q j The formula for it is as follows:

3. The method according to claim 2, wherein The estimated value es_min2(min1, es_min2_idx) of the variable - node second - minimum value is obtained through combinational - logic mapping according to the variable - node second - minimum value estimation parameter es_min2_idx and min1.

4. The method according to claim 2, wherein In Step S4, hard decision is made on the posterior probability APP obtained in Step S34, the speculated codeword is updated and the codeword is verified. When the verification is successful, the decoding result is output.

5. The method according to claim 1, wherein Step S4 also includes updating the second - minimum value estimation parameter es_min2_idx. The specific steps are as follows: After each iteration, calculate the number of non - zero parity - check equations in the syndrome of the parity - check matrix that are satisfied by all the hard - decision results. The number of equations is denoted as the parity - check weight. According to the size range of the parity - check weight, the second - minimum value estimation parameter es_min2_idx is obtained by referring to the mapping table. This parameter is used for the next decoding iteration.

6. According to the method described in claim 2, after the information is updated in Step S33, there is also a cyclic - shift unit. According to the globally configured cyclic - shift value, the row information min1 and min1_idx of the entire column - layer update of the current parity - check node are shifted so that the next column - layer can directly use them.

7. A low-complexity and high-performance LDPC soft decoding device, characterized in that, A device capable of implementing the method according to any one of claims 1 to 6, the device includes: A control state machine, an input / output control module, a node - information operation module, a second - minimum value estimation mapping module, and an information storage module; The control state machine is used to statically configure decoding parameters such as matrix parameters and the maximum number of iterations; The input / output control module is used to control the streaming transmission of the decoding result and the input channel LLR value; The node - information operation module includes a parity - check node operation unit, a variable - node information minimum - value update operation unit, and an APP operation unit. The parity - check node operation unit is used to calculate the information from the parity - check node to the variable node. The variable - node information minimum - value update operation unit is used to update the information from the calculation unit to the parity - check node. The APP operation unit uses an adder summation operation to obtain the posterior probability; The second - minimum value estimation mapping module is used for the estimation of the variable - node second - minimum value, including a variable - node second - minimum value parameter mapping unit and a variable - node second - minimum value estimation calculation unit. The variable - node second - minimum value parameter mapping unit is used to map and generate the variable - node second - minimum value estimation parameter es_min2_idx. The variable - node second - minimum value estimation calculation unit is used to estimate and calculate the second - minimum value of the variable - node information; The information storage module includes an LLR storage RAM, a variable - node information storage RAM, a variable - node information minimum - value storage register, a variable - node information minimum - value address register, and a parity - check node sign - bit RAM.

8. The device according to claim 7, characterized in that, The mapping in the second - minimum value estimation calculation unit has been block - divided and simplified. The hardware can be built with combinational - logic NAND gates and does not require a data selector.

9. The device according to claim 7, wherein The device adopts a column - hierarchical pipelined decoding architecture.

Images