QC-LDPC code check matrix construction method and device, medium and product

Abstract

The invention discloses a QC-LDPC code check matrix construction method and device, a medium and a product, and relates to the technical field of channel coding, and the method comprises the steps: firstly generating an initial check matrix without four rings; secondly, screening out a target column which is easy to cause decoding oscillation based on pre-decoding, and reducing non-zero items with the maximum number of six rings to generate an intermediate check matrix; and finally, optimizing six-ring distribution of the intermediate matrix column by column, and generating a target check matrix with mixed column weight. In order to solve the problem of decoding error leveling caused by short rings (four rings and six rings) in a QC-LDPC code with high code rate and long code word, the check matrix structure is dynamically optimized through a three-step construction method, the number of harmful short rings in the check matrix is remarkably reduced, the decoding performance is improved, and the error leveling is reduced.

Description

Technical Field

[0001] This application relates to the technical field of channel coding, and in particular, to a method, device, medium, and product for constructing a parity-check matrix of a QC-LDPC code. Background Art

[0002] Quasi-cyclic low-density parity-check (QC-LDPC) codes have been widely used in 5G communications, satellite communications, and storage systems due to their regular cyclic structure, low coding complexity, and performance close to the Shannon limit. However, in the scenarios of high code rate and long codewords, short cycles (especially four-cycles and six-cycles) in the parity-check matrix will form trap sets, causing the iterative decoding algorithm to fall into a local optimum and resulting in the error floor phenomenon. Existing technologies usually eliminate four-cycles through algebraic construction or random search, but it is difficult to balance the optimization of six-cycles under the constraint of high code rate, and there is a lack of dynamic positioning ability for trap sets, resulting in limited decoding performance.

[0003] Therefore, there is an urgent need for a method for constructing a parity-check matrix of a high-code-rate QC-LDPC code, which can effectively eliminate harmful short cycles while maintaining a high code rate, and optimize the matrix structure to reduce the influence of trap sets. Summary of the Invention

[0004] This application provides a method, device, medium, and product for constructing a parity-check matrix of a QC-LDPC code to solve the problems of short-cycle residue and difficult accurate positioning of trap sets in the high-code-rate scenario of the existing solutions.

[0005] This application provides a method for constructing a parity-check matrix of a QC-LDPC code, and the method includes: Generating an initial parity-check matrix; the initial parity-check matrix has no four-cycle structure; Performing pre-decoding on the initial parity-check matrix, screening out target columns whose oscillation frequency exceeds a preset threshold during the decoding process, and eliminating the non-zero terms with the largest number of six-cycles in the target columns to generate an intermediate parity-check matrix; Eliminating the non-zero terms with the largest number of six-cycles in the intermediate parity-check matrix column by column to generate a target parity-check matrix.

[0006] This application also provides an electronic device, including: a memory for storing a computer program; a processor for implementing the steps of any of the above methods for constructing a parity-check matrix of a QC-LDPC code when executing the computer program.

[0007] This application also provides a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed by a processor, the steps of any of the above methods for constructing a parity-check matrix of a QC-LDPC code are implemented.

[0008] The present application also provides a computer program product, including a computer program which, when executed by a processor, implements the steps of any of the above QC-LDPC code parity-check matrix construction methods.

[0009] Through the present application, the three-step progressive construction method systematically optimizes the performance of the QC-LDPC code parity-check matrix. An initial parity-check matrix without a four-cycle structure is generated, directly avoiding the local decoding trap set caused by four-cycles, reducing the error floor phenomenon in iterative decoding, and improving the error correction reliability in the initial stage. The construction of the initial parity-check matrix fundamentally avoids the interference of four-cycles on the decoding stability, providing a high-reliability basis for subsequent optimization. The pre-decoding filters the target columns and reduces the non-zero terms with the largest number of six-cycles. By simulating decoding to locate the problem columns that are actually prone to oscillation, the dense regions of harmful six-cycles in the target columns are specifically eliminated, optimizing the local error correction ability. The key columns that are prone to instability in actual decoding are accurately located, avoiding the waste of resources caused by blind global optimization in traditional methods. By reducing the non-zero terms with the largest number of six-cycles in the target columns (such as setting the corresponding circulant permutation matrix to zero or adjusting the shift value), the local six-cycle density is significantly reduced, generating an intermediate parity-check matrix. This operation weakens the influence of the local trap set in stages while retaining most of the error correction ability of the original matrix, providing a smooth transition for the final optimization. The six-cycle non-zero terms of the intermediate parity-check matrix are eliminated column by column, systematically reducing the total number of global six-cycles, avoiding the formation of cascaded trap sets by residual six-cycles, thereby comprehensively improving the decoding convergence performance of the target parity-check matrix and reducing the bit error rate in the high signal-to-noise ratio region. The finally generated target parity-check matrix has both the characteristics of no four-cycles and low six-cycle density, significantly suppressing the error floor phenomenon while maintaining the encoding efficiency of the quasi-cyclic structure. Through three-step progressive optimization, the present application lays the foundation for decoding stability by eliminating four-cycles in the first stage, realizes precise optimization through pre-decoding dynamic positioning and local six-cycle reduction in the second stage, and completely eliminates residual six-cycles through global column-by-column cleaning in the third stage. This method systematically solves the trap set problem caused by short cycles in high code rate scenarios, avoiding the defects of incomplete short cycle elimination and unbalanced optimization resource allocation in traditional schemes, while maintaining the low complexity characteristics of matrix construction and encoding, providing high-reliability and low-bit-error-rate encoding support for high-speed communication systems. Description of the Drawings

[0010] In order to more clearly illustrate the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0011] Figure 1 It is a schematic flowchart of a method for constructing a QC-LDPC code parity-check matrix provided by an embodiment of the present application; Figure 2 Schematic flow chart of a method for constructing a check matrix of a high code rate long codeword QC-LDPC code provided by an embodiment of the present application; Figure 3 Schematic diagram of the format of the initial check matrix H1 provided by an embodiment of the present application; Figure 4 Schematic flow chart of a method for performing secondary column weight elimination on an intermediate check matrix provided by an embodiment of the present application; Figure 5 Schematic diagram of the total number of six-cycles of three check matrices provided by an embodiment of the present application; Figure 6 Schematic diagram of the performance test results of three check matrices provided by an embodiment of the present application; Figure 7 Schematic diagram of the decoding simulation results of three check matrices provided by an embodiment of the present application; Figure 8 Schematic structural diagram of a QC-LDPC code check matrix construction device provided by an embodiment of the present application; Figure 9 Schematic structural diagram of a computer device provided by an embodiment of the present application. Detailed implementation manners

[0012] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present application.

[0013] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variation thereof are intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0014] In order to enable those skilled in the art of the present technology to better understand the solution of the present application, the present application will be further described in detail below in conjunction with the accompanying drawings and specific implementation manners.

[0015] Combined with the specific application environment architecture or specific hardware architecture on which the execution of the QC-LDPC code check matrix construction method depends, the specific application environment architecture or specific hardware architecture is described herein.

[0016] Quasi-cyclic low-density parity-check (QC-LDPC) codes have become the core coding scheme for 5G communication, satellite communication, and storage systems due to their regular cyclic structure, performance close to the Shannon limit, and efficient hardware implementation capabilities. However, in application scenarios with high code rates and long codewords, short cycles (such as four-cycles and six-cycles) in the parity-check matrix will form trapsets, causing the iterative decoding algorithm to fall into a local optimal solution and triggering the error floor phenomenon. Existing technologies usually eliminate the four-cycle structure through algebraic construction or random search methods, but it is difficult to balance the optimization of six-cycles under high code rate constraints, and they lack the ability to dynamically locate trapsets. In addition, traditional methods often adopt a single column weight design, which cannot balance the error correction capabilities and complexities of different regions, resulting in limited decoding performance in the high signal-to-noise ratio region and making it difficult to meet the stringent requirements of high-speed communication systems for low bit error rates.

[0017] In existing QC-LDPC code construction schemes, progressive edge growth (PEG) and random methods are widely used to generate sparse parity-check matrices. However, the elimination of short cycles in these methods is mostly static rule design, which is difficult to adapt to dynamic channel conditions. For example, some schemes avoid short cycles by fixing the shift value or constraint formula, but this will discard the randomness of the matrix and reduce the error correction potential; although some other schemes introduce a decoding feedback mechanism, they lack targeted optimization of harmful short cycles, resulting in resource waste and performance bottlenecks. Especially in high code rate scenarios, the contradiction between the sparsity requirement of the parity-check matrix and the elimination of short cycles is further exacerbated, and it is difficult for existing technologies to systematically eliminate trapsets while maintaining a high code rate.

[0018] Therefore, there is an urgent need for a method for constructing a parity-check matrix of high code rate QC-LDPC codes, which can dynamically locate and optimize the six-cycle dense region on the basis of eliminating four-cycles, and at the same time balance the error correction capabilities of different regions through differential design. This method needs to combine data-driven decoding simulation and a global column-by-column optimization strategy to significantly reduce the error floor and adapt to the high-performance requirements in multi-noise environments, so as to provide a highly reliable and low-complexity coding solution for high-speed communication systems.

[0019] Therefore, the embodiments of this application provide a method for constructing a parity-check matrix of QC-LDPC codes, and the method is described in detail in combination with the execution process of the method for constructing a parity-check matrix of QC-LDPC codes.

[0020] First, the terms involved in this application are introduced.

[0021] LDPC (Low Density Parity Check Code): Low Density Parity Check Code; QC-LDPC (Quasi-cyclic LDPC): Quasi-cyclic Low Density Parity Check Code; PEG (Progressive Edge-Growth): Progressive Edge-Growth; AWGN (Additive White Gaussian Noise): Additive White Gaussian Noise; LLR value (LogLikelihood Ratio): Logarithmic Likelihood Ratio; RLMS (Row Layered Normalized Min-Sum): Row Layered Normalized Min-Sum.

[0022] Embodiments of this application provide a method for constructing a QC-LDPC code check matrix. The specific process of this method is as Figure 1 shown, and specifically includes the following steps.

[0023] S101. Generate an initial check matrix.

[0024] Specifically, in step S101, the initial check matrix is the basic matrix of the quasi-cyclic low density parity check (QC-LDPC) code, which is composed of a cyclic permutation matrix and an all-zero matrix. Its structure follows the quasi-cyclic property, that is, sub-matrix blocks are generated by cyclic shift, which is convenient for hardware encoding and decoding implementation. This basic matrix is usually generated by an algebraic construction method (such as based on a finite field) or a random method to ensure that the matrix is sparse and meets the code rate requirements.

[0025] The initial check matrix has no four-cycle structure. Among them, a four-cycle refers to a closed loop formed by four variable nodes and four check nodes in the check matrix. For example, if there is a rectangular structure composed of four non-zero elements, a four-cycle is formed.

[0026] S102. Perform pre-decoding on the initial check matrix, screen out the target columns whose oscillation frequency exceeds the preset threshold during the decoding process, and eliminate the non-zero terms with the largest number of six-cycles in the target columns to generate an intermediate check matrix.

[0027] Specifically, in step S102, pre-decoding refers to simulating the actual decoding process before formal decoding, injecting errors and iteratively decoding, and observing the decoding behavior of each column in the matrix. It is used to identify the "problem columns" that are prone to cause decoding oscillation and provide data support for optimization.

[0028] The oscillation frequency refers to the number of times the soft information (such as the logarithmic likelihood ratio LLR) of the variable node repeatedly flips during iterative decoding. For example, if the LLR value of a certain column undergoes 5 sign flips in 10 iterations, its oscillation frequency is 50%.

[0029] The preset threshold is the critical value of the oscillation frequency set in advance (such as 30%). If the oscillation frequency of a certain column exceeds this value, it is marked as the "target column" to be optimized. The target column is selected by statistically analyzing the oscillation frequencies of all columns, and several columns with the highest values are chosen as the optimization objects.

[0030] A 6-cycle is a closed loop formed by six variable nodes and six check nodes. Its existence will reduce the decoding performance, but the impact is weaker than that of a 4-cycle. For each non-zero item in the target column, count the number of 6-cycles it participates in, select the non-zero item with the greatest contribution, and set the corresponding cyclic permutation matrix to zero or replace the shift value.

[0031] By eliminating the non-zero items of the 6-cycles in the target column, an optimized intermediate matrix is obtained, and its local 6-cycle density is significantly reduced.

[0032] S103. Eliminate the non-zero item with the largest number of 6-cycles in the intermediate check matrix column by column to generate the target check matrix.

[0033] Specifically, in step S103, column-by-column elimination means that for each column of the intermediate matrix, count the number of 6-cycles participated by all its non-zero items; select the non-zero item with the largest number of 6-cycles in each column for elimination (such as setting it to zero or adjusting the shift value). Systematically reduce the total number of global 6-cycles to avoid the formation of cascaded trap sets by residual 6-cycles.

[0034] The finally obtained target check matrix has no 4-cycle structure (guaranteed by step S101); the local and global 6-cycle densities are greatly reduced (achieved by step S102 and step S103); the mixed column weight design (part of the column weight is reduced, and part of the original column weight is retained) balances the error correction ability and complexity.

[0035] The QC-LDPC code check matrix construction method provided in the embodiment of the present application systematically optimizes the performance of the QC-LDPC code check matrix through a three-step progressive construction method. Generate an initial check matrix without a four-ring structure, directly avoid the local decoding trap set caused by the four-ring, reduce the error flattening phenomenon in iterative decoding, and improve the error correction reliability in the initial stage. The construction of the initial check matrix fundamentally avoids the interference of the four-ring on the decoding stability, providing a high reliability basis for subsequent optimization. Pre-decoding screens the target column and eliminates the non-zero items with the largest number of six rings. Through simulated decoding, locate the problem column that is actually prone to oscillation, and specifically eliminate the dense area of ​​harmful six rings in the target column to optimize the local error correction capability. Accurately locate the key columns that are prone to instability in actual decoding, and avoid the waste of resources caused by blind global optimization in traditional methods. By eliminating the non-zero items with the largest number of six rings in the target column (such as setting the corresponding cyclic permutation matrix to zero or adjusting the shift value), the local six-ring density is significantly reduced, and an intermediate check matrix is ​​generated. This operation, while retaining most of the error correction capabilities of the original matrix, weakens the impact of local trap sets in stages, providing a smooth transition for the final optimization. Eliminate the six-ring non-zero items of the intermediate check matrix column by column, systematically reduce the total number of global six rings, and avoid the residual six rings from forming a cascade trap set, thereby comprehensively improving the decoding convergence performance of the target check matrix and reducing the bit error rate in high signal-to-noise ratio areas. The target check matrix finally generated has both the characteristics of no four rings and low six-ring density, significantly suppressing the error flattening phenomenon, while maintaining the coding efficiency of the quasi-cyclic structure. This application uses a three-step progressive optimization. In the first stage, the foundation for decoding stability is laid through the elimination of four rings. In the second stage, precise optimization is achieved through pre-decoding dynamic positioning and local six-ring reduction. In the final stage, the residual six rings are completely eliminated through global column-by-column cleaning. This method systematically solves the trap set problem caused by short rings in high-code rate scenarios, avoids the defects of incomplete elimination of short rings and unbalanced optimization of resource allocation in traditional solutions, and maintains the low complexity characteristics of matrix construction and coding, providing high-reliability and low-bit-error-rate coding support for high-speed communication systems.

[0036] In an optional implementation, an initial check matrix is ​​generated, including: generating an initial index matrix of a QC-LDPC code based on a progressive edge growth algorithm or a random method; determining a four-ring structure in the initial index matrix by a four-ring detection formula, and adjusting a shift value of a circulant permutation matrix in the initial index matrix to eliminate the four-ring, thereby obtaining an index matrix; replacing each non-zero element in the index matrix with a circulant permutation matrix, and replacing zero elements in the index matrix with an all-zero matrix; the shift value of the circulant permutation matrix is ​​determined by the non-zero element value in the index matrix; and combining all replaced circulant permutation matrices and all-zero matrices to obtain an initial check matrix.

[0037] Actively detect and eliminate the four-loop structure through the four-loop detection formula, directly avoid the local decoding trap set caused by the four-loop, prevent the iterative decoding from falling into the "deadlock" state, and improve the reliability of the initial parity-check matrix. At the same time, replace the numbers in the index matrix with circulant permutation matrices / all-zero matrices, retain the quasi-cyclic characteristics of the QC-LDPC code, ensure that the encoding process can be efficiently implemented through shift registers, and reduce the hardware implementation complexity.

[0038] In an alternative embodiment, generate the initial index matrix of the QC-LDPC code based on the progressive edge growth algorithm or the random method, including: generating a seed matrix based on the progressive edge growth algorithm or the random method; the seed matrix is an invertible lower triangular matrix, and the diagonal elements of the seed matrix are generated by randomly adding the shift values of the circulant permutation matrix; randomly add the shift values of the circulant permutation matrix at the non-diagonal positions of the seed matrix, and avoid the generation of four-loops and six-loops through the four-loop detection formula and the six-loop detection formula to generate the initial index matrix.

[0039] The invertibility of the lower triangular seed matrix lays the foundation for the subsequent generation of an approximate lower triangular parity-check matrix, ensuring that the parity bits can be quickly generated through linear operations during encoding and avoiding complex matrix inversion operations. Randomly adding shift values at the non-diagonal positions not only ensures the random sparsity of the matrix (improving the error correction ability) but also constrains its structure through the detection formula, avoiding the risk of short loops introduced by randomness.

[0040] In an alternative embodiment, pre-decode the initial parity-check matrix and screen out the target columns whose oscillation frequencies exceed a preset threshold during the decoding process, including: performing simulated decoding on the initial parity-check matrix using the layered normalized min-sum algorithm; during the simulated decoding process, inject a preset number of random errors into the encoded codeword sequence and count the number of oscillations at each bit position during the iterative decoding; according to the comparison result between the number of oscillations and the preset threshold, screen out the target columns whose decoding oscillation frequencies exceed the threshold.

[0041] Simulate the actual channel noise by injecting random errors, combined with the iterative decoding process of the layered normalized min-sum algorithm, accurately reproduce the decoding oscillation phenomenon, and ensure that the selected target columns are highly correlated with the actual decoding bottlenecks. Use the number of oscillations as a quantitative indicator to locate the problem columns and avoid resource waste caused by subjective assumptions or global traversal.

[0042] In addition, when pre-decoding and screening the target columns, inject multiple preset types of error patterns into the encoded codeword sequence, including single-bit independent errors, double-bit consecutive errors, and multi-bit random distribution errors, and count the oscillation frequencies of each column under each error pattern; assign weight coefficients to each error type according to the channel characteristics, calculate the comprehensive oscillation frequency values of each column, and screen out the target columns whose comprehensive values exceed the preset threshold as the optimization objects.

[0043] Specifically, when counting the oscillation frequency, the following steps may further be included: Sequentially inject single-bit independent errors, double-bit consecutive errors, and multi-bit randomly distributed errors into the encoded codeword sequence; separately count the oscillation frequencies of each column under each error type; assign preset weight coefficients to the single-bit independent errors, double-bit consecutive errors, and multi-bit randomly distributed errors according to the noise characteristics of the target channel; based on the weight coefficients, calculate the comprehensive oscillation frequency value of each column by weighting; and screen out the target columns whose comprehensive oscillation frequency values exceed the preset threshold.

[0044] In an alternative embodiment, eliminating the non-zero term with the largest number of six-cycles in the target column to generate an intermediate parity-check matrix includes: for each non-zero term in the target column, counting the number of six-cycles each non-zero term participates in; replacing the cyclic permutation matrix corresponding to the non-zero term with the largest number of six-cycles with a all-zero matrix or a new cyclic shift value to obtain the intermediate parity-check matrix.

[0045] For the high-oscillation columns screened out by pre-decoding, preferentially reduce the non-zero term with the highest six-cycle density in it, directly weakening the contribution of this column to the trap set and avoiding the loss of error correction ability caused by the "one-size-fits-all" type of optimization. Generate an intermediate matrix by local reduction. While retaining most of the error correction ability of the original matrix, gradually reduce the number of six-cycles stage by stage to provide a smooth transition for global optimization.

[0046] In an alternative embodiment, eliminating the non-zero term with the largest number of six-cycles in each column of the intermediate parity-check matrix to generate the target parity-check matrix includes: constructing a six-cycle distribution matrix with the same dimension as the intermediate parity-check matrix and counting the number of six-cycles each non-zero term participates in; for each column of the intermediate parity-check matrix, selecting the non-zero term with the largest value in the six-cycle distribution matrix for reduction; repeating the reduction operation until the preset six-cycle elimination target is reached to obtain the target parity-check matrix.

[0047] Completely count the six-cycle participation degree of each non-zero term through the six-cycle distribution matrix, and reduce the maximum contribution term column by column to ensure the comprehensiveness and thoroughness of six-cycle elimination and avoid the formation of cascaded trap sets by residual six-cycles. Taking the preset six-cycle elimination target as the termination condition, flexibly adapt to different code lengths and code rate requirements, and balance the optimization depth and computational complexity.

[0048] In an alternative embodiment, after generating the target parity-check matrix, it further includes: dividing the blocks in the target parity-check matrix with a column weight lower than the preset threshold into independent data blocks, and independently generating outer code parity-check bits for each data block; combining the outer code parity-check bits with the encoding result of the target parity-check matrix to obtain a concatenated coding output.

[0049] Due to fewer connected check nodes, the low column weight blocks have weak fault tolerance. They are independently encoded by an outer code (such as BCH code) to form a dual protection mechanism of "LDPC global error correction + outer code local reinforcement", significantly reducing the bit error rate in critical areas. Only add outer code check bits to the low column weight blocks to avoid the redundant overhead of full matrix concatenation and maintain the high code rate advantage.

[0050] In an alternative embodiment, the outer code is a BCH code, and the code length of the outer code is determined by the data length of the blocks with column weight lower than a preset column weight threshold.

[0051] The strong error correction ability of the BCH code (such as single-bit error correction) precisely matches the fault tolerance requirements of the low column weight blocks, ensuring that the resource investment is proportional to the performance improvement. Adjust the BCH code length according to the data length of the low column weight blocks to avoid waste or insufficient coverage of check bits caused by a fixed code length.

[0052] In an alternative embodiment, the method further includes: in the decoding stage, use a layered normalized min-sum algorithm for iterative decoding, and extract the decision results of the blocks with column weight lower than the preset threshold after each layer of decoding; combine the decision results with the corresponding outer code check bits and input them into an outer code decoder for error correction; if the outer code decoder detects correctable errors, adjust the confidence information of the corresponding bits according to the outer code decoding results; the adjustment includes setting the log-likelihood ratio of the corresponding bits to the maximum or minimum value; after updating the confidence information, continue to perform the next layer of iterative decoding; when a preset condition is reached, it indicates successful decoding.

[0053] The outer code decoding results are directly fed back to the confidence information, breaking the local convergence deadlock of iterative decoding by forcibly setting the LLR extreme values (such as +7 / -7), and accelerating the propagation of correct information. Reduce the ineffective iterations caused by the repeated oscillation of the low column weight blocks, shorten the decoding convergence time, and improve real-time performance.

[0054] In an alternative embodiment, when a preset condition is reached, it indicates successful decoding, including: when the product of the target check matrix and the decision result is a zero vector or reaches a preset maximum number of iterations, it indicates successful decoding; if decoding fails, re-initialize the confidence information and restart the decoding process. Ensure the absolute reliability of the output codeword, and at the same time limit the maximum number of iterations to prevent infinite loops in case of poor channel conditions, and balance the decoding performance and computational resource consumption.

[0055] In an alternative embodiment, the column weight of the initial parity-check matrix is a first preset column weight; the first preset column weight is determined by the target code rate and the channel condition; and during the construction of the initial parity-check matrix, the column weight of each column is equal to the first preset column weight; the column weight of the intermediate parity-check matrix is a mixed structure of the first preset column weight and a second preset column weight; the second preset column weight is obtained by reducing the non-zero terms of the target column in the initial parity-check matrix; the column weight of the target parity-check matrix is a mixed structure of the first preset column weight, the second preset column weight, and a third preset column weight; the third preset column weight is obtained by reducing the non-zero terms of the intermediate parity-check matrix column by column; the distribution ratio of the mixed structure is determined based on the target code rate and the channel noise condition.

[0056] The high column weight region (such as column weight 5) enhances the error correction ability, and the low column weight region (such as column weight 3) reduces the connection degree and complexity, achieving a balance between performance and resources through differential design. Dynamically adjust the mixing ratio according to the target code rate and channel noise (such as increasing the proportion of high column weight under high noise), expanding the applicable scenarios of the scheme.

[0057] In an alternative embodiment, the four-ring detection formula is: ; wherein, i k , j k , i k+1 and j k+1 are all the row and column positions in the matrix where the non-zero terms are located, and L is the dimension of the submatrix; The six-ring detection formula is: ; wherein, i k , j k , i k+1 , j k+1 , i k+2 and j k+2 are all the row and column positions in the matrix where the non-zero terms are located, L is the dimension of the submatrix, and P is the shift value of the other submatrices except the all-zero submatrix.

[0058] In summary, the QC-LDPC code parity-check matrix construction method provided by the embodiments of the present application comprehensively optimizes the performance of the parity-check matrix of the QC-LDPC code through the synergistic effect of progressive technical features. First, an initial index matrix is generated based on the progressive edge growth or random method, and the four-cycle structure is eliminated through the four-cycle detection formula and extended into a combination of cyclic permutation matrices, ensuring that the initial parity-check matrix has both the four-cycle-free property and the quasi-cyclic regularity, laying a foundation for efficient encoding and stable decoding. Secondly, the layered normalized min-sum algorithm is used to simulate decoding and inject random errors, and the high-oscillation target columns are screened out. The non-zero terms with the largest number of six-cycles in them are specifically reduced to generate an intermediate parity-check matrix, achieving precise weakening of local trap sets while retaining the error correction ability of the original matrix. Further, a six-cycle distribution matrix is constructed, and the residual six-cycles in the intermediate matrix are eliminated column by column to generate the target parity-check matrix, systematically reducing the global six-cycle density and avoiding the long-term drag on the decoding performance by cascaded trap sets. On this basis, BCH check bits are independently generated for low-column-weight blocks in the target matrix and cascaded for encoding. The dynamic error correction ability of the outer code is used to strengthen the vulnerable areas, combined with the forced correction of the LLR extreme values fed back by the outer code during the decoding process, breaking the iterative deadlock and accelerating convergence. Finally, through the hybrid column-weight design and dynamic ratio adjustment, the error correction strength in the high-column-weight area and the complexity in the low-column-weight area are balanced to adapt to the requirements of multi-code rate and multi-noise scenarios. From four-cycle elimination, six-cycle optimization to outer code cascaded protection, the progressive technical features form a "construction-optimization-reinforcement" full-link solution, significantly suppressing the error floor, improving the decoding efficiency and reliability, and at the same time, through the structural flexibility and dynamic adaptation mechanism, meeting the stringent performance requirements of high-code-rate LDPC codes for high-speed communication systems.

[0059] Based on the QC-LDPC code parity-check matrix construction method provided by the above embodiments, a specific example will be used to illustrate it in detail below.

[0060] As a special type of codeword with a sparse parity-check matrix, low-density parity-check (LDPC) codes have attracted the attention of many researchers due to their theoretical performance close to the Shannon limit and high information transfer rate. Quasi-cyclic low-density parity-check (QC-LDPC) codes, as an important subclass of LDPC codes, exhibit many advantages by virtue of their unique algebraic structure and cyclic characteristics. QC-LDPC codes have a regular parity-check matrix structure, which enables the encoding and decoding processes to be efficiently implemented, reducing the hardware complexity and playing an important role in high-speed communication systems such as optical communication, satellite communication, 5G communication, and the storage industry.

[0061] However, the existence of trap sets in LDPC codes leads to the error floor phenomenon during the decoding process, which hinders the further improvement of decoding performance. During the decoding process of LDPC codes, a trap set is a special codeword structure that causes the iterative decoding algorithm to fall into a local optimal solution and unable to converge to the correct codeword. This results in the occurrence of bit errors during the decoding process, even when the difference between the received signal and the transmitted signal is small, due to the influence of trap sets. This poses an obstacle to its further application in some fields with low bit error rate requirements, such as storage and deep space communication. Therefore, it is urgent to find effective solutions to overcome this problem.

[0062] Short cycles are one of the main reasons for the formation of trap sets. Therefore, the method proposed in this embodiment focuses on reducing the short cycles in the parity-check matrix and optimizing their distribution. Therefore, based on the QC-LDPC code parity-check matrix construction method of the above embodiment, this embodiment also provides a high code rate long codeword QC-LDPC code parity-check matrix construction method. For the parity-check matrix constructed by this method, this embodiment also proposes a decoding method adapted to this type of matrix.

[0063] The construction process of the high code rate long codeword QC-LDPC code parity-check matrix includes the determination of the dimension, code rate, and sub-matrix dimension of the index matrix of the initial QC-LDPC parity-check matrix; the construction of the index matrix H1; using the H1 matrix for decoding by the layered normalized min-sum method to screen out the positions of the oscillation points of the target number in the index matrix; setting an elimination interval, performing column optimization for the positions of the oscillation points within the interval, counting the number of six-cycles corresponding to each non-zero term at this position, and eliminating the shift value corresponding to the largest number of six-cycles in the target column to obtain the corresponding H2 matrix; constructing the frequency matrix of the occurrence of each non-zero element corresponding to H2 in the six-cycle, setting an elimination interval, and sequentially eliminating the positions of the columns with the largest number of six-cycles in each column within the target interval to obtain the final parity-check matrix H3, where the column weight of the H3 matrix is a matrix mixed with 3, 4, and 5.

[0064] The sub-matrix of the QC-LDPC code parity-check matrix is a zero matrix, an identity matrix, or a shift matrix formed by cyclically shifting the identity matrix to the right by a fixed value. Usually, the zero matrix, the identity matrix, and the cyclic permutation matrix are represented by the numbers "-1", "0", and positive integers between 0 and q - 1 respectively, where q is the sub-matrix dimension.

[0065] In this embodiment, the quadratic elimination method is used to construct the final parity-check matrix, and the specific construction process is as Figure 2 shown, including the following steps.

[0066] For the convenience of fast encoding, the format of the matrix H1 is as Figure 3 shown, Figure 3Among them, A, B, C, D, E, and T represent different positions of a parity-check matrix. n, m, and g represent the code width and code length of the parity-check matrix. The format of the T matrix is an invertible lower triangular matrix, that is, the elements above the upper right of the T matrix are all 0, and the elements on its main diagonal are non-zero. For the construction of the parity-check matrix H1, the specific method is as follows.

[0067] First, determine the dimensions m×n of the initial parity-check matrix, the dimension g×g of the T matrix, the maximum column weight column_weight_T of the T matrix, and the column weight of the H1 matrix is 5. And the sub-matrix dimension p×p. Generate the T matrix using methods such as the random method. First, randomly add shift values on the diagonal of the T matrix. When adding shift values at other positions in the T matrix, randomly select row and column positions to add random shift values. For each added shift value, use the four-cycle detection formula and six-cycle detection formula of the above embodiments to determine the four-cycle and six-cycle. If the detection formula is satisfied, randomly modify the added shift value. Until there are no six-cycles and four-cycles in the constructed T matrix and it meets the maximum column weight constraint of the T matrix.

[0068] Next, using the T matrix as the seed matrix, according to the actual position of each cyclic permutation matrix in the T matrix in the H1 matrix, and the magnitude of the shift value of the cyclic permutation matrix in the T matrix. Use matrix construction methods such as the PEG method or the random method to construct the target matrix H1, determine the position of the cyclic permutation matrix in the H1 matrix. When adding the shift factors of other matrices in the H1 matrix except the T matrix, for each added shift factor, use the above four-cycle detection formula to perform four-cycle verification. If the above four-cycle detection formula is satisfied, randomly modify the added shift value until all cyclic permutation matrices are added. At this time, the construction of the H1 matrix is completed, where the column weight of all columns of the H1 matrix is 5.

[0069] Although there are no four-cycles in the parity-check matrix H1 obtained through the above steps, due to the limitation of the high code rate of the matrix, it cannot be guaranteed that there are no six-cycles in the generated parity-check matrix when adding shift factors. In fact, when the column weight is 5, each cyclic permutation matrix in the generated parity-check matrix H1 will appear on multiple six-cycles at the same time. The existence of short cycles in the matrix is an important reason for the formation of trap sets. However, not all short cycles are harmful. The existence of cycles itself also has certain benefits. Appropriate cycles can improve the minimum Hamming distance of the code and enhance the information flow, thereby further improving the performance of the code.

[0070] In order to select the "harmful" short cycles, in this embodiment, the layered normalized min-sum method is used for pre-decoding to quickly screen out the positions of the points that oscillate during the decoding process.

[0071] The process of the layered normalized min-sum pre-decoding for counting oscillation points is as follows: Set the maximum number of iterations, the number of oscillations at the oscillation points, and the number of codewords generated; generate the initial codeword sequence 1 of a random binary 01 sequence, and the oscillation number sequence 2 for each point, where sequence 2 is initialized to 0; encode the initial codewords using the H matrix according to the encoding calculation method of the RU format matrix to obtain the encoded codeword sequence 3; perform random flipping of fixed bits on the encoded codewords to inject a fixed number of errors to obtain the codeword sequence 4; perform BPSK modulation on the flipped codeword sequence 4, generally modulating 0 to "1" and 1 to "-1" to obtain the modulated codeword sequence 5; initialize the LLR information at the corresponding positions according to the modulated codeword sequence 5, where when the modulated value is 1, the corresponding LLR information is initialized to 7, and when the modulated value is -1, the corresponding LLR information is initialized to -7, denoted as LQ, and Lr is initialized to 0; Calculate the corresponding position Lq = LQ – Lr; calculate the cumulative product sign_all of all Lq symbols in this row. After taking the absolute value of each Lq in this row, select the minimum value, the second minimum value, and the column index position where the minimum value is located. If the column positions are not equal, select the minimum value; if the column positions are the same, select the second minimum value. Update Lr for each position, Lr = sign_all × the symbol at the current position × (minimum value / second minimum value) × α, where α is a normalization factor with a value between 0.5 and 1.

[0072] Calculate LQ = Lr + Lq; when LQ is greater than 0, mark this position as 1, and when LQ is less than 0, mark this position as 0 to obtain the decoded codeword sequence 6. Since the sign of LQ represents whether the final decision result is 0 or 1, for each position of LQ, if the sign of LQ flips between two adjacent iterations, the decision result will also flip, and at this time, it represents that an oscillation has occurred at this position, and the oscillation count of LQ at this position is incremented by 1.

[0073] Calculate H·cT; where c is the codeword sequence 6. If the result is 0, the check passes. If H·cT ≠ 0, the check fails. At this time, perform iteration on the next layer of data, and repeat the calculation of the corresponding position Lq and the calculation of LQ until the decoding is successful or the set maximum number of iterations is reached. At this time, record the positions of the oscillation points that reach the target oscillation count, generate the next random binary 01 sequence, and reread the above oscillation point statistics process until the target number of codewords is reached.

[0074] By injecting different numbers of fixed errors, the positions of the oscillation points where these errors occur are counted, and the positions with high frequencies of oscillation are counted under different initial errors. Set the elimination interval (avoiding the check bit interval), select the column positions in the index matrix corresponding to these oscillation point positions, count the number of six-cycles corresponding to each non-zero term at this position, and obtain the corresponding H2 matrix by eliminating the shift value with the largest number of six-cycles in the target column.

[0075] The H2 matrix is a mixed matrix with column weights of 4 and 5. Although eliminating a certain number of non-zero terms reduces the number of six-cycles in the parity-check matrix, there are still a certain number of six-cycles. To further reduce the probability of decoding failure when errors occur at high column weights of H2 and improve the performance of the matrix in the waterfall region, in this embodiment, the H2 matrix is subjected to secondary column weight elimination, and the specific process is as Figure 4 shown, including the following steps: Step 1: Determine the column elimination index and the total number of columns in the H2 matrix according to a random or sequential method.

[0076] Step 2: Construct an H2' matrix with the same dimension as the H2 matrix as the six-cycle distribution matrix of the H2 matrix, and initialize the values in the H2' matrix to all 0. Starting from the first non-zero term in the first column of the parity-check matrix H2, for each non-zero term in each column, use the above six-cycle detection formula to perform six-cycle statistics, and fill the number of times each non-zero term appears in the six-cycle into the corresponding row and column positions of the H2' matrix.

[0077] Step 3: Initialize the first row of the selected column to the initial maximum value and the row index row_idx where the maximum value is located. Start comparing row by row in this column, select the maximum value in this column of the H2' matrix, that is, the point with the largest number of six-cycles in the corresponding H2 matrix, and record the row and column positions where the maximum value is located at the same time. Set the shift value corresponding to this row and column position in the H2 matrix to "-1", that is, replace the identity matrix or the identity circulant matrix at this position with a matrix of all 0s to obtain the H2'' matrix.

[0078] Step 4: Select the next column, initialize the values in the H2' matrix to all 0 again, replace the H2 matrix in Step 1 with the H2'' matrix, repeat Step 2 and then Step 3 until the total number and index of the columns with eliminated shift values reach the set value to obtain the H3 matrix.

[0079] Since some columns have been eliminated during the oscillation point elimination in the secondary elimination, there will be some columns with column weight 3 in the final H3 matrix. The H3 matrix is a mixed matrix with column weights of 3, 4, and 5. The number of short cycles in H3 is further reduced compared to H2. It can be seen from the simulations in subsequent embodiments that the decoding performance of this matrix is further enhanced. This is because when errors occur at high column weights, the probability of decoding failure is reduced.

[0080] In order to further reduce the error floor in the decoding process and improve the decoding performance when errors occur at positions with a column weight of 3, this embodiment also provides a BCH concatenated coding and decoding method adapted to this type of matrix.

[0081] In the encoding stage, after the initial information is LDPC encoded using the RU encoding method, it is further encoded using the BCH code for positions with a column weight of 3 for secondary protection. The parity bit information of the BCH generated by the column weight of 3 is not sent to the LDPC decoder during the decoding process. The length of the BCH code is exactly such that it can correct errors when there is less than 1 bit of error in the block information protected by the column weight of 3.

[0082] In the decoding stage, the decoding method of the LDPC code also uses the layered normalized min-sum algorithm, and the specific steps are as follows.

[0083] Set the maximum number of iterations and the maximum / minimum values of the LLR information. Modulate the LDPC codeword to be decoded using BPSK, mapping 0 to "1" and 1 to "-1" to obtain the modulated codeword sequence a. Initialize the LLR information at the corresponding positions according to the modulated codeword sequence a. When the modulated value is 1, the corresponding LLR information is initialized to 7, and when the modulated value is -1, the corresponding LLR information is initialized to -7, denoted as LQ, and Lr is initialized to 0. Calculate the corresponding Lq = LQ – Lr; calculate the product sign_all of all Lq symbols in this row. After taking the absolute value of each Lq in this row, select the minimum value and the second minimum value, as well as the column index position where the minimum value is located. If the column positions are not equal, select the minimum value; if the column positions are the same, select the second minimum value. Update Lr at each position, Lr = sign_all × the symbol at the current position × (minimum value / second minimum value) × α, where α is the normalization factor, and its value is between 0.5 and 1.

[0084] Calculate LQ = Lr + Lq; perform a decision on the codeword. When LQ is greater than 0, mark this position as 1, and when LQ is less than 0, mark this position as 0 to obtain the decoded codeword sequence c. Send the interval with a column weight of 3 in the decoded codeword sequence c into the BCH decoder, combine it with the corresponding BCH parity bits, and start the BCH decoding process.

[0085] If the BCH decoder can exactly detect errors less than 1 bit, change the values of all LQ in the current BCH protection interval to the set maximum and minimum values of LQ according to the positive and negative sign relationship of LQ at this time.

[0086] Perform a secondary judgment on the entire codeword. When LQ is greater than 0, mark this position as 1. When LQ is less than 0, mark this position as 0 to obtain the codeword sequence c after judgment. Calculate H·cT. If the result is 0, the check passes. If H·cT ≠ 0, the check fails. At this time, perform iteration on the data of the next layer, and repeat the above steps until the final decoding is successful or the set maximum number of iterations is reached.

[0087] Exemplarily, a specific matrix example is used for illustration.

[0088] According to the method in this embodiment, a 29×287 matrix is constructed, where the sub-matrix dimension is 128, the code length of the corresponding LDPC code is 36736, and the code rate of the corresponding LDPC code is 0.89895.

[0089] First, the dimension of the T matrix is determined to be 25×25, and a lower triangular T matrix is constructed. Subsequently, on this basis, the PEG method is further used to construct a parity-check matrix H1 with a column weight of all 5 and a structure conforming to the RU algorithm matrix structure. Set the initial mis-injected bits to 280, 275, and 270, and set the maximum number of iterations to 10 times. According to the pre-error correction method described in this application, 76 column oscillation points are screened out, and the non-zero terms corresponding to the largest six cycles in the columns where the oscillation points are located are eliminated to obtain the matrix H2. On this basis, further select the first 150 columns of the matrix and perform column elimination according to the method described in this application. Finally, the matrix H3 is obtained. The numbers of columns with column weights of 3, 4, and 5 in the finally obtained matrix H3 are: 62 columns, 102 columns, and 123 columns respectively.

[0090] There are no any four cycles in the constructed H1, H2, and H3 matrices corresponding to the 29×287 matrix. The total number of six cycles in these three matrices is counted, and the statistical results of the total number of six cycles are as Figure 5 shown. The number of six cycles in H3 is only one-sixth of the initial H1 matrix. It shows that the matrix constructed by the three-step method can significantly reduce the total number of six cycles in the matrix. This has a positive significance for the elimination of trap sets in the matrix.

[0091] Further performance tests are carried out on the constructed three matrices. The decoding algorithm is the layered normalized min-sum decoding algorithm. The performance test results are as Figure 6 shown. The performance of the matrix in the waterfall region has been further improved.

[0092] The decoding simulation is carried out on the finally constructed H3 matrix according to the decoding algorithm in this application. During the encoding process, since there are 128 bit data in each region with a column weight of 3, the length of the BCH code is 144. Its decoding performance is as Figure 7 shown. It can be seen that the decoding performance is greatly enhanced.

[0093] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0094] An embodiment of the present application also provides a QC-LDPC code parity-check matrix construction device, and the structure of the device is as Figure 8 shown, including: An initial generation module 801, configured to generate an initial parity-check matrix; the initial parity-check matrix has no four-cycle structure; An intermediate generation module 802, configured to perform pre-decoding on the initial parity-check matrix, screen out target columns whose oscillation frequency exceeds a preset threshold during the decoding process, and eliminate the non-zero terms with the largest number of six-cycles in the target columns to generate an intermediate parity-check matrix; A target generation module 803, configured to eliminate the non-zero terms with the largest number of six-cycles in the intermediate parity-check matrix column by column to generate a target parity-check matrix.

[0095] For the description of the features in the embodiment corresponding to the QC-LDPC code parity-check matrix construction device, reference can be made to the relevant description of the embodiment corresponding to the QC-LDPC code parity-check matrix construction method, which will not be elaborated here one by one.

[0096] An embodiment of the present application also provides an electronic device, as Figure 9 shown, including a memory 14 and a processor 20. A computer program is stored in the memory 10, and the processor 20 is configured to run the computer program to execute the steps in any of the above embodiments of the QC-LDPC code parity-check matrix construction method.

[0097] An embodiment of the present application also provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps in any of the above embodiments of the QC-LDPC code parity-check matrix construction method when running.

[0098] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: USB flash drives, read-only memories (ROM for short), random access memories (RAM for short), mobile hard disks, magnetic disks, or optical discs and other various media that can store computer programs.

[0099] An embodiment of the present application also provides a computer program product. The above computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above embodiments of the QC-LDPC code parity-check matrix construction method.

[0100] Embodiments of the present application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, and the computer program, when executed by a processor, implements the steps in any of the above-described embodiments of the QC-LDPC code check matrix construction method.

[0101] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described according to their functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0102] The above has introduced in detail a method, apparatus, device, storage medium, and program product for constructing a QC-LDPC code check matrix provided by the present application. Specific examples are used herein to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art in the technical field, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A method for constructing a QC-LDPC code parity-check matrix, characterized in that, The method includes: Generating an initial parity-check matrix; the initial parity-check matrix has no four-cycle structure; Performing pre-decoding on the initial parity-check matrix, screening out target columns whose oscillation frequency exceeds a preset threshold during the decoding process, and eliminating the non-zero terms with the largest number of six-cycles in the target columns to generate an intermediate parity-check matrix; Eliminating the non-zero terms with the largest number of six-cycles in the intermediate parity-check matrix column by column to generate a target parity-check matrix.

2. The method according to claim 1, wherein The generating of the initial parity-check matrix includes: Generating an initial index matrix of a QC-LDPC code based on the progressive edge-growth algorithm or a random method; Determining the four-cycle structure in the initial index matrix through a four-cycle detection formula, and adjusting the shift values of the cyclic permutation matrices in the initial index matrix to eliminate four-cycles to obtain an index matrix; Replacing each non-zero element in the index matrix with a cyclic permutation matrix, and replacing the zero elements in the index matrix with all-zero matrices; the shift value of the cyclic permutation matrix is determined by the non-zero element value in the index matrix; Combining all the replaced cyclic permutation matrices and all-zero matrices to obtain an initial parity-check matrix.

3. The method according to claim 2, wherein The generating of the initial index matrix of a QC-LDPC code based on the progressive edge-growth algorithm or a random method includes: Generating a seed matrix based on the progressive edge-growth algorithm or a random method; the seed matrix is an invertible lower triangular matrix, and the diagonal elements of the seed matrix are generated by randomly adding the shift values of cyclic permutation matrices; Randomly adding the shift values of cyclic permutation matrices at the non-diagonal positions of the seed matrix, and avoiding the generation of four-cycles and six-cycles through the four-cycle detection formula and the six-cycle detection formula to generate an initial index matrix.

4. The method according to claim 3, characterized in that The performing of pre-decoding on the initial parity-check matrix and screening out target columns whose oscillation frequency exceeds a preset threshold during the decoding process includes: Performing simulated decoding on the initial parity-check matrix using the layered normalized min-sum algorithm; During the simulated decoding process, injecting a preset number of random errors into the encoded codeword sequence, and counting the number of oscillations at each bit position during iterative decoding; According to the comparison result between the number of oscillations and the preset threshold, screening out the target columns whose decoding oscillation frequency exceeds the threshold.

5. The method according to claim 4, characterized in that The eliminating of the non-zero terms with the largest number of six-cycles in the target columns to generate an intermediate parity-check matrix includes: For each non-zero term in the target column, counting the number of six-cycles participated by each non-zero term; Replacing the cyclic permutation matrix corresponding to the non-zero term with the largest number of six-cycles with an all-zero matrix or a new cyclic shift value to obtain an intermediate parity-check matrix.

6. The method according to claim 5, characterized in that, The eliminating of the non-zero terms with the largest number of six-cycles in the intermediate parity-check matrix column by column to generate a target parity-check matrix includes: Constructing a six-cycle distribution matrix with the same dimension as the intermediate parity-check matrix, and counting the number of six-cycles participated by each non-zero term; For each column of the intermediate parity-check matrix, selecting the non-zero term with the largest value in the six-cycle distribution matrix for reduction; Repeating the reduction operation until a preset six-cycle elimination target is reached to obtain a target parity-check matrix.

7. The method according to claim 6, wherein After the generating of the target parity-check matrix, it further includes: Dividing the blocks in the target parity-check matrix with a column weight lower than a preset threshold into independent data blocks, and independently generating outer code check bits for each data block; Combining the outer code check bits with the encoding result of the target parity-check matrix to obtain a concatenated coding output.

8. The method according to claim 7, wherein The outer code is a BCH code, and the code length of the outer code is determined by the data length of the block whose column weight is lower than a preset column weight threshold.

9. The method according to claim 7, wherein The method further includes: In the decoding stage, a layered normalized min-sum algorithm is used for iterative decoding, and the decision results of the blocks whose column weight is lower than a preset threshold are extracted after decoding each layer; The decision results are combined with the corresponding outer code check bits and input into an outer code decoder for error correction; If the outer code decoder detects correctable errors, the confidence information of the corresponding bits is adjusted according to the outer code decoding result; the adjustment includes setting the log-likelihood ratio of the corresponding bits to the maximum value or the minimum value; After updating the confidence information, continue to perform the next-layer iterative decoding; When a preset condition is reached, it indicates successful decoding.

10. The method according to claim 9, characterized in that, The "when a preset condition is reached, it indicates successful decoding" includes: When the product of the target parity-check matrix and the decision result is a zero vector or a preset maximum number of iterations is reached, it indicates successful decoding; If decoding fails, re-initialize the confidence information and restart the decoding process.

11. The method according to claim 10, wherein The column weight of the initial parity-check matrix is a first preset column weight; the first preset column weight is determined by the target code rate and the channel condition; and in the construction process of the initial parity-check matrix, the column weight of each column is equal to the first preset column weight; The column weight of the intermediate parity-check matrix is a mixed structure of a first preset column weight and a second preset column weight; The second preset column weight is obtained by subtracting the non-zero terms of the target column in the initial parity-check matrix; The column weight of the target parity-check matrix is a mixed structure of a first preset column weight, a second preset column weight, and a third preset column weight; The third preset column weight is obtained by subtracting the non-zero terms of the intermediate parity-check matrix column by column; The distribution ratio of the mixed structure is determined based on the target code rate and the channel noise condition.

12. The method according to any one of claims 1 to 11, characterized in that, The four-ring detection formula is: ； where i k , j k , i k+1 and j k+1 are the row and column positions in the matrix where the non - zero terms are located, and L is the dimension of the sub - matrix; The six-ring detection formula is: ； where i k , j k , i k+1 , j k+1 , i k+2 and j k+2 are the row and column positions in the matrix where the non-zero terms are located, L is the dimension of the sub-matrix, and P is the shift value of other sub-matrices outside the all-zero sub-matrix.

13. An electronic device, characterized in that, including: A memory for storing a computer program; A processor for implementing the steps of the QC-LDPC code parity-check matrix construction method according to any one of claims 1 to 12 when executing the computer program.

14. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium, wherein the computer program implements the steps of the QC-LDPC code parity-check matrix construction method according to any one of claims 1 to 12 when executed by a processor.

15. A computer program product comprising a computer program, characterized in that, The computer program implements the steps of the QC-LDPC code parity-check matrix construction method according to any one of claims 1 to 12 when executed by a processor.

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