Congestion control method and device in PCIe (Peripheral Component Interface Express)

Abstract

The invention relates to the technical field of serial interfaces, and discloses a congestion control method and device in PCIe, the method is applied to a PCIe data transmission system, the PCIe data transmission system comprises a central device and at least two PCIe links, the central device communicates with corresponding PCIe devices through the at least two PCIe links, and the central device communicates with the PCIe devices through the at least two PCIe links. The method comprises the following steps: when detecting that a credit value of a target message to be sent in a target PCIe link does not meet a sending condition, triggering a timer; and when the timing of the timer reaches the maximum waiting time, closing the target PCIe link, and reporting the congestion information of the target PCIe link. According to the scheme, under the condition that the opposite terminal cannot return the credit value to cause the message sending congestion of the home terminal, when the congestion is detected to reach the maximum waiting time, the link is automatically closed, the equipment operation fault caused by the fact that the CPU does not receive the reading response is avoided, and the operation reliability of the PCIe data transmission system is improved.

Description

Technical Field

[0001] This application relates to the technical field of serial interfaces, and in particular, to a congestion control method and device in PCIE. Background Art

[0002] The PCIe (Peripheral Component Interconnect Express, a high-speed serial bus standard) bus is commonly used for interconnection between chips.

[0003] PCIe adopts a credit-based flow control mechanism. According to the PCIe protocol, when the credit value is insufficient, TLP packets cannot be sent. However, the protocol does not specify how to handle the situation where there is no credit value for a long time. Figure 1 Fig. shows a data transmission process of PCIe in the prior art. As Figure 1 shown, a chip connects two PCIe devices. When the connected pcie_dev1 does not update the credit value for PCIe_rp1. PCIe_rp_1 cannot send packets. At this time, the CPU sends a read operation, and the destination address points to PCIe_rp1. Since PCIe_rp1 has insufficient credit value, it cannot send the read operation and cannot return the read response. At this time, the CPU will enter a deadlock state due to not receiving the read response, which will further cause the device operation to fail. Summary of the Invention

[0004] In view of this, this application provides a congestion control method and device in PCIe, which avoids the device operation failure caused by the CPU not receiving the read response.

[0005] In a first aspect, this application provides a congestion control method in PCIe. The method is applied to a PCIe data transmission system, which includes a central device and at least two PCIe links. The central device communicates with corresponding PCIe devices through at least two PCIe links respectively. The method includes:

[0006] When it is detected that the credit value of the target packet to be sent in the target PCIe link does not meet the sending condition, a timer is triggered;

[0007] When the timing of the timer reaches the maximum waiting time, the target PCIe link is closed, and the congestion information of the target PCIe link is reported.

[0008] In a possible implementation manner, the method further includes:

[0009] If it is detected that the credit value of the target packet changes before the timing of the timer reaches the maximum waiting time, and the changed credit value meets the sending condition, the timer is set to 0.

[0010] In a possible implementation, when it is detected that the credit value of the target packet to be sent in the target PCIe link does not meet the sending condition, triggering a timer includes:

[0011] When it is detected that the credit value of the target packet to be sent in the target PCIe link does not meet the sending condition, and the target PCIe link enables the flow control function, trigger the timer.

[0012] In a possible implementation, the method further includes:

[0013] If, before the timing of the timer reaches the maximum waiting time, it is detected that the credit value of the target packet changes and the changed credit value meets the sending condition, then set the timer to 0;

[0014] Alternatively, if, before the timing of the timer reaches the maximum waiting time, it is detected that the target PCIe link disables the flow control function, then set the timer to 0.

[0015] In a second aspect, a congestion control device in PCIe is provided. The device is applied to a PCIe data transmission system, and the PCIe data transmission system includes a central device and at least two PCIe links. The central device communicates with corresponding PCIe devices through at least two PCIe links respectively. The device includes:

[0016] A blocking timer, which is triggered when it is detected that the credit value of the target packet to be sent in the target PCIe link does not meet the sending condition;

[0017] A comparator; a first input end of the comparator is connected to an output end of the blocking timer; a second input end of the comparator is connected to the maximum waiting time;

[0018] A status register; a first input end of the status register is connected to an output end of the comparator; an output end of the status register is used to output a prohibition signal; the prohibition signal is used to close the target PCIe link.

[0019] In a possible implementation, the device further includes a first logic unit;

[0020] A first input end of the first logic unit is connected to a credit check flag; a second input end of the first logic unit is connected to a function start signal; an output end of the first logic unit is connected to a reset end of the blocking timer; when the credit value of the target packet does not meet the sending condition, the credit check flag is at a low level; when the target PCIe link enables the flow control function, the function start signal is at a high level;

[0021] The first logic unit is configured to output a low level at its output terminal when the credit check flag is at a low level and the function start signal is at a high level.

[0022] In a possible implementation, the first logic unit is further configured to output a high level at its output terminal when the credit check flag is at a high level and the function start signal is at a low level;

[0023] The first logic unit is further configured to output a high level at its output terminal when the credit check flag is at a high level and the function start signal is at a high level;

[0024] The first logic unit is further configured to output a high level at its output terminal when the credit check flag is at a low level and the function start signal is at a low level.

[0025] In a possible implementation, the second input terminal of the status register is further configured to receive the function start signal;

[0026] When the first input terminal of the status register is at a high level and the second input terminal of the status register is at a high level, the status register outputs a disable signal at its output terminal.

[0027] In a possible implementation, when the second input terminal of the status register is at a low level, the status register is reset.

[0028] In a possible implementation, the device further includes a second logic unit; the first input terminal of the second logic unit is configured to receive a pre-configured disable signal; the second input terminal of the second logic unit is configured to receive the disable signal output by the status register;

[0029] When at least one of the first input terminal of the second logic unit and the second input terminal of the second logic unit is at a high level, the second logic unit sends a link close signal to close the target PCIe link through the physical layer.

[0030] The technical solution provided by this application may include the following beneficial effects:

[0031] The data transmission system in PCIe includes a central device and at least two PCIe links. The central device communicates with corresponding PCIe devices through at least two PCIe links respectively. At this time, the PCIe data transmission system can detect the credit value of the target message to be sent in the target PCIe link. When it is detected that the credit value of the target message to be sent in the target PCIe link does not meet the sending condition, it means that the TLP message cannot be sent normally and there may be congestion in the link. At this time, a timer is triggered. And when the timing of the timer reaches the maximum waiting time, the PCIe data transmission system closes the target PCIe link and reports the congestion information of the target PCIe link. The above solution can automatically close the link when the congestion reaches the maximum waiting time in the case where the peer end cannot return the credit value, resulting in congestion of the local end's sent messages, avoiding the device operation failure caused by the CPU not receiving the read response, and improving the reliability of the operation of the PCIe data transmission system. Description of the Drawings

[0032] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0033] Figure 1 Shows a data transmission process of PCIe in the prior art.

[0034] Figure 2 Shows a congestion control method in PCIe provided by an embodiment of the present application.

[0035] Figure 3 Shows a congestion control device in PCIe provided by an embodiment of the present application.

[0036] Figure 4 Shows the functional block diagram of the congestion control device in PCIe.

[0037] Figure 5 Is a schematic structural diagram of a computer device provided by an optional embodiment of the present application. Detailed Embodiments

[0038] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the following will clearly and completely describe the technical solutions in the embodiments of this application with reference to the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are some, but not all, of the embodiments of this application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of this application without creative efforts shall fall within the protection scope of this application.

[0039] In the description of the embodiments of this application, the term "corresponding" may indicate a direct or indirect corresponding relationship between two entities, may also indicate an associated relationship between the two, or may be a relationship such as indication and being indicated, configuration and being configured, etc.

[0040] The PCIe bus is commonly used for interconnection between chips. PCIe adopts a credit-based flow control mechanism. According to the PCIe protocol, when the credit value is insufficient, TLP packets cannot be sent. However, the protocol does not specify how to handle the situation where there is no credit value for a long time. As Figure 1 shown, the chip connects two PCIe devices. When the connected pcie_dev1 does not update the credit value for PCIe_rp1, PCIe_rp_1 cannot send packets. At this time, the CPU sends a read operation, and the destination address points to PCIe_rp1. Since PCIe_rp1 cannot send the read operation due to insufficient credit value, it also cannot return a read response. The CPU enters a deadlock state because it does not receive the read response, and the PCIe protocol does not specify how to handle the situation where packets cannot be sent due to insufficient credit value for a long time.

[0041] For example, Figure 1 component X in has only one axi_master port and sends operations to pcie_dev1 and pcie_dev2. Since PCIe_rp_1 cannot send packets, the axi_master port of component X is back pressured, and component X cannot send operations to PCIe_rp_1 either. Therefore, to solve the above problems, please refer to Figure 2 , which is a congestion control method in PCIe provided by the embodiments of this application. This method is applied to a PCIe data transmission system, and the PCIe data transmission system includes a central device and at least two PCIe links. The central device communicates with corresponding PCIe devices through at least two PCIe links respectively (for example Figure 1 is a PCIe data transmission system), and this method includes:

[0042] Step 201, when it is detected that the credit value of the target packet to be sent in the target PCIe link does not meet the sending condition, trigger a timer.

[0043] In PCIe, the credit mechanism ensures that the sender can only send a TLP (Transaction Layer Packet) when there are sufficient buffer resources at the receiver. Therefore, if the credit value of the target packet to be sent does not meet the sending condition, it means that the sender does not have enough credit to legally send a new TLP at this time.

[0044] For example, when the sender continuously sends multiple TLP packets, it consumes the pre-allocated credit value, and the receiver has not returned a new credit update in time. At this time, the available credit of the sender is insufficient to meet the sending requirements of subsequent packets; or, if a downstream device (such as a PCIe device) cannot update the credit in time due to internal processing or link congestion, etc., the credit value of the sender will remain at a low level or be exhausted for a long time, resulting in the inability to send subsequent packets; or, in a PCIe system, multiple devices may share the same credit pool or link resources. When other devices occupy a large amount of credit, a single device may temporarily not be able to obtain enough credit to send packets.

[0045] That is to say, if the credit value of the target packet to be sent in the target PCIe link does not meet the sending condition, it can be considered that the target PCIe link is already in a link congestion state. At this time, a timer needs to be triggered to record the time when the target PCIe link is in the link congestion state.

[0046] Step 202, when the timing of the timer reaches the maximum waiting time, close the target PCIe link and report the congestion information of the target PCIe link.

[0047] In practical applications, the PCIe data transmission system can also be designed such that when it is detected that the credit value of the target packet to be sent in the target PCIe link does not meet the sending condition, the target PCIe link is directly closed. That is, when the target PCIe link is congested, in order to avoid the impact of the target PCIe link congestion on the CPU, the target PCIe link is directly closed. Although this solution can minimize the impact of the target PCIe link congestion on other links, in fact, in many cases, the congestion of the PCIe link can be recovered. For example, when the sender continuously sends multiple TLP packets and consumes the pre-allocated credit value, and the receiver has not returned a new credit update in time, resulting in insufficient available credit of the sender to meet the sending requirements of subsequent packets, the congestion may be automatically recovered after receiving a new credit update in a few seconds. Therefore, in the embodiments of this application, the congestion time can be recorded through a timer and compared with the maximum waiting time to determine in what circumstances the PCIe link needs to be closed.

[0048] In a possible implementation manner of the embodiment of the present application, the maximum waiting time can be preset by a developer. For example, it can be set to 15 seconds.

[0049] In another possible implementation manner of the embodiment of the present application, the maximum waiting time can also be adjusted according to the working state of the PCIe link. For example, after the developer sets the maximum waiting time to 15 seconds, during the working process, the PCIe data transmission system detects that due to the packet credit value not meeting the sending condition, and after the timer reaches the maximum waiting time, the number of closed PCIe links is greater than the quantity threshold (for example, greater than 2 or the ratio is greater than 50%). That is to say, the transmission environment of the PCIe data transmission system requires a larger maximum waiting time. At this time, the PCIe data transmission system can increase the maximum waiting time (for example, increase by 5s). And because the number of closed PCIe links is relatively large at this time, the PCIe data transmission system can also directly reset the entire system through the CPU. After the reset, the system uses the increased maximum waiting time.

[0050] In the embodiment of the present application, if before the timer reaches the maximum waiting time, it is detected that the credit value of the target packet changes, and the changed credit value meets the sending condition, the timer is set to 0. Before the timer reaches the maximum waiting time, the credit value of the target packet has changed, and the changed credit value meets the sending condition, which means that at this time the TLP packet meets the sending condition and can be normally sent, and the congestion of the target PCIe link naturally recovers. At this time, there is no need to record the congestion time of the target PCIe link anymore. Therefore, the timer can be directly set to zero, and the timer will restart when the credit value of the packet to be sent in the target PCIe link is insufficient again.

[0051] Optionally, step 201 further includes:

[0052] When it is detected that the credit value of the target packet to be sent in the target PCIe link does not meet the sending condition, and the target PCIe link enables the flow control function, the timer is triggered.

[0053] That is, in the solution shown in the embodiment of the present application, it can be determined whether to start through the flow control function set in the target PCIe link. When the target PCIe link enables the flow control function and the credit value of the target packet does not meet the sending condition, the timer will be triggered.

[0054] Furthermore, in multiple PCIe links of the PCIe data transmission system, one or more of them can be enabled with the flow control function according to requirements.

[0055] Further, in the case where a flow control function is set in the PCIe data transmission system, if the credit value of the target packet is detected to change before the timer reaches the maximum waiting time, and the changed credit value meets the sending condition, the timer is set to 0.

[0056] Or, if it is detected that the target PCIe link closes the flow control function before the timer reaches the maximum waiting time, the timer is set to 0.

[0057] That is to say, when the timer is in the timing state and has not reached the maximum waiting time, there are two cases where the timer can stop timing and be set to zero. One is that the credit value of the target packet changes, and the changed credit value meets the sending condition, that is, the target PCIe link naturally recovers from the congested state.

[0058] The other case is that the developer temporarily closes the flow control function of the target PCIe link. Due to the temporary closure of the flow control function, the target PCIe link will not be closed because the congestion time reaches the maximum waiting time, and the timer does not need to time the congestion of the target PCIe link anymore.

[0059] In summary, the data transmission system in PCIe includes a central device and at least two PCIe links. The central device communicates with the corresponding PCIe devices through at least two PCIe links respectively. At this time, the PCIe data transmission system can detect the credit value of the target packet to be sent in the target PCIe link. When it is detected that the credit value of the target packet to be sent in the target PCIe link does not meet the sending condition, it means that the TLP packet cannot be sent normally and the link may be congested. At this time, the timer is triggered. And when the timer reaches the maximum waiting time, the PCIe data transmission system closes the target PCIe link and reports the congestion information of the target PCIe link. The above solution can automatically close the link when it is detected that the congestion reaches the maximum waiting time in the case where the peer end cannot return the credit value, resulting in congestion of the local end's sent packets, avoiding device operation failures caused by the CPU not receiving the read response, and improving the reliability of the operation of the PCIe data transmission system.

[0060] The embodiment of the present application also provides a congestion control device in PCIe. This device can be applied to the PCIe data transmission system to implement various functions shown in the above-mentioned congestion control method in PCIe, such as Figure 3 As shown, the device includes:

[0061] A blocking timer, which is triggered when it is detected that the credit value of the target packet to be sent in the target PCIe link does not meet the sending condition.

[0062] Comparator; the first input terminal of the comparator is connected to the output terminal of the blocking timer; the second input terminal of the comparator is connected to the maximum waiting time;

[0063] Status register; the first input terminal of the status register is connected to the output terminal of the comparator; the output terminal of the status register is used to output a prohibition signal; the prohibition signal is used to close the target PCIe link.

[0064] In the device as Figure 3 shown, the blocking timer is triggered when it detects that the credit value of the target packet does not meet the sending condition, and increments the count in each clock cycle after being triggered, so as to record the duration since entering the credit shortage state. If the credit is restored or other conditions change (such as the flow control function is turned off) during this period, the timer will be reset; otherwise, the count continues until the preset maximum waiting time is reached.

[0065] Then, the comparator is responsible for comparing the current count value output by the blocking timer with the preset maximum waiting time. The first input terminal is used to connect to the output of the blocking timer (that is, the current timing value). The second input terminal is used to connect to the configured maximum waiting time (block_timer_limit). When the output value of the timer reaches or exceeds this preset threshold, the comparator outputs a signal (high level), indicating that the timeout has occurred, that is, the congestion state has lasted for too long.

[0066] The status register is used to latch the output of the comparator and generate a final prohibition signal, which is used to close the target PCIe link. The first input terminal of the status register receives the output signal of the comparator. When the comparator detects that the timing value reaches the maximum waiting time, the status register will be set and the prohibition signal will be output. The prohibition signal is used to indicate that the system enters the congestion protection state, closes or disables the target PCIe link, so as to prevent system deadlock or other abnormalities caused by long-term credit shortage.

[0067] Further, please refer to Figure 4 , which shows a functional block diagram of the congestion control device in PCIe.

[0068] As Figure 4 shown, where block_timer[15:0] is the above-mentioned blocking timer, and the counting range is [15:0]. block_timer_limit[15:0] is the above-mentioned maximum waiting time, and the configurable range is also [15:0].

[0069] Optionally, as Figure 4 shown, the congestion control device involved in the embodiment of the present application further includes a first logic unit;

[0070] The first input terminal of the first logic unit is connected to a credit check flag (fc_pass); the second input terminal of the first logic unit is connected to a function start signal (fc_block_int_en); the output terminal of the first logic unit is connected to the reset terminal of the blocking timer; when the credit value of the target packet does not meet the sending condition, the credit check flag is at a low level; when the target PCIe link enables the flow control function, the function start signal is at a high level;

[0071] Specifically, after receiving the credit check flag and the function start signal, the first logic unit first takes the inverse of them through a logical NOT operation "!", and then performs a logical operation on them, so that when the credit check flag is at a low level and the function start signal is at a high level, the output terminal outputs a low level.

[0072] Furthermore, the first logic unit is also used to output a high level at the output terminal when the credit check flag is at a high level and the function start signal is at a low level;

[0073] The first logic unit is also used to output a high level at the output terminal when the credit check flag is at a high level and the function start signal is at a high level;

[0074] The first logic unit is also used to output a high level at the output terminal when the credit check flag is at a low level and the function start signal is at a low level.

[0075] Specifically, it is 0 when there is a packet to be sent but the credit value is insufficient, otherwise it is 1. That is to say, in the embodiment of the present application, by introducing the fc_pass variable, it is used for the timing of the subsequent block_timer variable. In the embodiment of the present application, a software-configurable register is added to output the function start signal fc_block_int_en to enable or disable the flow control function. Configured as 1 means enabling this function, and configured as 0 means disabling. This configurable register provides users with flexible options to enable or disable the flow control function. When this function is not needed, it can be turned off to reduce processing overhead; while when needed, the function can be activated by simply setting this register, improving the flexibility of the system.

[0076] Therefore, the blocking timer in the embodiment of the present application will be reset to 0 when fc_pass is 1 or fc_block_int_en is 0; conversely, if neither of these two conditions is met, the counter increments by 1 every clock cycle. The design of block_timer realizes the accurate measurement of the congestion duration. It can be automatically reset under appropriate conditions, ensuring the accuracy of counting. At the same time, through the periodic increment operation, it provides a basis for judging whether the preset maximum congestion time is reached, effectively avoiding long-term invalid waiting and optimizing the resource utilization efficiency.

[0077] In the embodiments of the present application, a register is further provided to set the block_timer_limit, allowing the user to define the maximum time period to wait in a congested state. The user is allowed to set the maximum waiting time according to the actual network conditions, ensuring that even in the case of a short-term network congestion, the system will not wait indefinitely for recovery. This not only improves the response speed of the system but also enhances the adaptability to different network environments.

[0078] Further, as Figure 4 shown, in the congestion control device involved in the embodiments of the present application, the second input terminal of the status register is further used to access the function start signal; when the first input terminal of the status register is at a high level and the second input terminal of the status register is at a high level, the output terminal of the status register outputs a prohibition signal. Further, when the second input terminal of the status register is at a low level, the status register is reset.

[0079] Specifically, when fc_block_int_en is 1 and the block_timer reaches the time limit set by block_timer_limit, the output of the status register (i.e., the prohibition signal Link_dis) is set to 1, indicating that the link enters the disable state. In other cases, the output of the status register remains unchanged. Once congestion is detected and the set time limit is exceeded, the system will automatically enter the disable state and stop further data transmission. In the above solution design, the proactive traffic management strategy helps to protect the entire communication link from overloading, reduces the possibility of data conflicts and errors, and also promotes the overall stability and reliability of the network.

[0080] Further, the prohibition signal Link_dis is reported to the local CPU as an interrupt source, so as to respond and process congestion events in a timely manner. Reporting the prohibition signal Link_dis to the local CPU as an interrupt source enables the CPU to obtain congestion information in a timely manner and take corresponding measures for processing. This greatly shortens the fault response time, improves the real-time performance of the system, and is conducive to quickly resuming normal services.

[0081] Further, as Figure 4 shown, in the congestion control device involved in the embodiments of the present application, the device further includes a second logic unit; the first input terminal of the second logic unit is used to access a pre-configured disable signal (Cfg_link_dis); the second input terminal of the second logic unit is used to access the prohibition signal (Link_dis) output by the status register;

[0082] When at least one of the first input terminal and the second input terminal of the second logic unit is at a high level, the second logic unit sends a link shutdown signal (Cfg_link_dis_Itssm) to shut down the target PCIe link through the physical layer.

[0083] That is, in the congestion control device shown in the embodiments of the present application, the target PCIe link is not necessarily shut down by the prohibition signal (Link_dis) output by the status register. The user can also trigger the pre-configured disable signal (Cfg_link_dis) through software to directly shut down the target PCIe link.

[0084] And in the above solution, during system startup, the block_timer_limit parameter should be configured first, and then this function is activated by setting fc_block_int_en to 1, so as to ensure that the flow control mechanism is in the correct working state from the very beginning. And in the PCIe data transmission system, it is also necessary to monitor the interrupt signal from this device (that is, monitor the congestion information reported through the prohibition signal), identify specific interrupt types, and record the corresponding event information for subsequent analysis and troubleshooting. In the embodiments of the present application, data processing software can also be correspondingly set to identify specific types of interrupt events and record relevant information for analysis, which helps maintenance personnel to perform troubleshooting and system optimization work.

[0085] To sum up, the data transmission system in PCIe includes a central device and at least two PCIe links. The central device communicates with corresponding PCIe devices through at least two PCIe links respectively. At this time, the PCIe data transmission system can detect the credit value of the target message to be sent in the target PCIe link. When it is detected that the credit value of the target message to be sent in the target PCIe link does not meet the sending condition, it means that the TLP message cannot be sent normally and the link may be congested. At this time, a timer is triggered. And when the timing of the timer reaches the maximum waiting time, the PCIe data transmission system shuts down the target PCIe link and reports the congestion information of the target PCIe link. The above solution can automatically shut down the link when it is detected that the congestion reaches the maximum waiting time in the case where the peer end cannot return the credit value, resulting in congestion of the local end's sent messages, avoiding device operation failures caused by the CPU not receiving the read response, and improving the reliability of the operation of the PCIe data transmission system.

[0086] The data transmission system in this embodiment is presented in the form of functional units. Here, the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and a memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0087] An embodiment of the present application also provides a computer device, which can be implemented as the central device in the PCIe data transmission system shown in the embodiment of the present application to implement congestion control based on PCIe. Please refer to Figure 5 , Figure 5 FIG. is a schematic structural diagram of a computer device provided by an optional embodiment of the present application. As shown in Figure 5 , the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Each component communicates with each other using different buses and can be installed on a common motherboard or installed in other ways as needed. The processor can process instructions executed within the computer device, including instructions stored in the memory or on the memory to display graphic information in a graphical user interface on an external input / output device (such as a display device coupled to the interface). In some alternative embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (such as a server array, a set of blade servers, or a multi-processor system). Figure 5 In [reference], one processor 10 is taken as an example.

[0088] The processor 10 can be a central processor, a network processor, or a combination thereof. Among them, the processor 10 can further include a hardware chip. The above hardware chip can be an application specific integrated circuit, a programmable logic device, or a combination thereof. The above programmable logic device can be a complex programmable logic device, a field programmable gate array, a generic array logic, or any combination thereof.

[0089] Among them, the memory 20 stores instructions executable by at least one processor 10, so that at least one processor 10 executes the method shown in the above embodiment.

[0090] The memory 20 may include a program storage area and a data storage area. Among them, the program storage area can store an operating system and application programs required for at least one function; the data storage area can store data created according to the use of the computer device and the like. In addition, the memory 20 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state storage devices. In some alternative embodiments, the memory 20 may optionally include a memory remotely provided with respect to the processor 10, and these remote memories can be connected to the computer device through a network. Examples of the above network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0091] The memory 20 may include volatile memory, for example, random access memory; the memory may also include non-volatile memory, for example, flash memory, a hard disk, or a solid-state drive; the memory 20 may further include a combination of the above types of memory.

[0092] The computer device further includes a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0093] The embodiments of the present application also provide a computer-readable storage medium. The methods according to the embodiments of the present application can be implemented in hardware, firmware, or be implemented as computer code that can be recorded on a storage medium, or be implemented as computer code originally stored in a remote storage medium or a non-transitory machine-readable storage medium and downloaded through a network and to be stored in a local storage medium, so that the methods described herein can be stored in such software processes on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid-state drive, etc.; further, the storage medium can also include a combination of the above types of memory. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code, and when the software or computer code is accessed and executed by the computer, the processor, or the hardware, the methods shown in the above embodiments are implemented.

[0094] A part of this application can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can call or provide the methods and / or technical solutions according to this application through the operations of the computer. Those skilled in the art should understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executes the instructions, or the computer compiles the instructions and then executes the corresponding compiled program, or the computer reads and executes the instructions, or the computer reads and installs the instructions and then executes the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to the computer.

[0095] Although the embodiments of this application are described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A congestion control method in PCIe, characterized in that: The method is applied to a PCIe data transmission system, wherein the PCIe data transmission system includes a central device and at least two PCIe links, wherein the central device communicates with corresponding PCIe devices through the at least two PCIe links respectively, and the method includes: When it is detected that the credit value of the target message to be sent in the target PCIe link does not meet the sending condition, the timer is triggered; When the timing of the timer reaches the maximum waiting time, the target PCIe link is closed and congestion information of the target PCIe link is reported.

2. The method according to claim 1, characterized in that The method further comprises: If a change in the credit value of the target message is detected before the timer reaches the maximum waiting time, and the changed credit value meets the sending condition, the timer is set to 0.

3. The method according to claim 1, characterized in that When it is detected that the credit value of the target message to be sent in the target PCIe link does not meet the sending condition, triggering the timer includes: When it is detected that the credit value of the target message to be sent in the target PCIe link does not meet the sending condition and the target PCIe link enables the flow control function, the timer is triggered.

4. The method according to claim 3, characterized in that The method further comprises: If a change in the credit value of the target message is detected before the timer reaches the maximum waiting time, and the changed credit value meets the sending condition, the timer is set to 0; Alternatively, if it is detected that the target PCIe link has disabled the flow control function before the timer reaches the maximum waiting time, the timer is set to 0.

5. A congestion control device in PCIe, characterized in that: The device is applied to a PCIe data transmission system, wherein the PCIe data transmission system includes a central device and at least two PCIe links, wherein the central device communicates with corresponding PCIe devices through at least two PCIe links respectively; the device includes: A blocking timer is used to be triggered when it is detected that the credit value of the target message to be sent in the target PCIe link does not meet the sending condition; A comparator; a first input terminal of the comparator is connected to an output terminal of the blocking timer; a second input terminal of the comparator is connected to a maximum waiting time; status register; the first input end of the status register is connected to the output end of the comparator; the output end of the status register is used to output a disable signal; the disable signal is used to close the target PCIe link.

6. The device according to claim 5, characterized in that The apparatus further comprises a first logic unit; The first input end of the first logic unit is connected to a credit check flag; the second input end of the first logic unit is connected to a function start signal; the output end of the first logic unit is connected to the blocking timer reset end; when the target message credit value does not meet the sending condition, the credit check flag is a low level; when the target PCIe link enables the flow control function, the function start signal is a high level; The first logic unit is used for outputting a low level at the output terminal when the credit check flag is at a low level and the function start signal is at a high level.

7. The device according to claim 6, characterized in that The first logic unit is also used for outputting a high level at the output terminal when the credit check flag is at a high level and the function start signal is at a low level; The first logic unit is also used for outputting a high level at the output terminal when the credit check flag is at a high level and the function start signal is at a high level; The first logic unit is also used for the output terminal to output a high level when the credit check flag is at a low level and the function start signal is at a low level.

8. The device according to claim 6, characterized in that The second input terminal of the status register is also used to receive the function start signal; When the first input terminal of the status register is at a high level and the second input terminal of the status register is at a high level, the output terminal of the status register outputs a prohibition signal.

9. The device according to claim 8, characterized in that When the second input terminal of the status register is at a low level, the status register is reset.

10. The device according to any one of claims 6 to 9, characterized in that: The device further comprises a second logic unit; a first input end of the second logic unit is used to access a preconfigured disable signal; a second input end of the second logic unit is used to access a disable signal output by a status register; When at least one of the first input terminal of the second logic unit and the second input terminal of the second logic unit is at a high level, the second logic unit sends a link closing signal to close the target PCIe link through a physical layer.

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