Frequency detector for optical coding system and method for operating same

Abstract

A light source control circuit includes a light detector, a frequency detector, a differential amplifier, an NMOS driver, and a light source. The frequency detector determines a signal frequency according to a detection voltage signal output by the light detector and generates a control signal according to the signal frequency. The NMOS driver changes the driving current of the light source according to the output of the differential amplifier. The differential amplifier varies its bandwidth according to a control signal from the frequency detector to adjust a response time to vary the drive current of the light source.

Description

[0001] This application is a divisional application of a Chinese invention patent application with the application number 202110660538.5, the application date of June 15, 2021, and the title "Light source control circuit adaptable to input signal frequency and its operation method". Technical Field

[0002] The present invention relates to a light source control circuit, and more particularly to a light source control circuit adaptable to frequency changes of an input signal in an optical encoding system and its operation method. Background Art

[0003] Optical detection systems generally require the detected light intensity to be stable, and one way is to control the system light source to maintain a stable emission intensity.

[0004] For example, Figure 1 shows a known optical detection system, which includes a photodetector 91, a reference voltage generator 93, a differential amplifier 95, an NMOS driver 97, and a light emitting diode LED. The photodetector 91 is used to detect modulated light to generate a detection signal, for example, Figure 2A as shown. The photodetector 91 also extracts the common mode voltage V CM of the detection signal as the output signal Vdet. The reference voltage generator 93 outputs a reference voltage Vref based on the expected common mode voltage. The differential amplifier 95 then compares the output signal Vdet and the reference voltage Vref to eliminate common mode noise. The NMOS driver 97 adjusts the drive current of the light emitting diode LED according to the output of the differential amplifier 95 to control its emission intensity.

[0005] However, the signal frequency of the output signal Vdet of the photodetector 91 changes with the rotation speed of the detected axis, so it is desired that the regulation response time for adjusting the light emitting diode LED can also change with the signal frequency of the output signal Vdet.

[0006] In view of this, a light source control circuit for an optical encoding system and its operation method that can adapt to frequency changes of a detection signal are needed. Summary of the Invention

[0007] The present invention provides a light source control circuit for an optical encoding system and its operation method that adjusts the regulation rate of a light source drive current according to a comparison result between a detection signal frequency and at least one frequency threshold.

[0008] The present invention also provides a light source control circuit and an operating method thereof for an optical encoding system, which can adjust the driving current of a light source in different directions for the encoding medium of the optical encoding system to regulate the response time.

[0009] The present invention provides a frequency detector for an optical encoding system, which includes a low-pass filter, a first comparator, a second comparator, and a flip-flop. The frequency detector is used to receive a first detection signal and a second detection signal from a differential amplifier of the optical encoding system. The low-pass filter is used to filter the first detection signal and has a cut-off frequency. The first comparator is used to compare the filtered first detection signal with a first reference voltage to output a comparison signal. The second comparator is used to compare the second detection signal with a second reference voltage to output a clock signal. The data input terminal of the flip-flop is used to receive the comparison signal, its clock input is used to receive the clock signal, and its output terminal is used to generate an output signal when the phase of the first detection signal leads the phase of the second detection signal, so as to change the bandwidth of the differential amplifier of the optical encoding system.

[0010] The present invention also provides an operating method for a frequency detector of an optical encoding system. The optical encoding system includes a differential amplifier. The frequency detector includes a low-pass filter, a first comparator, a second comparator, and a first flip-flop. The operating method includes the following steps: receiving a first detection signal from the differential amplifier by the low-pass filter and outputting the filtered first detection signal; comparing the filtered first detection signal with a first reference voltage by the first comparator to output a comparison signal; receiving a second detection signal from the differential amplifier by the second comparator and comparing the second detection signal with a second reference voltage to output a clock signal, wherein the phase of the first detection signal leads or lags the second detection signal by 90 degrees; and when the phase of the first detection signal leads the phase of the second detection signal, receiving the comparison signal and the clock signal by the first flip-flop and generating a first output signal to change the bandwidth of the differential amplifier of the optical encoding system.

[0011] In the light source control circuit according to an embodiment of the present invention, the reference voltage generating circuit can be composed of a fixed voltage source, a circuit including a reference square circuit and a conversion circuit, or other voltage generators.

[0012] In the optical encoding system of the present invention, different codes are made on the encoding medium to modulate the incident light. The modulated reflected light is incident on different photodiodes of a photodetector to generate current signals with a 90-degree phase difference from each other, such as a sine signal and a cosine signal. A transresistance amplifier is used to amplify the current signals and convert them into voltage signals.

[0013] To make the above and other objects, features, and advantages of the present invention more apparent, the following will be described in detail with reference to the accompanying drawings. In addition, in the description of the present invention, the same components are denoted by the same reference numerals, which are hereby stated in advance. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a schematic diagram of a known light source control circuit;

[0015] Figure 2A is Figure 1 the voltage signal without DC offset output by the light source control circuit of

[0016] Figure 2B is Figure 1 the voltage signal with DC offset output by the light source control circuit of

[0017] Figure 3 is a schematic diagram of an optical encoding system according to an embodiment of the present invention;

[0018] Figure 4 is a block diagram of a light source control circuit according to an embodiment of the present invention;

[0019] Figure 5 is a schematic diagram of a common-mode voltage circuit of a light source control circuit according to an embodiment of the present invention;

[0020] Figure 6 is a circuit diagram of a square circuit of a light source control circuit according to an embodiment of the present invention;

[0021] Figure 7 is a partial circuit diagram of a controller of a light source control circuit according to an embodiment of the present invention;

[0022] Figure 8 is a schematic diagram of the sum of current squares of a light source control circuit according to an embodiment of the present invention;

[0023] Figure 9 is a circuit diagram of a light source control circuit according to an embodiment of the present invention;

[0024] Figure 10A is a block schematic diagram of a light source control circuit according to another embodiment of the present invention;

[0025] Figure 10B is another block schematic diagram of a light source control circuit according to another embodiment of the present invention;

[0026] Figure 11 is a block schematic diagram of a frequency detector of a light source control circuit according to another embodiment of the present invention;

[0027] Figures 12A - 12F is a signal timing diagram of a frequency detector of a light source control circuit according to another embodiment of the present invention, wherein the signal frequency is lower than the cut-off frequency;

[0028] Figures 13A - 13F It is a signal timing diagram of the frequency detector of the light source control circuit according to another embodiment of the present invention, where the signal frequency is higher than the cut-off frequency;

[0029] Figures 14A - 14F It is a signal timing diagram of the frequency detector of the light source control circuit according to another embodiment of the present invention, where the rotation direction of the encoding medium is Figures 12A - 12F opposite;

[0030] Figure 15 It is a schematic block diagram of the light source control circuit according to still another embodiment of the present invention; and

[0031] Figure 16 It is a flowchart of the operation method of the light source control circuit according to another embodiment of the present invention.

[0032] Description of Reference Numerals

[0033] 100, 100’, 100” Optical Encoding System

[0034] 10 Controller

[0035] 20 Reference Voltage Generation Circuit

[0036] 30 Light Source

[0037] 40 Encoding Medium

[0038] 50 Photo-detector

[0039] 60 Transresistance Amplifier

[0040] 70 Frequency Detector

[0041] 71 Low-pass Filter

[0042] 72 First Comparator

[0043] 73 Second Comparator

[0044] 74 First Flip-flop

[0045] 75 Second Inverter

[0046] 76 First Inverter

[0047] 77 Second Flip-flop

[0048] 78 OR Gate Detailed Description of the Invention

[0049] Please refer to Figure 3As shown, it is a schematic diagram of the optical encoding system 100 according to an embodiment of the present invention. The optical encoding system 100 includes a controller 10, a reference voltage generation circuit 20, a light source 30, an encoding medium 40, a photodetector 50, and a trans-impedance amplifier (TIA) 60. In a non-limiting embodiment, the controller 10, the reference voltage generation circuit 20, the light source 30, the photodetector 50, and the trans-impedance amplifier 60 of the optical encoding system 100 are formed, for example, in the same package to form a control module, and decoding operations can be performed as long as they are arranged relative to the encoding medium 40.

[0050] In a non-limiting embodiment, the controller 10, the reference voltage generation circuit 20, and the trans-impedance amplifier 60 form the light source control circuit of the embodiment of the present invention, which is used to control the light source 30 to emit light with a stable intensity according to the detection result of the photodetector 50.

[0051] The encoding medium 40 is, for example, a code disk, on which different encodings are formed to modulate the incident light from the light source 30. The light source 30 is, for example, a light-emitting diode or a laser diode, which is used to emit emitted light Le with a predetermined wavelength (such as red light or infrared light) to irradiate the encoding medium 40, so as to generate modulated reflected light Lm through the encodings on the encoding medium 40. Figure 3 It is shown that the code disk is controlled by a motor to rotate counterclockwise, so different encodings on it are irradiated by the emitted light Le of the light source 30 to generate modulated reflected light Lm. Since the encoding method of the encoding medium 40 is not the purpose of the present invention, as long as the photodetector 50 can detect the modulated reflected light Lm to generate a predetermined current signal (illustrated later), any known method can be used for encoding.

[0052] The optical detector 50 is disposed at an appropriate position to receive the modulated reflected light Lm. The optical detector 50 is, for example, a CCD image sensor, a CMOS image sensor, or other sensors for detecting light energy to generate an electrical signal. For example, the optical detector 50 includes a first photodiode PD1, a second photodiode PD2, a third photodiode PD3, and a fourth photodiode PD4 for receiving the modulated reflected light Lm and respectively generating a first current signal I_sin-, a second current signal I_sin+, a third current signal I_cos-, and a fourth current signal I_cos+, wherein the first current signal I_sin- and the second current signal I_sin+ (e.g., a sine signal) are in opposite phases, and the third current signal I_cos- and the fourth current signal I_cos+ (e.g., a cosine signal) are in opposite phases. The first current signal I_sin- and the third current signal I_cos- have a 90-degree phase difference (orthogonal), and the second current signal I_sin+ and the fourth current signal I_cos+ have a 90-degree phase difference (orthogonal).

[0053] It should be noted that although Figure 3 only four photodiodes PD1 to PD4 are shown, the present invention is not limited thereto. In a non-limiting embodiment, Figure 3 each of the photodiodes PD1 to PD4 may include a plurality of photodiodes, and each current signal is the average current or the sum of currents for each group of the plurality of photodiodes. For example, the first current signal I_sin- is the average output current or the sum of currents of a plurality of first photodiodes PD1, the second current signal I_sin+ is the average output current or the sum of currents of a plurality of second photodiodes PD2, and so on.

[0054] The transimpedance amplifier (TIA) 60 may use a known single-stage or multi-stage transimpedance amplifier without specific limitation as long as it can amplify the input signal to a predetermined peak-to-peak value (e.g., but not limited to, 1 volt peak-to-peak) with a predetermined gain. The transimpedance amplifier 60 is used to amplify and convert the first current signal I_sin-, the second current signal I_sin+, the third current signal I_cos-, and the fourth current signal I_cos+ to respectively generate and output a first detection signal V_sin-, a second detection signal V_sin+, a third detection signal V_cos-, and a fourth detection signal V_cos+, wherein the first detection signal V_sin- and the third detection signal V_cos- have a 90-degree phase difference, the third detection signal V_cos- and the second detection signal V_sin+ have a 90-degree phase difference, and the second detection signal V_sin+ and the fourth detection signal V_cos+ have a 90-degree phase difference.

[0055] In one embodiment, when the transresistance amplifier 60 performs current-voltage conversion, it does not change the phases of the first current signal I_sin-, the second current signal I_sin+, the third current signal I_cos-, and the fourth current signal I_cos+. Therefore, the first detection signal V_sin-, the second detection signal V_sin+, the third detection signal V_cos-, and the fourth detection signal V_cos+ have the same phases as the first current signal I_sin-, the second current signal I_sin+, the third current signal I_cos-, and the fourth current signal I_cos+ respectively.

[0056] In another embodiment, when the transresistance amplifier 60 performs current-voltage conversion, it changes the same phases of the first current signal I_sin-, the second current signal I_sin+, the third current signal I_cos-, and the fourth current signal I_cos+. Therefore, the first detection signal V_sin-, the second detection signal V_sin+, the third detection signal V_cos-, and the fourth detection signal V_cos+ have the same phase differences as the first current signal I_sin-, the second current signal I_sin+, the third current signal I_cos-, and the fourth current signal I_cos+ respectively. That is, the phase relationships among the first detection signal V_sin-, the second detection signal V_sin+, the third detection signal V_cos-, and the fourth detection signal V_cos+ are the same as the phase relationships among the first current signal I_sin-, the second current signal I_sin+, the third current signal I_cos-, and the fourth current signal I_cos+.

[0057] Please refer to Figure 4 , which is a block diagram of the light source control circuit according to an embodiment of the present invention. It should be noted that although Figure 3 the reference voltage generation circuit 20 and the transresistance amplifier 60 are shown to be disposed outside the controller 10, the present invention is not limited thereto. In a non-limiting embodiment, the reference voltage generation circuit 20 and the transresistance amplifier 60 may be included within the controller 10.

[0058] The detection voltage generation circuit 101 of the controller 10 includes a common-mode voltage circuit 110, a first squaring circuit 111, a second squaring circuit 113, a sum-of-squares circuit, and a first conversion circuit 115. The controller 10 further includes a differential amplifier (error amplifier) 13 and an NMOS driver 15.

[0059] The common-mode voltage circuit 110 includes an averaging resistor circuit for averaging the first detection signal V_sin-, the second detection signal V_sin+, the third detection signal V_cos-, and the fourth detection signal V_cos+. For example, refer to Figure 5, the average resistance circuit of the common-mode voltage circuit 110 includes an average resistance R1 that receives the first detection signal V_sin-, an average resistance R2 that receives the second detection signal V_sin+, an average resistance R3 that receives the third detection signal V_cos-, and an average resistance R4 that receives the fourth detection signal V_cos+. The average resistance circuit of the common-mode voltage circuit 110 further includes an average resistance R5 connected to the average resistances R1 and R2, and an average resistance R6 connected to the average resistances R3 and R4. The common-mode voltage circuit 110 generates a common-mode voltage signal V based on the first detection signal V_sin-, the second detection signal V_sin+, the third detection signal V_cos-, and the fourth detection signal V_cos+ CM .

[0060] The first squaring circuit 111 is configured to receive the first detection signal V_sin-, the second detection signal V_sin+, and the common-mode voltage signal V CM and output a first current squared signal I_sin 2 . Please refer to Figure 6 , which is the circuit diagram of the first squaring circuit 111 of the embodiment of the present invention. The first squaring circuit 111 includes a first transistor group 1111, a second transistor group 1113, a first subtraction circuit 1115, and a first bias circuit 1117. Figure 6 It is shown that the transistors of the first transistor group 1111, the second transistor group 1113, and the first bias circuit 1117 are PMOS transistors, while the transistors of the first subtraction circuit 1115 are NMOS transistors, but the present invention is not limited thereto.

[0061] As Figure 6 shown, the first transistor group 1111 includes two transistors M1 and M2 with their drains connected to each other and their sources connected to each other. The gates of the two transistors M1 and M2 of the first transistor group 1111 respectively receive the common-mode voltage signal V CM . The first transistor group 1111 is configured to output a first current I1.

[0062] As Figure 6 shown, the second transistor group 1113 includes two transistors M3 and M4 with their drains connected to each other and their sources connected to each other. The gates of the two transistors M3 and M4 of the second transistor group 1113 respectively receive the first detection signal V_sin- and the second detection signal V_sin+. The second transistor group 1113 is configured to output a second current I2.

[0063] As Figure 6As shown, the first bias circuit 1117 is connected between the voltage source Vs and the first transistor group 1111 and the second transistor group 1113. The first bias circuit 1117 includes two transistors M10 and M10' with gates interconnected. The sources of the two transistors M10 and M10' of the first bias circuit 1117 are connected to the voltage source Vs. The gate of one of the two transistors of the first bias circuit 1117 (shown here as M10) is connected to its drain. The drain of the other of the two transistors of the first bias circuit 1117 (shown here as M10') is connected to the sources of the two transistors M1 and M2 of the first transistor group 1111 and the sources of the two transistors M3 and M4 of the second transistor group 1113.

[0064] As Figure 6 shown, the first subtraction circuit 1115 is connected between the ground voltage Vg and the first transistor group 1111 and the second transistor group 1113. The first subtraction circuit 1115 is used to perform a difference on the first current I1 and the second current I2 to generate a first current square signal I_sin 2 .

[0065] According to the transistor principle, the drain current Id3 of transistor M3 can be expressed by Equation (1)

[0066] Id3 = [Vs - (V G + Vamp1) - Vtp] 2 × K / 2 = (Vr - Vamp1) 2 × K / 2 (1)

[0067] where, Vr = Vs - V G - Vtp, V G is the gate voltage of transistor M3, Vamp1 is the amplitude of V_sin-, K is the conductive parameter, and Vtp is the threshold voltage.

[0068] Similarly, the drain current Id4 of transistor M4 can be expressed by Equation (2)

[0069] Id4 = (Vr - Vamp2) 2 × K / 2 (2)

[0070] where, Vamp2 is the amplitude of V_sin+

[0071] Similarly, the drain current Id1 of transistor M1 and the drain current Id2 of transistor M2 can be expressed by Equation (3)

[0072] Id1 = Id2 = K × Vr 2(3)

[0073] Assume Vamp1 = Vamp2 = Vamp, then (Id3 + Id4) - (Id1 + Id2) = K × Vamp 2 = I_sin 2 , which is referred to as the first current square signal in this specification.

[0074] The first subtraction circuit 1115 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a ninth transistor M9.

[0075] The gate of the fifth transistor M5 is connected to its drain, and the drain of the fifth transistor M5 is connected to the drains of the two transistors M1 and M2 of the first transistor group 1111 to receive the first current I1.

[0076] The gate of the sixth transistor M6 is connected to the gate of the fifth transistor M5, and the drain of the sixth transistor M6 is connected to the drains of the two transistors M3 and M4 of the second transistor group 1113 to receive the second current I2.

[0077] The gate of the seventh transistor M7 is connected to its drain, the drain of the seventh transistor M7 is connected to the source of the fifth transistor M5, and the source of the seventh transistor M7 is connected to the ground voltage Vg.

[0078] The gate of the eighth transistor M8 is connected to the gate of the seventh transistor M7, the drain of the eighth transistor M8 is connected to the source of the sixth transistor M6, and the source of the eighth transistor M8 is connected to the ground voltage Vg.

[0079] The gate of the ninth transistor M9 is connected to its drain, the drain of the ninth transistor M9 is connected between the drain of the sixth transistor M6 and the second transistor group 1113, and the source of the ninth transistor M9 is connected to the ground voltage Vg. The first current square signal I_sin 2 flows through the ninth transistor M9.

[0080] It should be noted that although Figure 6 it shows that the first current I1 flows through two series-connected transistors M5 and M7, and the second current I2 flows through two series-connected transistors M6 and M8, the present invention is not limited thereto. The number of transistors through which the first current I1 and the second current I2 respectively flow is not limited to 2, and this number is determined according to circuit parameters.

[0081] The second square circuit 113 is used to receive the third detection signal V_cos-, the fourth detection signal V_cos+, and the common-mode voltage signal V CM and output the second current square signal I_cos 2 .

[0082] Please refer toFigure 7 , which is a partial circuit diagram of the controller 10 according to an embodiment of the present invention. The second squaring circuit 113 is similar to the first squaring circuit 111, and the main difference between them is the different detection signals received by the two. The second squaring circuit 113 includes a third transistor group M11 and M12, a fourth transistor group M13 and M14, a second bias circuit, and a second subtraction circuit. To simplify the drawing, Figure 7 the third transistor group, the fourth transistor group, the second bias circuit, and the second subtraction circuit are not labeled with reference numerals.

[0083] Figure 7 It is shown that the transistors of the third transistor group, the fourth transistor group, and the second bias circuit are PMOS transistors, while the transistors of the second subtraction circuit are NMOS transistors, but this is not limited thereto.

[0084] As Figure 7 shown, the third transistor group includes two transistors M11 and M12 with their drains connected to each other and their sources connected to each other. The gates of the two transistors M11 and M12 of the third transistor group respectively receive the common-mode voltage signal V CM . The third transistor group is used to output a third current I3.

[0085] As Figure 7 shown, the fourth transistor group includes two transistors M13 and M14 with their drains connected to each other and their sources connected to each other. The gates of the two transistors M13 and M14 of the fourth transistor group respectively receive a third detection signal V_cos- and a fourth detection signal V_cos+. The fourth transistor group is used to output a fourth current I4.

[0086] As Figure 7 shown, the second bias circuit is connected between the voltage source Vs and the third transistor group and the fourth transistor group. The second bias circuit includes two transistors M10 and M10” with their gates connected to each other. The sources of the two transistors M10 and M10” of the second bias circuit are connected to the voltage source Vs. The gate of one of the two transistors of the second bias circuit (shown as M10 here) is connected to its drain, and the drain of the other of the two transistors of the second bias circuit (shown as M10” here) is connected to the sources of the two transistors M11 and M12 of the third transistor group and the sources of the two transistors M13 and M14 of the fourth transistor group.

[0087] As Figure 7 shown, the second subtraction circuit is connected between the ground voltage Vg and the third transistor group and the fourth transistor group, and is used to perform a difference on the third current I3 and the fourth current I4 to generate a second current square signal I_cos 2, wherein the second squaring circuit 113 generates a second current squared signal I_cos according to the third current I3 and the fourth current I4 2 in a manner similar to that in which the first squaring circuit 111 generates the first current squared signal I_sin 2 , for example, referring to equations (1)-(3), so it will not be elaborated herein. The second subtraction circuit includes transistors M15, M16, M17, M18, and M19, and their connection manner and functions are similar to those of the first subtraction circuit 1115 and have been shown in Figure 7 , so it will not be elaborated herein.

[0088] Please refer to Figure 7 , the sum-of-squares circuit 1151 is used to calculate the sum of squares of the currents of the first current squared signal I_sin 2 and the second squaring circuit I_cos 2 (I_sin 2 + I_cos 2 ) to generate a DC signal Idetect. Please refer to Figure 8 as shown.

[0089] The sum-of-squares circuit 1151 includes a fifth transistor group M9' and M19' and a sum-of-squares transistor M40, where Figure 7 it is shown that the fifth transistor group includes NMOS transistors and the sum-of-squares transistor M40 is a PMOS transistor, but the present invention is not limited thereto. The fifth transistor group includes two transistors M9' and M19' with their drains connected to each other and their sources connected to each other. The gates of the two transistors M9' and M19' of the fifth transistor group are respectively connected to the gate of the transistor M9 of the first subtraction circuit 1115 and the gate of the transistor M19 of the second subtraction circuit to mirror the first current squared signal I_sin 2 and the second current squared signal I_cos 2 . That is, the transistor M9' and the transistor M9 form a current mirror; the transistor M19' and the transistor M19 form another current mirror. Here, it is assumed that the mirror ratio of the current mirror is 1.

[0090] The source of the sum-of-squares transistor M40 is connected to the voltage source Vs, the gate of the sum-of-squares transistor M40 is connected to its drain, and the drain of the sum-of-squares transistor M40 is connected to the drains of the two transistors M9' and M19' of the fifth transistor group, and is used to generate the sum of squares of the currents Idetect = (I_sin 2 + I_cos 2 ).

[0091] Please refer to Figure 9As shown, it is the circuit diagram of the light source control circuit according to an embodiment of the present invention. The first conversion circuit 1153 is used to convert the sum of squared currents Idetect into a detection voltage signal Vdetect. The first conversion circuit 1153 includes a first conversion transistor M40' and a first conversion resistor Rt1 that are connected to each other.

[0092] The gate of the first conversion transistor M40' is connected to the gate of the sum-of-squares transistor M40 to generate a mirror current Im of the sum of squared currents (I_sin 2 +I_cos 2 ). When the mirror ratio is 1, the mirror current Im is approximately equal to the sum of squared currents Idetect = (I_sin 2 +I_cos 2 ).

[0093] When the mirror current Im of the sum of squared currents flows through the first conversion resistor Rt1, the detection voltage signal Vdetect is generated. Thus, the detection voltage generation circuit 101 converts voltage signals of different phases (such as Figure 5 shown) into a DC signal, which is used as a negative feedback signal for controlling the drive current of the light source 30.

[0094] The reference voltage generation circuit 20 is used to generate a reference voltage signal Vref to one input terminal of the differential amplifier 13, such as Figure 4 shown as the positive input terminal. The reference voltage signal Vref is a predetermined voltage value used to control the NMOS driver 15 to drive the light source 30 with a desired drive current.

[0095] In a non-limiting embodiment, the reference voltage generation circuit 20 includes a constant voltage source for outputting the reference voltage signal Vref.

[0096] In a non-limiting embodiment, as Figure 4 shown, the reference voltage generation circuit 20 includes a reference voltage generator 210, a reference squaring circuit 211, and a second conversion circuit 215. The reference squaring circuit 211 uses the same circuit structure as the first squaring circuit 111 to cope with environmental (voltage, temperature) changes, and the difference is that the input voltage signals of the two are different.

[0097] The reference voltage generator 210 is used to generate a desired first amplitude voltage V HIGH , a desired second amplitude voltage V LOW , and a desired common-mode voltage V CMP (all determined in advance), where the desired common-mode voltage V CMP is the average value of the desired first amplitude voltage V HIGH and the desired second amplitude voltage V LOW , and the desired first amplitude voltage VHIGH higher than the desired second amplitude voltage V LOW . In a non-limiting embodiment, the first amplitude voltage V HIGH and the desired second amplitude voltage V LOW are selected according to product specifications. The desired common-mode voltage V CMP is a predetermined voltage value that defines the magnitude of the drive current for driving the light source 30. That is, when the detected voltage signal Vdetect is greater than the desired common-mode voltage V CMP , the NMOS driver 15 reduces the drive current of the light source 30 to reduce the light emission intensity; conversely, when the detected voltage signal Vdetect is less than the desired common-mode voltage V CMP , the NMOS driver 15 increases the light emission intensity of the light source 30 to maintain a substantially constant drive current.

[0098] The reference square circuit 211 is used to receive the desired first amplitude voltage V HIGH , the desired second amplitude voltage V LOW and the desired common-mode voltage V CMP and output a reference current square signal Iref 2 . The second conversion circuit 215 includes a second conversion transistor M50' and a second conversion resistor Rt2 connected to each other for converting the reference current square signal Iref 2 into a reference voltage signal Vref. The functions of the second conversion transistor M50' and the second conversion resistor Rt2 are similar to those of the first conversion transistor M40' and the first conversion resistor Rt1.

[0099] For example, referring to Figure 9 , the reference square circuit 211 includes a sixth transistor group M21 and M22, a seventh transistor group M23 and M24, a third bias circuit M30 and M30', a third subtraction circuit M25 to M29, and a current mirror circuit M50 and M29'.

[0100] As Figure 9 shown, the sixth transistor group includes two transistors M21 and M22 with their drains connected to each other and their sources connected to each other (shown here as PMOS transistors), and the gates of the two transistors M21 and M22 of the sixth transistor group respectively receive the desired common-mode voltage V CMP . The sixth transistor group is used to output a sixth current I6.

[0101] As Figure 9 shown, the seventh transistor group includes two transistors M23 and M24 with their drains connected to each other and their sources connected to each other (shown here as PMOS transistors), and the gates of the two transistors M23 and M24 of the seventh transistor group respectively receive the desired second amplitude voltage V LOWand the desired first amplitude voltage V HIGH The seventh transistor group is used to output a seventh current I7.

[0102] The third bias circuit is connected between the voltage source Vs and the sixth transistor group and the seventh transistor group. For example, the third bias circuit includes two transistors M30 and M30' with gates interconnected (shown here as PMOS transistors). The sources of the two transistors M30 and M30' of the third bias circuit are connected to the voltage source Vs. The gate of one of the two transistors of the third bias circuit (shown here as M30) is connected to its drain. The drain of the other of the two transistors of the third bias circuit (shown here as M30') is connected to the sources of the two transistors M21 and M22 of the sixth transistor group and the sources of the two transistors M23 and M24 of the seventh transistor group.

[0103] The third subtraction circuit is connected between the ground voltage Vg and the sixth transistor group and the seventh transistor group, and is used to perform a difference between the sixth current I6 and the seventh current I7 to generate a reference current square signal Iref 2 For example, the third subtraction circuit includes a transistor M25, a transistor M26, a transistor M27, a transistor M28, and a transistor M29, where Figure 9 It is shown that all components included in the third subtraction circuit are NMOS transistors, but it is not limited thereto.

[0104] The gate of the transistor M25 is connected to its drain, and the drain of the transistor M25 is connected to the drains of the two transistors M21 and M22 of the sixth transistor group to receive the sixth current I6.

[0105] The gate of the transistor M26 is connected to the gate of the transistor M25, and the drain of the transistor M26 is connected to the drains of the two transistors M23 and M24 of the seventh transistor group to receive the seventh current I7.

[0106] The gate of the transistor M27 is connected to its drain, the drain of the transistor M27 is connected to the source of the transistor M25, and the source of the transistor M27 is connected to the ground voltage Vg.

[0107] The gate of the transistor M28 is connected to the gate of the transistor M27, the drain of the transistor M28 is connected to the source of the transistor M26, and the source of the transistor M28 is connected to the ground voltage Vg.

[0108] The gate of the transistor M29 is connected to its drain, the drain of the transistor M29 is connected between the drain of the transistor M26 and the seventh transistor group, and the source of the transistor M29 is connected to the ground voltage Vg. The drain current of the transistor M29 is the subtraction of the seventh current I7 from the sixth current I6 to serve as the reference current square signal Iref2 . Generate Iref 2 in a manner similar to I_sin 2 , so equations (1) to (3) can be referred to.

[0109] The current mirror circuit is used to generate the reference current squared signal Iref 2 of the first mirror current Im1. When the mirror ratio is 1, the first mirror current Im1 is approximately equal to the reference current squared signal Iref 2 . The current mirror circuit includes a transistor M29' to form a current mirror with transistor M29, and includes a transistor M50 to form a current mirror with the second conversion transistor M50' in the second conversion circuit 25.

[0110] The second conversion circuit 25 includes a second conversion transistor M50' and a second conversion resistor Rt2 connected to each other. The gate of the second conversion transistor M50' is connected to the gate of the transistor M50 of the current mirror circuit to mirror the first mirror current Im1 to generate the reference current squared signal Iref 2 of the second mirror current Im2. Similarly, when the mirror ratio of the second current mirrors M50 and M50' is 1, the second mirror current Im2 is equal to the reference current squared signal Iref 2 . When the second mirror current Im2 of the reference current squared signal Iref 2 flows through the second conversion resistor Rt2, a reference voltage signal Vref is generated.

[0111] The connection of other components not described can be referred to Figure 9 as shown.

[0112] The first input terminal (shown as the - terminal here) of the differential amplifier 13 receives the detection voltage signal Vdetect, and the second input terminal (shown as the + terminal here) of the differential amplifier 13 receives the reference voltage signal Vref for comparison. It should be noted that the voltage signals received by the first input terminal and the second input terminal of the differential amplifier 13 can be interchanged.

[0113] The NMOS driver 15 is connected to the output terminal of the differential amplifier 13 and is used to adjust its drain current Id according to the comparison result output by the differential amplifier 13, where the drain current Id is used as the drive current of the light source 30.

[0114] It should be noted that although in the above embodiments, the mirror ratio of each current mirror is assumed to be 1 for illustration, it is not intended to limit the present invention. As long as the reference voltage signal Vref input to the differential amplifier 13 is controlled to the desired value, the mirror ratio of each current mirror can be not 1.

[0115] It should be noted that although in the above embodiments, the encoded medium 40 is described by taking the reflective and rotational motion as an example, the present invention is not limited thereto. In other embodiments, the encoded medium 40 can be transmissive (i.e., the light source and the light detector are located on different sides thereof), and the encoded medium 40 is transparent or semi-transparent to the light of the light source 30. In other embodiments, the encoded medium 40 can perform linear motion in one dimension, two dimensions or three dimensions.

[0116] It should be noted that although in the above embodiments, the light source control circuit is described by taking the application to the optical encoding system 100 as an example, the present invention is not limited thereto. The light source control circuit can be applied to any application that requires stable control of the luminous intensity of the light source. In addition, controlling the luminous intensity of the light source is not limited to controlling its drive current, and its drive voltage can also be controlled, depending on the light source used. For example, the drain current flowing through the NMOS driver is made to flow through a resistor to generate a drive voltage.

[0117] The present invention also provides an optical encoding system 100' and 100" that adjusts the adjustment response time of the drain current of the NMOS driver according to the rotation speed of the encoded medium 40 (relative to the rotation speed of the motor). The optical encoding systems 100' and 100" detect the signal frequency of the detection signal related to the encoded medium 40 (which is determined by the rotation speed of the encoded medium 40) by using a frequency detector 70. The control signal I_ctrl output by the frequency detector 70 is used to turn on or off the bias current 131 in the differential amplifier 13 to adjust the response time of the drive current (i.e., the drain current) of the light source 30.

[0118] Please refer to Figure 10A , which is a block schematic diagram of an optical encoding system 100' according to another embodiment of the present invention. Figure 10A Differing from Figure 3 is that Figure 10A the optical encoding system 100' of

[0119] also includes a frequency detector 70 that receives detection signals (here shown as the second detection signal V_sin+ and the fourth detection signal V_cos+) and determines the signal frequency based thereon, and controls the bias current 131 in the differential amplifier 13 according to the comparison result between the signal frequency and a predetermined frequency, wherein the bias current 131 can increase or decrease the bandwidth of the differential amplifier 13 to adjust the response time of the drive current of the light source 30.

[0120] More specifically, when the rotation speed of the encoded medium 40 is relatively high, the adjustment response time of the light source 30 is preferably relatively fast to accelerate the adjustment speed; and when the rotation speed of the encoded medium 40 is relatively low, the adjustment response time of the light source 30 is preferably relatively slow to reduce the adjustment speed. Figure 10AAs shown, the controller 10 receives a first detection signal V_sin-, a second detection signal V_sin+, a third detection signal V_cos-, and a fourth detection signal V_cos+ related to the encoded medium 40. The method of generating these four detection signals has been described above, so it will not be elaborated here.

[0121] Please refer to Figure 10B , which is another block diagram of the optical encoding system 100' according to another embodiment of the present invention. As described above, the optical encoding system 100' includes a detection voltage generation circuit 101, a differential amplifier 13, and an NMOS driver 15. The output of the differential amplifier 13 is used to control the driving current of the light source 30, which has been described above, so it will not be elaborated here. The differential amplifier 13 of the optical encoding system 100' includes a bias current 131 controlled by a control signal I_ctrl, such as turning on / off or increasing / decreasing. It should be noted that the implementation manner of the controller 10 is not limited to Figure 10B As shown, as long as it is a circuit for generating a detection voltage signal based on the first detection signal V_sin-, the second detection signal V_sin+, the third detection signal V_cos-, and the fourth detection signal V_cos+ as an input of the differential amplifier 13 to compare with a reference voltage signal.

[0122] Please refer to Figure 11 , which is a block schematic diagram of the frequency detector 70 of the light source control circuit of the optical encoding system 100' according to another embodiment of the present invention. The frequency detector 70 receives the second control signal V_sin+ and the fourth detection signal V_cos+ and generates a control signal I_ctrl to control the bias current 131 in the differential amplifier 13. In one implementation manner, the frequency detector 70 includes a low-pass filter 71, a first comparator 72, a second comparator 73, a first flip-flop 74, and a second inverter 75. In another implementation manner, according to the circuit configuration in the differential amplifier 13, the frequency detector 70 may not include the second inverter 75. For example, the differential amplifier 13 includes an inverter connected upstream of the bias current 131 as one of the control elements of the bias current 131.

[0123] Please also refer to Figures 12A - 12F As shown, the operation mode of the frequency detector 70 will be described below when the phase of the second detection signal V_sin+ leads the fourth detection signal V_cos+ (e.g., by about 90 degrees) and the input signal is a low frequency.

[0124] The low-pass filter 71 has a cut-off frequency Fc (e.g., used as a frequency threshold for judging the signal frequency high or low) and is used to filter the second detection signal V_sin+, which has a signal frequency Fin. As Figure 12AAs shown, it is assumed that the signal frequency Fin is less than the cut-off frequency Fc and has a peak-to-peak value of approximately 1 volt. Since the signal frequency Fin is less than the cut-off frequency Fc, as Figure 12B shown, the peak-to-peak value of the filtered second detection signal V_sin+_F is approximately equal to (neglecting the attenuation of the filter) the second detection signal V_sin+.

[0125] The first comparator 72 is used to compare the filtered second detection signal V_sin+_F with the first reference voltage CVref to output a comparison signal C_out. The first reference voltage CVref is set, for example, to the average voltage of the second detection signal V_sin+ (e.g., 2.5 volts) plus a predetermined voltage value (e.g., 0.35 volts), as Figure 12B shown, CVref is 2.85 volts, but the present invention is not limited thereto. As long as the first reference voltage CVref is less than the peak value of the second detection signal V_sin+ to generate Figure 12C a pulse, the first reference voltage CVref can be set to any appropriate value.

[0126] As Figure 12C shown, when the filtered second detection signal V_sin+_F is greater than the first reference voltage CVref, a positive pulse appears in the comparison signal C_out.

[0127] The second comparator 73 is used to compare the fourth detection signal V_cos+ with the second reference voltage Vs / 2 to output a clock signal CLK, as Figure 12D shown, where Vs is, for example, the voltage source voltage of the controller 10, but is not limited thereto. As long as it can generate Figure 12D a pulse, Vs / 2 can be selected as other values. When the fourth detection signal V_cos+ is greater than the second reference voltage Vs / 2, a positive pulse of the clock signal CLK is generated.

[0128] The data input terminal D of the first flip-flop 74 is used to receive the comparison signal C_out, its clock input CLK_in is used to receive the clock signal CLK, and its output terminal Q is used to generate a first output signal F1_out, which is used to change the bandwidth of the differential amplifier 13 to adjust the response time of the drive current of the light source 30. As Figures 12C - 12D shown, the output terminal Q of the first flip-flop 74 tracks the comparison signal C_out at the rising edge of the clock signal CLK, so its first output signal F1_out is at a high level (e.g., shown as 1 volt, but not limited thereto), as Figure 12E shown.

[0129] As described above, when the frequency detector 70 does not include the second inverter 75, the frequency detector 70 outputs a first output signal F1_out at a high level (as the control signal I_ctrl) to the differential amplifier 13. At this time, the frequency detector 70 may not include an OR gate 78. When the frequency detector 70 includes the second inverter 75 connected between the first flip-flop 74 and the differential amplifier 13, the frequency detector 70 outputs a control signal I_ctrl at a low level (such as 0 volts, but not limited thereto) to the differential amplifier 13, as Figure 12F shown.

[0130] In this embodiment, when the signal frequency Fin of the second detection signal V_sin+ is lower than the cut-off frequency Fc, the control signal I_ctrl does not turn on the bias current 131. In the present invention, turning on the bias current 131 means accelerating the response time of the differential amplifier 13.

[0131] Next, the operation mode of the frequency detector 70 when the phase of the second detection signal V_sin+ leads the fourth detection signal V_cos+ (such as about 90 degrees) and the input signal is a high frequency is described.

[0132] As Figure 13A shown, it is assumed that the signal frequency Fin is greater than or equal to the cut-off frequency Fc and has a peak-to-peak value of about 1 volt. Since the signal frequency Fin is greater than the cut-off frequency Fc, the peak-to-peak value of the filtered second detection signal V_sin+_F will be less than the second detection signal V_sin+, as Figure 13B shown.

[0133] The first comparator 72 is used to compare the filtered second detection signal V_sin+_F with the first reference voltage CVref to output a comparison signal C_out.

[0134] As Figure 13C shown, since the second detection signal V_sin+_F is always less than the first reference voltage CVref, the comparison signal C_out is approximately 0, but its value is not limited to 0.

[0135] Similarly, the second comparator 73 is used to compare the fourth detection signal V_cos+ with the second reference voltage Vs / 2 to output a clock signal CLK, as Figure 13D shown. When the fourth detection signal V_cos+ is greater than the second reference voltage Vs / 2, a positive pulse of the clock signal CLK is generated.

[0136] Similarly, the data input terminal D of the first flip-flop 74 is used to receive the comparison signal C_out, its clock input CLK_in is used to receive the clock signal CLK, and its output terminal Q is used to generate a first output signal F1_out. As Figures 13C - 13DAs shown, the output terminal Q of the first flip-flop 74 tracks the comparison signal C_out at the rising edge of the clock signal CLK. Therefore, its first output signal F1_out is always at a low level (for example, shown as 0 volts, but not limited to this), as Figure 13E shown.

[0137] As described above, when the frequency detector 70 does not include the second inverter 75, the frequency detector 70 outputs the first output signal F1_out at a low level (as the control signal I_ctrl) to the differential amplifier 13. When the frequency detector 70 includes the second inverter 75 connected between the first flip-flop 74 and the differential amplifier 13, the frequency detector 70 outputs a control signal I_ctrl at a high level (for example, 1 volt, but not limited to this) to the differential amplifier 13, as Figure 13F shown.

[0138] In this embodiment, when the signal frequency Fin of the second detection signal V_sin+ is higher than the cut-off frequency Fc, the control signal I_ctrl turns on the bias current 131 to accelerate the adjustment response time of the differential amplifier 13 corresponding to the relatively fast rotating coding medium 40.

[0139] The above embodiment shows that the coding medium 40 can only rotate in one direction (i.e., the direction in which V_sin+ leads V_cos+). When the coding medium 40 can rotate in two opposite directions, such that the phase of the second detection signal V_sin+ leads or lags the fourth detection signal V_cos+ by about 90 degrees, in order to be able to control the bias current 131 in the differential amplifier 13 in both directions, the frequency detector 70 further includes a first inverter 76, a second flip-flop 77, and an OR gate 78, referring to Figure 11 .

[0140] When the coding medium 40 rotates in the direction such that V_sin+ leads V_cos+, the frequency detector 70 operates according to the above relative Figures 12A - 12F and Figures 13A - 13F way, so that the first flip-flop 74 generates the first output signal F1_out to the OR gate 78.

[0141] When the coding medium 40 rotates in the direction such that V_sin+ lags V_cos+, the first inverter 76 phase-inverts the clock signal CLK to generate an inverted clock signal CLK_B. The data input terminal D of the second flip-flop 77 is used to receive the comparison signal C_out, its clock input CLK_in is used to receive the inverted clock signal CLK_B, and its output terminal Q is used to generate a second output signal F2_out to change the bandwidth of the differential amplifier 13 to adjust the response time of the drive current of the light source 30.

[0142] Please also refer to Figures 14A - 14FAs shown, the operation of the frequency detector 70 when the phase of the second detection signal V_sin+ lags behind the fourth detection signal V_cos+ (e.g., by about 90 degrees) and the input signal is a low frequency will be described next.

[0143] The low-pass filter 71 has a cut-off frequency Fc and is used to filter the second detection signal V_sin+, which has a signal frequency Fin. As Figure 14A shown, it is assumed that the signal frequency Fin is less than the cut-off frequency Fc and has a peak-to-peak value of about 1 volt. Since the signal frequency Fin is less than the cut-off frequency Fc, the peak-to-peak value of the filtered second detection signal V_sin+_F is approximately equal to the second detection signal V_sin+.

[0144] The first comparator 72 is used to compare the filtered second detection signal V_sin+_F with a first reference voltage CVref ( Figure 14B also shown as 2.85 volts, but not limited to this) to output a comparison signal C_out.

[0145] As Figure 14C shown, when the filtered second detection signal V_sin+_F is greater than the first reference voltage CVref, a positive pulse appears in the comparison signal C_out.

[0146] Similarly, the second comparator 73 is used to compare the fourth detection signal V_cos+ with a second reference voltage Vs / 2 to output a clock signal CLK. Figure 14D The inverted clock signal CLK_B after inversion by the first inverter 76 is shown.

[0147] The data input terminal D of the second flip-flop 77 is used to receive the comparison signal C_out, its clock input CLK_in is used to receive the inverted clock signal CLK_B, and its output terminal Q is used to generate a second output signal F2_out, which is used to change the bandwidth of the differential amplifier 13 to adjust the response time of the drive current of the light source 30. As Figures 14C - 14D shown, the output terminal Q of the second flip-flop 77 tracks the comparison signal C_out at the rising edge of the inverted clock signal CLK_B, so its second output signal F2_out is at a high level (e.g., shown as 1 volt, but not limited to this), as Figure 14E shown.

[0148] In this embodiment, the first flip-flop 77 also operates but only outputs a first output signal F1_out at a low level.

[0149] The operation of the frequency detector 70 when the phase of the second detection signal V_sin+ lags behind the fourth detection signal V_cos+ (e.g., by about 90 degrees) and the input signal is a high frequency will be described with reference to Figures 13A - 13F and Figures 14A - 14FIt can be understood after the description thereof, so it will not be elaborated here.

[0150] In this embodiment, the OR gate 78 is used to receive the first output signal F1_out and the second output signal F2_out. When the frequency detector 70 does not include the second inverter 75, the output of the OR gate 78 serves as the control signal I_ctrl to control the bias current 131 in the differential amplifier 13. When the frequency detector 70 includes the second inverter 75 connected between the OR gate 78 and the differential amplifier 13, the output of the second inverter 75 serves as the control signal I_ctrl.

[0151] In this embodiment, when the signal frequency Fin of the second detection signal V_sin+ is lower than the cut-off frequency Fc, the control signal I_ctrl (i.e., the first output signal F1_out, the second output signal F2_out, the inverted first output signal, or the inverted second output signal) does not turn on the bias current 131; when the signal frequency Fin of the second detection signal V_sin+ is higher than or equal to the cut-off frequency Fc, the control signal I_ctrl turns on the bias current 131 to accelerate the adjustment response time of the differential amplifier 13 corresponding to the relatively fast rotating encoding medium 40.

[0152] In addition, the present invention can also control different current values of the bias current 131 according to different rotation speeds of the encoding medium 40. For example, referring to Figure 15 which is a block schematic diagram of the optical encoding system 100 according to another embodiment of the present invention. Figure 15 It is different from Figure 10A in that Figure 15 the optical encoding system 100 of

[0153] each of the multiple frequency detectors has Figure 11 a structure for generating a control signal (such as shown as I_ctrl1, I_ctrl2, and I_ctrl3) according to the second detection signal V_sin+ and the fourth detection signal V_cos+ to change the bandwidth of the differential amplifier 13 to adjust the response time of the driving current of the light source 30. In this embodiment, the low-pass filter of each of the multiple frequency detectors has its own cut-off frequency Fc as the frequency threshold for comparing with the signal frequency Fin of the input signal (i.e., the detection signal), and is used to generate respective control signals for different motor rotation speeds. Among them, the manner in which each frequency detector generates its own control signal is as described above, so it will not be elaborated here.

[0154] If it is adopted as Figure 15For the "optical encoding system 100" shown, the differential amplifier 13 can be controlled relative to six or three motor speeds to generate six (combining three control signals) or three (not combining three control signals) regulated response times. The control signals I_ctrl1, I_ctrl2, and I_ctrl3 can control their respective bias currents separately or together control the same bias current.

[0155] Similarly, Figure 15 An implementation of the controller 10 as Figure 10B shown also includes a detection voltage generation circuit 101, a differential amplifier 13, and an NMOS driver 15, but is not limited thereto.

[0156] Please refer to Figure 16 shown, which is a flowchart showing the operation mode of the light source control circuit of the optical encoding system 100' according to an embodiment of the present invention, and includes the following steps: receiving a detection signal related to the encoding medium 40 with a low-pass filter 71 and outputting a filtered detection signal (step S161); comparing the filtered detection signal with a first reference voltage with a first comparator 72 to output a comparison signal (step S162); receiving another detection signal related to the encoding medium 40 with a second comparator 73 and comparing the other detection signal with a second reference voltage to output a clock signal, wherein the phase of the detection signal leads or lags the other detection signal by 90 degrees (step S163); and when the phase of the detection signal leads the other detection signal, receiving the comparison signal and the clock signal with a first flip-flop 71 and generating a first output signal to change the bandwidth of the differential amplifier 13 so as to adjust the response time of the drive current of the light source 30 (step S164).

[0157] As described above, the transimpedance amplifier 60 generates a first detection signal V_sin-, a second detection signal V_sin+, a third detection signal V_cos-, and a fourth detection signal V_cos+ based on the first current signal I_sin-, the second current signal I_sin+, the third current signal I_cos-, and the fourth current signal I_cos+ generated by the optical detector 50, respectively. The low-pass filter 71 receives the second detection signal V_sin+ and outputs a filtered detection signal V_sin+_F (step S161). Next, the first comparator 72 compares the filtered detection signal V_sin+_F with the first reference voltage CVref and outputs a comparison signal C_out (step S162). At the same time, the second comparator 73 receives the fourth detection signal V_cos+ and compares the fourth detection signal V_cos+ with the second reference voltage Vs / 2 to output a clock signal CLK (step S163). When the phase of the second detection signal V_sin+ leads the fourth detection signal V_cos+, the first flip-flop 71 receives the comparison signal C_out and the clock signal CLK and generates a first output signal F1_out, refer to Figures 12A - 12F , Figures 13A - 13F and its related description.

[0158] When the encoded medium 40 can only detect rotation in a single direction, the first output signal F1_out or the first output signal after being inverted by the second inverter 75 is used as the control signal I_ctrl.

[0159] However, when the phase of the second detection signal V_sin+ lags behind the fourth detection signal V_cos+ due to different rotations of the encoded medium 40, the first inverter 76 inverts the clock signal CLK to generate an inverted clock signal CLK_B. Then, the second flip-flop 77 receives the comparison signal C_out and the inverted clock signal CLK_B and generates a second output signal F2_out, refer to Figures 14A - 14F and its description.

[0160] Next, the OR gate 78 receives the first output signal F1_out and the second output signal F2_out. It should be noted that the first flip-flop 74 and the second flip-flop 77 can operate simultaneously, but only one of them will output a high-level output signal at a low input signal frequency.

[0161] As described above, when the light source control circuit does not include the second inverter 75, the output signal of the OR gate 78 is used as the control signal I_ctrl to change the bandwidth of the differential amplifier 13 to adjust the response time of the drive current of the light source 30. When the light source control circuit includes the second inverter 75, the second inverter 75 inverts the output signal of the OR gate 78, and the inverted signal is used as the control signal I_ctrl.

[0162] As described above, in Figure 11 under the architecture of, when the signal frequency Fin of the second detection signal V_sin+ is lower than the cut-off frequency Fc of the low-pass filter 71, the first output signal F1_out or the second output signal F2_out does not turn on the bias current 131; when the signal frequency Fin of the second detection signal V_sin+ is higher than or equal to the cut-off frequency Fc of the low-pass filter 71, the first output signal F1_out or the second output signal F2_out turns on the bias current 131.

[0163] It must be noted that although Figures 10A - 10B , Figure 11 and Figure 15 show that the frequency detector 70 generates the control signal I_ctrl according to the second detection signal V_sin+ and the fourth detection signal V_cos+, the present invention is not limited thereto. In other embodiments, the frequency detector 70 generates the control signal I_ctrl according to the first control signal V_sin- and the third detection signal V_cos-. That is, one of the input signals of the frequency detector 70 is a sine voltage signal and the other is a cosine voltage signal.

[0164] It must be noted that although Figures 12A - 12B , Figures 13A - 13B and Figures 14A - 14B show that the detection signal is a sine wave, the present invention is not limited thereto. According to different configurations of the slits on the coding medium 40, the detection signal can be other waveforms.

[0165] It must be noted that in the above embodiments, although the frequency detector 70 is described by taking the inclusion of the low-pass filter 71 as an example, the present invention is not limited thereto. In other embodiments, the frequency detector 70 may include a high-pass filter or a band-pass filter to replace the low-pass filter, so that when the filtered detection signal input to the first comparator 72 is within or outside a predetermined signal frequency range, a positive pulse can be generated or not generated for the comparison signal to serve as the data input of the flip-flop. For example, when using a high-pass filter, the frequency detector 70 does not include the second inverter 75.

[0166] When necessary, the control signal I_ctrl output by the frequency detector 70 can also be used to control other components in the optical coding systems 100' and 100" other than the differential amplifier 13.

[0167] In summary, it is known that the light source control circuit is affected by dark current leakage and reflected light leakage and cannot accurately control the brightness of the light source. Therefore, the present invention further provides a light source control circuit ( Figure 9 ) and an optical coding system ( Figure 1) It first eliminates the common-mode voltage of the detection signal through a squaring circuit and then compares the detected voltage signal with the desired control voltage. Since the DC offset has been eliminated in the differential operation and the desired control voltage also changes synchronously according to environmental variations, the driving current of the power supply can be effectively stabilized.

[0168] Although the present invention has been disclosed by the foregoing examples, it is not intended to limit the present invention. Any person having ordinary knowledge and skills in the technical field to which the present invention pertains may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the appended claims.

Claims

1. A frequency detector for an optical coding system, the frequency detector being configured to receive a first detection signal and a second detection signal from a differential amplifier of the optical coding system, the frequency detector comprising: A low-pass filter configured to filter the first detection signal and having a cut-off frequency; A first comparator configured to compare the filtered first detection signal with a first reference voltage to output a comparison signal; A second comparator configured to compare the second detection signal with a second reference voltage to output a clock signal; And A flip-flop, wherein a data input terminal of the flip-flop is configured to receive the comparison signal, a clock input thereof is configured to receive the clock signal, and an output terminal thereof is configured to generate an output signal for changing a bandwidth of the differential amplifier of the optical coding system when a phase of the first detection signal leads a phase of the second detection signal.

2. The frequency detector according to claim 1, further comprising an inverter connected downstream of the flip-flop.

3. The frequency detector according to claim 1, wherein The first reference voltage is an average voltage of the first detection signal plus a predetermined voltage value, and The first reference voltage is less than a peak value of the first detection signal.

4. The frequency detector according to claim 1, wherein, The first detection signal is a sinusoidal voltage signal and the second detection signal is a cosine voltage signal.

5. The frequency detector according to claim 1, wherein, The output signal is configured to be output to a controller of the optical coding system to adjust a response time of a drive current of a light source by changing the bandwidth of the differential amplifier.

6. The frequency detector according to claim 5, wherein, The second reference voltage is half of a voltage source voltage of the controller.

7. The frequency detector according to claim 1, further comprising: An inverter configured to invert a phase of the clock signal; and A second flip-flop, wherein a data input terminal of the second flip-flop is configured to receive the comparison signal, a clock input thereof is configured to receive the inverted clock signal, and an output terminal thereof is configured to generate another output signal for changing the bandwidth of the differential amplifier when the phase of the first detection signal lags the phase of the second detection signal.

8. The frequency detector according to claim 1, further comprising: An OR gate configured to receive the output signal and the another output signal.

9. A method of operating a frequency detector of an optical coding system, the optical coding system comprising a differential amplifier, and the frequency detector comprising a low-pass filter, a first comparator, a second comparator, and a first flip-flop, the method of operating comprising: Receiving, by the low-pass filter, a first detection signal from the differential amplifier and outputting the filtered first detection signal; Comparing, by the first comparator, the filtered first detection signal with a first reference voltage to output a comparison signal; Receiving, by the second comparator, a second detection signal from the differential amplifier and comparing the second detection signal with a second reference voltage to output a clock signal, wherein The phase of the first detection signal leads or lags the second detection signal by 90 degrees; And When the phase of the first detection signal leads the phase of the second detection signal, the first flip-flop receives the comparison signal and the clock signal to generate a first output signal to change the bandwidth of the differential amplifier of the optical encoding system.

10. The operating method according to claim 9, wherein, The frequency detector further includes a first inverter and a second flip-flop. When the phase of the first detection signal lags the phase of the second detection signal, the operating method further includes: inverting the clock signal with the first inverter; and receiving, by the second flip-flop, the comparison signal and the inverted clock signal and generating a second output signal to change the bandwidth of the differential amplifier.

11. The operating method according to claim 10, wherein, The frequency detector further includes an OR gate and a second inverter connected downstream of the OR gate. The operating method further includes: receiving, by the OR gate, the first output signal and the second output signal; and inverting the output signal of the OR gate with the second inverter.

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