Semiconductor element having at least one air gap and method for producing same

Abstract

The invention discloses a semiconductor element and a manufacturing method thereof. The semiconductor element comprises an upper metal wire and a lower metal wire. The upper metal wire is arranged on the lower metal wire. At least one air gap is disposed between the upper metal line and the lower metal line.

Description

Technical Field

[0001] This application claims the priority of U.S. Patent Application No. 18 / 396,816 (i.e., the priority date is "December 27, 2023"), the content of which is incorporated herein by reference in its entirety.

[0002] This disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device. More particularly, it relates to a semiconductor device having at least one air gap. Background Art

[0003] In a semiconductor device, an upper metal wire may be disposed over a lower metal wire, which may result in unwanted parasitic capacitance. Such capacitance has a negative impact on the response speed of the device, especially as electronic devices are made smaller and the gaps between metal wires become smaller.

[0004] The discussion of the prior art paragraphs provides only background information. The statements in the discussion of the prior art paragraphs do not admit that the content disclosed in this paragraph constitutes the prior art of this disclosure, and any part of the discussion in the prior art paragraphs shall not be used as an admission that any part of this application, including the part in the discussion of the prior art paragraphs, constitutes the prior art of this disclosure. Summary of the Invention

[0005] One aspect of the present disclosure provides a semiconductor device. The semiconductor device includes: a substrate having a drain region and a source region disposed in the substrate; a gate structure disposed over the substrate and between the drain region and the source region; a first dielectric disposed over the substrate and covering the substrate and the gate structure; a plug disposed in the first dielectric, wherein the plug includes a first portion extending through the first dielectric and contacting the source region of the substrate, and a second portion protruding from the first dielectric; a storage node contact pad disposed over an exposed portion of the second portion of the plug; a second dielectric disposed over the first dielectric and covering the storage node contact pad; at least one air gap disposed in the second dielectric; a bit line extending through the second dielectric and the first dielectric and connected to the substrate; a third dielectric disposed over the bit line; and a storage node disposed over the third dielectric, wherein the storage node extends through the third dielectric and the second dielectric and contacts the storage node contact pad.

[0006] Another aspect of the present disclosure provides a semiconductor device. The semiconductor device includes: a substrate having a source region, a drain region, and a bit line disposed in the substrate; a dielectric layer disposed on the substrate; at least one air gap disposed in the dielectric layer; a plug disposed in the dielectric layer; a barrier layer disposed on a sidewall of the plug; and a contact pad disposed on the dielectric layer. The barrier layer includes a top portion located above the dielectric layer.

[0007] Another aspect of the present disclosure provides a method of manufacturing a semiconductor device. The manufacturing method includes: providing a substrate having a gate structure disposed thereon; forming a first interlayer dielectric covering the substrate and the gate structure; forming a plug in the first interlayer dielectric; exposing a portion of the plug; forming a storage node contact pad on the exposed portion of the plug; forming a second interlayer dielectric on the first interlayer dielectric, wherein the second interlayer dielectric includes at least one air gap; forming a bit line extending through the second interlayer dielectric and the first interlayer dielectric and connecting to the substrate; forming a third interlayer dielectric on the bit line; and forming a storage node on the third interlayer dielectric.

[0008] By utilizing at least one air gap in the semiconductor device, the parasitic capacitance between the upper metal line and the lower metal line can be reduced, thereby improving the efficiency of the semiconductor device.

[0009] The technical features and advantages of the present disclosure have been outlined quite extensively above so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those of ordinary skill in the art to which the present disclosure pertains should understand that the concepts and specific embodiments disclosed below can be quite easily utilized as a basis for modifying or designing other structures or processes to achieve the same purposes as the present disclosure. Those of ordinary skill in the art to which the present disclosure pertains should also understand that such equivalent structures cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] When considering the embodiments and the claims in conjunction with the drawings, a more complete understanding of the disclosure of the present application can be obtained. It should be noted that, in accordance with the standard industry practice, the various features are not drawn to scale. For the sake of clarity in discussion, the dimensions of the various features can be arbitrarily increased or decreased.

[0011] Figure 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 2 is a flowchart illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0013] Figures 3 to 10 is a cross-sectional view illustrating an intermediate stage in the formation process of a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 11 is a flowchart illustrating a method of forming a semiconductor device according to another embodiment of the present disclosure.

[0015] Figures 12 to 13 is a cross-sectional view illustrating an intermediate stage in the formation process of a semiconductor device according to some embodiments of the present disclosure.

[0016] Figure 14 is a top view illustrating an intermediate stage according to Figure 13 the intermediate stage.

[0017] Figures 15 to 17 is a cross-sectional view illustrating an intermediate stage in the formation process of a semiconductor device according to some embodiments of the present disclosure.

[0018] Figure 18 is a top view illustrating an intermediate stage according to Figure 17 the intermediate stage.

[0019] Figures 19 to 20 is a cross-sectional view illustrating an intermediate stage in the formation process of a semiconductor device according to some embodiments of the present disclosure.

[0020] Figure 21 is a top view illustrating an intermediate stage according to Figure 20 the intermediate stage.

[0021] Figure 22 is a cross-sectional view illustrating an intermediate stage in the formation process of a semiconductor device according to some embodiments of the present disclosure.

[0022] Figure 23 is a top view illustrating an intermediate stage according to Figure 22 the intermediate stage.

[0023] Figure 24 is a cross-sectional view illustrating an intermediate stage in the formation process of a semiconductor device according to some embodiments of the present disclosure.

[0024] Figure 25 is a top view illustrating an intermediate stage according to Figure 24 the intermediate stage.

[0025] Figure 26 is a cross-sectional view illustrating an intermediate stage in the formation process of a semiconductor device according to some embodiments of the present disclosure.

[0026] Figure 27 is a top view illustrating an intermediate stage according to Figure 26 the intermediate stage.

[0027] Figure 28is a cross-sectional view illustrating an intermediate stage in the formation process of a semiconductor device according to some embodiments of the present disclosure.

[0028] Figure 29 is a top view illustrating an intermediate stage according to Figure 28 the intermediate stage.

[0029] Figure 30 is a cross-sectional view illustrating an intermediate stage in the formation process of a semiconductor device according to some embodiments of the present disclosure.

[0030] Figure 31 is a top view illustrating an intermediate stage according to Figure 30 the intermediate stage.

[0031] Figures 32 to 35 is a cross-sectional view illustrating an intermediate stage in the formation process of a semiconductor device according to some embodiments of the present disclosure.

[0032] Figures 36 to 39 is a cross-sectional view illustrating semiconductor devices according to various embodiments of the present disclosure.

[0033] Among them, the reference numerals are explained as follows:

[0034] 1: Method

[0035] 10: Method

[0036] 100: Semiconductor device

[0037] 101: Substrate

[0038] 103: Isolation structure

[0039] 105: Active region

[0040] 110: Substrate

[0041] 112: Source region

[0042] 114: Drain region

[0043] 120: Gate structure

[0044] 121: Silicide

[0045] 122: Polysilicon

[0046] 123: Gate oxide

[0047] 124: Spacer

[0048] 131: First interlayer dielectric

[0049] 131a: Plug contact hole

[0050] 132: Second interlayer dielectric

[0051] 132a: Bit line contact hole

[0052] 133: Third interlayer dielectric

[0053] 133a: Storage node contact hole

[0054] 140: Plug

[0055] 141: First part

[0056] 142: Second part

[0057] 150: Storage node contact pad

[0058] 151: Support part

[0059] 153: Air gap

[0060] 160: Bit line

[0061] 170: Storage node

[0062] 180: Bit line contact pad

[0063] 200: Semiconductor element

[0064] 201: Word line

[0065] 203: Bottom layer

[0066] 205: Intermediate layer

[0067] 207: Top layer

[0068] 209: Trench opening

[0069] 251: Support part

[0070] 253: Air gap

[0071] 301: First doped region

[0072] 303: Second doped region

[0073] 351: Support part

[0074] 353: Air gap

[0075] 401: Contact

[0076] 402: Contact hole

[0077] 402-1: Filling material

[0078] 403: Capacitor contact

[0079] 403-1: Neck

[0080] 403-2: Head

[0081] 403-3: Curved side wall

[0082] 404: Deformation hole

[0083] 404-1: Narrow part

[0084] 404-2: Wide part

[0085] 405: Bit line contact

[0086] 407: First covering layer

[0087] 408: Bit line groove opening

[0088] 408-1: Filling material

[0089] 409: Bit line

[0090] 411: Capacitor plug

[0091] 411A: Protruding part

[0092] 412: Barrier layer

[0093] 412A: Top part

[0094] 451: Support part

[0095] 453: Air gap

[0096] 551: Support part

[0097] 553: Air gap

[0098] 801: First insulating layer

[0099] 803: Second insulating layer

[0100] 805: Third insulating layer

[0101] 807: Fourth insulating layer

[0102] 808: Liner

[0103] 808A: First silicide layer

[0104] 808B: Second silicide layer

[0105] 810: Contact pad

[0106] C: Center line

[0107] H1: Height

[0108] H2: Height

[0109] S1: Side surface

[0110] S2: Side surface

[0111] S3: Side wall

[0112] S4: Side wall

[0113] W01: Width

[0114] W02: Width

[0115] W11: Width

[0116] W12: Width

[0117] W21: Width

[0118] W22: Width

[0119] W31: Width

[0120] W32: Width

[0121] W41: Width

[0122] W42: Width

[0123] W51: Width

[0124] W52: Width

[0125] W1: Upper width

[0126] W2: Upper width

[0127] W3: Width

[0128] W4: Width

[0129] S11: Step

[0130] S13: Step

[0131] S15: Step

[0132] S17: Step

[0133] S21: Step

[0134] S22: Step

[0135] S23: Step

[0136] S24: Step

[0137] S25: Step

[0138] S26: Step

[0139] S27: Step

[0140] S28: Step

[0141] S29: Step Detailed implementation

[0142] Embodiments or examples of the present disclosure shown in the drawings are now described using a specific language. It should be understood that the scope of the present disclosure is not intended to be limited herein. Any changes or modifications to the described embodiments, as well as any further applications of the principles described in this document, should be considered as normally contemplated by those of ordinary skill in the technical field to which the present disclosure pertains. Element symbols may be repeated throughout the embodiments, but this does not necessarily mean that one (or more) features of one embodiment apply to another embodiment, even if they share the same element symbols.

[0143] It should be understood that although terms such as first, second, third, etc. may be used herein to describe various components, members, regions, layers, or parts, these components, members, regions, layers, or parts should not be limited by these terms. Instead, these terms are only used to distinguish one component, member, region, layer, or part from another component, member, region, layer, or part. Thus, the first component, member, region, layer, or part discussed below may be referred to as the second component, member, region, layer, or part without departing from the teachings of the present disclosure.

[0144] The terms used herein are only for describing specific exemplary embodiments and are not intended to limit the inventive concept. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It should be further understood that when the terms "comprises" and "comprising" are used in this specification, they specify the presence of the stated features, integers, steps, operations, components, or members, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, members, or groups thereof.

[0145] Figure 1 is a cross-sectional view illustrating a semiconductor element 100 according to an embodiment of the present disclosure. The semiconductor element 100 includes a substrate 110, a first interlayer dielectric 131, a second interlayer dielectric 132, a plug 140, a storage node contact pad 150, a bit line 160, a third interlayer dielectric 133, and a storage node 170.

[0146] See Figure 1 , the substrate 110 includes a source region 112 and a drain region 114 disposed in the substrate 110. In some embodiments, the substrate 110 is a semiconductor substrate, such as a silicon substrate. A gate structure 120 is disposed on the substrate 110 and between the source region 112 and the drain region 114. In some embodiments, the gate structure 120 includes a silicide 121, a polysilicon 122, a gate oxide 123, and a spacer 124.

[0147] The first interlayer dielectric 131 is disposed above the substrate 110 and below the second interlayer dielectric 132. The second interlayer dielectric 132 is disposed above the first interlayer dielectric 131 and below the third interlayer dielectric 133. In some embodiments, the first interlayer dielectric 131, the second interlayer dielectric 132, and the third interlayer dielectric 133 are formed of a material such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), a low dielectric constant (low-k) dielectric material, and / or other suitable dielectric materials. In some embodiments, the first interlayer dielectric 131, the second interlayer dielectric 132, and the third interlayer dielectric 133 are formed by a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a thermal oxidation process, or a similar process.

[0148] In some embodiments, at least one air gap 153 is formed in the second interlayer dielectric 132. In some embodiments, the air gap is formed by an etching process performed on the second interlayer dielectric 132, such as a dry etching process. After the air gap is formed, each remaining portion of the second interlayer dielectric 132 is referred to as a support portion.

[0149] The plug 140 includes a first portion 141 and a second portion 142. The first portion 141 of the plug 140 is disposed in the first interlayer dielectric 131 and contacts the source region 112 of the substrate 110. The second portion 142 of the plug 140 protrudes from the first interlayer dielectric 131 and is disposed in the second interlayer dielectric 132.

[0150] The storage node contact pad 150 covers the second portion 142 of the plug 140 located in the second interlayer dielectric 132. In some embodiments, the plug 140 is made of copper, and the storage node contact pad 150 is made of copper germanide (Cu3Ge). However, other materials may also be used to form the plug 140 and the storage node contact pad 150. In some other embodiments, the plug 140 is made of tungsten or aluminum, and the storage node contact pad 150 is made of gold, silver, or aluminum.

[0151] The bit line 160 is disposed between the second interlayer dielectric 132 and the third interlayer dielectric 133 and is electrically connected to the drain region 114 of the substrate 110. In some embodiments, the substrate 110 includes a bit line contact pad 180, which allows the bit line 160 to be connected to the drain region 114 of the substrate 110 by contacting the bit line contact pad 180.

[0152] The storage node 170 is disposed on the third interlayer dielectric 133 and extends through the third interlayer dielectric 133 and the second interlayer dielectric 132 to connect to the storage node contact pad 150, the plug 140, and the source region 112 of the substrate 110.

[0153] Figure 2 is a flowchart illustrating a manufacturing method 1 of a semiconductor device 100 according to an embodiment of the present disclosure. Figures 3 to 10 is a cross-sectional view illustrating an intermediate stage in the formation of a semiconductor device 100 according to an embodiment of the present disclosure. The stage illustrated in Figures 3 to 10 is also schematically shown in the Figure 2 flowchart. In the following discussion, the stage illustrated in Figures 3 to 10 describes the Figure 2 process steps shown. Method 1 includes a plurality of operations, and the description and illustration should not be construed as limiting the order of these operations. Method 1 includes a plurality of steps (S21, S22, S23, S24, S25, S26, S27, S28, and S29).

[0154] Refer to Figure 2 and Figure 3 , in step S21, a substrate 110 having a gate structure 120 disposed thereon is provided. The substrate 110 includes a drain region 114 and a source region 112. The gate structure 120 is disposed between the drain region 114 and the source region 112. In some embodiments, the substrate 110 includes bit line contact pads 180 to simplify subsequent process stages.

[0155] Refer to Figure 2 and Figure 4 , in step S22, a first interlayer dielectric 131 is formed over the substrate 110 and the gate structure 120. In some embodiments, the first interlayer dielectric 131 is formed by depositing borophosphosilicate glass (BPSG) over the substrate 110. In some embodiments, the first interlayer dielectric 131 is formed by a chemical vapor deposition (CVD) process.

[0156] Refer to Figure 2 and Figure 5, in step S23, a plug 140 is formed in the first interlayer dielectric 131. The plug 140 includes a first portion 141 that contacts the substrate 110 at the source region 112. In some embodiments, the plug 140 is formed by a process that includes: forming a plug contact hole 131a by etching the first interlayer dielectric 131 using a buffered oxide etchant (BOE) as an etchant; depositing a conductive material (not shown) on the first interlayer dielectric 131 and filling the plug contact hole 131a such that the conductive material contacts the source region 112 of the substrate 110; etching the first interlayer dielectric 131 to remove a portion of the conductive material from the first interlayer dielectric 131 such that only the conductive material located in the plug contact hole 131a remains in place. After removing the above portion of the conductive material, the plug 140 is formed of the remaining conductive material. In some embodiments, the plug 140 is made of copper. In some embodiments, the plug 140 is made of tungsten. In some embodiments, the plug 140 is formed by a chemical vapor deposition (CVD) process. In some embodiments, a planarization process is performed after forming the plug 140.

[0157] See Figure 2 and Figure 6 , in step S24, a second portion 142 of the plug 140 is formed by exposing a portion of the plug 140 from the first interlayer dielectric 131. In some embodiments, conventional techniques for oxide polishing such as chemical mechanical polishing (CMP) are used to remove a portion of the first interlayer dielectric 131 to expose the above portion of the plug 140. The exposed portion of the plug 140 is referred to as the second portion 142 of the plug 140. In some embodiments, an oxide etchant is used in an etching process to remove a portion of the first interlayer dielectric 131 and expose the second portion 142 of the plug 140.

[0158] See Figure 2 and Figure 7 , in step S25, a storage node contact pad 150 is formed on the second portion 142 of the plug 140. In some embodiments, the plug 140 is made of copper and by applying a gas such as germane (GeH4) after step S24 as in Figure 6In the structure shown, a storage node contact pad 150 is formed. Germane reacts with the second portion 142 of the plug 140 and forms a copper germanide (Cu3Ge) layer covering the second portion 142 of the plug 140, where the copper germanide (Cu3Ge) layer forms the storage node contact pad 150. Since germane does not react with the first interlayer dielectric 131 (e.g., composed of borophosphosilicate glass (BPSG)), the copper germanide (Cu3Ge) layer can be selectively formed on the second portion 142 of the plug 140. Accordingly, the formation of such a Cu3Ge layer can simplify the manufacturing process as patterning is not required. In addition, the high selectivity of the chemical reaction allows the storage node contact pad 150 to be self-align, thus avoiding undesired coupling between two adjacent storage node contact pads 150 caused by patterning defects, such as stringer or bridge phenomena. In some embodiments, different processes are used to form the storage node contact pad 150. In some embodiments, an electroplating process is used to form the storage node contact pad 150 on the second portion 142 of the plug 140 because the plug 140 is a highly selective layer compared to the first interlayer dielectric 131.

[0159] See Figure 2 and Figure 8 , in step S26, a second interlayer dielectric 132 is formed on the first interlayer dielectric 131 and covers the storage node contact pad 150. In some embodiments, borophosphosilicate glass (BPSG) is deposited on the first interlayer dielectric 131 by a chemical vapor deposition (CVD) process to form the second interlayer dielectric 132.

[0160] Still see Figure 2 and Figure 8 , in step S26, at least one air gap 153 is formed in the second interlayer dielectric 132. In some embodiments, the air gap 153 is formed by an etching process, such as a dry etching process, performed on the second interlayer dielectric 132. In some embodiments, the air gap 153 extends through the second interlayer dielectric 132 and divides the second interlayer dielectric 132 into several parts, thus forming a plurality of support parts 151. In some embodiments, the width W01 of each air gap 153 is less than the width W02 of the gate structure 120.

[0161] See Figure 2 and Figure 9, in step S27, bit line 160 is formed over the second interlayer dielectric 132, extends through the second interlayer dielectric 132 and the first interlayer dielectric 131, and is connected to the drain region 114 of the substrate 110 via the bit line contact pad 180. In some embodiments, bit line 160 is formed by a process that includes: forming a bit line contact hole 132a through the first interlayer dielectric 131 and the second interlayer dielectric 132 to expose the bit line contact pad 180; forming a conductive layer (not shown) on the second interlayer dielectric 132 to fill the bit line contact hole 132a; and patterning the conductive layer to form bit line 160. In some embodiments, buffered oxide etchant (BOE) can be used to etch the second interlayer dielectric 132 to form the bit line contact hole 132a.

[0162] See Figure 2 and Figure 10 , in step S28, a third interlayer dielectric 133 is formed on the bit line 160. In some embodiments, borophosphosilicate glass (BPSG) is deposited on the bit line 160 by chemical vapor deposition (CVD) process to form the third interlayer dielectric 133.

[0163] See Figure 1 and Figure 2 , in step S29, a storage node 170 is formed on the third interlayer dielectric 133. The storage node 170 extends through the third interlayer dielectric 133 and the second interlayer dielectric 132 and contacts the storage node contact pad 150. In some embodiments, the storage node 170 is formed by a process that includes: forming a storage node contact hole 133a through the first interlayer dielectric 131 and the second interlayer dielectric 132; depositing a conductive layer (not shown) on the third interlayer dielectric 133 to fill the storage node contact hole 133a; and patterning the conductive layer using a lithography process to form the storage node 170.

[0164] Figure 11 is a flowchart illustrating a method 10 for forming a semiconductor device 200 according to another embodiment of the present disclosure. Figures 12 to 35 is an intermediate stage of forming the semiconductor device 200 according to the method 10, wherein Figure 12 , Figure 13 , Figure 15 , Figure 16 , Figure 17 , Figure 19 , Figure 20 , Figure 22 , Figure 24 , Figure 26 , Figure 28 , Figure 30 , Figure 32 , Figure 33 ,Figure 34 , Figure 35 is a cross-sectional view, and Figure 14 , Figure 18 , Figure 21 , Figure 23 , Figure 25 , Figure 27 , Figure 29 and Figure 31 are respectively Figure 13 , Figure 17 , Figure 20 , Figure 22 , Figure 24 , Figure 26 , Figure 28 and Figure 30 the top views of.

[0165] Refer to Figure 11 and Figures 12 to 19 , in step S11, a substrate 101 is provided. An isolation structure 103, a word line 201, a first doped region 301, and a second doped region 303 are formed in the substrate 101.

[0166] Refer to Figure 12 , the substrate 101 has a first region (not shown) and a second region (not shown) provided in the substrate 101. The substrate 101 is formed of, for example, silicon, doped silicon, silicon germanium, silicon-on-insulator, silicon-on-sapphire, silicon-germanium-on-insulator, silicon carbide, germanium, gallium arsenide, gallium phosphide, gallium arsenide phosphide, indium phosphide, or indium gallium phosphide.

[0167] Refer to Figure 13 and Figure 14 , an isolation structure 103 is formed in the substrate 101. Pairs of isolation structures 103 define active regions 105 and are provided on opposite sides of the active regions 105. For example, the isolation structure 103 is formed of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, fluorine-doped silicate, or a similar material. The active regions 105 may extend in a direction inclined with respect to the X direction in the top view. It should be noted that the silicon oxynitride in the present disclosure refers to a substance containing silicon, nitrogen, and oxygen, and in which the proportion of oxygen is greater than that of nitrogen. The silicon nitride oxide refers to a substance containing silicon, oxygen, and nitrogen, and in which the proportion of nitrogen is greater than that of oxygen.

[0168] Refer to Figures 15 to 18 , a word line 201 is formed in the substrate 101. In some embodiments, the word line 201 extends along the X direction. The word line 201 includes a bottom layer 203, an intermediate layer 205, a top layer 207, and a trench opening 209. Refer to Figure 15, in some embodiments, a lithography process is used to pattern the substrate 101 to define the positions of the trench openings 209. An etching process, for example, an anisotropic dry etching process, is performed to form the trench openings 209 in the substrate 101. Refer to Figure 16 , after the etching process, a bottom layer 203 is formed and attached to the sidewalls and bottom of the trench openings 209. The bottom layer 203 is formed of, for example, silicon oxide, silicon oxynitride, silicon nitride, silicon oxynitride, or similar materials.

[0169] Refer to Figure 17 and Figure 18 , an intermediate layer 205 is disposed on the bottom layer 203. The top surface of the intermediate layer 205 is lower than the top surface of the substrate 101. The intermediate layer 205 is formed of, for example, doped polysilicon, a metal material, or a metal silicide. The metal silicide can be, for example, nickel silicide, platinum silicide, titanium silicide, molybdenum silicide, cobalt silicide, tantalum silicide, tungsten silicide, or similar materials. A top layer 207 is disposed on the intermediate layer 205. The top surface of the top layer 207 is at the same vertical height as the top surface of the substrate 101. The top layer 207 is formed of, for example, silicon oxide, silicon oxynitride, silicon nitride, silicon oxynitride, or similar materials.

[0170] Refer to Figure 19 , a first doped region 301 and a second doped region 303 are formed in the active region 105 of the substrate 101. The first doped region 301 is disposed between two adjacent word lines 201. The second doped region 303 is disposed between the isolation structure 103 and the word line 201. The first doped region 301 and the second doped region 303 are doped with dopants such as phosphorus, arsenic, or antimony. The first doped region 301 and the second doped region 303 have a dopant concentration ranging from about 1E17 atoms / cm 3 to about 1E19 atoms / cm 3 .

[0171] Refer to Figure 11 and Figures 20 to 31 , in step S13, a first insulating layer 801, a second insulating layer 803, a third insulating layer 805, a contact 401, at least one air gap 153, a capacitor contact 403, a bit line contact 405, and a bit line 409 are formed on the substrate 101.

[0172] Refer to Figure 20 and Figure 21, a first insulating layer 801 is formed on a substrate 101. Contacts 401 and air gaps 153 are disposed in the first insulating layer 801. The first insulating layer 801 can be formed of, for example, silicon nitride, silicon oxide, silicon oxynitride, undoped silicon oxide glass, borosilicate glass, phosphatase glass, borophosphosilicate glass, or a combination thereof, but is not limited thereto. The first insulating layer 801 is formed by a deposition process, such as chemical vapor deposition, physical vapor deposition, sputtering, or a similar process.

[0173] In some embodiments, the contacts 401 are formed by the following process, which includes: performing a lithography process to define the positions of the contacts 401; performing an etching process, such as an anisotropic dry etching process, to form openings (not shown) in the first insulating layer 801; depositing a conductive material in the openings and performing a metallization process to form the contacts 401; and performing a planarization process to remove the excess deposited material and provide a substantially flat surface for subsequent process steps. In some embodiments, the conductive material includes aluminum, copper, tungsten, cobalt, or other suitable metals or metal alloys. In some embodiments, the metallization process is chemical vapor deposition, physical vapor deposition, sputtering, or a similar process.

[0174] In some embodiments, the contacts 401 are disposed on the first doped region 301 and are electrically connected to the first doped region 301. In some embodiments, the contacts 401 are made of tungsten.

[0175] In some embodiments, air gaps 153 are disposed in the first insulating layer 801. In some embodiments, the air gaps 153 are disposed on opposite sides of the contacts 401 and are separated from the contacts 401. The width W11 of each air gap 153 is substantially less than, equal to, or greater than the width W12 of the word line 201. The center line C of the air gap 153 is substantially aligned with the side surface S1 or the side surface S2 of the word line 201, where the side surfaces S1 and S2 face the contacts 401. The air gaps 153 are formed by the following process, which includes: performing a lithography process to define the positions of each air gap 153; performing an etching process, such as an anisotropic dry etching process, to form the air gaps 153 in the first insulating layer 801; and performing a planarization process, such as chemical mechanical polishing, to provide a substantially flat surface for subsequent process steps. After the contacts 401 and the air gaps 153 are formed, each remaining portion of the first insulating layer 801 is referred to as a support portion 151.

[0176] See Figure 22 and Figure 23, a second insulating layer 803 is formed on the first insulating layer 801. A bit line contact 405 is formed in the second insulating layer 803. The second insulating layer 803 may be made of the same material as that used to form the first insulating layer 801, but is not limited thereto. The second insulating layer 803 is formed by the same process as that used to form the first insulating layer 801.

[0177] In some embodiments, the bit line contact 405 is formed by the following process, which includes: performing a lithography process to define the position of the bit line contact 405; performing an etching process, such as an anisotropic dry etching process, to form a bit line contact opening (not shown) in the second insulating layer 803 and expose the top surface of the contact 401 through the bit line contact opening; optionally performing a cleaning process using a reducing agent to remove defects on the top surface of the contact 401, where the contact 401 includes tungsten; forming a first capping layer 407 to cover the bottom and sidewalls of the bit line contact opening; depositing a conductive material in the bit line contact opening and performing a metallization process to form the bit line contact 405; and performing a planarization process to remove the excess deposited material and provide a substantially flat surface for subsequent process steps. In some embodiments, the reducing agent is titanium tetrachloride, tantalum tetrachloride, or a combination thereof. In some embodiments, the first capping layer 407 includes tungsten nitride. In some embodiments, the conductive material includes aluminum, copper, tungsten, cobalt, or other suitable metals or metal alloys. In some embodiments, the metallization process is chemical vapor deposition, physical vapor deposition, sputtering, or a similar process. In some embodiments, the planarization process is chemical mechanical polishing.

[0178] In some embodiments, the bit line contact 405 is electrically connected to the contact 401. Accordingly, the bit line contact 405 is electrically coupled to the first doped region 301.

[0179] See Figure 24 and Figure 25 , a third insulating layer 805 is formed on the second insulating layer 803, a contact hole 402 is formed on the substrate 101, and a bit line trench opening 408 is formed on the bit line contact 405. The third insulating layer 805 may be made of the same material as that used to form the first insulating layer 801, but is not limited thereto. The third insulating layer 805 is formed by the same process as that used to form the first insulating layer 801.

[0180] In some embodiments, a bit line trench opening 408 is formed by the following process, which includes: performing a lithography process to define the position of the bit line trench opening 408, and performing an etching process, such as an anisotropic dry etching process, to form the bit line trench opening 408 in the third insulating layer 805. In some embodiments, the lithography process can also define the position of the contact hole 402, and performing the above etching process can form the contact hole 402 that penetrates through the third insulating layer 805, the second insulating layer 803, and the first insulating layer 801. The contact hole 402 can also be referred to as a deep hole, while the bit line trench opening 408 is relatively shallow.

[0181] See Figure 26 and Figure 27 , in some embodiments, a process, such as chemical vapor deposition, physical vapor deposition, or sputtering, is used to fill the bit line trench opening 408 and the contact hole 402 with a material. In some embodiments, the depth of the contact hole 402 is greater than the depth of the bit line trench opening 408. Therefore, the bit line trench opening 408 is filled with the filling material 408-1, and the contact hole 402 is partially filled with the filling material 402-1, and the filling material 402-1 can be the same as the filling material 408-1. In addition, in some embodiments, the upper part of the contact hole 402 located in the third insulating layer 805 is not filled with the filling material 402-1.

[0182] See Figure 28 and Figure 29 , a deformed hole 404 is formed above the second doped region 303 of the substrate 101. In some embodiments, an etching process, such as an isotropic etching process, is performed to remove a part of the third insulating layer 805 surrounding the contact hole 402 to form the deformed hole 404, and the deformed hole 404 has a narrow part 404-1 and a wide part 404-2, where the narrow part 404-1 is located in the second insulating layer 803 and occupied by the filling material 402-1, and the wide part 404-2 is located in the third insulating layer 805.

[0183] See Figure 30 and Figure 31 , a bit line 409 is formed above the bit line contact 405, and a capacitor contact 403 is formed above the second doped region 303.

[0184] In some embodiments, the fill material 402-1 can be stripped from the deformed holes 404, and the fill material 408-1 can be stripped from the bit line trench openings 408. After removing the fill material, a conductive material, such as a material of aluminum, copper, tungsten, cobalt, or other suitable metal or metal alloy, can be deposited. A metallization process is used to form a bit line 409 in the bit line trench opening 408 and a capacitor contact 403 in the deformed hole 404. In some embodiments, the metallization process is chemical vapor deposition, physical vapor deposition, or sputtering. A planarization process, such as chemical mechanical polishing, is performed after the metallization process to remove the excess deposited material and provide a substantially flat surface for subsequent process steps.

[0185] In some embodiments, the capacitor contact 403 includes a neck 403-1 and a head 403-2 located above the neck 403-1. The upper width W1 of the head 403-2 is greater than the upper width W2 of the neck 403-1. In some embodiments, the upper width W2 of the neck 403-1 is substantially equal to the bottom width of the head 403-2. In some embodiments, the head 403-2 has a curved sidewall 403-3. In some embodiments, the head 403-2 has a tapered cross-sectional profile.

[0186] In some embodiments, the bit line 409 extends in the Y direction and appears as a wavy line in a top view. A bit line contact 405 is provided at the intersection of the bit line 409 and the active region 105. Presenting the bit line 409 as a wavy line can increase the contact area between the bit line contact 405 and the active region 105. Therefore, the contact resistance between the bit line contact 405 and the active region 105 can be reduced.

[0187] See Figure 11 and Figures 32 to 33, in step S15, a fourth insulating layer 807 is formed over the third insulating layer 805, and a capacitor plug 411 is formed in the fourth insulating layer 807. The fourth insulating layer 807 may be made of the same material as that used to form the first insulating layer 801, but is not limited thereto. The fourth insulating layer 807 is formed by the same process as that used to form the first insulating layer 801. The capacitor plug 411 is formed by the following process, which includes: performing a lithography process to define the position of the capacitor plug 411; performing an etching process, such as an anisotropic dry etching process, to form a capacitor plug opening (not shown) extending through the fourth insulating layer 807; depositing a conductive material over the fourth insulating layer 807 and in the capacitor plug opening; performing a metallization process in the capacitor plug opening to form the capacitor plug 411 over the head 403-2 of the capacitor contact 403; and performing a planarization process, such as chemical mechanical polishing, to remove the excess deposited material and provide a substantially flat surface for subsequent process steps. In some embodiments, the conductive material includes aluminum, copper, tungsten, cobalt, or other suitable metal or metal alloy. In some embodiments, the metallization process is chemical vapor deposition, physical vapor deposition, or sputtering. In some embodiments, a barrier layer 412 is disposed between the capacitor plug 411 and the fourth insulating layer 807. The barrier layer 412 is disposed on the sidewalls of the capacitor plug 411 and adheres to the sidewalls S3 and S4 of the capacitor plug 411. The barrier layer 412 is made of titanium (Ti), titanium nitride (TiN), or a combination thereof.

[0188] See Figure 33 , an etching process is performed to remove a portion of the fourth insulating layer 807, exposing the protruding portion 411A of the capacitor plug 411. In some embodiments, a re-etching process is performed to remove the top portion of the fourth insulating layer 807, exposing the protruding portion 411A of the capacitor plug 411 and the top portion 412A of the barrier layer 412. In some embodiments, after the re-etching process, the top surface of the capacitor plug 411 is higher than the top surface of the fourth insulating layer 807, and the sidewalls of the top portion 412A are exposed.

[0189] See Figure 11 and Figures 34 to 35 , in step S17, a contact pad 810 is formed over the fourth insulating layer 807.

[0190] See Figure 34 , a deposition process is performed to form a liner 808 covering the top surface of the fourth insulating layer 807, the top surface of the protruding portion 411A, and the sidewalls of the top portion 412A. In some embodiments, the liner 808 is a silicon-containing layer, such as a polysilicon layer.

[0191] See Figure 35, a heating process is performed to form a contact pad 810 on the fourth insulating layer 807. In some embodiments, a silicidation process (heating process) is performed to form a contact pad 810 on the fourth insulating layer 807, where the contact pad 810 includes a protruding portion 411A of the capacitor plug 411, a top portion 412A of the barrier layer 412, a first silicide layer (metal silicide) 808A located above the protruding portion 411A, and a second silicide layer (metal silicide) 808B located on the sidewalls of the protruding portion 411A. In some embodiments, the heating process transforms a portion of the protruding portion 411A and the liner 808 into the first silicide layer 808A. In some embodiments, the heating process transforms the top portion 412A of the barrier layer 412 and the liner 808 into the second silicide layer 808B. In other words, the contact pad 810 is formed without using lithography technology, that is, the contact pad 810 is self-aligned with the capacitor plug 411. In some embodiments, the thickness and shape of the protruding portion 411A and the top portion 412A can be changed (not shown in the figure).

[0192] In some embodiments, an etching process, such as an anisotropic dry etching process, is performed to remove the portion of the liner 808 that is not transformed into metal silicide by the heating process. In some embodiments, the silicidation process between the top portion 412A and the liner 808 proceeds faster than the silicidation process between the protruding portion 411A and the liner 808, and the top end of the second silicide layer 808B is higher than the top end of the first silicide layer 808A. In other words, since the height H2 of the second silicide layer 808B is greater than the height H1 of the first silicide layer 808A, a stepped structure is formed between the first silicide layer 808A and the second silicide layer 808B. In some embodiments, the second silicide layer 808B surrounds the first silicide layer 808A, and the width W4 of the second silicide layer 808B is greater than the width W3 of the first silicide layer 808A.

[0193] Figures 36 to 39 are semiconductor devices according to various embodiments of the present disclosure. These semiconductor devices are similar to the semiconductor device 200 in many aspects, and the description of the similar features will not be repeated here.

[0194] See Figure 36 , at least one air gap 253 is disposed in the second insulating layer 803 and on opposite sides of the bit line contact 405. The width W21 of each air gap 253 is substantially less than, equal to, or greater than the width W22 of the word line 201. The center line C of each air gap 253 is aligned with the side surface S1 or the side surface S2 of the word line 201, where the side surfaces S1 and S2 face the bit line contact 405. After the air gap 253 is formed, each remaining portion of the second insulating layer 803 is referred to as a support portion 251.

[0195] See Figure 37 , at least one air gap 353 is disposed in and passes through the first insulating layer 801 and the second insulating layer 803. The air gap 353 is disposed on opposite sides of the bit line contact 405. The width W31 of each air gap 353 is substantially less than, equal to, or greater than the width W32 of the word line 201. The center line C of each air gap 353 is aligned with the side surface S1 or the side surface S2 of the word line 201, where the side surfaces S1 and S2 face the bit line contact 405. After forming the air gap 353, the remaining portions of the first insulating layer 801 and the second insulating layer 803 are referred to as the support portions 351.

[0196] See Figure 38 , at least one air gap 453 is disposed in and passes through the second insulating layer 803 and the third insulating layer 805. The air gap 453 is disposed on opposite sides of the bit line 409. The width W41 of each air gap 453 is substantially less than, equal to, or greater than the width W42 of the word line 201. The center line C of each air gap 453 is aligned with the side surface S1 or the side surface S2 of the word line 201, where the side surfaces S1 and S2 face the bit line 409. After forming the air gap 453, the remaining portions of the second insulating layer 803 and the third insulating layer 805 are referred to as the support portions 451.

[0197] See Figure 39 , at least one air gap 553 is disposed in and passes through the first insulating layer 801, the second insulating layer 803, and the third insulating layer 805. The air gap 553 is disposed on opposite sides of the contact 401. The width W51 of each air gap 553 is substantially less than, equal to, or greater than the width W52 of the word line 201. The center line C of each air gap 553 is aligned with the side surface S1 or the side surface S2 of the word line 201, where the side surfaces S1 and S2 face the contact 401. After forming the air gap 553, the remaining portions of the first insulating layer 801, the second insulating layer 803, and the third insulating layer 805 are referred to as the support portions 551.

[0198] One aspect of the present disclosure provides a semiconductor device. The semiconductor device includes: a substrate having a drain region and a source region disposed therein; a gate structure disposed on the substrate and between the drain region and the source region; a first dielectric disposed on the substrate and covering the substrate and the gate structure; a plug disposed in the first dielectric, wherein the plug includes a first portion extending through the first dielectric and contacting the source region of the substrate, and a second portion protruding from the first dielectric; a storage node contact pad disposed on an exposed portion of the second portion of the plug; a second dielectric disposed on the first dielectric and covering the storage node contact pad; at least one air gap disposed in the second dielectric; a bit line extending through the second dielectric and the first dielectric and connected to the substrate; a third dielectric disposed on the bit line; and a storage node disposed on the third dielectric, wherein the storage node extends through the third dielectric and the second dielectric and contacts the storage node contact pad.

[0199] Another aspect of the present disclosure provides a semiconductor device. The semiconductor device includes: a substrate having a source region, a drain region, and a bit line disposed therein; a dielectric layer disposed on the substrate; at least one air gap disposed in the dielectric layer; a plug disposed in the dielectric layer; a barrier layer disposed on a sidewall of the plug; and a contact pad disposed on the dielectric layer. The barrier layer includes a top portion located above the dielectric layer.

[0200] Another aspect of the present disclosure provides a method of manufacturing a semiconductor device. The method of manufacturing includes: providing a substrate having a gate structure disposed thereon; forming a first interlayer dielectric covering the substrate and the gate structure; forming a plug in the first interlayer dielectric; exposing a portion of the plug; forming a storage node contact pad on the exposed portion of the plug; forming a second interlayer dielectric on the first interlayer dielectric, wherein the second interlayer dielectric includes at least one air gap; forming a bit line extending through the second interlayer dielectric and the first interlayer dielectric and connected to the substrate; forming a third interlayer dielectric on the bit line; and forming a storage node on the third interlayer dielectric.

[0201] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the processes described above can be implemented in different ways, and many of the processes described above can be replaced by other processes or combinations thereof.

[0202] Moreover, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art can understand from the disclosure of the present disclosure that existing or future-developed processes, machines, manufactures, compositions of matter, means, methods, or steps that can be used according to the present disclosure and have the same functions or achieve substantially the same results as the corresponding embodiments described herein. Accordingly, such processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A semiconductor element, comprising: A substrate having a drain region and a source region disposed in the substrate; A gate structure is disposed on the substrate and between the drain region and the source region; A first dielectric is disposed on the substrate and covers the substrate and the gate structure; a plug disposed in the first dielectric, wherein the plug includes a first portion extending through the first dielectric and contacting the source region of the substrate, and a second portion protruding from the first dielectric; a storage node contact pad disposed on an exposed portion of the second portion of the plug; a second dielectric disposed on the first dielectric and covering the storage node contact pad; at least one air gap disposed in the second dielectric; a bit line extending through the second dielectric and the first dielectric and connected to the substrate; a third dielectric disposed on the bit line; and A storage node is disposed on the third dielectric, wherein the storage node extends through the third dielectric and the second dielectric and contacts the storage node contact pad.

2. The semiconductor device according to claim 1, further comprising: A plurality of support portions are disposed in the second dielectric, wherein the plurality of support portions are separated from each other to define the air gap. 3 . The semiconductor device as claimed in claim 2 , wherein the plurality of support portions are separated by the air gap. 4 . The semiconductor device as claimed in claim 2 , wherein the plurality of support portions are formed during the formation of the air gap. 5 . The semiconductor device as claimed in claim 2 , wherein the plurality of support portions are disposed between an upper metal line and a lower metal line. 6 . The semiconductor device as claimed in claim 5 , wherein the plurality of support portions are disposed above the first dielectric and below the second dielectric for supporting the upper metal line. The semiconductor device as claimed in claim 1 , wherein the air gap extends through the second dielectric. 8 . The semiconductor device as claimed in claim 1 , wherein a width of the air gap is smaller than a width of the gate structure in a cross-sectional view. 9 . The semiconductor device as claimed in claim 1 , wherein a center line of the air gap is aligned with a center line of the gate structure.

10. The semiconductor device according to claim 1, further comprising: A bit line contact pad is located on the drain region of the substrate, wherein the bit line is connected to the drain region of the substrate by contacting the bit line contact pad.

11. The semiconductor device of claim 1, wherein the plug comprises copper, and the storage node comprises copper germanium (Cu3Ge). 12 . The semiconductor device as claimed in claim 1 , wherein the gate structure further comprises a silicide, a polysilicon, a gate oxide and a spacer.

13. A semiconductor element, comprising: A substrate having a source region, a drain region and a bit line disposed in the substrate; a dielectric layer disposed on the substrate; at least one air gap disposed in the dielectric layer; a plug disposed in the dielectric layer; a barrier layer disposed on the sidewalls of the plug, wherein the barrier layer includes a top portion located above the dielectric layer; and A contact pad is disposed on the dielectric layer. 14 . The semiconductor device as claimed in claim 13 , wherein the dielectric layer comprises a first dielectric layer, a second dielectric layer, a third dielectric layer and a fourth dielectric layer. The semiconductor device as claimed in claim 14 , wherein the air gap is disposed in the first dielectric layer.

16. The semiconductor device according to claim 15, further comprising: A plurality of support portions are disposed in the first dielectric layer, wherein the plurality of support portions are separated from each other to define the air gap. 17 . The semiconductor device as claimed in claim 15 , wherein a width of the air gap is smaller than, equal to, or larger than a width of the bit line. 18 . The semiconductor device as claimed in claim 15 , wherein a center line of the air gap is aligned with a side surface of the bit line. The semiconductor device as claimed in claim 14 , wherein the air gap is disposed in the second dielectric layer.

20. The semiconductor device according to claim 19, further comprising: A plurality of support portions are disposed in the second dielectric layer, wherein the plurality of support portions are separated from each other to define the air gap.

Images