Semiconductor device, semiconductor device preparation method and storage system

Abstract

The invention discloses a semiconductor device, a semiconductor device preparation method and a memory system, the semiconductor device comprises a stacking structure, the stacking structure comprises a memory string, the memory string penetrates through the stacking structure, the memory string comprises a semiconductor column and at least one stacking unit distributed along a first direction, the semiconductor column extends along the first direction, and the stacking unit is arranged on the semiconductor column. A first insulating layer is arranged on the peripheral surface of the semiconductor column; the stacking unit comprises a first active layer, at least one second active layer and a middle layer arranged between the first active layer and the second active layer, the first active layer, the second active layer and the middle layer are stacked in the first direction, and the first active layer, the second active layer and the middle layer are arranged around the semiconductor column. According to the semiconductor device provided by the embodiment of the invention, the semiconductor column, the first active layer, the second active layer and the intermediate layer form the storage unit for storing and reading data, a capacitor structure does not need to be additionally arranged, and the storage unit can reach a smaller size, so that the storage density of the semiconductor device is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and particularly to a semiconductor device, a method for manufacturing a semiconductor device, and a storage system. Background Art

[0002] Some semiconductor devices, such as dynamic random access memory (DRAM), may include storage cells arranged in an array and a control circuit. The control circuit can control the storage cells to operate the storage cells for reading, writing, or erasing. The storage cell includes a transistor and a capacitor connected to the transistor. The capacitor is used to store data, and the transistor is used to control the reading and writing operations of the capacitor. Among them, in the process of forming the storage cell, there are still some problems that need to be further solved. Summary of the Invention

[0003] Embodiments of the present application provide a semiconductor device, a method for manufacturing a semiconductor device, and a storage system, aiming to solve the problem that the storage density of existing semiconductor devices cannot be improved due to the influence of the capacitor size.

[0004] Embodiments of the present application provide a semiconductor device. The semiconductor device includes a stacked structure. The stacked structure includes a storage string that penetrates the stacked structure. The storage string includes:

[0005] A semiconductor column extending in a first direction, and a first insulating layer is provided on the outer peripheral surface of the semiconductor column;

[0006] At least one stacked unit distributed along the first direction. The stacked unit includes a first active layer, at least one second active layer stacked along the first direction, and an intermediate layer provided between the first active layer and the second active layer. The first active layer, the second active layer, and the intermediate layer respectively surround the semiconductor column.

[0007] In some embodiments, the stacked unit includes two second active layers, and the two second active layers are distributed on both sides of the first active layer along the first direction.

[0008] In some embodiments, the stacked unit includes one second active layer.

[0009] In some embodiments, the stacked structure includes a plurality of the stacked units distributed in sequence along the first direction; a second insulating layer surrounding the semiconductor column is provided between two adjacent stacked units.

[0010] In some embodiments, the intermediate layer includes a semiconductor doping portion surrounding the semiconductor column.

[0011] In some embodiments, the intermediate layer further includes a semiconductor portion disposed around the semiconductor column, and the semiconductor doping portion is located between the semiconductor portion and the semiconductor column.

[0012] In some embodiments, the material of the semiconductor doping portion includes boron-doped polysilicon, and the material of the semiconductor portion includes germanium.

[0013] In some embodiments, the intermediate layer further includes a third insulating layer located between the semiconductor portion and the semiconductor doping portion.

[0014] In some embodiments, the stacked structure includes multiple columns of the memory strings, each column of the memory strings is arranged in sequence along a second direction, and the multiple columns of the memory strings are distributed in sequence along a third direction. The second direction and the third direction intersect with each other and are respectively perpendicular to the first direction; an isolation layer is provided between two adjacent columns of the memory strings.

[0015] In some embodiments, the semiconductor device further includes multiple word lines provided on one side of the stacked structure along the first direction. The multiple word lines are distributed in sequence along the second direction. The word lines extend along the third direction, and the word lines are connected to one semiconductor column of multiple columns of the memory strings;

[0016] The second active layers of the memory strings in the same column form a bit line extending along the second direction.

[0017] In some embodiments, the first active layers of multiple memory strings are connected together.

[0018] The embodiment of the present application further provides a method for manufacturing a semiconductor device, and the method includes:

[0019] Providing a substrate;

[0020] Forming at least one stacked unit on the substrate, the stacked unit includes a layer of first active layer, at least one layer of second active layer, and an intermediate layer disposed between the first active layer and the second active layer, which are stacked along a first direction. The first direction is perpendicular to the substrate;

[0021] Forming a semiconductor column penetrating the stacked unit along the first direction, and a first insulating layer disposed on the outer peripheral surface of the semiconductor column.

[0022] In some embodiments, the forming at least one stacked unit on the substrate includes:

[0023] Forming a layer of first active layer, at least one layer of second active layer, and a semiconductor portion disposed between the first active layer and the second active layer on the substrate, which are stacked along the first direction, to form a stacked layer;

[0024] Form a via hole in the stacked layer that penetrates the first active layer, the second active layer, and the semiconductor portion along the first direction;

[0025] Form a semiconductor doping portion on one side of the semiconductor portion facing the via hole to form the intermediate layer.

[0026] In some embodiments, forming, on the substrate, a layer of first active layer, at least one layer of second active layer, and a semiconductor portion disposed between the first active layer and the second active layer, includes:

[0027] Form a second active layer, a semiconductor portion, a first active layer, a semiconductor portion, and a second active layer on the substrate in sequence along the first direction.

[0028] In some embodiments, forming, on the substrate, a layer of first active layer, at least one layer of second active layer, and a semiconductor portion disposed between the first active layer and the second active layer, includes:

[0029] Form a second active layer, a semiconductor portion, and a first active layer on the substrate in sequence.

[0030] In some embodiments, forming the semiconductor doping portion on one side of the semiconductor portion facing the via hole to form the intermediate layer, includes:

[0031] Form a third insulating layer on one side of the semiconductor portion facing the via hole;

[0032] Form the semiconductor doping portion on one side of the third insulating layer facing the via hole to form the intermediate layer.

[0033] In some embodiments, the material of the semiconductor portion includes germanium; the material of the semiconductor doping portion includes boron-doped polysilicon.

[0034] In some embodiments, forming a semiconductor column that penetrates the stacked unit along the first direction, and a first insulating layer disposed on the outer peripheral surface of the semiconductor column, includes:

[0035] Form the first insulating layer on the inner peripheral surface of the via hole;

[0036] Fill the via hole with a semiconductor material to form the semiconductor column.

[0037] In some embodiments, forming at least one stacked unit on the substrate, includes:

[0038] Form a plurality of second insulating layers and a plurality of the stacked units that are alternately distributed in a first direction on the substrate.

[0039] In some embodiments, the semiconductor device includes multiple columns of the memory strings, each column of the memory strings is arranged in sequence in a second direction, and the multiple columns of the memory strings are distributed in sequence in a third direction. The second direction and the third direction intersect with each other and are perpendicular to the first direction respectively; the method further includes:

[0040] Form an isolation layer between two adjacent columns of the memory strings.

[0041] In some embodiments, the second active layers of the memory strings in the same column form bit lines extending in the second direction; the method further includes:

[0042] Form a plurality of word lines that are distributed in sequence in the second direction on a side of the stacked layer facing away from the substrate. The word lines extend in the third direction, and the word lines are connected to one semiconductor pillar of the multiple columns of the memory strings.

[0043] An embodiment of the present application further provides a storage system, the storage system includes a memory and a controller, the controller is coupled to the memory and is used to control the memory to store data;

[0044] Wherein, the memory includes the semiconductor device as described above; or, the memory includes a semiconductor device prepared by the semiconductor device preparation method as described above; the semiconductor device includes a stacked structure, the stacked structure includes a memory string, the memory string penetrates the stacked structure, and the memory string includes:

[0045] A semiconductor pillar extending in a first direction, and a first insulating layer is provided on an outer peripheral surface of the semiconductor pillar;

[0046] At least one stacked unit distributed in the first direction, the stacked unit includes a first active layer, at least one second active layer, and an intermediate layer that are stacked in the first direction, and the first active layer, the second active layer, and the intermediate layer respectively surround the semiconductor pillar.

[0047] In the semiconductor device provided by the embodiment of the present application, the memory string penetrating the stacked structure includes a semiconductor column extending in a first direction and at least one stacked unit distributed in the first direction. A first insulating layer is provided on the outer peripheral surface of the semiconductor column. The first active layer, the second active layer and the intermediate layer of the stacked unit are stacked in the first direction and respectively surround the semiconductor column. Thus, the semiconductor column, the first active layer, the second active layer and the intermediate layer can form a memory cell for storing data. By applying certain voltages to the semiconductor column and the second active layer respectively, the intermediate layer between the second active layer and the first active layer can store certain charges, thereby realizing data storage. When data needs to be read, certain voltages are applied to the semiconductor column and the second active layer respectively.

[0048] Since the semiconductor column, the first active layer, the second active layer and the intermediate layer form a memory cell, the memory cell can be made to have a smaller size and a higher density, thereby improving the storage density of the semiconductor device. Description of the Drawings

[0049] The following will, by way of a detailed description of the specific embodiments of the present application in conjunction with the drawings, make the technical solutions and other beneficial effects of the present application obvious.

[0050] Figure 1 It is a partial top view of an embodiment of the semiconductor device provided by the embodiment of the present application;

[0051] Figure 2 is Figure 1 a cross-sectional view taken along the A-A direction in, where some of the lower stacked units are omitted;

[0052] Figure 3 is Figure 2 a cross-sectional view taken along the B-B direction in;

[0053] Figure 4 is Figure 2 a cross-sectional view taken along the C-C direction in;

[0054] Figure 5 It is a top view of an embodiment after forming a stacked layer in the method for manufacturing a semiconductor device provided by the embodiment of the present application;

[0055] Figure 6 is Figure 5 a cross-sectional view taken along the D-D direction in, where some of the upper stacked layers are omitted;

[0056] Figure 7 It is a top view of an embodiment after forming a via in the method for manufacturing a semiconductor device provided by the embodiment of the present application;

[0057] Figure 8 isFigure 7 A cross-sectional view taken along the E-E direction, in which the upper part of the stacked layers is omitted;

[0058] Figure 9 A top view of an embodiment after forming a groove in the method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0059] Figure 10 is Figure 9 A cross-sectional view taken along the F-F direction, in which the upper part of the stacked layers is omitted;

[0060] Figure 11 A top view of an embodiment after forming an insulating material layer in the method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0061] Figure 12 is Figure 11 A cross-sectional view taken along the G-G direction, in which the upper part of the stacked layers is omitted;

[0062] Figure 13 A top view of an embodiment after forming a third insulating layer in the method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0063] Figure 14 is Figure 13 A cross-sectional view taken along the H-H direction, in which the upper part of the stacked layers is omitted;

[0064] Figure 15 A top view of an embodiment after forming a semiconductor doping portion in the method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0065] Figure 16 is Figure 15 A cross-sectional view taken along the I-I direction, in which the upper part of the stacked layers is omitted;

[0066] Figure 17 A top view of an embodiment after forming a first insulating layer in the method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0067] Figure 18 is Figure 17 A cross-sectional view taken along the J-J direction, in which the upper part of the stacked layers is omitted;

[0068] Figure 19 A top view of an embodiment after forming a semiconductor pillar in the method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0069] Figure 20 is Figure 19Cross-sectional view along the K-K direction, in which the upper part of the stacked layers is omitted;

[0070] Figure 21 Top view of an embodiment after forming the first photoresist, the first anti-reflection layer, and the first hard mask layer in the semiconductor device manufacturing method provided by the embodiment of the present application;

[0071] Figure 22 Is Figure 21 Cross-sectional view along the L-L direction, in which the lower part of the stacked layers is omitted;

[0072] Figure 23 Top view of an embodiment after forming the isolation trench in the semiconductor device manufacturing method provided by the embodiment of the present application;

[0073] Figure 24 Is Figure 22 Cross-sectional view along the M-M direction, in which the middle part of the stacked layers is omitted;

[0074] Figure 25 Top view of an embodiment after forming the isolation part in the semiconductor device manufacturing method provided by the embodiment of the present application;

[0075] Figure 26 Is Figure 25 Cross-sectional view along the N-N direction, in which the middle part of the stacked layers is omitted;

[0076] Figure 27 Top view of an embodiment after forming the second hard mask layer in the semiconductor device manufacturing method provided by the embodiment of the present application;

[0077] Figure 28 Top view of an embodiment after forming the word line in the semiconductor device manufacturing method provided by the embodiment of the present application;

[0078] Figure 29 Flow chart of an embodiment of the semiconductor device manufacturing method provided by the embodiment of the present application;

[0079] Figure 30 Structural schematic diagram of an embodiment of the storage system provided by the embodiment of the present application;

[0080] Figure 31 Structural schematic diagram of an embodiment of the electronic device provided by the embodiment of the present application.

[0081] Semiconductor device 1; storage system 2; controller 3; memory 4; electronic device 5; host 6; central processing unit 7; substrate 10; stacked structure 20; stacked cell 21; stacked layer 22; semiconductor pillar 30; first insulating layer 40; isolation layer 50; first photoresist 51; first anti-reflection layer 52; first hard mask layer 53; isolation trench 54; word line 60; second hard mask layer 61; word line trench 62; insulating segment 63; bit line 70; third insulating layer 80; memory string 90; via 200; first active layer 211; second active layer 212; intermediate layer 213; semiconductor doping portion 214; semiconductor portion 215; second insulating layer 216; groove 217; insulating material layer 218; first direction X; second direction Y; third direction Z. Detailed implementation manners

[0082] The technical solutions in the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts fall within the protection scope of the present disclosure.

[0083] It should be understood that although the terms first, second, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another. For example, the first component may be referred to as the second component, and similarly, the second component may be referred to as the first component without departing from the scope of the present disclosure.

[0084] It should be understood that when a component is referred to as being "on" another component or "connected" to another component, it may be directly on the other component or connected to the other component, or there may also be intervening components. Other words used to describe the relationship between components should be interpreted in a similar manner.

[0085] As used herein, the term "layer" refers to a portion of a material that includes a region having a thickness. The layer has a top side and a bottom side, where the bottom side of the layer is relatively closer to the substrate, and the top side is relatively farther from the substrate. The layer may extend over the entire underlying or overlying structure, or may have a range less than the range of the underlying or overlying structure. In addition, the layer may be a region of a uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any set of horizontal planes at the top and bottom surfaces. The layer may extend horizontally, vertically, and / or along a tapered surface. The substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. The layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and contact layers (where contacts, interconnect lines, and one or more dielectric layers are formed).

[0086] Semiconductor devices, such as dynamic random access memories (DRAMs), may include memory cells arranged in an array and control circuits. The control circuits can control the memory cells, operate the memory cells to read, write, or erase. Each memory cell includes a transistor and a capacitor connected to the transistor. The capacitor is used to store data, and the transistor is used to control the read and write operations of the capacitor. Due to the relatively large size of the capacitor, each capacitor occupies a relatively large area, making the overall size of the memory cell composed of the capacitor and the transistor relatively large, thereby affecting the improvement of the storage density of the semiconductor device.

[0087] To solve the above problems, embodiments of the present application provide a semiconductor device, a method for manufacturing a semiconductor device, and a storage system. The following will be described in detail respectively.

[0088] First, embodiments of the present application provide a semiconductor device.

[0089] Figure 1 It is a partial top view of an embodiment of the semiconductor device provided by the embodiment of the present application. Figure 2 is Figure 1 a cross-sectional view taken along the A-A direction in. As Figure 1 and Figure 2 shown, the semiconductor device 1 includes a stacked structure 20. The stacked structure 20 includes a memory string 90. The memory string 90 penetrates the stacked structure 20, and the memory string 90 includes a plurality of memory cells sequentially distributed along a first direction X. Each memory cell is respectively used to store data.

[0090] As Figure 1 and Figure 2 shown, the memory string 90 includes a semiconductor column 30 extending along the first direction X and at least one stacked unit 21 distributed along the first direction X. The material of the semiconductor column 30 can be polysilicon (poly) or other semiconductor materials. A first insulating layer 40 is provided on the outer peripheral surface of the semiconductor column 30. Specifically, the first insulating layer 40 is disposed around the circumferential direction of the semiconductor column 30, and one end of the semiconductor column 30 along the first direction X is covered by the first insulating layer 40. The material of the first insulating layer 40 can be an oxide insulating material or other materials with insulating properties. Among them, the first insulating layer 40 can be formed by a spacer process.

[0091] The stacked unit 21 includes a layer of first active layer 211, at least one layer of second active layer 212 stacked along the first direction X, and an intermediate layer 213 disposed between the first active layer 211 and the second active layer 212. The first active layer 211, the second active layer 212, and the intermediate layer 213 are respectively disposed around the semiconductor column 30.

[0092] Thus, the semiconductor pillar 30, the first active layer 211, the second active layer 212, and the intermediate layer 213 can form a memory cell for storing data. By applying certain voltages to the semiconductor pillar 30 and the second active layer 212 respectively, a certain amount of charge can be stored in the intermediate layer 213 between the second active layer 212 and the first active layer 211, thereby realizing data storage. When data needs to be read, it can be achieved by applying certain voltages to the semiconductor pillar 30 and the second active layer 212 respectively.

[0093] Since the semiconductor pillar 30, the first active layer 211, the second active layer 212, and the intermediate layer 213 can form a memory cell without the need to separately form a capacitor structure, the memory cell can be made to have a smaller size, a higher density, and is not limited by the size of the capacitor structure, which is beneficial to improving the storage density of the semiconductor device 1.

[0094] Among them, the material of the first active layer 211 includes silicon or other semiconductor materials. The first active layer 211 can be a structure formed by using the Lightly Doped Drain (LDD) process. Specifically, the first active layer 211 is an active layer structure formed by ion implantation (IMP) of a silicon layer. Similarly, the material of the second active layer 212 includes silicon or other semiconductor materials. The second active layer 212 can be a structure formed by using the Lightly Doped Drain (LDD) process. Specifically, the second active layer 212 is an active layer structure formed by ion implantation (IMP) of a silicon layer.

[0095] In some embodiments, as Figure 2 and Figure 3 shown, the intermediate layer 213 includes a semiconductor doping portion 214 disposed around the semiconductor pillar 30. By applying certain voltages to the semiconductor pillar 30 and the second active layer 212 respectively, a certain amount of charge can be stored in the semiconductor doping portion 214 between the second active layer 212 and the first active layer 211, thereby realizing data storage. The material of the semiconductor doping portion 214 can include boron-doped polysilicon or other materials capable of storing charge.

[0096] Among them, the intermediate layer 213 can further include a semiconductor portion 215 disposed around the semiconductor pillar 30, and the semiconductor doping portion 214 is located between the semiconductor portion 215 and the semiconductor pillar 30, which is convenient for forming the semiconductor doping portion 214 based on the semiconductor portion 215 during the manufacturing process of the semiconductor device 1. The material of the semiconductor portion 215 includes germanium or other semiconductor materials that are beneficial to forming the semiconductor doping portion 214.

[0097] In some embodiments, the intermediate layer 213 further includes a third insulating layer 80 located between the semiconductor portion 215 and the semiconductor doping portion 214. The third insulating layer 80 is used to isolate the semiconductor portion 215 from the semiconductor doping portion 214 to prevent the charges in the semiconductor doping portion 214 from entering the semiconductor portion 215. The material of the third insulating layer 80 can be an oxide insulating material or other materials with insulating properties.

[0098] In some embodiments, the stacked unit 21 may include two second active layers 212. The two second active layers 212 are distributed on both sides of the first active layer 211 along the first direction X. Intermediate layers 213 are respectively provided between the two second active layers 212 and the first active layer 211. Thus, the semiconductor column 30, the first active layer 211, the two second active layers 212, and the two intermediate layers 213 can form two storage units distributed in sequence along the first direction X. And the two storage units share a first active layer 211, which can improve the storage density while minimizing the thickness of the storage unit in the first direction X.

[0099] In other embodiments, the stacked unit 21 may also include one second active layer 212. Then, the first active layer 211, the second active layer 212, the intermediate layer 213 of the stacked unit 21 and the semiconductor column 30 constitute a storage unit.

[0100] In some embodiments, the stacked structure 20 may include a plurality of stacked units 21 distributed in sequence along the first direction X, so that the memory string 90 includes a plurality of storage units distributed in sequence along the first direction X, to further improve the storage density of the semiconductor device 1.

[0101] Wherein, a second insulating layer 216 surrounding the semiconductor column 30 is provided between two adjacent stacked units 21. Thus, the second insulating layer 216 can isolate two adjacent stacked units 21 distributed along the first direction X to avoid interference between the storage units of two adjacent stacked units 21. The material of the second insulating layer 216 can be an oxide insulating material or other materials with insulating properties.

[0102] In some embodiments, such as Figure 3 and Figure 4As shown, the semiconductor device 1 may include multiple columns of memory strings 90. Multiple memory strings 90 in each column of memory strings 90 are arranged in sequence along the second direction Y. Multiple columns of memory strings 90 are distributed in sequence along the third direction X. The second direction Y and the third direction X intersect with each other and are respectively perpendicular to the first direction X, so as to form multiple memory cells arrayed along the second direction Y and the third direction X within the stacked structure 20, thereby increasing the data storage capacity of the semiconductor device 1. In particular, when the memory string 90 includes multiple stacked units 21, memory cells with a multi-layer array distribution can be formed within the stacked structure 20, significantly increasing the storage density and data storage capacity of the semiconductor device 1. The included angle formed by the second direction Y and the third direction X can be a right angle or an acute angle.

[0103] Wherein, an isolation layer 50 may be provided between two adjacent columns of memory strings 90 to separate the two adjacent columns of memory strings 90 and prevent interference between the two adjacent columns of memory strings 90. The material of the isolation layer 50 may be an oxide insulating material or other materials with insulating properties.

[0104] Specifically, as Figure 2 and Figure 3 shown, the semiconductor device 1 includes multiple layers of isolation layers 50. The multiple layers of isolation layers 50 and the multiple columns of memory strings 90 are alternately distributed along the second direction Y, so that there is a column of memory strings 90 between two adjacent isolation layers 50, and there is a layer of isolation layer 50 between two adjacent columns of memory strings 90. Wherein, the side surface of the isolation layer 50 is perpendicular to the second direction Y. The second direction Y and the third direction X are perpendicular.

[0105] In some embodiments, the semiconductor device 1 may further include a substrate 10, and the substrate 10 is perpendicular to the first direction X. The stacked structure 20 of the semiconductor device 1 is located on one side of the substrate 10 along the first direction X. The substrate 10 can be used as a base for forming the stacked structure 20 to facilitate the formation of the stacked structure 20. After the stacked structure 20 of the semiconductor device 1 is fabricated, the substrate 10 can be retained or removed.

[0106] Wherein, the substrate 10 and the second active layer 212 closest to the substrate 10 in the stacked structure 20 can be an integral structure. Specifically, a part of the lowermost semiconductor layer of the semiconductor device 1 can be etched to form the lowermost substrate 10 and the second active layer 212 located on the substrate 10. Of course, the substrate 10 and the second active layer 212 closest to the substrate 10 in the stacked structure 20 can also be two semiconductor layers formed successively. Specifically, the substrate 10 can be formed first, and then the second active layer 212 can be formed on one side of the substrate 10 along the first direction X. The material of the substrate 10 may include silicon or other semiconductor materials.

[0107] As Figure 1 and Figure 2As shown, the semiconductor device 1 further includes a plurality of word lines 60 disposed on one side of the stacked structure 20 along the first direction X. The plurality of word lines 60 are sequentially distributed along the second direction Y, and the word lines 60 extend along the third direction X. The word lines 60 are connected to one semiconductor pillar 30 of multiple columns of memory strings 90 to apply a voltage to the semiconductor pillar 30 through the word lines 60. Among them, different word lines 60 can apply voltages to different semiconductor pillars 30, and one word line 60 can apply voltages to multiple semiconductor pillars 30 connected to the word line 60.

[0108] As Figure 4 shown, the second active layers 212 of the same column of memory strings 90 form bit lines 70 extending along the second direction Y. Thus, a voltage can be applied to the second active layers 212 of the same column of memory strings 90 through the bit lines 70. Among them, the second active layers 212 of the same layer of the same column of memory strings 90 form bit lines 70 extending along the second direction Y. The second active layers 212 of different layers of the same column of memory strings 90 respectively form different layers of bit lines 70 extending along the second direction Y.

[0109] When data needs to be stored in the memory cells of a certain memory string 90, a corresponding voltage can be applied to the word line 60 connected to the semiconductor pillar 30 of the memory cell, and a corresponding voltage can be applied to the bit line 70 connected to the second active layer 212 of the memory cell, so that the intermediate layer 213 of the memory cell stores charges. When data stored in the memory cell needs to be read, a corresponding voltage can be applied to the word line 60 connected to the semiconductor pillar 30 of the memory cell, and a corresponding voltage can be applied to the bit line 70 connected to the second active layer 212 of the memory cell.

[0110] The first active layers 211 of multiple memory strings 90 are connected together to keep the potentials of the first active layers 211 of multiple memory strings 90 consistent. Among them, all the first active layers 211 of multiple memory strings 90 can be connected together, or a part of the first active layers 211 of multiple memory strings 90 can be connected together. For example: the first active layers 211 of different layers of all memory strings 90 can be connected together; or, the first active layers 211 of the same layer of all memory strings 90 can be connected together.

[0111] Specifically, the second active layer 212 can be used as the drain, and the first active layer 211 can be used as the source. The sources of multiple memory strings 90 go out through source contacts, and the sources of multiple memory strings 90 are connected together.

[0112] The drains of the memory strings 90 in the same column are sequentially connected along the second direction Y to form bit lines 70 extending along the second direction Y. Each bit line 70 is respectively connected out through a corresponding bit line contact. Among them, when the memory string 90 includes a plurality of memory cells sequentially distributed along the first direction X, the memory strings 90 in the same column include a plurality of bit lines 70 sequentially distributed along the first direction X. One ends of the multiple bit lines 70 of the memory strings 90 in the same column can be stepped in the first direction X, so that one ends of the multiple bit lines 70 of the memory strings 90 in the same column are respectively connected out through corresponding bit line contacts.

[0113] The semiconductor pillars 30 can serve as the gates of the respective memory cells of the memory string 90. The number of word lines 60 is the same as the number of memory strings 90 included in each column of memory strings 90, etc. The multiple word lines 60 are respectively connected to the ends of the semiconductor pillars 30 of the multiple memory strings 90 in a column of memory strings 90 in a one-to-one correspondence. Each word line 60 is respectively connected out through a corresponding word line contact.

[0114] In some embodiments, the number of memory cells connected to one bit line 70 can be 2048. Among them, the number of memory strings 90 connected to one bit line 70 can be determined according to the memory cells or stacked units 21 included in each memory string 90. For example: each memory string 90 includes 128 stacked units 21, and each stacked unit 21 includes one memory cell, then one bit line 70 can be connected to the semiconductor pillars 30 of 16 memory strings 90, so that the number of memory cells connected to one bit line 70 is 128 * 16 = 2048. Or, each memory string 90 includes 128 stacked units 21, and each stacked unit 21 includes 2 memory cells, then one bit line 70 can be connected to the semiconductor pillars 30 of 8 memory strings 90, so that the number of memory cells connected to one bit line 70 is 128 * 8 * 2 = 2048.

[0115] To better fabricate the semiconductor device provided in the embodiments of the present application, the embodiments of the present application further provide a method for fabricating a semiconductor device. As Figure 29 shown, the method for fabricating a semiconductor device may include steps S210 to S230, which are described in detail as follows:

[0116] S210. Provide a substrate 10.

[0117] Among them, the substrate 10 can serve as the base of other structures of the semiconductor device 1, and other structures of the semiconductor device 1 are sequentially formed on the substrate 10. After other structures of the semiconductor device 1 are formed, the substrate 10 can be retained or the substrate 10 can be removed. The material of the substrate 10 can be silicon or other semiconductor materials.

[0118] S220. Form at least one stacked unit 21 on the substrate 10. The stacked unit 21 includes a first active layer 211, at least one second active layer 212, and an intermediate layer 213 disposed between the first active layer 211 and the second active layer 212, which are stacked along the first direction X perpendicular to the substrate 10.

[0119] Among them, the materials of the first active layer 211, the second active layer 212, and the intermediate layer 213 can refer to the above embodiments and will not be elaborated here. The first active layer 211, the second active layer 212, and the intermediate layer 213 can be deposited in a predetermined order by deposition methods such as chemical vapor deposition (CVD) and physical vapor deposition (PVD). The first active layer 211 and the second active layer 212 can be formed by the same process. For example: first deposit a silicon layer, and then perform ion implantation on the silicon layer to form the first active layer 211 or the second active layer 212.

[0120] S230. Form a semiconductor column 30 penetrating the stacked unit 21 along the first direction X, and a first insulating layer 40 disposed on the outer peripheral surface of the semiconductor column 30 to form a memory string 90 of the semiconductor device 1.

[0121] Among them, the material of the semiconductor column 30 can be polysilicon (poly) or other semiconductor materials. The first insulating layer 40 is disposed around the circumferential direction of the semiconductor column 30 to separate the semiconductor column 30 from the stacked unit 21. The material of the first insulating layer 40 can be an oxide insulating material or other materials with insulating properties.

[0122] The semiconductor device manufacturing method provided by the embodiments of the present application forms at least one stacked unit 21 on the substrate 10, forms a semiconductor column 30 penetrating the stacked unit 21, and a first insulating layer 40 disposed on the outer peripheral surface of the semiconductor column 30, so that the first active layer 211, the second active layer 212, and the intermediate layer 213 of the stacked unit 21 are stacked along the first direction X and are respectively disposed around the semiconductor column 30. Thus, the semiconductor column 30, the first active layer 211, the second active layer 212, and the intermediate layer 213 can form a memory cell for storing data. By applying certain voltages to the semiconductor column 30 and the second active layer 212 respectively, the intermediate layer 213 between the second active layer 212 and the first active layer 211 can store a certain amount of charge, thereby realizing data storage. When data needs to be read, certain voltages are applied to the semiconductor column 30 and the second active layer 212 respectively.

[0123] Since the memory cell formed by the semiconductor column 30, the first active layer 211, the second active layer 212, and the intermediate layer 213 does not require a capacitor structure, the memory cell can be made smaller in size and higher in density, thereby improving the storage density of the semiconductor device 1.

[0124] In some embodiments, the step of forming at least one stacked unit 21 on the substrate 10 may include steps S221 to S223, which are described in detail as follows:

[0125] S221, as Figure 5 and Figure 6 shown, form a layer of first active layer 211, at least one layer of second active layer 212 stacked along the first direction X on the substrate 10, and a semiconductor part 215 disposed between the first active layer 211 and the second active layer 212 to form a stacked layer 22.

[0126] Among them, the first active layer 211, the semiconductor part 215, and the second active layer 212 may be sequentially formed on the substrate 10 along the first direction X, or the second active layer 212, the semiconductor part 215, and the first active layer 211 may be sequentially formed on the substrate 10 along the first direction X. The material of the semiconductor part 215 may include germanium or other semiconductor materials.

[0127] S222, as Figure 7 and Figure 8 shown, form a via 200 penetrating the first active layer 211, the second active layer 212, and the semiconductor part 215 along the first direction X in the stacked layer 22.

[0128] Among them, the stacked layer 22 may be etched to form a via 200 penetrating the first active layer 211, the second active layer 212, and the semiconductor part 215 along the first direction X in the stacked layer 22. The via 200 does not penetrate the substrate 10. The first active layer 211 or the second active layer 212 close to the substrate 10 and the substrate 10 are of an integral structure. Specifically, for example: when the first active layer 211, the semiconductor part 215, and the second active layer 212 are sequentially formed on the substrate 10 along the first direction X, the substrate 10 and the first active layer 211 may be of an integral structure; when the second active layer 212, the semiconductor part 215, and the first active layer 211 are sequentially formed on the substrate 10 along the first direction X, the second active layer 212 and the substrate 10 may be of an integral structure.

[0129] S223, as Figures 9 to 16 shown, form a semiconductor doping part 214 on one side of the semiconductor part 215 facing the via 200 to form an intermediate layer 213.

[0130] Charge storage can be achieved through the semiconductor doping part 214, so that the semiconductor column 30 and the first active layer 211, the second active layer 212, and the intermediate layer 213 can constitute a storage unit for storing data. The material of the semiconductor doping part 214 may include boron-doped polysilicon or other materials capable of storing charges.

[0131] In some embodiments, a semiconductor doping portion 214 may be formed by deposition on the inner side of the semiconductor portion 215 facing the via 200. Among them, as Figure 15 and Figure 16 shown, the step of forming the semiconductor doping portion 214 on one side of the semiconductor portion 215 facing the via 200 to form the intermediate layer 213 may include: forming a third insulating layer 80 on one side of the semiconductor portion 215 facing the via 200; forming the semiconductor doping portion 214 on one side of the third insulating layer 80 facing the via 200 to form the intermediate layer 213.

[0132] Thereby, the semiconductor doping portion 214 can be isolated from the semiconductor portion 215 by the third insulating layer 80, preventing the charges in the semiconductor doping portion 214 from entering the semiconductor portion 215. The material of the third insulating layer 80 may be an oxide insulating material or other materials with insulating properties.

[0133] Specifically, as Figure 11 and Figure 12 shown, an insulating material layer 218 may be formed on the inner surface of the via 200. Then, as Figure 13 and Figure 14 shown, the portions of the insulating material layer 218 located on the sides of the first active layer 211 and the second active layer 212 facing the via 200 are removed, and the portion of the insulating material layer 218 located on the side of the semiconductor portion 215 facing the via 200 is retained to form the third insulating layer 80. Among them, the materials of the first active layer 211 and the second active layer 212 include silicon, and the material of the semiconductor portion 215 includes germanium. Due to the different oxidation rates and etching rates of silicon and germanium, based on this, it can be realized that the portions of the insulating material layer 218 located on the sides of the first active layer 211 and the second active layer 212 facing the via 200 are quickly etched and removed, while the portion of the insulating material layer 218 located on the side of the semiconductor portion 215 facing the via 200 is etched at a slower rate and a remaining portion is retained to form the third insulating layer 80.

[0134] In some embodiments, before forming the third insulating layer 80 on one side of the semiconductor portion 215 facing the via 200, as Figure 9 and Figure 10 shown, a portion of the material on one side of the semiconductor portion 215 facing the via 200 may also be removed to form a groove 217 on one side of the semiconductor portion 215 facing the via 200. The subsequently formed third insulating layer 80 and semiconductor doping portion 214 can be accommodated in the groove 217.

[0135] In some embodiments, the step of forming, on the substrate 10, a first active layer 211, at least one second active layer 212, and a semiconductor portion 215 disposed between the first active layer 211 and the second active layer 212, which are stacked along the first direction X, may include: sequentially forming, on the substrate 10 along the first direction X, the second active layer 212, the semiconductor portion 215, the first active layer 211, the semiconductor portion 215, and the second active layer 212.

[0136] Thereby, two memory cells can be formed in one stacked unit 21, and the two memory cells share one first active layer 211, thereby improving the storage density and minimizing the thickness of the memory cells in the first direction X.

[0137] In other embodiments, the step of forming, on the substrate 10, a first active layer 211, at least one second active layer 212, and a semiconductor portion 215 disposed between the first active layer 211 and the second active layer 212, which are stacked along the first direction X, includes: sequentially forming, on the substrate 10, the second active layer 212, the semiconductor portion 215, and the first active layer 211 to form one memory cell within one stacked unit 21.

[0138] In some embodiments, forming at least one stacked unit 21 on the substrate 10 includes: forming, on the substrate 10, multiple second insulating layers 216 and multiple stacked units 21 that are alternately distributed along the first direction X.

[0139] Thereby, multiple memory cells can be formed in the memory string 90 and distributed sequentially along the first direction X. Moreover, adjacent two memory cells are isolated by a third insulating layer 80 to further improve the storage density of the semiconductor device 1 and prevent the memory cells of adjacent two stacked units 21 from interfering with each other. The material of the second insulating layer 216 may be an oxide insulating material or other materials with insulating properties.

[0140] It should be noted that when the number of stacked units 21 is multiple, the number of second active layers 212 included in each stacked unit 21, and the relative distribution manner of the first active layer 211 and the second active layer 212 may be the same or different, as long as the memory cells within each stacked unit 21 can store and read data without interfering with each other.

[0141] In some preferred embodiments, each stacked unit 21 may include a second active layer 212, a semiconductor portion 215, a first active layer 211, a semiconductor portion 215, and a second active layer 212 that are sequentially distributed in a direction away from the substrate 10. Thus, each stacked unit 21 includes two memory cells and has the minimum thickness in the first direction X. While effectively increasing the number of memory cells in the memory string 90, the length of the memory string 90 in the first direction X is made as small as possible.

[0142] In some embodiments, as Figures 17 to 20 shown, forming the semiconductor column 30 that penetrates the stacked unit 21 along the first direction X, and the first insulating layer 40 disposed on the outer peripheral surface of the semiconductor column 30, includes: as Figure 17 and Figure 18 shown, forming the first insulating layer 40 on the inner peripheral surface of the via 200. As Figure 19 and Figure 20 shown, filling the via 200 with a semiconductor material to form the semiconductor column 30.

[0143] Among them, the first insulating layer 40 may be formed on the inner surface of the via 200. The first insulating layer 40 may be formed by a spacer process or other means. By filling the via 200 with a semiconductor material to form the semiconductor column 30, the semiconductor column 30, the first active layer 211, the second active layer 212, and the intermediate layer 213 constitute the memory string 90 of the memory device 4.

[0144] As Figure 19 and Figure 20 shown, the semiconductor device 1 includes multiple columns of memory strings 90. Each column of memory strings 90 is arranged in sequence along the second direction Y. The multiple columns of memory strings 90 are sequentially distributed along the third direction X. The second direction Y and the third direction X intersect with each other and are respectively perpendicular to the first direction X to form a plurality of memory cells that are arrayed along the second direction Y and the third direction X in the stacked structure 20, thereby increasing the data storage capacity of the semiconductor device 1.

[0145] In some embodiments, as Figures 21 to 26 shown, the method for manufacturing the semiconductor device further includes: forming an isolation layer 50 between two adjacent columns of memory strings 90 to separate the two adjacent columns of memory strings 90 and prevent interference between the two adjacent columns of memory strings 90. The material of the isolation layer 50 may be an oxide insulating material or other materials with insulating properties.

[0146] Among them, as Figures 23 to 24 shown, an isolation groove 54 may be formed between two adjacent columns of memory strings 90. Then, as Figure 25 to and Figure 26As shown, an insulating material is filled in the isolation trench 54 to form an isolation layer 50 in the isolation trench 54, separating two adjacent columns of memory strings 90. Specifically, as Figure 21 and Figure 22 shown, a first photoresist 51, a first anti-reflection layer 52, and a first hard mask layer 53 can be sequentially formed on the side of the stacked layer 22 away from the substrate 10. Then, as Figure 23 and Figure 24 shown, the stacked layer 22 is etched through the first hard mask layer 53 to form an isolation trench 54 that penetrates the first active layer 211, the intermediate layer 213, and the second active layer 212 of the stacked layer 22. After that, as Figure 25 and Figure 26 shown, an insulating material is filled in the isolation trench 54 to form an isolation layer 50 that separates two adjacent columns of memory strings 90.

[0147] In some embodiments, as Figure 27 and Figure 28 shown, the method for manufacturing a semiconductor device further includes: forming a plurality of word lines 60 sequentially distributed along the second direction Y on the side of the stacked layer 22 away from the substrate 10. The word lines 60 extend along the third direction X, and the word lines 60 are connected to one semiconductor pillar 30 of multiple columns of memory strings 90. Thus, a voltage can be applied to the semiconductor pillar 30 through the word lines 60. Among them, different voltages can be applied to different semiconductor pillars 30 through different word lines 60, and a voltage can be applied to multiple semiconductor pillars 30 connected to the same word line 60 through one word line 60.

[0148] Specifically, as Figure 27 shown, a second hard mask layer 61 can be formed on the side of the stacked layer 22 away from the substrate 10, and the second hard mask layer 61 forms a plurality of word line grooves 62 sequentially distributed along the second direction Y. The word line grooves 62 extend along the third direction X, and the word line grooves 62 are connected to the end of the first semiconductor pillar 30 of multiple columns of memory strings 90 away from the substrate 10. By filling tungsten or other conductive materials in the word line grooves 62, a word line 60 connected to one semiconductor pillar 30 of multiple columns of memory strings 90 is formed.

[0149] After that, as Figure 28 shown, the hard mask can be removed. Then, as Figure 1 shown, an insulating material is filled between two adjacent word lines 60 to form an insulating segment 63 that separates two adjacent word lines 60.

[0150] As Figure 4As shown, the second active layer 212 of the same column of memory strings 90 forms a bit line 70 extending along the second direction Y, so that a voltage is applied to the second active layer 212 of the same column of memory strings 90 through the bit line 70. The same layer of the second active layer 212 of the same column of memory strings 90 forms the bit line 70 extending along the second direction Y. The second active layers 212 of different layers of the same column of memory strings 90 respectively form different layers of bit lines 70 extending along the second direction Y.

[0151] The first active layers 211 of the plurality of storage strings 90 are connected together to keep the potentials of the first active layers 211 of the plurality of storage strings 90 consistent. In particular, all the first active layers 211 of the plurality of storage strings 90 may be connected together, or a portion of the first active layers 211 of the plurality of storage strings 90 may be connected together.

[0152] An embodiment of the present application also provides a memory, which includes a semiconductor device. The specific structure of the semiconductor device refers to the above embodiment. Since the present memory adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here.

[0153] See also Figure 30 The embodiment of the present application further provides a storage system. The storage system 2 includes a controller 3 and a memory 4. The controller 3 is coupled to the memory 4 and is used to control the memory 4 to store data. The memory 4 includes the semiconductor device 1 in any of the above embodiments.

[0154] The semiconductor device 1 may be an array wafer memory 4 or a device combined with a CMOS (complementary metal oxide semiconductor) peripheral circuit.

[0155] Specifically, the semiconductor device 1 can be stacked with the peripheral circuit or staggered with the peripheral circuit, which is not limited in the present application. The peripheral circuit is electrically connected to the semiconductor device 1 to transmit signals to the semiconductor device 1. The peripheral circuit can be used for logical operations and to control and detect the switching state of each storage unit in the semiconductor device 1 through metal wiring to achieve data storage and reading.

[0156] Specifically, the memory 4 may be a DRAM memory.

[0157] Specifically, the controller 3 can control the memory 4 through the channel CH, and the memory 4 can perform operations in response to requests from the host 6 based on the control of the controller 3. The memory 4 can receive a command CMD and an address ADDR from the controller 3 through the channel CH and access a region selected from the memory cell array in response to the address. In other words, the memory 4 can perform internal operations corresponding to the command on the region selected by the address.

[0158] In some embodiments, the storage system 2 can be implemented as a universal flash storage (UFS) device, a solid state drive (SSD), a multimedia card in the form of an MMC, eMMC, RS-MMC, and micro MMC, a secure digital card in the form of an SD, mini SD, and micro SD, a storage device of the personal computer memory card international association (PCMCIA) card type, a storage device of the peripheral component interconnect (PCI) type, a high-speed PCI (PCI-E) type storage device, a compact flash (CF) card, a smart media card, or a memory stick, etc.

[0159] Specifically, the above storage system 2 can be used in terminal products such as computers, televisions, set-top boxes, and in-vehicle devices.

[0160] Please refer to Figure 31 , this embodiment of the present application also provides an electronic device. The electronic device 5 includes a central processing unit 7 and the above storage system 2 provided by this embodiment of the present application. Specifically, the electronic device 5 can be any device capable of storing data, such as a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, an in-vehicle device, a wearable device, a mobile power supply, etc.

[0161] The central processing unit 7 is used for information data exchange with the storage system 2.

[0162] An electronic device provided by this embodiment of the present application has the same beneficial effects as the above storage system due to the provision of the storage system provided by this embodiment of the present application.

[0163] In the above embodiments, the descriptions of the respective embodiments have their own focuses. For parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0164] The above has introduced in detail a semiconductor device, a semiconductor device manufacturing method, and a storage system provided by the embodiments of the present application. Specific examples are used herein to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the technical solution and its core idea of the present application. Those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments or perform equivalent replacements on some of the technical features. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes a stacked structure, the stacked structure includes a memory string, the memory string penetrates the stacked structure, and the memory string includes: A semiconductor column extending in a first direction, and a first insulating layer is provided on an outer peripheral surface of the semiconductor column; At least one stacked unit distributed along the first direction, the stacked unit includes a first active layer, at least one second active layer stacked along the first direction, and an intermediate layer provided between the first active layer and the second active layer, and the first active layer, the second active layer and the intermediate layer respectively surround the semiconductor column.

2. The semiconductor device according to claim 1, wherein, The stacked unit includes two layers of the second active layer, and the two layers of the second active layer are distributed on both sides of the first active layer along the first direction.

3. The semiconductor device according to claim 1, characterized in that, The stacked unit includes one layer of the second active layer.

4. The semiconductor device according to claim 1, characterized in that, The stacked structure includes a plurality of the stacked units sequentially distributed along the first direction; a second insulating layer surrounding the semiconductor column is provided between two adjacent stacked units.

5. The semiconductor device according to claim 1, wherein, The intermediate layer includes a semiconductor doping portion surrounding the semiconductor column.

6. The semiconductor device according to claim 5, characterized in that, The intermediate layer further includes a semiconductor portion surrounding the semiconductor column, and the semiconductor doping portion is located between the semiconductor portion and the semiconductor column.

7. The semiconductor device according to claim 6, wherein, The material of the semiconductor doping portion includes boron-doped polysilicon, and the material of the semiconductor portion includes germanium.

8. The semiconductor device according to claim 6, wherein The intermediate layer further includes a third insulating layer located between the semiconductor portion and the semiconductor doping portion.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that, The stacked structure includes multiple columns of the memory strings, each column of the memory strings is sequentially arranged along a second direction, and the multiple columns of the memory strings are sequentially distributed along a third direction, the second direction and the third direction intersect with each other and are respectively perpendicular to the first direction; an isolation layer is provided between two adjacent columns of the memory strings.

10. The semiconductor device according to claim 9, wherein, The semiconductor device further includes a plurality of word lines provided on one side of the stacked structure along the first direction, the plurality of word lines are sequentially distributed along the second direction, the word lines extend along the third direction, and the word lines are connected to one semiconductor column of multiple columns of the memory strings; The second active layers of the memory strings in the same column form a bit line extending along the second direction.

11. The semiconductor device according to claim 9, wherein, The first active layers of the multiple memory strings are connected together.

12. A method for manufacturing a semiconductor device, characterized in that, The method includes: Providing a substrate; Forming at least one stacked unit on the substrate, the stacked unit includes a first active layer, at least one second active layer stacked along a first direction, and an intermediate layer provided between the first active layer and the second active layer, and the first direction is perpendicular to the substrate; Forming a semiconductor column penetrating the stacked unit along the first direction, and a first insulating layer provided on an outer peripheral surface of the semiconductor column to form a memory string of the semiconductor device.

13. The method for manufacturing a semiconductor device according to claim 12, characterized in that, The forming at least one stacked unit on the substrate includes: Forming a first active layer, at least one second active layer stacked along the first direction, and a semiconductor portion provided between the first active layer and the second active layer on the substrate to form a stacked layer; Forming a via penetrating the first active layer, the second active layer and the semiconductor portion along the first direction in the stacked layer; A semiconductor doping portion is formed on a side of the semiconductor portion facing the via to form the intermediate layer.

14. The method for manufacturing a semiconductor device according to claim 13, wherein, Forming, on the substrate, a first active layer, at least one second active layer, and a semiconductor portion disposed between the first active layer and the second active layer, which are stacked along the first direction, includes: Forming, on the substrate, a second active layer, a semiconductor portion, a first active layer, a semiconductor portion, and a second active layer in sequence along the first direction.

15. The method for manufacturing a semiconductor device according to claim 13, wherein, Forming, on the substrate, a first active layer, at least one second active layer, and a semiconductor portion disposed between the first active layer and the second active layer, which are stacked along the first direction, includes: Forming, on the substrate, a second active layer, a semiconductor portion, and a first active layer in sequence.

16. The method for manufacturing a semiconductor device according to claim 13, wherein, Forming a semiconductor doping portion on a side of the semiconductor portion facing the via to form the intermediate layer includes: Forming a third insulating layer on a side of the semiconductor portion facing the via; Forming the semiconductor doping portion on a side of the third insulating layer facing the via to form the intermediate layer.

17. The method for manufacturing a semiconductor device according to claim 13, wherein, The material of the semiconductor portion includes germanium; the material of the semiconductor doping portion includes boron-doped polysilicon.

18. The method for manufacturing a semiconductor device according to claim 13, wherein, Forming a semiconductor column that penetrates the stacked unit along the first direction, and a first insulating layer disposed on an outer peripheral surface of the semiconductor column, includes: Forming the first insulating layer on an inner peripheral surface of the via; Filling the via with a semiconductor material to form the semiconductor column.

19. The method for manufacturing a semiconductor device according to any one of claims 13 to 18, characterized in that, Forming at least one stacked unit on the substrate includes: Forming, on the substrate, a plurality of second insulating layers and a plurality of the stacked units that are alternately distributed along the first direction.

20. The method for manufacturing a semiconductor device according to claim 19, wherein, The semiconductor device includes a plurality of columns of the memory strings, each column of the memory strings is arranged in sequence along the second direction, and the plurality of columns of the memory strings are distributed in sequence along the third direction. The second direction and the third direction intersect with each other and are respectively perpendicular to the first direction; The method further includes: Forming an isolation layer between two adjacent columns of the memory strings.

21. The method for manufacturing a semiconductor device according to claim 20, wherein, The second active layers of the memory strings in the same column form bit lines extending along the second direction; the method further includes: Forming, on a side of the stacked layer facing away from the substrate, a plurality of word lines distributed in sequence along the second direction. The word lines extend along the third direction, and the word lines are connected to one semiconductor column of the plurality of columns of the memory strings.

22. A storage system, characterized in that, The storage system includes a memory and a controller. The controller is coupled to the memory and is configured to control the memory to store data; Wherein, the memory includes the semiconductor device according to any one of claims 1 to 11; or, the memory includes a semiconductor device prepared by the semiconductor device preparation method according to any one of claims 12 to 21.

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